Semiconductor device

Abstract

Embodiments of the present application relate to a semiconductor device. The semiconductor device of the embodiments includes a transistor region, a diode region, and a terminal region. The diode region includes a first set of trenches extending in a first direction and repeatedly arranged in a second direction, and the terminal region includes the first set of trenches. The first set of trenches includes a first trench, a second trench, a third trench, and a fourth trench. The first trench and the second trench are connected in the terminal region, and the third trench and the fourth trench are connected in the terminal region. The second trench and the third trench are adjacent in the second direction, and a first minimum distance in the second direction between the second trench and the third trench in the terminal region is smaller than a second minimum distance in the second direction between the second trench and the third trench in the diode region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-211668 (filed on December 4, 2024). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] An example of a semiconductor device used in power applications is the Insulated Gate Bipolar Transistor (IGBT). An IGBT, for example, has a p-type collector region, an n-type drift region, and a p-type base region on its collector electrode. Furthermore, a gate electrode is formed by sandwiching a gate insulating film within a trench that extends through the p-type base region and reaches the n-type drift region. Finally, an n-type emitter region, connected to the emitter electrode, is formed on the surface of the p-type base region adjacent to the trench.

[0005] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and freewheeling diodes onto the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode allows current to flow in the opposite direction to the IGBT's on-state current. Integrating the IGBT and freewheeling diode onto the same semiconductor chip offers many advantages, including simplified assembly processes and dispersed heat-generating components.

[0006] Because it is formed on the same semiconductor chip as the IGBT, the construction and process of the freewheeling diode may not be optimized, and sometimes the characteristics of the freewheeling diode are degraded. It is desirable to improve the characteristics of the freewheeling diode in the RC-IGBT. Summary of the Invention

[0007] A semiconductor device according to an embodiment includes: a transistor region; a diode region; and an end region surrounding the transistor region and the diode region. The diode region includes: a semiconductor layer having a first surface and a second surface facing the first surface; a first semiconductor region of a first conductivity type disposed in the semiconductor layer; a second semiconductor region of a first conductivity type disposed in the semiconductor layer and disposed between the first semiconductor region and the first surface, wherein the first conductivity type impurity concentration of the second semiconductor region is lower than that of the first semiconductor region; a third semiconductor region of a second conductivity type disposed in the semiconductor layer and disposed between the second semiconductor region and the first surface; a first set of trenches disposed on one side of the first surface in the semiconductor layer, extending in a first direction parallel to the first surface, the first set of trenches being disposed in a second direction parallel to the first surface and perpendicular to the first direction, and in contact with the second semiconductor region and the third semiconductor region; and a first electrode. The third semiconductor region is electrically connected; and a second electrode is connected to the first semiconductor region. The end region includes: the semiconductor layer; the second semiconductor region; a fourth semiconductor region of a second conductivity type, disposed in the semiconductor layer and between the second semiconductor region and the first surface, electrically connected to the first electrode, the depth of the fourth semiconductor region being deeper than the depth of the third semiconductor region; the trenches of the first group; and the second electrode. The trenches of the first group include a first trench, a second trench, a third trench, and a fourth trench. The first trench and the second trench are physically connected in the end region, the third trench and the fourth trench are physically connected in the end region, the second trench and the third trench are adjacent in the second direction, and the first minimum distance in the second direction between the second trench and the third trench in the end region is less than the second minimum distance in the second direction between the second trench and the third trench in the diode region.

[0008] According to embodiments of the present invention, a semiconductor device capable of improving performance can be provided, comprising an RC-IGBT having an IGBT and a diode. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0011] Figure 3 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0013] Figure 5 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0014] Figure 6 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0015] Figure 7 This is a schematic top view of a part of the semiconductor device according to the first embodiment.

[0016] Figure 8 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0017] Figure 9 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment.

[0018] Figure 10 This is a schematic cross-sectional view of a portion of a comparative example semiconductor device.

[0019] Figure 11 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0020] Figure 12 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0021] Figure 13 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0022] Figure 14 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0023] Figure 15 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0024] Figure 16 This is a schematic cross-sectional view of a semiconductor device in a first variation of the first embodiment.

[0025] Figure 17 This is an explanatory diagram illustrating the function and effect of the semiconductor device in the first variation of the first embodiment.

[0026] Figure 18 This is a schematic cross-sectional view of a semiconductor device in a second variation of the first embodiment.

[0027] Figure 19This is an explanatory diagram illustrating the operation and effects of the semiconductor device in the second variation of the first embodiment.

[0028] Figure 20 This is a schematic top view of a part of the semiconductor device according to the second embodiment.

[0029] Figure 21 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0030] Figure 22 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment.

[0031] Explanation of reference numerals in the attached figures

[0032] 10 semiconductor layers

[0033] 12 Upper electrode (first electrode)

[0034] 14. Lower electrode (second electrode)

[0035] 21 First group of trenches

[0036] 21b B-groove (first groove)

[0037] 21c C-groove (second groove, fifth groove)

[0038] 21d D-groove (third groove, second groove, seventh groove)

[0039] 21e E-groove (fourth groove, third groove, second groove)

[0040] 21f F-groove (sixth groove, third groove)

[0041] 21g G-groove (fourth groove, sixth groove)

[0042] 21h H-groove (Eighth Groove)

[0043] 21i I trench (fourth trench)

[0044] 22 Second group of trenches

[0045] 26 collector regions (sixth semiconductor region)

[0046] 27. Drift Region (Second Semiconductor Region)

[0047] 28-cell base region (seventh semiconductor region)

[0048] 29-unit emitter region (eighth semiconductor region)

[0049] 31. Cathode region (first semiconductor region)

[0050] 32. Anode region (third semiconductor region)

[0051] 34. Guard ring region (fourth semiconductor region)

[0052] 34a high concentration area (Region 1)

[0053] 34b low concentration area (second region)

[0054] 35. Backside p-region (fifth semiconductor region) at the end

[0055] 100RC-IGBT (Semiconductor Device)

[0056] 101 transistor region

[0057] 102 diode region

[0058] 103 terminal region

[0059] 110RC-IGBT (Semiconductor Device)

[0060] 120RC-IGBT (Semiconductor Device)

[0061] 200RC-IGBT (Semiconductor Device)

[0062] d1 First minimum distance d2 Second minimum distance F1 First face F2 Second face Detailed Implementation

[0063] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have been described once will be appropriately omitted.

[0064] In this specification, when there is n + Type, n-type, n - In the case of the type expression, it means that the concentration of n-type impurities is according to n + Type, n-type, n - The order of the type decreases. Furthermore, in the presence of p... + Type, p type, p - In the case of p-type marking, it means that the concentration of p-type impurities is according to p + Type, p type, p - The order of the types decreases.

[0065] In this specification, the n-type impurity concentration does not represent the actual n-type impurity concentration, but rather the compensated effective n-type impurity concentration. Similarly, the p-type impurity concentration does not represent the actual p-type impurity concentration, but rather the compensated effective p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is set as the n-type impurity concentration. The same applies to the p-type impurity concentration.

[0066] In this specification, the distribution and absolute value of impurity concentration in the semiconductor region can be determined, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitude of impurity concentration in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentration can be determined, for example, using spreading resistance analysis (SRA). The relative magnitude and absolute value of carrier concentration in the semiconductor regions are determined using SCM and SRA. By assuming the impurity activation rate, the relative magnitude, distribution, and absolute value of impurity concentration between the two semiconductor regions can be determined based on the SCM and SRA measurements.

[0067] Unless otherwise specified in the specification, the maximum concentration in the semiconductor region shall be used as the representative impurity concentration.

[0068] (First Implementation)

[0069] The semiconductor device of the first embodiment includes a transistor region; a diode region; and an end region surrounding the transistor region and the diode region. The diode region includes: a semiconductor layer having a first surface and a second surface facing the first surface; a first semiconductor region of a first conductivity type disposed within the semiconductor layer; a second semiconductor region of a first conductivity type disposed within the semiconductor layer and between the first semiconductor region and the first surface, wherein the first conductivity type impurity concentration of the second semiconductor region is lower than that of the first semiconductor region; a third semiconductor region of a second conductivity type disposed within the semiconductor layer and between the second semiconductor region and the first surface; a first set of trenches disposed on one side of the first surface in the semiconductor layer, extending in a first direction parallel to the first surface, the first set of trenches being arranged in a second direction parallel to the first surface and perpendicular to the first direction, and connected to the second semiconductor region and the third semiconductor region; a first electrode electrically connected to the third semiconductor region; and a second electrode connected to the first semiconductor region. The terminal region includes: a semiconductor layer; a second semiconductor region; a fourth semiconductor region of a second conductivity type, disposed in the semiconductor layer and between the second semiconductor region and the first surface, electrically connected to the first electrode, the depth of the fourth semiconductor region being greater than the depth of the third semiconductor region; a first group of trenches; and a second electrode. The first group of trenches includes a first trench, a second trench, a third trench, and a fourth trench. The first trench and the second trench are physically connected in the terminal region, and the third trench and the fourth trench are physically connected in the terminal region. The second trench and the third trench are adjacent in a second direction. The first minimum distance in the second direction between the second trench and the third trench in the terminal region is less than the second minimum distance in the second direction between the second trench and the third trench in the diode region.

[0070] The semiconductor device of the first embodiment is an RC-IGBT 100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT 100 has a trench-gate type IGBT with a gate electrode formed in a trench in a semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

[0071] Figure 1 This is a schematic diagram of the semiconductor device according to the first embodiment.

[0072] like Figure 1 As shown, the RC-IGBT 100 has a transistor region 101, a diode region 102, and a terminal region 103. The transistor region 101 and the diode region 102 are alternately arranged in a second direction perpendicular to the first direction. The terminal region 103 surrounds the transistor region 101 and the diode region 102.

[0073] Transistor region 101 operates as an IGBT. Diode region 102 operates as a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD).

[0074] When the RC-IGBT 100 is in the off state, the end region 103 reduces the intensity of the electric field applied to the ends of the pn junctions in the transistor region 101 and the diode region 102. The end region 103 also has the function of increasing the breakdown voltage of the RC-IGBT 100.

[0075] A gate electrode pad 104 is provided in the end region 103. More specifically, it is disposed above the diffusion layer of the p-type guard ring region 34, which will be described later, through an insulating film.

[0076] The RC-IGBT 100 of the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a virtual gate insulating film 42, a trench insulating film 43, a gate electrode 51, a virtual gate electrode 52, a conductive layer 53, an interlayer insulating layer 60, and a gate electrode pad 104.

[0077] In the semiconductor layer 10, a first group of trenches 21, a second group of trenches 22, and p are provided. + Type 26 collector region (sixth semiconductor region), n - The drift region 27 of the n-type (second semiconductor region), the cell base region 28 of the p-type (seventh semiconductor region), and the n-type... + Type 29 emitter region (eighth semiconductor region), p + Type of unit contact area 30, n + p-type cathode region 31 (first semiconductor region), p-type anode region 32 (third semiconductor region), p + The diode contact region 33 of the p-type diode, the guard ring region 34 (fourth semiconductor region) of the p-type diode, and the p-type guard ring region 34 (fourth semiconductor region) of the p-type diode. + The end back p region 35 (fifth semiconductor region) of the type.

[0078] The first group of grooves 21 includes groove A 21a, groove B 21b, groove C 21c, groove D 21d, groove E 21e, groove F 21f, groove G 21g, groove H 21h, groove I 21i, and groove J 21j.

[0079] The second set of trenches 22 includes gate trench 22x and dummy gate trench 22y.

[0080] In this specification, "trench" refers to a groove disposed in semiconductor layer 10. A "trench" is a part of semiconductor layer 10. A "trench" is filled, for example, by a conductor or an insulator.

[0081] The semiconductor layer 10 has a first surface F1 and a second surface F2 opposite to the first surface F1. The semiconductor layer 10 is, for example, monocrystalline silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0082] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. Furthermore, a direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. Additionally, in this specification, "depth" is defined as the distance from the first surface F1 towards the second surface F2.

[0083] Figure 2 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 This is a schematic cross-sectional view of the transistor region. Figure 2 yes Figure 1 AA' section.

[0084] Figure 3 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 3 This is a top view of the first surface F1 of the transistor region. Figure 2 yes Figure 3 AA' section.

[0085] The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a dummy gate insulating film 42, a gate electrode 51, a dummy gate electrode 52, and an interlayer insulating layer 60.

[0086] In the semiconductor layer 10 of transistor region 101, there are a second set of trenches 22, collector region 26 (sixth semiconductor region), drift region 27 (second semiconductor region), unit base region 28 (seventh semiconductor region), unit emitter region 29 (eighth semiconductor region), and unit contact region 30.

[0087] The upper electrode 12 is disposed on the first surface F1 side of the semiconductor layer 10. At least a portion of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0088] The upper electrode 12 functions as the emitter electrode of the IGBT within the transistor region 101. The upper electrode 12 is, for example, metal.

[0089] The upper electrode 12 is connected to the unit emitter region 29 and the unit contact region 30. The upper electrode 12 is electrically connected to the unit emitter region 29. Hereinafter, the portion of the upper electrode 12 that is connected to the unit emitter region 29 and the unit contact region 30 will be referred to as the unit contact portion CC.

[0090] The upper electrode 12 is connected to the cell contact region 30. The upper electrode 12 is electrically connected to the cell contact region 30. The upper electrode 12 is electrically connected to the cell base region 28 via the cell contact region 30.

[0091] The lower electrode 14 is disposed on the second surface F2 side of the semiconductor layer 10. At least a portion of the lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0092] The lower electrode 14 functions as the collector electrode of the IGBT in the transistor region 101. The lower electrode 14 is, for example, metal.

[0093] The lower electrode 14 is connected to the collector region 26 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 26 in the transistor region 101.

[0094] Collector region 26 is p + The collector region 26 is a semiconductor region of a certain type. The collector region 26 is connected to the second surface F2. The collector region 26 is electrically connected to the lower electrode 14. The collector region 26 is connected to the lower electrode 14. When the IGBT is in the on state, the collector region 26 becomes a source of holes.

[0095] Drift region 27 is n - A type of semiconductor region. Drift region 27 is disposed between collector region 26 and first surface F1.

[0096] The drift region 27 becomes the path for the conducting current when the IGBT is in the on state. The drift region 27 also has the function of depleting itself when the IGBT is in the off state, thus maintaining the IGBT's withstand voltage.

[0097] The base region 28 is a p-type semiconductor region. The base region 28 is disposed between the drift region 27 and the first surface F1. The drift region 27 is sandwiched between the base region 28 and the collector region 26.

[0098] In the cell base region 28, opposite the gate electrode 51 to which the gate voltage Vg is applied, an n-type inversion layer is formed when the IGBT is in the on state. The cell base region 28 functions as the channel region of the transistor.

[0099] Unit emitter region 29 is n + A semiconductor region of the type. The cell emitter region 29 is disposed between the cell base region 28 and the first surface F1. The cell emitter region 29 is in contact with the gate insulating film 41.

[0100] The n-type impurity concentration in the emitter region 29 is higher than that in the drift region 27.

[0101] The emitter region 29 of the unit is connected to the upper electrode 12. The emitter region 29 of the unit is electrically connected to the upper electrode 12. When the transistor is in the on state, the emitter region 29 becomes a source of electrons.

[0102] Unit contact area 30 is p + A semiconductor region of the type. A cell contact region 30 is disposed between the cell base region 28 and the first surface F1. The cell contact region 30 is connected to the upper electrode 12. The cell contact region 30 is electrically connected to the upper electrode 12.

[0103] The p-type impurity concentration in the cell contact region 30 is higher than that in the cell base region 28.

[0104] The second set of trenches 22 is disposed on the first surface F1 side of the semiconductor layer 10. The second set of trenches 22 are trenches disposed on the semiconductor layer 10. The second set of trenches 22 is a part of the semiconductor layer 10.

[0105] like Figure 3 As shown, the second set of grooves 22 extends on the first surface F1 along a first direction parallel to the first surface F1. The second set of grooves 22 has a stripe shape. The second set of grooves 22 is repeatedly arranged in a second direction perpendicular to the first direction, with 10 or more grooves.

[0106] The second set of trenches 22 connects to the drift region 27, the unit base region 28, and the unit emitter region 29. The second set of trenches 22 penetrates the unit base region 28 and reaches the drift region 27.

[0107] The second set of trenches 22 includes gate trenches 22x and dummy gate trenches 22y. Gate trenches 22x and dummy gate trenches 22y are arranged alternately, for example, one after another, in the second direction.

[0108] The gate electrode 51 is disposed within the gate trench 22x. The gate electrode 51 is, for example, a semiconductor or a metal. The gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0109] The gate electrode 51 is electrically connected to the gate electrode pad 104.

[0110] A gate insulating film 41 is disposed between the gate electrode 51 and the semiconductor layer 10. The gate insulating film 41 is disposed between the gate electrode 51 and the drift region 27, between the gate electrode 51 and the cell base region 28, and between the gate electrode 51 and the cell emitter region 29. The gate electrode 51 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The gate insulating film 41 is, for example, silicon oxide.

[0111] A virtual gate electrode 52 is disposed in a virtual gate trench 22y. The virtual gate electrode 52 is, for example, a semiconductor or a metal. The virtual gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0112] The virtual gate electrode 52 is electrically connected to the upper electrode 12, for example.

[0113] A virtual gate insulating film 42 is disposed between the virtual gate electrode 52 and the semiconductor layer 10. The virtual gate insulating film 42 is disposed between the virtual gate electrode 52 and the drift region 27, between the virtual gate electrode 52 and the cell base region 28, and between the virtual gate electrode 52 and the cell emitter region 29. The virtual gate insulating film 42 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The virtual gate insulating film 42 is, for example, silicon oxide.

[0114] Furthermore, the dummy gate trench 22y may not be provided in the transistor region 101. Additionally, the proportion of the gate trench 22x in the second group of trenches 22 in the transistor region 101 may not be the same as the proportion of the dummy gate trench 22y in the second group of trenches 22.

[0115] An interlayer insulating layer 60 is disposed between the gate electrode 51 and the upper electrode 12, and between the dummy gate electrode 52 and the upper electrode 12. The interlayer insulating layer 60 electrically separates the gate electrode 51 from the upper electrode 12, and the dummy gate electrode 52 from the upper electrode 12. The interlayer insulating layer 60 is, for example, silicon oxide.

[0116] Figure 4 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 4 It is a top view of the first surface F1, which includes the boundary between the transistor region and the end region. Figure 4 yes Figure 1 A top view of the area R1 enclosed by a dashed line.

[0117] exist Figure 4 The layout pattern of the second group of grooves 22 is shown. Additionally, in Figure 4 The diagram shows the layout of the drift region 27, the guard ring region 34, the cell base region 28, the cell emitter region 29, and the cell contact region 30.

[0118] The end region 103 includes a second set of trenches 22. For example... Figure 4 As shown, in the end region 103, the minimum distance in the second direction between any two adjacent trenches in the second set of trenches 22 is approximately the same. In other words, in the end region 103, the second set of trenches 22 are arranged at approximately equal intervals in the second direction.

[0119] Furthermore, in the end region 103, the second set of trenches 22 are not physically connected to each other. The second set of trenches 22 are physically independent.

[0120] For example, in Figure 4 In the gate contact portion CG shown, the gate electrode 51 in the gate trench 22x is connected to a gate wiring (not shown). The gate wiring is electrically connected to the gate electrode pad 104.

[0121] For example, in Figure 4 In the virtual gate contact portion CDG shown, the virtual gate electrode 52 in the virtual gate trench 22y is connected to the upper electrode 12 (not shown).

[0122] exist Figure 4 The diagram also shows a pattern of a unit contact portion CC disposed between two adjacent second set of grooves 22.

[0123] Figure 5 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 This is a schematic cross-sectional view of diode region 102. Figure 5 yes Figure 1 BB' section.

[0124] Figure 6 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 6 This is a top view of the first surface F1 of the diode region. Figure 5 yes Figure 6 BB' section.

[0125] The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a trench insulating film 43, a conductive layer 53, and an interlayer insulating layer 60.

[0126] Within the semiconductor layer 10 of the diode region 102, there are a first set of trenches 21, a cathode region 31 (first semiconductor region), a drift region 27 (second semiconductor region), an anode region 32 (third semiconductor region), and a diode contact region 33.

[0127] The first group of grooves 21 includes groove A 21a, groove B 21b, groove C 21c, groove D 21d, groove E 21e, groove F 21f, groove G 21g, groove H 21h, groove I 21i, and groove J 21j.

[0128] The upper electrode 12 functions as the anode electrode of the diode in the diode region 102. The upper electrode 12 is connected to the diode contact region 33. The upper electrode 12 is electrically connected to the diode contact region 33. The upper electrode 12 is electrically connected to the anode region 32 via the diode contact region 33. The upper electrode 12 is also connected to the anode region 32, for example. Hereinafter, the portion of the upper electrode 12 that is connected to both the diode contact region 33 and the anode region 32 will be referred to as the diode contact portion CD.

[0129] The lower electrode 14 functions as the cathode electrode of the diode in the diode region 102. The lower electrode 14 is connected to the cathode region 31.

[0130] Cathode region 31 is n + The cathode region 31 is connected to the second surface F2. When the diode is in the conducting state, the cathode region 31 becomes the electron supply source. The cathode region 31 is connected to the lower electrode 14.

[0131] Drift region 27 is n - The n-type semiconductor region. The drift region 27 is disposed between the cathode region 31 and the first surface F1. The n-type impurity concentration in the drift region 27 is lower than that in the cathode region 31.

[0132] Drift region 27 becomes the path for conduction current when the diode is in the conducting state.

[0133] The anode region 32 is a p-type semiconductor region. The anode region 32 is disposed between the drift region 27 and the first surface F1. The drift region 27 is sandwiched between the anode region 32 and the cathode region 31.

[0134] The anode region 32 becomes a source of holes when the diode is in the on state.

[0135] The p-type impurity concentration in the anode region 32 is, for example, lower than that in the guard ring region 34. The depth of the anode region 32 is, for example, the same as the depth of the unit base region 28. Sometimes, an n-type layer with a higher impurity concentration than the drift region 27 is formed directly below the unit base region 28. In this case, the depth of the anode region 32 is sometimes deeper than that of the unit base region 28.

[0136] Diode contact area 33 is p + A semiconductor region of the type. The diode contact region 33 is disposed between the anode region 32 and the first surface F1.

[0137] The diode contact area 33 is connected to the upper electrode 12. The diode contact area 33 is electrically connected to the upper electrode 12.

[0138] The p-type impurity concentration in diode contact region 33 is higher than that in anode region 32.

[0139] The first set of trenches 21 is disposed on the first surface F1 side of the semiconductor layer 10. The first set of trenches 21 are trenches disposed on the semiconductor layer 10. The first set of trenches 21 is a part of the semiconductor layer 10.

[0140] like Figure 6 As shown, the first set of grooves 21 extends along a first direction parallel to the first surface F1. The first set of grooves 21 has a stripe shape. The first set of grooves 21 is repeatedly arranged in a second direction perpendicular to the first direction.

[0141] For example, grooves A 21a, B 21b, C 21c, D 21d, E 21e, F 21f, G 21g, H 21h, I 21i, and J 21j are arranged sequentially in the second direction.

[0142] The first set of trenches 21 connects to the drift region 27 and the anode region 32. The first set of trenches 21 penetrates the anode region 32 and reaches the drift region 27.

[0143] A conductive layer 53 is disposed in each of the first set of trenches 21. The conductive layer 53 is, for example, a semiconductor or a metal. The conductive layer 53 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0144] The conductive layer 53 is electrically connected to the upper electrode 12, for example.

[0145] A trench insulating film 43 is disposed between the conductive layer 53 and the semiconductor layer 10. The trench insulating film 43 is disposed between the conductive layer 53 and the drift region 27, and between the conductive layer 53 and the anode region 32. The conductive layer 53 is in contact with both the drift region 27 and the anode region 32. The conductive layer 53 is, for example, silicon oxide.

[0146] An interlayer insulating layer 60 is disposed between the conductive layer 53 and the upper electrode 12. The interlayer insulating layer 60 electrically separates the conductive layer 53 from the upper electrode 12.

[0147] Figure 7 This is a schematic top view of a part of the semiconductor device according to the first embodiment. Figure 7 It is a top view of the first surface F1, which includes the boundary between the diode region and the end region. Figure 7 yes Figure 1 A top view of the area R2 enclosed by a dashed line.

[0148] Figure 7 This indicates the layout pattern of the first group of grooves 21. Additionally, in Figure 7The diagram shows the layout of the drift region 27, the guard ring region 34, the anode region 32, and the diode contact region 33.

[0149] The end region 103 includes a first set of trenches 21. The end region 103 includes trench A 21a, trench B 21b, trench C 21c, trench D 21d, trench E 21e, trench F 21f, trench G 21g, trench H 21h, trench I 21i, and trench J 21j.

[0150] In the terminal region 103, the first set of trenches 21 includes a first trench, a second trench, a third trench, and a fourth trench. The first trench and the second trench are physically connected in the terminal region 103, and the third trench and the fourth trench are also physically connected in the terminal region 103. The second trench and the third trench are adjacent in a second direction, and the first minimum distance in the second direction between the second trench and the third trench in the terminal region 103 is less than the second minimum distance in the second direction between the second trench and the third trench in the diode region 102.

[0151] Groove B 21b is an example of the first groove. Groove C 21c is an example of the second groove. Groove D 21d is an example of the third groove. Groove E 21e is an example of the fourth groove.

[0152] Grooves B 21b and C 21c are physically connected in the end region 103. Grooves D 21d and E 21e are physically connected in the end region 103. Grooves C 21c and D 21d are adjacent in the second direction.

[0153] The first minimum distance in the second direction between groove C 21c and groove D 21d in the end region 103 ( Figure 7 d1) is less than the second minimum distance in the second direction between the C trench 21c and the D trench 21d in diode region 102. Figure 7 (d2 in the middle).

[0154] The first minimum distance d1 is, for example, more than 1 / 10 and less than 1 / 2 of the second minimum distance d2.

[0155] Furthermore, for example, the distance in the second direction between groove C 21c and groove D 21d in the end region 103 is the length in the first direction of the portion below the second minimum distance d2. Figure 7 L) is longer than the second minimum distance d2 and is less than 100 times the second minimum distance d2.

[0156] For example, in Figure 7 In the conductive layer contact portion CCN shown, the conductive layer 53 in the first set of trenches 21 is connected to the upper electrode 12 (not shown).

[0157] exist Figure 7 The diagram also shows a pattern of diode contacts CD disposed between two adjacent first set of trenches 21.

[0158] Figure 8 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 8 It is a schematic cross-sectional view of the boundary between diode region 102 and end region 103. Figure 8 yes Figure 7 The CC' section.

[0159] Figure 9 This is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 9 It is a schematic cross-sectional view of the boundary between diode region 102 and end region 103. Figure 9 yes Figure 7 The DD' section.

[0160] The end region 103 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate insulating film 41, a virtual gate insulating film 42, a trench insulating film 43, a gate electrode 51, a virtual gate electrode 52, a conductive layer 53, and an interlayer insulating layer 60.

[0161] In the semiconductor layer 10 of the end region 103, a first set of trenches 21, a second set of trenches 22, a drift region 27, a guard ring region 34 (fourth semiconductor region) and an end back p region 35 (fifth semiconductor region) are provided.

[0162] In the terminal region 103, a parasitic diode is formed that includes a pn junction between the guard ring region 34 and the drift region 27.

[0163] The p region 35 on the back of the end is p + A semiconductor region of type 35. The p-region 35 on the back end is connected to the second surface F2. The p-region 35 on the back end is connected to the lower electrode 14.

[0164] The boundary between the p-region 35 on the back end and the cathode region 31 exists, for example, within the diode region 102. The distance in the first direction between the guard ring region 34 and the cathode region 31 ( Figure 8 The d3 in the figure is, for example, greater than 100 μm and less than 300 μm.

[0165] Furthermore, providing the p-region 35 on the back side of the end is not necessary. For example, the cathode region 31 can also be provided below the guard ring region 34 of the end region 103.

[0166] Drift region 27 is n -A type of semiconductor region. Drift region 27 is disposed between the end back p region 35 and the first surface F1.

[0167] Drift region 27 becomes the path for conduction current when the parasitic diode is in the conducting state.

[0168] The guard ring region 34 is a p-type semiconductor region. The guard ring region 34 is disposed between the drift region 27 and the first surface F1. The guard ring region 34 sandwiches the drift region 27 between itself and the p-region 35 on the end back side.

[0169] The depth of the guard ring region 34 is greater than the depth of the anode region 32. Furthermore, the depth of the guard ring region 34 is preferably greater than the depth of the first set of trenches 21. Additionally, the depth of the guard ring region 34 is preferably greater than the depth of the second set of trenches 22.

[0170] The guard ring region 34 surrounds the transistor region 101 and the diode region 102. The guard ring region 34 is formed in a ring shape on the first surface F1. The guard ring region 34 has the function of mitigating the intensity of the electric field applied to the ends of the pn junctions of the transistor region 101 and the diode region 102.

[0171] Furthermore, the guard ring region 34 becomes a source of holes when the parasitic diode is in the on state.

[0172] For example, an annular p-shaped region can be further provided as a protective ring outside the protective ring region 34 of the end region 103 in a manner that surrounds the protective ring region 34.

[0173] The concentration of p-type impurities in the guard ring region 34 is, for example, higher than the concentration of p-type impurities in the anode region 32. The concentration of p-type impurities in the guard ring region 34 is, for example, more than 5 times and less than 100 times the concentration of p-type impurities in the anode region 32.

[0174] An interlayer insulating layer 60 is disposed between the semiconductor layer 10 and the upper electrode 12. For example, the interlayer insulating layer 60 is disposed between the guard ring region 34 and the upper electrode 12.

[0175] Next, the function and effects of the semiconductor device in the first embodiment will be explained.

[0176] Figure 10 This is a schematic cross-sectional view of a portion of a comparative example semiconductor device. Figure 10 It is the same as the first embodiment. Figure 7 The corresponding diagram.

[0177] The comparative example semiconductor device is an RC-IGBT 900, which forms an IGBT and a freewheeling diode on the same semiconductor chip. The RC-IGBT 900 of the comparative example differs from the RC-IGBT 100 of the first embodiment in that, in the end region, the minimum distance in the second direction between any two adjacent trenches in the second set of trenches is approximately the same, and the trenches in the second set are not physically connected to each other.

[0178] like Figure 10 As shown, in the end region 103, the minimum distance in the second direction between any two adjacent trenches in the first group of trenches 21 is approximately the same. In other words, in the end region 103, the first group of trenches 21 are arranged at approximately equal intervals in the second direction.

[0179] Furthermore, in the end region 103, the second set of trenches 22 are not physically connected to each other. The second set of trenches 22 are independent.

[0180] Figure 11 and Figure 12 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 11 and Figure 12 This is a diagram showing the current flow in diode region 102 of the comparative example RC-IGBT 900 when the diode is in the on state. Figure 11 Is with Figure 10 The corresponding diagram. Figure 12 yes Figure 10 The EE' section.

[0181] exist Figure 11 and Figure 12 In the diagram, arrows represent the flow of electric current.

[0182] like Figure 11 As shown, when the diode in diode region 102 is in the conducting state, current flows from anode region 32 toward guard ring region 34. Current flows from diode contact CD through the first set of trenches 21 to guard ring region 34.

[0183] like Figure 12 As shown, the current flowing into the guard ring region 34 further flows into the drift region 27. In other words, holes are injected into the drift region 27. In other words, when the diode in the diode region 102 is in a conducting state, the parasitic diode in the terminal region 103 also becomes conducting, injecting holes from the guard ring region 34 into the drift region 27. Therefore, in the drift region 27 near the terminal region 103, holes become excessive.

[0184] In the drift region 27 near the end region 103 of diode region 102, holes are in excess, thus delaying the discharge of holes to the upper electrode 12. Consequently, the reverse recovery current (Irr) during reverse recovery of the diode increases, and the reverse recovery loss (Err) of the diode increases.

[0185] For example, when carriers accumulated in the drift region 27 of the terminal region during the on-state are discharged to the emitter or anode electrode during the off-state, current may concentrate in the guard ring region. In this case, the p-type impurity concentration in the guard ring region is increased to mitigate current concentration. Therefore, when the diode in diode region 102 is in the on-state, the amount of hole injected in the drift region 27 near the terminal region 103 connected to diode region 102 further increases, resulting in a further hole excess. Consequently, the reverse recovery loss (Err) of the diode further increases.

[0186] Figure 13 , Figure 14 as well as Figure 15 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 13 , Figure 14 and Figure 15 This is a diagram showing the current flow when the diode in diode region 102 of the RC-IGBT 100 of the first embodiment is in the on state. Figure 13 Is with Figure 7 The corresponding diagram. Figure 14 Is with Figure 8 The corresponding diagram. Figure 15 Is with Figure 9 The corresponding diagram.

[0187] exist Figure 13 , Figure 14 as well as Figure 15 In the diagram, arrows represent the flow of electric current.

[0188] according to Figure 13 as well as Figure 14 It is known that when the diode is in the conducting state, the current flowing from the anode region 32 toward the guard ring region 34 between the two trenches 21 of the first group physically connected in the terminal region 103, such as trench B 21b and trench C 21c, is interrupted by the first group of trenches 21. By setting the depth of the guard ring region 34 to the same level as the depth of the first group of trenches 21, the diffusion layer is completely cut off by the trenches, thus increasing the current interruption effect. However, even if the depth of the guard ring region 34 is deeper than the depth of the first group of trenches 21, since the impurity concentration in the guard ring region 34 decreases from the surface to the bottom, the bottom of the guard ring region 34 becomes a high resistance even if the guard ring region 34 is not completely cut off by the trenches, thereby achieving the current interruption effect. Therefore, as Figure 14 As shown, in particular, the number of holes injected from the protective ring region 34, which is located on the outer side of the first set of grooves 21, into the drift region 27 is reduced compared to the RC-IGBT 900 of the comparative example.

[0189] In addition, from Figure 13 and Figure 15 It can be seen that when the diode is in the conducting state, the current flowing from the anode region 32 toward the guard ring region 34 between two adjacent, unconnected trenches 21, such as trench C 21c and trench D 21d, increases in resistance due to the narrowing of the space between trench C 21c and trench D 21d, thus reducing the current flow compared to the RC-IGBT 900 of the comparative example. Therefore, the number of holes injected from the guard ring region 34 into the drift region 27 is reduced compared to the RC-IGBT 900 of the comparative example.

[0190] When the diode is in the on state, the number of holes injected from the guard ring region 34 to the drift region 27 decreases, thereby reducing the reverse recovery current (Irr) during reverse recovery and decreasing the reverse recovery loss (Err). Therefore, according to the first embodiment, the reverse recovery loss (Err) of the RC-IGBT 100 is reduced.

[0191] In the RC-IGBT 100, the first minimum distance d1 is preferably less than half of the second minimum distance d2, more preferably less than one-third, and even more preferably less than one-fifth. The resistance between the two trenches 21 of the first group is further increased, the holes injected from the guard ring region 34 to the drift region 27 are further reduced, and the reverse recovery loss (Err) of the RC-IGBT 100 is further reduced.

[0192] In the RC-IGBT 100, the distance in the second direction between the C-groove 21c and the D-groove 21d in the end region 103 is the length in the first direction of the portion below the second minimum distance d2. Figure 7 The distance L in the first group is preferably longer than the second minimum distance d2, more preferably more than twice the second minimum distance d2, further preferably more than five times, and most preferably more than ten times. The resistance between the two trenches 21 in the first group is further increased, the holes injected from the guard ring region 34 to the drift region 27 are further reduced, and the reverse recovery loss (Err) of the RC-IGBT 100 is further reduced.

[0193] The distance in the first direction between the protective ring region 34 and the cathode region 31 ( Figure 8The distance d3 in the first direction between the guard ring region 34 and the cathode region 31 is preferably 100 μm or more. As the distance d3 between the guard ring region 34 and the cathode region 31 increases, the number of holes injected from the guard ring region 34 into the drift region 27 is further reduced, and the reverse recovery loss (Err) of the RC-IGBT 100 is further reduced.

[0194] (First variation)

[0195] The semiconductor device of the first variant of the first embodiment differs from the semiconductor device of the first embodiment in that the first group of trenches further includes a fifth trench and a sixth trench, the fifth trench being disposed between the first group of trenches and the second trench, and the sixth trench being disposed between the third trench and the fourth trench.

[0196] The semiconductor device in the first variation of the first embodiment is an RC-IGBT 110.

[0197] Figure 16 This is a schematic cross-sectional view of a semiconductor device in a first variation of the first embodiment. Figure 16 It is the same as the first embodiment. Figure 7 The corresponding diagram.

[0198] Groove B 21b is an example of the first groove. Groove D 21d is an example of the second groove. Groove E 21e is an example of the third groove. Groove G 21g is an example of the fourth groove. Groove C 21c is an example of the fifth groove. Groove F 21f is an example of the sixth groove.

[0199] Grooves B 21b and D 21d are physically connected in end region 103. Grooves E 21e and G 21g are physically connected in end region 103. Grooves D 21d and E 21e are adjacent in the second direction.

[0200] Groove C 21c is disposed between groove B 21b and groove D 21d. Groove F 21f is disposed between groove E 21e and groove G 21g.

[0201] The first minimum distance in the second direction between the D-groove 21d and the E-groove 21e in the end region 103 ( Figure 16 In the diode region 102, d1) is less than the second minimum distance in the second direction between the D trench 21d and the E trench 21e. Figure 16 (d2 in the middle).

[0202] Furthermore, for example, the distance in the second direction between the D groove 21d and the E groove 21e in the end region 103 is the length in the first direction of the portion below the second minimum distance d2. Figure 16 L) is longer than the second minimum distance d2 and is less than 100 times the second minimum distance d2.

[0203] Figure 17 This is an explanatory diagram illustrating the function and effect of the semiconductor device in the first variation of the first embodiment. Figure 17 This is a diagram showing the current flow in the diode region 102 of the RC-IGBT 110 of the first embodiment when the diode is in the on state. Figure 17 It is the same as the first embodiment. Figure 13 The corresponding diagram.

[0204] exist Figure 17 In the diagram, arrows represent the flow of electric current.

[0205] Depend on Figure 17 It can be seen that when the diode is in the conducting state, the proportion of the current flowing from the anode region 32 to the guard ring region 34 that is interrupted by the physically connected first set of trenches 21 increases. Furthermore, the number of paths between adjacent, unconnected first set of trenches 21 also decreases. Therefore, the current flowing from the anode region 32 to the guard ring region 34 is further reduced.

[0206] Therefore, the number of holes injected from the guard ring region 34 to the drift region 27 is further reduced. Consequently, the reverse recovery loss (Err) of the RC-IGBT 110 is further reduced.

[0207] According to a first variation of the first embodiment, similar to the first embodiment, the reverse recovery loss (Err) of the RC-IGBT is reduced.

[0208] (Second variation)

[0209] The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first modification of the first embodiment in that the first group of trenches further includes a seventh trench and an eighth trench, the seventh trench being disposed between the fifth trench and the second trench, and the eighth trench being disposed between the sixth trench and the fourth trench.

[0210] The semiconductor device in the second variation of the first embodiment is an RC-IGBT 120.

[0211] Figure 18 This is a schematic cross-sectional view of a semiconductor device in a second variation of the first embodiment. Figure 18 It is the same as the first embodiment. Figure 7 The corresponding diagram.

[0212] Groove B 21b is an example of the first groove. Groove E 21e is an example of the second groove. Groove F 21f is an example of the third groove. Groove I 21i is an example of the fourth groove. Groove C 21c is an example of the fifth groove. Groove G 21g is an example of the sixth groove. Groove D 21d is an example of the seventh groove. Groove H 21h is an example of the eighth groove.

[0213] Grooves B 21b and E 21e are physically connected in the end region 103. Grooves F 21f and I 21i are physically connected in the end region 103. Grooves E 21e and F 21f are adjacent in the second direction.

[0214] Groove C 21c is located between groove B 21b and groove E 21e. Groove G 21g is located between groove F 21f and groove I 21i.

[0215] D-groove 21d is located between C-groove 21c and E-groove 21e. H-groove 21h is located between G-groove 21g and I-groove 21i.

[0216] The first minimum distance in the second direction between the E trench 21e and the F trench 21f in the end region 103 ( Figure 18 d1) is less than the second minimum distance in the second direction between the E trench 21e and the F trench 21f in diode region 102. Figure 18 (d2 in the middle).

[0217] Furthermore, for example, the distance in the second direction between the E-groove 21e and the F-groove 21f in the end region 103 is the length in the first direction of the portion below the second minimum distance d2. Figure 18 L) is longer than the second minimum distance d2 and is less than 100 times the second minimum distance d2.

[0218] Figure 19 This is an explanatory diagram illustrating the operation and effects of the semiconductor device in the second variation of the first embodiment. Figure 19 This is a diagram showing the current flow in the diode region 102 of the RC-IGBT 120 of the second variation of the first embodiment when the diode is in the on state. Figure 19 It is the same as the first embodiment. Figure 13 The corresponding diagram.

[0219] exist Figure 19 In the diagram, arrows represent the flow of electric current.

[0220] Depend on Figure 19It can be seen that when the diode is in the conducting state, the proportion of the current flowing from the anode region 32 to the guard ring region 34 that is interrupted by the physically connected first set of trenches 21 further increases. Furthermore, the number of paths between adjacent, unconnected first set of trenches 21 is further reduced. Therefore, the current flowing from the anode region 32 to the guard ring region 34 is further reduced.

[0221] Therefore, the number of holes injected from the guard ring region 34 to the drift region 27 is further reduced. Consequently, the reverse recovery loss (Err) of the RC-IGBT 120 is further reduced.

[0222] According to a second variation of the first embodiment, similar to the first embodiment, the reverse recovery loss (Err) of the RC-IGBT is reduced.

[0223] Based on the first embodiment and its variations, a semiconductor device comprising an RC-IGBT having an IGBT and a diode can be realized, which can improve its characteristics by reducing reverse recovery loss (Err).

[0224] (Second Implementation)

[0225] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that the fourth semiconductor region includes a first region and a second region, the second region being disposed between the first region and the third semiconductor region, and the concentration of the second conductivity type impurity is lower than that of the first region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0226] The semiconductor device in the second embodiment is an RC-IGBT 200 in which the IGBT and the freewheeling diode are formed on the same semiconductor chip.

[0227] Figure 20 This is a schematic top view of a part of the semiconductor device according to the second embodiment. Figure 20 It is the same as the first embodiment. Figure 7 The corresponding diagram.

[0228] Figure 21 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. Figure 21 It is a schematic cross-sectional view of the boundary between the diode region and the terminal region. Figure 21 yes Figure 20 The FF' section.

[0229] Figure 22 This is a schematic cross-sectional view of a part of the semiconductor device according to the second embodiment. Figure 22 It is a schematic cross-sectional view of the boundary between the diode region and the terminal region. Figure 22 yes Figure 20 The GG' section.

[0230] The guard ring region 34 (fourth semiconductor region) includes a high-concentration region 34a (first region) and a low-concentration region 34b (second region).

[0231] The low-concentration region 34b is positioned between the high-concentration region 34a and the anode region 32 (the third semiconductor region).

[0232] The concentration of p-type impurities in the low-concentration region 34b is lower than that in the high-concentration region 34a. For example, the concentration of p-type impurities in the low-concentration region 34b is more than one-tenth and less than one-half of the concentration of p-type impurities in the high-concentration region 34a.

[0233] The concentration of p-type impurities in the high-concentration region 34a is, for example, higher than the concentration of p-type impurities in the anode region 32. The concentration of p-type impurities in the low-concentration region 34b is, for example, higher than the concentration of p-type impurities in the anode region 32.

[0234] In the second embodiment of the RC-IGBT 200, by providing a low-concentration region 34b between the high-concentration region 34a and the anode region 32 (the third semiconductor region), the resistance of the path from the anode region 32 to the guard ring region 34 increases when the diode is in the on-state. Therefore, the current flowing from the anode region 32 to the guard ring region 34 is further reduced compared to the first embodiment of the RC-IGBT 100.

[0235] Therefore, the number of holes injected from the guard ring region 34 to the drift region 27 is further reduced. Consequently, the reverse recovery loss (Err) of the RC-IGBT 200 is further reduced.

[0236] The concentration of p-type impurities in the low-concentration region 34b is preferably less than half the concentration of p-type impurities in the high-concentration region 34a, and more preferably less than one-fifth. Because the resistance of the path from the anode region 32 to the guard ring region 34 increases, the current flowing from the anode region 32 to the guard ring region 34 is further reduced.

[0237] According to the second embodiment, a semiconductor device comprising an RC-IGBT having an IGBT and a diode, whose characteristics can be improved by reducing reverse recovery loss (Err), can be realized.

[0238] In the first and second embodiments, the case where the semiconductor layer is monocrystalline silicon was described as an example, but the semiconductor layer is not limited to monocrystalline silicon. For example, it could also be other monocrystalline semiconductors such as monocrystalline silicon carbide.

[0239] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type is used as an example for explanation, but the first conductivity type can also be set to p-type and the second conductivity type to n-type.

[0240] The layout pattern in the end region of the second set of trenches included in the transistor region is not necessarily limited to that in the first embodiment. Figure 4 The pattern shown. For example, it is also possible to physically connect a portion of the second set of trenches in the end region.

[0241] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: transistor region; Diode region; and The end region surrounding the transistor region and the diode region. The diode region includes: A semiconductor layer having a first side and a second side facing the first side; A first semiconductor region of a first conductivity type is disposed within the semiconductor layer; A second semiconductor region of a first conductivity type is disposed within the semiconductor layer and between the first semiconductor region and the first surface, wherein the first conductivity type impurity concentration of the second semiconductor region is lower than that of the first conductivity type impurity concentration of the first semiconductor region. A third semiconductor region of a second conductivity type is disposed within the semiconductor layer and between the second semiconductor region and the first surface; The first set of trenches is disposed on one side of the first surface in the semiconductor layer and extends in a first direction parallel to the first surface. The first set of trenches is arranged in a second direction parallel to the first surface and perpendicular to the first direction and is connected to the second semiconductor region and the third semiconductor region. The first electrode is electrically connected to the third semiconductor region; as well as The second electrode is connected to the first semiconductor region. The terminal region includes: The semiconductor layer; The second semiconductor region; A fourth semiconductor region of the second conductivity type is disposed in the semiconductor layer and between the second semiconductor region and the first surface, and is electrically connected to the first electrode. The depth of the fourth semiconductor region is greater than the depth of the third semiconductor region. The trenches in the first group; as well as The second electrode, The first group of grooves includes a first groove, a second groove, a third groove, and a fourth groove. The first trench and the second trench are physically connected in the end region. The third and fourth grooves are physically connected in the end region. The second trench and the third trench are adjacent in the second direction. The first minimum distance in the second direction between the second trench and the third trench in the terminal region is less than the second minimum distance in the second direction between the second trench and the third trench in the diode region.

2. The semiconductor device according to claim 1, characterized in that, The first minimum distance is less than half of the second minimum distance.

3. The semiconductor device according to claim 1, characterized in that, The first group of grooves also includes a fifth groove and a sixth groove. The fifth groove is disposed between the first groove and the second groove. The sixth groove is disposed between the third groove and the fourth groove.

4. The semiconductor device according to claim 3, characterized in that, The first group of grooves also includes a seventh groove and an eighth groove. The seventh groove is disposed between the fifth groove and the second groove. The eighth groove is disposed between the sixth groove and the fourth groove.

5. The semiconductor device according to claim 1, characterized in that, The concentration of the second conductivity type impurity in the fourth semiconductor region is higher than that in the third semiconductor region.

6. The semiconductor device according to claim 1, characterized in that, The fourth semiconductor region includes a first region and a second region. The second region is disposed between the first region and the third semiconductor region, and the second conductivity type impurity concentration in the second region is lower than that in the first region.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor layer in the terminal region further comprises a fifth semiconductor region of a second conductivity type, which is disposed between the second semiconductor region and the second surface and is connected to the second electrode.

8. The semiconductor device according to claim 7, characterized in that, The boundary between the fifth semiconductor region and the first semiconductor region exists within the diode region, and the distance between the fourth semiconductor region and the first semiconductor region in the first direction is greater than 100 μm.

9. The semiconductor device according to claim 1, characterized in that, The distance in the second direction between the second groove and the third groove in the end region is the portion below the second minimum distance whose length in the first direction is longer than the second minimum distance.

10. The semiconductor device according to claim 1, characterized in that, The transistor region includes: The semiconductor layer; The second semiconductor region; A sixth semiconductor region of the second conductivity type is disposed in the semiconductor layer and between the second semiconductor region and the second surface; A seventh semiconductor region of the second conductivity type is disposed in the semiconductor layer and between the second semiconductor region and the first surface; An eighth semiconductor region of a first conductivity type is disposed in the semiconductor layer and between the seventh semiconductor region and the first surface. The second set of trenches is disposed on one side of the first surface in the semiconductor layer and extends in the first direction. More than 10 trenches are repeatedly arranged in the second direction and are connected to the second semiconductor region, the seventh semiconductor region and the eighth semiconductor region. The first electrode connected to the eighth semiconductor region; as well as The second electrode connected to the sixth semiconductor region, The end region also includes the trenches of the second group. In the terminal region, the minimum distance in the second direction between any two adjacent trenches in the second group is approximately the same. The trenches in the second group are not physically connected to each other.

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