Processing method of embedded package substrate and embedded package substrate

Abstract

The application discloses a processing method of an embedded packaging substrate and the embedded packaging substrate, and relates to the technical field of packaging substrates. The processing method comprises the following steps: providing a carrier substrate; manufacturing a first circuit layer on the surface of the carrier substrate, wherein the first circuit layer comprises an FC pad; obtaining a second substrate; arranging a first laminated insulating adhesive film on one side of the second substrate with the first circuit layer; performing exposure, development and curing on the first laminated insulating adhesive film to form a first blind groove, wherein the first blind groove corresponds to the position of the FC pad; manufacturing a second circuit layer on one side of the second substrate with the first laminated insulating adhesive film; arranging a second laminated insulating adhesive film on one side of the second substrate with the second circuit layer; and performing exposure, development and curing on the second laminated insulating adhesive film to form a second blind groove, wherein the second blind groove corresponds to the position of the first blind groove. The application aims at solving the problems of low production efficiency, high cost and carbon residue on the edge of the pad caused by the laser process for manufacturing the blind groove in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of packaging substrate technology, and particularly relates to a processing method for an embedded packaging substrate and an embedded packaging substrate. Background Technology

[0002] Chip stacking packaging technology is widely used in electronic devices such as smartphones and wearable devices where internal space requirements are high. To achieve chip stacking packaging, the packaging substrate generally adopts a blind slot structure. This is achieved by first creating the pads at the bottom of the slot, and then using a laser process to create the blind slot.

[0003] While existing technologies can create blind trenches using laser processes, deeper blind trenches can lead to reduced production efficiency, increased costs, and residual carbides at the pad edges. For example, when processing deeper blind trenches, laser equipment requires a significant amount of time for burning the trench, resulting in lower production efficiency and increased laser costs. Furthermore, the high temperatures generated during laser cutting can easily cause residual carbides at the bottom pad edges, affecting the soldering yield and electrical conduction efficiency of subsequent packaging. Summary of the Invention

[0004] The purpose of this application is to provide a processing method for an embedded packaging substrate and an embedded packaging substrate, so as to solve the problems of reduced production efficiency, increased cost and residual carbides on the edge of the pads caused by the use of laser technology to create blind slots in the prior art.

[0005] To solve the above-mentioned technical problems, this application adopts the following technical solution:

[0006] In a first aspect, this application provides a method for processing an embedded packaging substrate, comprising:

[0007] A carrier substrate is provided, the carrier substrate including a carrier plate, a first carrier copper foil disposed on the surface of the carrier plate, and a first ultrathin copper foil disposed on the surface of the first carrier copper foil;

[0008] A first circuit layer is fabricated on the surface of a carrier substrate, the first circuit layer including FC pads;

[0009] A dielectric layer and a copper foil layer are laminated onto the surface of a carrier substrate to obtain a first substrate;

[0010] The first carrier copper foil and the first ultrathin copper foil are peeled off, and the first carrier copper foil and the carrier plate are removed to obtain the second substrate;

[0011] A first laminated insulating film is disposed on one side of the second substrate having a first circuit layer;

[0012] The first layer of insulating film is exposed, developed and cured to form the first blind trench, which corresponds to the position of the FC pad.

[0013] A second circuit layer is formed on the side of the second substrate having the first laminated insulating film, the second circuit layer including wire bonding pads;

[0014] A second laminated insulating film is disposed on one side of the second substrate having a second circuit layer;

[0015] The second laminated insulating film is exposed, developed, and cured to form a second blind groove. The second blind groove corresponds to the position of the first blind groove and is connected to the first blind groove.

[0016] Furthermore, a first circuit layer is fabricated on the surface of the carrier substrate, specifically including:

[0017] A first dry film is formed on the surface of a carrier substrate;

[0018] The first dry film is exposed and developed to form the first line opening;

[0019] Electroplating is performed on the carrier substrate to form a first circuit layer at the first circuit opening;

[0020] Remove the first dry film.

[0021] Furthermore, after peeling off the first carrier copper foil and the first ultrathin copper foil, removing the first carrier copper foil and the carrier plate to obtain the second substrate, the process further includes:

[0022] A second dry film is disposed on the side of the second substrate having the first ultrathin copper foil;

[0023] The second dry film is exposed and developed to form a first pattern corresponding to the FC pads;

[0024] The developed second substrate is flash-etched to retain the first ultrathin copper foil covered by the first pattern.

[0025] Remove the second dry film.

[0026] Furthermore, a second circuit layer is formed on the side of the second substrate having the first laminated insulating film, specifically including:

[0027] A third dry film is disposed on the side of the second substrate having the first laminated insulating film;

[0028] The third dry film is exposed and developed to form the second circuit opening;

[0029] Electroplating is performed on the second substrate to form a second circuit layer at the opening of the second circuit;

[0030] Remove the third dry film.

[0031] Furthermore, after removing the third dry film, the process also includes:

[0032] The second substrate is flash-etched to remove the first ultrathin copper foil located on the FC pad, thereby exposing the FC pad.

[0033] Furthermore, after exposing, developing, and curing the second laminated insulating film to form the second blind groove, the process also includes:

[0034] A fourth dry film is disposed on one side of the second substrate having a second laminated insulating adhesive film, and a fifth dry film is disposed on the other side;

[0035] The fourth and fifth dry films are exposed and developed to form the third and fourth line openings;

[0036] Electroplating is performed on the second substrate to form a third circuit layer at the third circuit opening and a fourth circuit layer at the fourth circuit opening;

[0037] Remove the fourth and fifth dry films.

[0038] Furthermore, after removing the fourth and fifth dry films, the process also includes:

[0039] Ink is printed on the surface of the second substrate and pre-cured to obtain an ink layer;

[0040] The ink layer is exposed using solder resist exposure material;

[0041] The ink layer is developed and cured to form a solder resist ink layer.

[0042] Furthermore, it also includes:

[0043] A flip chip is placed in the first blind slot, with the active side of the flip chip facing the FC pad and electrically connected to the FC pad;

[0044] A stacked chip is placed in the second blind slot. The stacked chip is fixed to the back of the flip chip and is electrically connected to the wire bonding pad.

[0045] Furthermore, it also includes:

[0046] Molding material is filled into the first and second blind grooves to form a plastic-sealed structure;

[0047] The second substrate is baked and cured to obtain the encapsulation substrate.

[0048] Secondly, this application also provides an embedded packaging substrate, which is manufactured by the embedded packaging substrate processing method described in any of the preceding claims.

[0049] Beneficial effects:

[0050] The technical solution of this application replaces the original laser process by performing exposure, development, and curing on a multilayer insulating film. This effectively improves the fabrication efficiency of blind trenches and reduces costs, while avoiding the problem of residual carbides at the edges of the bottom pads, thus ensuring the soldering yield and electrical transmission efficiency of chip stacking packages. Specifically, after forming a second substrate with FC pads, a first multilayer insulating film is deposited on the surface. This film is then exposed, developed, and cured to form a first blind trench corresponding to the FC pads. A second blind trench is formed using the same process. When a deeper blind trench structure is required, laser processing is no longer necessary. The blind trench can be fabricated simply by exposing, developing, and curing the multilayer insulating film, effectively avoiding the low production efficiency and high cost associated with laser processing. It also avoids the potential hazards caused by residual carbides at the edges of the bottom pads due to high-temperature laser cutting. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a flowchart of a method for processing an embedded packaging substrate provided in this application;

[0053] Figure 2 This is a schematic diagram of the first structure corresponding to the processing method of an embedded packaging substrate provided in this application;

[0054] Figure 3 This is a second structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0055] Figure 4 This is a third structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0056] Figure 5 This is a fourth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0057] Figure 6 This is a fifth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0058] Figure 7 This is a sixth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0059] Figure 8This is a schematic diagram of the seventh structure corresponding to the processing method of an embedded packaging substrate provided in this application;

[0060] Figure 9 This is the eighth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0061] Figure 10 This is a schematic diagram of the ninth structure corresponding to the processing method of an embedded packaging substrate provided in this application;

[0062] Figure 11 This is a schematic diagram of the tenth structure corresponding to the processing method of an embedded packaging substrate provided in this application;

[0063] Figure 12 This is the eleventh structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0064] Figure 13 This is a schematic diagram of the twelfth structure corresponding to the processing method of an embedded packaging substrate provided in this application;

[0065] Figure 14 This is the thirteenth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0066] Figure 15 This is the fourteenth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0067] Figure 16 This is the fifteenth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0068] Figure 17 This is the sixteenth structural schematic diagram corresponding to the processing method of an embedded packaging substrate provided in this application;

[0069] Explanation of reference numerals in the attached figures:

[0070] 1. Carrier substrate; 2. Carrier board; 3. First carrier copper foil; 4. First ultra-thin copper foil; 5. First circuit layer; 6. FC pad; 7. Dielectric layer; 8. Copper foil layer; 9. Second ultra-thin copper foil; 10. Second carrier copper foil; 11. First substrate; 12. Second substrate; 13. Barrier layer; 14. First laminated insulating film; 15. First blind trench; 16. First via; 17. Second circuit layer; 18. Wire bonding pad; 19. Second laminated insulating film; 20. Second blind trench; 21. Second via; 22. Third via; 23. Third circuit layer; 24. Fourth circuit layer; 25. Solder resist layer; 26. Surface treatment layer; 27. Flip chip; 28. Stacked chip; 29. ​​Gold wire; 30. Molding structure; 31. Packaging substrate. Detailed Implementation

[0071] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use.

[0072] Example 1:

[0073] This embodiment provides a method for processing an embedded packaging substrate. For example... Figure 1 As shown, Figure 1 This is a flowchart of a method for fabricating an embedded packaging substrate. This flowchart only illustrates the logical sequence of the methods described in this embodiment. Without conflict, in other possible embodiments of the invention, different methods may be used. Figure 1 Complete the steps shown or described in the order indicated.

[0074] The embedded packaging substrate processing method provided in this embodiment includes the following steps:

[0075] S100: Provide a carrier substrate 1, the carrier substrate 1 includes a carrier plate 2, a first carrier copper foil 3 disposed on the surface of the carrier plate 2, and a first ultrathin copper foil 4 disposed on the surface of the first carrier copper foil 3;

[0076] Specifically, such as Figure 2 As shown, the carrier substrate 1 includes a carrier plate 2, a first carrier copper foil 3 disposed on the surface of the carrier plate 2, and a first ultrathin copper foil 4 disposed on the surface of the first carrier copper foil 3. The first carrier copper foil 3 and the first ultrathin copper foil 4 are peelable from each other. It should be noted that the first carrier copper foil 3 and the first ultrathin copper foil 4 can be disposed on the upper surface, lower surface, or both surfaces of the carrier plate 2. When the first carrier copper foil 3 and the first ultrathin copper foil 4 are disposed on both the upper and lower surfaces of the carrier plate 2, two second substrates 12 can be fabricated simultaneously. In this embodiment, the first carrier copper foil 3 and the first ultrathin copper foil 4 are disposed on both the upper and lower surfaces of the carrier plate 2. The thickness of the first carrier copper foil 3 is 17±2μm, and the thickness of the first ultrathin copper foil 4 is 3±0.3μm.

[0077] Specifically, the carrier substrate 1 is placed in an oven and baked at a temperature of 185-195℃ for 4 hours ± 15 minutes. Baking eliminates stress on the carrier substrate 1, improves warping, and ensures dimensional stability.

[0078] S200: A first circuit layer 5 is formed on the surface of the carrier substrate 1. The first circuit layer 5 includes FC pads 6.

[0079] Furthermore, S200 specifically includes the following steps:

[0080] S210: A first dry film is formed on the surface of the carrier substrate 1;

[0081] S220: Expose and develop the first dry film to form the first line opening;

[0082] S230: Electroplating is performed on the carrier substrate 1 to form a first circuit layer 5 at the first circuit opening;

[0083] S240: Remove the first dry film.

[0084] Specifically, such as Figure 3 As shown, before S210, the surface of the carrier substrate 1 is acid-washed to remove foreign matter. Then, a first dry film is laminated onto the upper and lower surfaces of the carrier substrate 1. Using first circuit data and first circuit mirror data, the first dry film is exposed and developed at an exposure energy of 60±10mJ to obtain the first circuit opening. Copper is electroplated to thicken the upper and lower surfaces of the carrier substrate 1. The first dry film is removed using a film-removing solution to obtain a carrier substrate 1 with a first circuit layer 5 on both the upper and lower surfaces. The first circuit layer 5 includes FC pads 6, which are used for electrical connection with the flip chip 27.

[0085] S300: A dielectric layer 7 and a copper foil layer 8 are laminated onto the surface of a carrier substrate 1 to obtain a first substrate 11;

[0086] Specifically, such as Figure 4 As shown, the carrier substrate 1 with the first circuit layer 5 on the upper and lower surfaces is browned to form a certain roughness, which is beneficial to the bonding between the carrier substrate 1 and the dielectric layer 7. The dielectric layer 7 and the copper foil layer 8 are stacked on the upper and lower surfaces of the carrier substrate 1, and the carrier substrate 1, the dielectric layer 7 and the copper foil layer 8 are pressed together under high temperature and high pressure to obtain the first substrate 11.

[0087] It should be noted that the dielectric layer 7 is a prepreg, and the copper foil layer 8 includes a second carrier copper foil 10 and a second ultrathin copper foil 9. The second ultrathin copper foil 9 is disposed on the surface of the dielectric layer 7, and the second carrier copper foil 10 is disposed on the surface of the second ultrathin copper foil 9. The second carrier copper foil 10 and the second ultrathin copper foil 9 can be peeled off from each other.

[0088] S400: Peel off the first carrier copper foil 3 and the first ultrathin copper foil 4, remove the first carrier copper foil 3 and the carrier plate 2, and obtain the second substrate 12;

[0089] Specifically, such as Figure 5 As shown, the first substrate 11 after lamination is mechanically peeled off along the contact surface of the first carrier copper foil 3 and the first ultrathin copper foil 4, and then the first carrier copper foil 3 and the carrier plate 2 are removed to obtain two identical second substrates 12.

[0090] Furthermore, the S400 then includes the following steps:

[0091] S410: A second dry film is disposed on the side of the second substrate 12 having the first ultrathin copper foil 4;

[0092] S420: Expose and develop the second dry film to form a first pattern corresponding to FC pad 6;

[0093] S430: Flash etching is performed on the developed second substrate 12 to retain the first ultrathin copper foil 4 covered by the first pattern;

[0094] S440: Remove the second dry film.

[0095] Specifically, such as Figure 6 As shown, before S410, the upper and lower surfaces of the second substrate 12 are acid-washed to remove surface foreign matter. Then, a second dry film is formed on the side of the second substrate 12 with the first ultrathin copper foil 4, and a second dry film is also formed on the other side of the second substrate 12 to protect it. The second dry film formed on the side with the first ultrathin copper foil 4 is exposed using first pattern data at an exposure energy of 60±10 mJ; the second dry film formed on the other side is exposed using full data exposure, ensuring that the entire second dry film on the other side is retained. The unexposed portions of the second dry film are removed using a developing solution to obtain a first pattern, which corresponds to the area of ​​the FC pad 6. Then, the second substrate 12 is flash-etched, retaining the area of ​​the first ultrathin copper foil 4 covered by the first pattern and removing the uncovered area. The second dry film is then removed using a stripping solution. The first ultrathin copper foil 4 corresponding to the FC pad 6 area acts as a barrier layer 13, protecting the FC pad 6.

[0096] S500: A first laminated insulating film 14 is provided on the side of the second substrate 12 having the first circuit layer 5;

[0097] Specifically, before S500, the surface of the second substrate 12 is browned to form a certain roughness, which is beneficial to interlayer bonding. Then, a first laminated insulating film 14 is formed on the side of the second substrate 12 with the first circuit layer 5. Then, heating and pressurization are performed in a vacuum chamber, and airbags are used to apply pressure evenly to eliminate air bubbles between the second substrate 12 and the first laminated insulating film 14, so that the first laminated insulating film 14 is tightly bonded to the second substrate 12.

[0098] S600: Expose, develop and cure the first laminated insulating film 14 to form a first blind groove 15, the first blind groove 15 corresponding to the position of the FC pad 6;

[0099] Specifically, such as Figure 7As shown, the first laminated insulating film 14 is selectively exposed using the first blind trench data to expose the first blind trench pattern. The exposure energy is 70±10 mJ, and the depth of the first blind trench 15 is 20~120 μm. Then, the first laminated insulating film 14 is selectively exposed using the first via data to expose the first via pattern. The exposure energy is 30±10 mJ. The unexposed portions of the first laminated insulating film are then removed using a developing solution and cured to obtain the first blind trench 15 and the first via 16.

[0100] S700: A second circuit layer 17 is formed on the side of the second substrate 12 having a first laminated insulating film 14. The second circuit layer 17 includes wire bonding pads 18.

[0101] Furthermore, the S700 specifically includes the following steps:

[0102] S710: A third dry film is disposed on the side of the second substrate 12 having the first laminated insulating film 14;

[0103] S720: Expose and develop the third dry film to form the second line opening;

[0104] S730: Electroplating is performed on the second substrate 12 to form a second circuit layer 17 at the second circuit opening;

[0105] S740: In the removal of the third dry film.

[0106] Specifically, prior to S710, chemical deposition is performed on the second substrate 12 to form copper foil on the surface of the second substrate 12, the inner wall of the first blind trench 15, and the first via 16, such as... Figure 8 As shown, Figure 8 A schematic diagram showing the formation of copper foil on the surface of the second substrate 12, the inner wall of the first blind trench 15 and the first via 16 for chemical deposition of the second substrate 12.

[0107] The surface of the second substrate 12 is acid-washed to remove surface foreign matter. A third dry film is formed on the side of the second substrate 12 with the first laminated insulating film 14, and a third dry film is also formed on the other side of the second substrate 12 to protect it. The third dry film formed on the side with the first laminated insulating film 14 is exposed using second circuit data with an exposure energy of 60±10mJ; the third dry film formed on the other side is exposed using full data to retain all of the third dry film on the other side. The unexposed portions of the third dry film are removed using a developing solution to obtain the second circuit opening. The surface of the second substrate 12 is thickened by electroplating copper to form a second circuit layer 17 at the second circuit opening. The third dry film is removed using a stripping solution to obtain the second substrate 12 with the second circuit layer 17. The second circuit layer 17 includes wire bonding pads 18 for electrical connection with the stacked chip 28.

[0108] Furthermore, the S740 then includes the following steps:

[0109] S750: Flash etching is performed on the second substrate 12 to remove the first ultrathin copper foil 4 located on the FC pad 6, thereby exposing the FC pad 6.

[0110] Specifically, such as Figure 9 As shown, the surface of the second substrate 12 is flash-etched to remove the copper foil formed by chemical deposition on the surface of the second substrate 12, the inner wall of the first blind trench 15 and the first via 16, and to remove the barrier layer 13 on the FC pad 6, thereby exposing the FC pad 6.

[0111] S800: A second laminated insulating film 19 is provided on the side of the second substrate 12 having a second circuit layer 17;

[0112] Specifically, before S800, the surface of the second substrate 12 is browned to form a certain roughness, which is beneficial to interlayer bonding. Then, a second laminated insulating film 19 is formed on the side of the second substrate 12 with the second circuit layer 17. Then, heating and pressurization are performed in a vacuum chamber, and airbags are used to apply pressure evenly to eliminate air bubbles between the second substrate 12 and the second laminated insulating film 19, so that the second laminated insulating film 19 is tightly bonded to the second substrate 12.

[0113] S900: Expose, develop and cure the second laminated insulating film 19 to form a second blind groove 20. The second blind groove 20 corresponds to the position of the first blind groove 15 and is connected to the first blind groove 15.

[0114] Specifically, such as Figure 10As shown, the second laminated insulating film 19 is selectively exposed using the second blind groove data to expose the second blind groove pattern. The exposure energy is 70±10 mJ, and the depth of the second blind groove 20 is 20~120 μm. Then, the second laminated insulating film 19 is selectively exposed using the second via data to expose the second via pattern. The exposure energy is 30±10 mJ. The unexposed portions of the second laminated insulating film are then removed using a developing solution and cured to obtain the second blind groove 20 and the second via 21.

[0115] Furthermore, the S900 then includes the following steps:

[0116] S910: A fourth dry film is provided on one side of the second substrate 12 where the second laminated insulating film 19 is provided, and a fifth dry film is provided on the other side;

[0117] S920: Expose and develop the fourth and fifth dry films to form the third and fourth line openings;

[0118] S930: Electroplating is performed on the second substrate 12 to form a third line layer 23 at the third line opening and a fourth line layer 24 at the fourth line opening.

[0119] S940: Removes the fourth and fifth dry films.

[0120] Specifically, such as Figure 11 As shown, before S910, mechanical peeling is performed along the contact surface of the second carrier copper foil 10 and the second ultrathin copper foil 9 to remove the second carrier copper foil 10. Then, laser drilling is performed on the side of the second substrate 12 with the second ultrathin copper foil 9 to obtain the third via 22. Chemical deposition is performed on the second substrate 12 to form copper foil on the surface of the second substrate 12, the inner wall of the first blind trench 15, the second blind trench 20, the second via 21, and the third via 22. Figure 12As shown, the surface of the second substrate 12 is acid-washed to remove surface foreign matter. A fourth dry film is formed on one side of the second substrate 12 with the second laminated insulating film 19, and a fifth dry film is formed on the other side of the second substrate 12. The fourth dry film is exposed using third circuit data at an exposure energy of 60±10 mJ; the fifth dry film is also exposed using fourth circuit data at an exposure energy of 60±10 mJ. Unexposed portions of the fourth and fifth dry films are removed using a developing solution, forming third circuit openings on the fourth dry film and fourth circuit openings on the fifth dry film. The surface of the second substrate 12 is thickened by electroplating copper, forming a third circuit layer 23 at the third circuit openings and a fourth circuit layer 24 at the fourth circuit openings. The fourth and fifth dry films are removed using a stripping solution. Then, the second substrate 12 is flash-etched to remove the copper foil formed by chemical deposition on the surface of the second substrate 12, the first blind trench 15, the second blind trench 20, the second via 21 and the inner wall of the third via 22, and to remove the second ultrathin copper foil 9 that is not covered by the fourth circuit layer 24.

[0121] Furthermore, S940, subsequently includes the following steps:

[0122] S950: Ink is printed on the surface of the second substrate 12 and pre-cured to obtain an ink layer;

[0123] S960: Expose the ink layer using solder resist exposure material;

[0124] S970: Develop and cure the ink layer to form a solder resist ink layer 25.

[0125] Specifically, such as Figure 13 As shown, the surface of the second substrate 12 is degreased and micro-etched to remove surface foreign matter and roughen the copper surface of the second substrate 12. Ink is printed on the surface of the second substrate 12, and the printed second substrate 12 is pre-cured to obtain an ink layer. The ink layer is exposed using solder resist exposure data. The unexposed ink layer is removed by developing solution, leaving the photosensitive ink layer. The second substrate 12 is baked and cured to form a solder resist ink layer 25. The solder resist ink layer 25 can prevent the circuit and copper surface from being oxidized, prevent moisture, electrolytes and mechanical external forces from damaging the circuit, and also serve as a solder resist.

[0126] Specifically, such as Figure 14As shown, nickel-palladium-gold plating is applied to the surfaces of the FC pad 6, wire bonding pad 18, third circuit layer 23, and fourth circuit layer 24 on the second substrate 12 to form a surface treatment layer 26. The gold thickness is 0.05-0.015 μm, the nickel thickness is 3-8 μm, and the palladium thickness is 0.05-0.015 μm. The nickel layer in the surface treatment layer 26 serves as the bottom layer, effectively isolating copper from air and moisture, preventing oxidation and corrosion, and extending the PCB's lifespan. The palladium layer, as the intermediate layer, addresses nickel layer corrosion and enhances bonding. The gold layer, as the outer layer, possesses excellent conductivity and chemical stability, and its smooth surface provides good soldering performance, ensuring strong and reliable solder joints and reducing issues such as cold solder joints and false solder joints.

[0127] Specifically, the second substrate 12 is processed to the production dimensions of the packaging substrate 31. The second substrate 12 is then subjected to electrical performance testing and visual inspection.

[0128] Furthermore, the processing method also includes the following steps:

[0129] S1000: A flip chip 27 is disposed in the first blind slot 15, the active surface of the flip chip 27 faces the FC pad 6 and is electrically connected to the FC pad 6.

[0130] Specifically, such as Figure 15 As shown, apply flux to FC pad 6, attach flip chip 27 to FC pad 6 and reflow solder.

[0131] S1100: A stacked chip 28 is disposed in the second blind slot 20. The stacked chip 28 is fixed to the back of the flip chip 27 and is electrically connected to the wire bonding pad 18.

[0132] Specifically, such as Figure 16 As shown, adhesive is applied to the back of the flip chip 27, and the stacked chip 28 is attached to the back of the flip chip 27 and cured by baking. Then, the stacked chip 28 is electrically connected to the wire bonding pad 18 via gold wire 29.

[0133] Furthermore, the processing method also includes the following steps:

[0134] S1200: Molding material is filled into the first blind groove 15 and the second blind groove 20 to form a plastic seal structure 30;

[0135] S1300: The second substrate 12 is baked and cured to obtain the encapsulation substrate 31.

[0136] Specifically, such as Figure 17 As shown, molding material is filled in the first blind slot 15 and the second blind slot 20 to seal the chip, which enhances the airtightness of the packaged chip and ensures the reliability of the product.

[0137] Example 2:

[0138] This embodiment provides an embedded packaging substrate, which is manufactured by the embedded packaging substrate processing method as described in any of the embodiments in Embodiment 1.

[0139] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used to explain the relative positional relationship and movement between components in a specific orientation. If the specific orientation changes, the directional indication will also change accordingly. These terms are used only for the convenience of describing this application and for simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0140] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0141] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0142] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for processing an embedded packaging substrate, characterized in that, include: A carrier substrate is provided, the carrier substrate including a carrier plate, a first carrier copper foil disposed on the surface of the carrier plate, and a first ultrathin copper foil disposed on the surface of the first carrier copper foil; A first circuit layer is formed on the surface of the carrier substrate, the first circuit layer including FC pads; A dielectric layer and a copper foil layer are laminated onto the surface of the carrier substrate to obtain a first substrate; The first carrier copper foil and the first ultrathin copper foil are peeled off, and the first carrier copper foil and the carrier plate are removed to obtain the second substrate. A first laminated insulating film is disposed on one side of the second substrate having a first circuit layer; The first laminated insulating film is exposed, developed and cured to form a first blind trench, the first blind trench corresponding to the position of the FC pad; A second circuit layer is formed on the side of the second substrate having the first laminated insulating film, the second circuit layer including wire bonding pads; A second laminated insulating film is disposed on one side of the second substrate having a second circuit layer; The second laminated insulating film is exposed, developed, and cured to form a second blind groove, which corresponds to the position of the first blind groove and is connected to the first blind groove. After peeling off the first carrier copper foil and the first ultrathin copper foil, removing the first carrier copper foil and the carrier plate to obtain the second substrate, the process further includes: A second dry film is disposed on the side of the second substrate having the first ultrathin copper foil; The second dry film is exposed and developed to form a first pattern corresponding to the FC pad; The developed second substrate is flash-etched to retain the first ultrathin copper foil covered by the first pattern; Remove the second dry film.

2. The method for processing an embedded packaging substrate according to claim 1, characterized in that, The fabrication of the first circuit layer on the surface of the carrier substrate specifically includes: A first dry film is formed on the surface of the carrier substrate; The first dry film is exposed and developed to form the first line opening; The carrier substrate is electroplated to form the first circuit layer at the first circuit opening; Remove the first dry film.

3. The method for processing an embedded packaging substrate according to claim 1, characterized in that, The step of fabricating a second circuit layer on the side of the second substrate having the first laminated insulating film specifically includes: A third dry film is disposed on the side of the second substrate having the first laminated insulating film; The third dry film is exposed and developed to form a second circuit opening; The second substrate is electroplated to form the second circuit layer at the opening of the second circuit; Remove the third dry film.

4. The method for processing an embedded packaging substrate according to claim 3, characterized in that, After removing the third dry film, the process further includes: The second substrate is flash-etched to remove the first ultrathin copper foil located on the FC pad, thereby exposing the FC pad.

5. The method for processing an embedded packaging substrate according to claim 1, characterized in that, After exposing, developing, and curing the second laminated insulating film to form the second blind groove, the process further includes: A fourth dry film is provided on one side of the second substrate having the second laminated insulating film, and a fifth dry film is provided on the other side; The fourth dry film and the fifth dry film are exposed and developed to form the third line opening and the fourth line opening; The second substrate is electroplated to form a third circuit layer at the third circuit opening and a fourth circuit layer at the fourth circuit opening. Remove the fourth dry film and the fifth dry film.

6. The method for processing an embedded packaging substrate according to claim 5, characterized in that, After removing the fourth and fifth dry films, the process further includes: Ink is printed on the surface of the second substrate and pre-cured to obtain an ink layer; The ink layer is exposed using solder resist exposure data; The ink layer is developed and cured to form a solder resist ink layer.

7. The method for processing an embedded packaging substrate according to claim 1, characterized in that, Also includes: A flip chip is disposed in the first blind slot, with the active surface of the flip chip facing the FC pad and electrically connected to the FC pad; A stacked chip is disposed in the second blind slot, the stacked chip is fixed to the back side of the flip chip, and the stacked chip is electrically connected to the wire bonding pad.

8. The method for processing an embedded packaging substrate according to claim 7, characterized in that, Also includes: The first blind groove and the second blind groove are filled with molding material to form a plastic seal structure; The second substrate is baked and cured to obtain the encapsulation substrate.

9. An embedded packaging substrate, characterized in that, It is manufactured by the processing method of the embedded packaging substrate as described in any one of claims 1 to 8.

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