Dual collimator physical vapor deposition processing chamber

Abstract

In some embodiments, a physical vapor deposition apparatus includes a top flux optimizer configured to be biased. The physical vapor deposition apparatus further includes a middle flux optimizer configured to be biased. The top flux optimizer and the middle flux optimizer are separated by a first distance. The physical vapor deposition apparatus further includes a bottom flux optimizer configured to be biased. The bottom flux optimizer and the middle flux optimizer are separated by a second distance. The physical vapor deposition apparatus further includes a top power supply coupled to the top flux optimizer, a middle power supply coupled to the middle flux optimizer, and a bottom power supply coupled to the bottom flux optimizer.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to the formation of physical vapor deposition (PVD) films on a substrate in a device manufacturing process, and more specifically, to apparatus and methods for depositing one or more film layers in features formed on a substrate. Background Technology

[0002] The semiconductor device manufacturing field is constantly evolving, with the development of new materials, processes, and equipment to meet the growing demand for smaller, faster, and more complex devices. One of the key challenges in device manufacturing is the need to deposit thin films of a variety of materials with high quality, uniformity, and precision.

[0003] Physical vapor deposition (PVD) is a common technique for depositing thin films of various metals and metal alloys. However, PVD deposition can damage the underlying layers of the substrate, especially when high-energy ions are used to enhance the deposition rate or when the substrate features are small and have a high aspect ratio. This damage can lead to poor step coverage and other defects, which can impair the performance and reliability of the apparatus.

[0004] Therefore, there is a need for an improved deposition apparatus that can produce high-quality and uniform films without compromising the performance and reliability of the formed device. Summary of the Invention

[0005] Embodiments of this disclosure generally relate to the formation of physical vapor deposition (PVD) films on a substrate in a device manufacturing process, and more specifically, to apparatus and methods for depositing one or more film layers in features formed on a substrate.

[0006] In some embodiments, a physical vapor deposition (PVD) apparatus includes a substrate support disposed within a processing region of a processing chamber of the PVD apparatus. The substrate support includes a substrate support surface. The PVD apparatus further includes a first flux optimizer disposed within the processing region. The first flux optimizer includes a plurality of vias extending therethrough and is configured to be biased relative to a ground reference. The PVD apparatus further includes a second flux optimizer disposed within the processing region. The second flux optimizer includes a plurality of vias extending therethrough and is configured to be biased relative to a ground reference. The second flux optimizer is disposed between the first flux optimizer and the substrate support. The PVD apparatus further includes a first power supply coupled to either the first or second flux optimizer. The first power supply is configured to supply a voltage to either the first or second flux optimizer. The first power supply is configured to generate a bias voltage between the first and second flux optimizers.

[0007] In some embodiments, a physical vapor deposition (PVD) apparatus includes a top flux optimizer configured to be biased. The PVD apparatus further includes an intermediate flux optimizer configured to be biased. The top flux optimizer and the intermediate flux optimizer are separated by a first distance. The PVD apparatus further includes a bottom flux optimizer configured to be biased. The bottom flux optimizer and the intermediate flux optimizer are separated by a second distance. The PVD apparatus further includes a top power supply coupled to the top flux optimizer, an intermediate power supply coupled to the intermediate flux optimizer, and a bottom power supply coupled to the bottom flux optimizer.

[0008] In some embodiments, a method for depositing a film onto a substrate includes applying a bias voltage to at least one of a plurality of biasable flux optimizers disposed in a processing region of a processing chamber. The voltage is supplied by a power source. At least one of the plurality of biasable flux optimizers is grounded. The plurality of biasable flux optimizers are positioned within the processing region between a sputtering target and a substrate support. The method further includes sputtering target material from a sputtering target by applying a bias voltage to the target to form a film on a surface of a substrate disposed on the substrate support. Brief description of the attached diagram

[0010] To gain a more detailed understanding of the features and methods used in this disclosure, a more specific description of the disclosure briefly outlined above can be made with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it will be noted that the drawings illustrate exemplary embodiments only and are not intended to limit the scope thereof, and may allow for other equivalent embodiments.

[0011] Figure 1 This is a schematic top view of an exemplary processing system according to an embodiment.

[0012] Figure 2A This is a cross-sectional view of an exemplary processing chamber according to an embodiment.

[0013] Figure 2B This is a cross-sectional view of an exemplary processing chamber according to an embodiment.

[0014] Figure 3A This is a perspective view of a biasable flux optimizer according to an embodiment.

[0015] Figure 3B This is a perspective view of a biasable flux optimizer according to an embodiment.

[0016] Figure 3C This is a top view of the biasable flux optimizer according to an embodiment.

[0017] Figure 3D This is a cross-sectional view of the biasable flux optimizer according to an embodiment.

[0018] Figure 4 This is a cross-sectional view of an exemplary processing chamber according to an embodiment.

[0019] Figure 5 This is a process flow diagram of the method according to the embodiment.

[0020] Figure 6 This is an illustrative representation of the copper ion flux relative to the distance from the substrate according to an embodiment.

[0021] Figure 7 This is an illustrative representation of the copper ion flux relative to the distance from the substrate according to an embodiment.

[0022] Figure 8 It is a cross-sectional representation of the processing area within the processing chamber according to an embodiment.

[0023] To facilitate understanding, the same reference numerals have been used where possible to identify common elements in the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0024] Embodiments of this disclosure include an apparatus comprising a physical vapor deposition (PVD) chamber design that includes a flux optimizer (e.g., collimator) design for forming thin films on a surface of a substrate including multiple features formed thereon. Embodiments of the invention generally provide a processing chamber for performing a PVD process for forming metal interconnects within features formed on a substrate. In one embodiment, the processing chamber design is adapted to use a multi-step PVD process to deposit a desired material. The processing chambers disclosed herein can be particularly useful for depositing films with improved deposition uniformity, feature sidewall coverage, and feature bottom coverage. Design features of the processing chamber may include a biasable flux optimizer (e.g., collimator), one or more sidewall electromagnets, an improved magnetron design, an improved substrate bias configuration, and an improved processing accessory design.

[0025] Exemplary processing system

[0026] Figure 1This is a schematic top view of an exemplary processing system 100 (also referred to as a "processing platform") according to certain embodiments. As described in detail below, the processing system 100 typically includes an equipment front-end module (EFEM) 102 for loading a substrate into the processing system 100, a first loading locking chamber 104 coupled to the EFEM 102, a transfer chamber 108 coupled to the first loading locking chamber 104, and a plurality of other chambers coupled to the transfer chamber 108. The EFEM 102 typically includes one or more robots 105 configured to transfer a substrate from a FOUP 103 to at least one of the first loading locking chamber 104 or a second loading locking chamber 106. The processing system 100, advancing counterclockwise from the buffer portion 108A of the first loading locking chamber 104 around the transfer chamber 108, includes a first degassing chamber 109, a first pre-cleaning chamber 110, a first through chamber 112, a second through chamber 113, a second pre-cleaning chamber 114, a second degassing chamber 116, and a second loading locking chamber 106. The buffer portion 108A of the transfer chamber 108 includes a first robot 115 configured to transfer a substrate to each of the loading locking chambers 104, 106, the degassing chambers 109, 116, the pre-cleaning chambers 110, 114, and the through chambers 112, 113.

[0027] The rear end portion 108B of the transfer chamber 108 includes a second robot 135 configured to transfer a substrate to a processing chamber that runs through each of the chambers 112, 113 and is coupled to the rear end portion 108B of the processing system 100. The processing chambers may include a first processing chamber 132, a second processing chamber 134, a third processing chamber 136, and a fourth processing chamber 138. Typically, the processing chambers 132, 134, 136, and 138 may include at least one of atomic layer deposition (ALD) chambers, chemical vapor deposition (CVD) chambers, physical vapor deposition (PVD) chambers, etching chambers, degassing chambers, annealing chambers, and other types of semiconductor substrate processing chambers. In some embodiments, one or more of the processing chambers 132, 134, 136, and 138 are PVD chambers similar to the configuration of the processing chamber 200 described below.

[0028] The buffer portion 108A and the rear end portion 108B of the transfer chamber 108, as well as each chamber coupled to the transfer chamber 108, are maintained in a vacuum state. As used herein, the term "vacuum" may refer to a pressure less than 760 Torr and will typically be maintained at around 10. -5 Torr (i.e., ~10)-3 Under pressures of (Pa). However, some high vacuum systems can operate at pressures below nearly 10 Pa. -7 Torr (i.e., ~10) -5 The vacuum is operated at a pressure of 100 Pa. In some embodiments, the vacuum is generated using a roughing pump and / or a turbomolecular pump coupled to each of the transfer chamber 108 and one or more processing chambers (e.g., processing chambers 109 to 138). However, other types of vacuum pumps are also contemplated.

[0029] A system controller 126 (such as a programmable computer) is coupled to the processing system 100 for controlling one or more components therein. For example, the system controller 126 may control the operation of the processing chamber 200, as described further below. In operation, the system controller 126 performs data collection and feedback from the respective components to coordinate processing within the processing system 100. The system controller 126 includes a programmable central processing unit (CPU) 152, which may operate in conjunction with memory 154 (e.g., non-volatile memory) and support circuitry 156. The support circuitry 156 (e.g., cache, clock circuitry, input / output subsystems, power supplies, etc., and combinations thereof) is conventionally coupled to the CPU 152 and to various components within the processing system 100.

[0030] In some embodiments, CPU 152 is one of any form of general-purpose computer processor used in an industrial setting for controlling various monitoring system components and subprocessors, such as a programmable logic controller (PLC). Memory 154 coupled to CPU 152 is one or more non-transitory and generally readily available types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage (local or remote).

[0031] In this document, memory 154 is in the form of a computer-readable storage medium containing instructions (e.g., non-volatile memory) that, when executed by CPU 152, facilitate the operation of processing system 100. The instructions in memory 154 are in the form of a program product, such as a program implementing the methods of this disclosure (e.g., middleware application, rig software application, etc.). The program code may conform to any of several different programming languages. In one example, this disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program product defines the functionality of embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media that permanently store information thereon (e.g., read-only memory devices within a computer, such as CD-ROM discs readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory); and (ii) writable storage media that store variable information thereon (e.g., floppy disks or hard disks within a disk drive or any type of solid-state random access semiconductor memory). When carrying computer-readable instructions that direct the function of the methods described herein, such a computer-readable storage medium is an embodiment of this disclosure.

[0032] Processing chamber example

[0033] Figure 2A An exemplary processing chamber 200 is shown, having an upper processing assembly 208, a processing accessory 250, and a base assembly 220, all configured to process a substrate 205 disposed in a processing region 210. The processing accessory 250 includes a one-piece grounding shield 260, a deposition ring 268, a cover ring 270, and an isolation ring assembly 280. In the illustrated version, the processing chamber 200 includes a sputtering chamber, also referred to as a PVD chamber, capable of depositing single-component or multi-component materials from a sputtering target 232 onto the substrate 205. Processing chamber 200 can also be used to deposit aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), hafnium (Hf), silver (Ag), chromium (Cr), gold (Au), molybdenum (Mo), silicon (Si), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), lanthanum (La), and aluminum oxide (AlO). x ), Lanthanum oxide (LaO) x ( ), nickel-platinum alloys (NiPt) and titanium (Ti) and combinations thereof. Such processing chambers are available from Applied Materials, Inc., located in Santa Clara, California. It will be anticipated that other processing chambers, including those from other manufacturers, may be suitable for benefiting from one or more embodiments of the present disclosure described herein.

[0034] Processing chamber 200 includes a chamber body 201 having sidewalls 204, a bottom wall 206, and an upper processing assembly 208 that enclose the processing region 210 or plasma zone. The chamber body 201 is typically made of a welded sheet of stainless steel or a monolithic block of aluminum. In one embodiment, the sidewalls comprise aluminum, and the bottom of the chamber includes one or more walls formed of a stainless steel sheet. The sidewalls 204 typically include a slit valve (not shown) to allow entry and exit of the substrate 205 from the processing chamber 200. Components in the upper processing assembly 208 of the processing chamber 200 cooperate with a grounding shield 260, a base assembly 220, and a cover ring 270 to confine the plasma formed in the processing region 210 to the area above the substrate 205.

[0035] The base assembly 220 is supported by the bottom wall 206 of the processing chamber 200. During processing, the base assembly 220 supports the deposition ring 268 along with the substrate 205. The base assembly 220 is coupled to the bottom wall 206 of the processing chamber 200 via a lifting mechanism 222 configured to move the base assembly 220 between an upper processing position and a lower transfer position. Additionally, in the lower transfer position, a lifting rod 223 moves through the base assembly 220 to position the substrate at a distance from the base assembly 220 to facilitate substrate exchange with a substrate transfer mechanism (such as a single-blade robot (not shown)) located outside the processing chamber 200. A bellows 224 is typically disposed between the base assembly 220 and the bottom wall 206 to isolate the processing area 210 from the interior of the base assembly 220 and the exterior of the chamber.

[0036] The base assembly 220 typically includes a support 226 hermetically coupled to a platform housing 228. The platform housing 228 is typically made of a metallic material, such as stainless steel or aluminum. A cooling plate (not shown) is typically disposed within the platform housing 228 to thermally regulate the support 226.

[0037] The support 226 may be made of aluminum or ceramic. The substrate support 226 has a substrate receiving surface 227 that receives and supports the substrate 205 during processing, the substrate receiving surface 227 being substantially parallel to the sputtering surface 233 of the sputtering target 232. The support 226 also has a peripheral edge 229 terminating before the overhanging edge 205A of the substrate 205. The support 226 may be an electrostatic chuck, a ceramic body, a heater, or a combination thereof. In one embodiment, the support 226 is an electrostatic chuck comprising a dielectric body having electrodes 226A embedded therein. The dielectric body is typically made of a high thermal conductivity dielectric material, such as pyrolytic boron nitride, aluminum nitride, silicon nitride, alumina, or equivalent materials. Other aspects of the base assembly 220 and the support 226 are further described below. In one embodiment, electrode 226A is configured such that when a DC voltage is applied to electrode 226A via electrostatic chuck power supply 243, substrate 205 disposed on substrate receiving surface 227 will be electrostatically chuckled onto the electrode to improve heat transfer between substrate 205 and support 226. In another embodiment, bias source 241 is also coupled to electrode 226A, allowing a voltage to be maintained on the substrate during processing to influence the interaction between plasma and the surface of substrate 205.

[0038] The system controller 126 has a readable program (or computer instructions) that determines which tasks can be performed on the substrate. Preferably, the program is software readable by the system controller 126, which includes code for performing tasks related to the monitoring, execution, and control of movement, as well as various processing formulation tasks and formulation steps performed in the processing system 100 and the processing chamber 200. For example, the system controller 126 may include program code including a substrate positioning instruction set for operating the base assembly 220; a gas flow control instruction set for operating a gas flow control valve to set the flow rate of sputtering gas to the processing chamber 200; a gas pressure control instruction set for operating a throttle valve or gate valve to maintain the pressure in the processing chamber 200; a temperature control instruction set for controlling a temperature control system (not shown) in the base assembly 220 or sidewall 204 to set the temperature of the substrate or sidewall 204 respectively; and a process monitoring instruction set for monitoring the process in the processing chamber 200.

[0039] Process chamber 200 also includes process fittings 250, which include various components that can be easily removed from process chamber 200, such as for cleaning sputtered deposits from component surfaces, replacing or repairing eroded components, or adapting process chamber 200 for other processes. In one embodiment, process fitting 250 includes an isolation ring assembly 280, a grounding shield 260, and a deposition ring 268 positioned around a peripheral edge 229 of a support 226, the peripheral edge 229 terminating before the overhanging edge of substrate 205.

[0040] The upper processing assembly 208 may also include an RF source 281, a direct current (DC) source 282, an adapter 202, a motor 293, and a cover assembly 230. The cover assembly 230 typically includes a sputtering target 232, a magnetron system 289, and a cover housing 291. When in the closed position, the upper processing assembly 208 is supported by sidewalls 204, such as... Figure 2A As shown. A ceramic target isolator 236 is disposed between the isolation ring assembly 280, the sputtering target 232, and the adapter 202 of the cap assembly 230 to prevent vacuum leakage therebetween. The adapter 202 is hermetically coupled to the sidewall 204 and is configured to facilitate the removal of the upper processing assembly 208 and the isolation ring assembly 280.

[0041] When in the processing position, the sputtering target 232 is positioned adjacent to the adapter 202 and exposed to the processing area 210 of the processing chamber 200. The sputtering target 232 contains material deposited on the substrate 205 during PVD or sputtering processes. An isolation ring assembly 280 is disposed between the sputtering target 232 and the shield 260 and the chamber body 201 to electrically isolate the sputtering target 232 from the shield 260 and the chamber body 201.

[0042] During processing, sputtering target 232 is biased relative to the grounded region of the processing chamber (e.g., chamber body 201 and adapter 202) by power supplies configured in RF source 281 and / or DC source 282. It is believed that by delivering RF energy and DC power to sputtering target 232 during high-voltage PVD processes, significant process advantages over conventional low-voltage DC plasma processing techniques can be achieved when combined with sputtering materials such as titanium, copper, nickel, ruthenium, aluminum, tantalum, molybdenum, and tungsten, to name just a few. In one embodiment, RF source 281 includes RF power supply 281A and RF match 281B, both configured to efficiently deliver RF energy to sputtering target 232. In one example, RF power supply 281A is capable of generating RF currents with frequencies between approximately 13.56 MHz and approximately 228 MHz at power levels between approximately 0 and approximately 5 kW. In one example, DC power supply 282A in DC source 282 is capable of delivering DC power between approximately 0 and approximately 50 kW.

[0043] In some embodiments, the processing chamber 200 also includes one or more auxiliary electromagnet assemblies, such as a first electromagnet assembly 261, a second electromagnet assembly 263, and a third electromagnet assembly 265, vertically aligned around the processing chamber. In some embodiments, the first, second, and third electromagnet assemblies each include a separate current source, such that each assembly can independently generate a magnetic field configured to limit and / or control the movement of electrons and ions generated in the plasma formed in the processing region 210 of the processing chamber.

[0044] In some embodiments, a first electromagnet assembly 261 includes a first current source 261A configured to bias a first magnetic coil assembly 261B. The first magnetic coil assembly 261B is positioned near a sputtering target 232 and is configured to regulate a magnetron-controlled plasma 213. A second electromagnet assembly 263 includes a second current source 263A configured to bias a second magnetic coil assembly 263B. The second magnetic coil assembly 263B is positioned in a central portion of a chamber and is configured to regulate a central portion of the plasma 211. A third electromagnet assembly 265 includes a third current source 265A configured to bias a third magnetic coil assembly 265B. The third magnetic coil assembly 265B is positioned near a support 226 and is configured to regulate plasma near a surface of a substrate 205. In some configurations, the first current source 261A, the second current source 263A, and the third current source 265A are capable of generating DC or RF current or voltage at a power between about 0 and about 5 kilowatts.

[0045] In operation, one or more electromagnet assemblies 261, 263, and 265 are vertically distributed and positioned outside the processing accessory 250 to generate a magnetic field within the processing region 210 to help alter and / or shape the radial distribution of the plasma formed together with the processing region 210 during processing. In some embodiments, the one or more electromagnet assemblies comprise a single electromagnet, a pair of electromagnets, or a quadruple electromagnet array. A quadruple electromagnet array comprises four solenoid coils wound in a generally circularly symmetrical manner around a central axis 294 of the processing chamber 200. In one configuration, the four electromagnets are configured as a top inner magnet (TIM), a top outer magnet (TOM), a bottom inner magnet (BIM), and a bottom outer magnet (BOM) (not shown). The magnetic field generated by the quadruple electromagnet array is modulated by controlling the direction and magnitude of the current flowing through each coil, or by selectively powering a particular combination of coils (e.g., outer / inner coils or top / bottom coils).

[0046] During processing, a gas (such as argon) is supplied from a gas source 242 to the processing zone 210 via a conduit 244. The gas source 242 may contain an inert gas, such as argon, krypton, helium, or xenon, which is capable of energetically impacting the surface of the sputtering target 232 and / or substrate 205 based on a bias applied by a bias source 241 and sputtering material from the surface of the sputtering target and / or substrate. The gas source 242 may also include a reactive gas, such as one or more of an oxygen-containing gas or a nitrogen-containing gas, which is capable of reacting with the sputtered material to form a layer on the substrate. Used processing gas and byproducts are discharged from the processing chamber 200 through a discharge port 246, which receives the used processing gas and directs it to a discharge conduit 248 having an adjustable position gate valve 247 to control the pressure in the processing zone 210 within the processing chamber 200. The discharge conduit 248 is connected to one or more discharge pumps 249, such as cryogenic pumps. Typically, the pressure of the sputtering gas in the processing chamber 200 during processing is set below atmospheric levels, such as in a vacuum environment, for example, a pressure of about 0.6 mTorr to about 400 mTorr. In one embodiment, the processing pressure is set to about 20 mTorr to about 100 mTorr. A plasma is formed by the gas between the substrate 205 and the sputtering target 232. Ions within the plasma are accelerated toward the sputtering target 232 and cause material to migrate from the sputtering target 232. The migrated target material is deposited on the substrate.

[0047] The housing 291 typically includes a conductive wall 285, a center feed 284, and a shield 286. Figure 2A In this configuration, a portion of the conductive wall 285, center feed 284, sputtering target 232, and motor 293 surrounds and forms a back surface region 234. The back surface region 234 is a sealed area disposed on the back surface of the sputtering target 232 and is typically filled with a flowing liquid during processing to remove heat generated at the sputtering target 232 during processing. In one embodiment, the conductive wall 285 and center feed 284 are configured to support the motor 293 and magnetron system 289, such that the motor 293 can rotate the magnetron system 289 during processing. In one embodiment, the motor 293 is electrically isolated from RF or DC power delivered from a power supply using a dielectric layer 293B (such as Delrin, G10, or Ardel).

[0048] Shielding member 286 may comprise one or more dielectric materials positioned to surround and prevent RF energy delivered to sputtering target 232 from interfering with and affecting the processing system 100. Figure 1Other processing chambers are provided within the [missing information]. In one configuration, shielding 286 may comprise Delrin, G10, Ardel, or other similar materials and / or a thin ground sheet metal RF shield.

[0049] To provide efficient sputtering, a magnetron system 289 is positioned on the back side of a sputtering target 232 in an upper processing assembly 208 to generate a magnetic field in the processing region 210 adjacent to the sputtering surface 233 of the sputtering target 232, which generates a magnetron-controlled plasma 213. The magnetic field generated by the magnetron system 289 traps electrons and ions, thereby increasing the plasma density above one or more regions of the target 232, and thus also increasing target utilization, control of deposition uniformity, and sputtering rate. According to one embodiment of this disclosure, the magnetron system 289 includes a source magnetron assembly 221 comprising an outer pole (not shown) and an inner pole (not shown). The magnetron system 289 is rotated about a central axis 294 of the processing chamber 200 using a motor 293. In some embodiments, a “closed-loop” magnetron is configured to be formed within the magnetron system 289 such that the outer pole (not shown) of the magnetron surrounds the inner pole (not shown), thereby forming a gap as a continuous loop between the poles. In a closed-loop configuration, a "closed-loop" pattern is formed by the magnetic field that appears and re-enters the sputtering target surface. This pattern can be used to confine electrons to the vicinity of the sputtering target surface in a closed pattern, often referred to as a "racetrack" type pattern. In contrast to an open-loop configuration, a closed-loop magnetron configuration can confine electrons and generate high-density plasma near the sputtering surface 233 of the sputtering target 232 to increase sputtering yield. In some other embodiments, an "open-loop" magnetron configuration is formed within the magnetron system 289 such that the outer pole of the magnetron surrounds the inner pole, thus forming a gap as a continuous loop between the poles. In an open-loop magnetron configuration, electrons trapped between the inner and outer poles migrate, leak, and escape from the B-field generated at the open end of the magnetron, thus retaining electrons for only a short period during the sputtering process due to the reduced electron confinement. It has been found that the use of an open-loop magnetron configuration, when combined with RF and DC sputtering of multi-component targets as described herein, can provide significant improvements in stepped coverage and improved material composition uniformity across the substrate surface.

[0050] In some embodiments of the processing chamber 200, a bias source 241 is coupled between an electrode and an RF ground to adjust the bias voltage on the substrate 205 during processing to control the degree of bombardment on the substrate surface. In some embodiments, the electrode is disposed adjacent to the substrate receiving surface 227 of the support 226 and includes an electrode 226A. In a PVD reactor, tuning the bombardment of the substrate surface by controlling the impedance of the electrode to ground will affect the properties of the stepped coverage, overhang geometry, and deposited film, such as grain size, film stress, crystal orientation, film density, roughness, characteristic bottom coverage, characteristic stepped coverage, and in some cases, film composition. Thus, the bias source 241 can be used to change the deposition rate, etching rate, and even the composition of multi-component films at the substrate surface. In one embodiment, the bias source 241 is used to achieve deposition or etching of a deposited film by appropriately adjusting the impedance of the electrode / substrate to ground. In one embodiment of the bias source 241, the bias source 241 has a variable capacitor tuning circuit with feedback circuitry to control the properties of the deposited metallic or non-metallic layer on the substrate.

[0051] In some embodiments, bias source 241 includes an RF source (not shown) coupled to electrode 226A and an impedance match (not shown). In some embodiments, the RF power supply is capable of generating RF currents at frequencies between about 11 MHz and about 228 MHz (such as 13.56 MHz) at a power between about 0 and about 5 kW.

[0052] Biasable flux optimizer

[0053] In some embodiments, such as Figure 2B As shown, the processing chamber 200 is modified to include a biasable flux optimizer 290 for further control of ion distribution and directionality within the chamber. In some embodiments, the biasable flux optimizer 290 is also referred to herein as a collimator. In one implementation, control of the ion flux directionality of the sputtered material can be achieved by positioning the biasable flux optimizer 290 between the sputtering target 232 and the base assembly 220. A power supply 251 is coupled to the biasable flux optimizer 290 to provide a bias potential for energizing the biasable flux optimizer 290 and attracting sputtered metal ions formed in the plasma.

[0054] Figure 3A A perspective view of a biasable flux optimizer 290 implemented according to this disclosure is depicted. Figure 3B Another perspective view depicts a biasable flux optimizer 290 implemented according to this disclosure. Figure 3C Depicting what can be Figure 2B The processing chamber 200 is set Figures 3A to 3BA top view of the biasable flux optimizer 290. The biasable flux optimizer 290 includes a shielding portion 310 coupled to a collimator portion 320. The collimator portion 320 includes a plurality of orifices to guide and allow gas and / or material flux within the processing chamber 200 to pass through it.

[0055] The collimator section 320 can be mechanically and electrically coupled to the one-piece shielding section 310. In one implementation, the collimator section 320 is integrated with the one-piece shielding section 310, such as... Figures 3A to 3B As shown. In one implementation, the collimator portion 320 is welded to the one-piece shield portion 310. In one implementation, the collimator portion 320 and the one-piece shield portion 310 are machined from a single piece of material. In one implementation, the collimator portion 320 and the one-piece shield portion 310 are composed of materials selected from aluminum, titanium, copper, and stainless steel. Alternatively, the one-piece shield portion 310 and the collimator portion 320 are formed as separate pieces and coupled together using suitable attachment means such as bolting, riveting, or welding. In one implementation, the collimator portion 320 may be electrically floating within the processing chamber 200. In one implementation, the collimator portion 320 may be coupled to an electrical power source.

[0056] like Figure 3C As shown, the collimator portion 320 is typically a body or honeycomb structure 330 having walls 336 that define and separate hexagonal apertures 338 in a closely packed arrangement. The aspect ratio of the hexagonal apertures 338 can be defined as the depth of the hexagonal apertures 338 (equal to the thickness of the collimator) divided by the width 339 of the hexagonal apertures 338. In some embodiments, the thickness of the walls 336 is between about 0.1 mm and about 10 mm in the transverse and / or cross-sectional directions, such as about 1 mm to about 7.5 mm, such as about 2.5 mm to about 5 mm, alternatively about 0.1 mm to about 1 mm, alternatively about 1 mm to about 2.5 mm, alternatively about 2.5 mm to about 3.5 mm, alternatively about 3.5 mm to about 5 mm, alternatively about 5 mm to about 7.5 mm, alternatively about 7.5 mm to about 10 mm. In one implementation, the collimator portion 320 is made of a material selected from aluminum, titanium, copper, and stainless steel.

[0057] The honeycomb structure 330 of the collimator section 320 can be used as an integrated flux optimizer to improve the flow path, ion fraction, and ion trajectory behavior of ions passing through the collimator section 320. In one implementation, the wall 336 adjacent to the shielding section has a tapered inlet portion and radius. The one-piece shielding section 310 of the collimator section 320 can facilitate the mounting of the collimator section 320 into the processing chamber 200.

[0058] In one implementation, the collimator portion 320 may be machined from a single piece of aluminum. The collimator portion 320 may optionally be coated or anodized. Alternatively, the collimator portion 320 may be made of other materials compatible with the processing environment and may consist of one or more segments. In some implementations, the wall 336 of the collimator portion 320 may be textured (e.g., sandblasted) to improve the adhesion of a high-stress film (e.g., a copper alloy) to the wall 336.

[0059] In one implementation, the collimator section 320 can be electrically biased in bipolar mode to control the orientation of ions passing through the collimator section 320. For example, as Figure 3C As shown, a controllable DC or AC power supply 390 can be coupled to the collimator section 320 to provide alternating pulsed positive or negative voltages to the collimator section 320 to bias the collimator section 320.

[0060] Collimator section 320 acts as a filter to capture ions and neutral substances emitted from material from sputtering target 232 at an angle greater than a selected angle and close to an angle orthogonal to substrate 205. The hexagonal aperture 338 of collimator section 320 is designed to allow different percentages of ions emitted from the central or peripheral regions of the material from sputtering target 232 to pass through collimator section 320. As a result, both the number of ions and the angle of arrival of the ions deposited on the peripheral and central regions of substrate 205 are adjusted and controlled. Consequently, material can be sputtered more uniformly across the surface of substrate 205. Additionally, material can be deposited more uniformly on the bottom and sidewalls of high aspect ratio features, particularly high aspect ratio vias and trenches located near the periphery of substrate 205.

[0061] Figure 3D The implementation method according to this disclosure is described. Figures 3A to 3B A cross-sectional view of the biasable flux optimizer 290. The collimator portion 320 includes a body or honeycomb structure 330 having a central region 342 with a first plurality of holes 322 having a high aspect ratio (e.g., from about 2.5:1 to about 3:1). The aspect ratio of a second plurality of holes 324 in the collimator portion 320 in the outer peripheral region 344 is reduced relative to the first plurality of holes 322 in the central region 342. In one implementation, the second plurality of holes 324 in the outer peripheral region 344 has an aspect ratio from about 1:1 to about 2:1. In one implementation, the second plurality of holes 324 in the outer peripheral region 344 has an aspect ratio of about 1:1. The higher aspect ratio allows for more holes in the central region 342 of the collimator portion 320. In one implementation, the central region includes 61 holes.

[0062] In one implementation, the radial reduction of the hexagonal aperture 338 is achieved by providing a third plurality of apertures 326 in a transition region 346 provided between the central region 342 and the outer peripheral region 344. The walls 336 defining the third plurality of apertures 326 are cut along a predetermined angle “α” such that the transition region 346 forms a conical shape surrounding the first plurality of apertures 322. In one implementation, the predetermined angle α is between 15 degrees and 45 degrees. The transition region 346 advantageously provides a circular profile of the aperture in the central region 342, which overcomes the six-point deposition of shadows near the edges of the substrate 205 caused by the corners of a conventional hexagonal collimator.

[0063] The upper portion of the wall 336 defining the hexagonal aperture 338 has an inlet portion 360 to reduce the rate at which the hexagonal aperture 338 becomes clogged by sputtered material. The inlet portion 360 has a tapered shape. The inlet portion 360 extends a predetermined distance 362 into the hexagonal aperture 338 and is formed at a predetermined angle 364. In one implementation, the predetermined distance 362 is between about 0.15 inches (3.81 mm) and about 1 inch (2.54 cm), and the predetermined angle 364 is between about 2 degrees and about 16 degrees. In another implementation, the predetermined distance 362 and the predetermined angle 364 are about 1 inch (2.54 cm) and 2.5 degrees, respectively.

[0064] Dual-biased flux optimizer

[0065] In some embodiments, such as Figure 4 As shown, the processing chamber 200 is modified to include a biasable flux optimizer 490 for further control of ion distribution and directionality within the chamber. Figure 4 This is a side cross-sectional view depicting the processing chamber 200 of a second type of biasable flux optimizer 490 implemented according to this disclosure. The biasable flux optimizer 490, referred to herein as a dual-biasable flux optimizer, can be compared with the one described above regarding... Figure 2BThe described biasable flux optimizer 290 is similarly positioned and configured. The biasable flux optimizer 490 includes a first biasable flux optimizer 492 and a second biasable flux optimizer 494. The first biasable flux optimizer 492 is electrically isolated from and spaced apart from the second biasable flux optimizer 494 by a distance 489. In one or more embodiments, the distance 489 separating the first biasable flux optimizer 492 from the second biasable flux optimizer 494 is about 10 cm or less, such as about 5 cm or less, such as about 1 cm or less, such as about 0.1 cm or less, such as about 0.01 cm or less. In some embodiments, the distance 489 separating the first biasable flux optimizer 492 and the second biasable flux optimizer 494 is from about 0.01 cm to about 25 cm, such as about 0.1 cm to about 20 cm, such as about 1 cm to about 15 cm, such as about 10 cm to about 10 cm, alternatively about 0.01 cm to about 0.1 cm, alternatively about 0.1 cm to about 1 cm, alternatively about 1 cm to about 5 cm, alternatively about 10 cm to about 15 cm, alternatively about 15 cm to about 20 cm, alternatively about 20 cm to about 25 cm.

[0066] Both the collimator portion 491 of the first biasable flux optimizer 492 and the collimator portion 493 of the second biasable flux optimizer 494 typically include a body structure with walls defining a plurality of orifices (e.g., hexagonal orifices 338), said orifices including openings 495 for guiding and allowing gas and sputtered material fluxes (e.g., ions and / or neutral particles) to pass through within the processing chamber 200. The first biasable flux optimizer 492 will typically include an inlet portion 486 and a collimator portion 491. The second biasable flux optimizer 494 will typically include an inlet portion 488 and a collimator portion 493. In one example, in Figures 3C to 3D The diagram shows a top view and a cross-sectional view of the collimator portion 491 of the first biasable flux optimizer 492 and the collimator portion 493 of the second biasable flux optimizer 494, which can be disposed in the processing chamber 200. Figure 4 As shown, openings 495 in a plurality of holes within the first biasable flux optimizer 492 and the second biasable flux optimizer 494 are aligned to allow gas and sputtered material fluxes (e.g., ions and / or neutral particles) to pass through them.

[0067] In some implementations described herein, a biasable flux optimizer 490 is provided to further control ion distribution and directionality during the process. The ability to individually bias individual flux optimizers (i.e., a first biasable flux optimizer 492 and a second biasable flux optimizer 494) allows control over the electric field through which sputtered material passes. In one embodiment, a first power supply 496 is coupled to the first biasable flux optimizer 492 to supply voltage to it, and a second power supply 497 is coupled to the second biasable flux optimizer 494 to supply voltage to it. In some alternative configurations, a relative bias is supplied between the first biasable flux optimizer 492 and the second biasable flux optimizer 494 via a power supply (not shown) coupled between the biasable flux optimizers 492 and 494, while one of the biasable flux optimizers 492 and 494 is coupled to a ground reference.

[0068] In one processing example, opposing biases are applied between biasable flux optimizers 492 and 494 during the deposition process, wherein a negative bias is applied to the second biasable flux optimizer 494 relative to the first biasable flux optimizer 492. In an alternative example of opposing biases, a negative bias is applied to the first biasable flux optimizer 492 relative to the second biasable flux optimizer 494. In some embodiments, the opposing biases applied between the first biasable flux optimizer 492 and the second biasable flux optimizer 494 are applied in a pulsed or alternating manner to facilitate localized deposition onto the substrate 205. The voltage pulses may include a series of asymmetric voltage pulses having pulse on-times between 5% and 95% of the pulse period, such as between 25% and 75%. The voltage pulses may be provided at frequencies between approximately 1 Hz and 500 kHz. The first power supply 496 and the second power supply 497 are each configured to provide negative and / or positive voltage pulses to their respective biasable flux optimizers for control in unipolar or bipolar modes as needed. In one embodiment, the biasable flux optimizer 490 is controlled in bipolar mode to control and capture ions to produce different ratios of ions and neutral particles passing through the biasable flux optimizer 490. Without being bound by theory, it is assumed that a positive voltage pulse applied relative to ground to the first biasable flux optimizer 492 and / or the second biasable flux optimizer 494 can attract electrons in the plasma toward the substrate surface and repel or slow down the ion flux toward the substrate surface. Conversely, a negative voltage pulse applied relative to ground to the first biasable flux optimizer 492 and / or the second biasable flux optimizer 494 can repel electrons in the plasma toward the target and increase the ion flux toward the substrate surface. Thus, by applying alternating positive and negative voltage pulses to the first biasable flux optimizer 492, the directionality of ions and neutral particles passing through the biasable flux optimizer 490 can be efficiently controlled.

[0069] In some embodiments, at least one of the first biasable flux optimizer 492 and / or the second biasable flux optimizer 494 is configured to be electrically grounded such that no voltage is applied to it. In at least one embodiment, the first biasable flux optimizer 492 is electrically grounded such that no voltage can be applied to it. In at least one embodiment, the second biasable flux optimizer 494 is electrically grounded such that no voltage can be applied to it.

[0070] In one or more embodiments, a voltage of about 10 V to about 200 V, such as about 50 V to about 150 V, such as about 70 V to about 120 V, is applied to the first biasable flux optimizer 492, alternatively about 10 V to about 50 V, alternatively about 50 V to about 70 V, alternatively about 70 V to about 100 V, alternatively about 100 V to about 120 V, alternatively about 120 V to about 150 V, alternatively about 150 V to about 200 V. In one or more embodiments, a voltage of about 10V to about 200V, such as about 50V to about 150V, such as about 70V to about 120V, is applied to the second biasable flux optimizer 494, alternatively about 10V to about 50V, alternatively about 50V to about 70V, alternatively about 70V to about 100V, alternatively about 100V to about 120V, alternatively about 120V to about 150V, alternatively about 150V to about 200V.

[0071] In one embodiment, at a bias frequency between approximately 400 Hz and approximately 500 kHz, the DC bias power pulses from the first power supply 496 and / or the second power supply 497 may have a duty cycle between approximately 5% (e.g., 5% on and 95% off) and approximately 70% (e.g., 70% on and 30% off), such as between approximately 5% and approximately 50%, such as between approximately 15% and 45%. Alternatively, the cycle of pulsed DC bias power to the first biasable flux optimizer 492 and / or the second biasable flux optimizer 494 may be controlled by a predetermined number of time periods. For example, the DC bias power may be pulsed between approximately 1 millisecond and approximately 100 milliseconds. Note that the duty cycle of the pulsed DC bias power to the first biasable flux optimizer 492 and / or the second biasable flux optimizer 494 may be repeated multiple times as needed. In one embodiment, the DC bias power may be controlled between approximately 1 kW and approximately 10 kW.

[0072] In some alternative embodiments, an RF bias may be applied to either or both of the first biasable flux optimizer 492 and / or the second biasable flux optimizer 494, wherein the frequency of the RF bias may be between 400 Hz and 60 MHz, such as a frequency between about 2 MHz and 13.56 MHz. In this configuration, a first power supply 496 and a second power supply 497 are configured to provide RF bias to the first biasable flux optimizer 492 or the second biasable flux optimizer 494, respectively. In some embodiments, opposing RF biases are applied between the first biasable flux optimizer 492 and the second biasable flux optimizer 494. In one example, a first RF bias is applied to the first biasable flux optimizer 492 and a second RF bias is applied to the second biasable flux optimizer 494. In some embodiments, the bias applied between the first biasable flux optimizer 492 and the second biasable flux optimizer 494 is applied in a pulsed or alternating manner to facilitate localized deposition onto the substrate 205.

[0073] Typically, membranes can be used via methods (such as...) Figure 5 Method 500 shown in the figure describes a processing chamber for deposition onto a substrate surface. In operation 510 of method 500, a plurality of biasable flux optimizers are positioned within the processing chamber between the sputtering target and the substrate. In operation 520 of method 500, a bias voltage is applied to at least one of the biasable flux optimizers. In operation 530 of method 500, at least one of the biasable flux optimizers is electrically grounded such that no voltage can be applied to it. In an alternative version of operation 530 of method 500, at least one of the biasable flux optimizers is electrically biased relative to another biasable flux optimizer. In operation 540 of method 500, a thin film is deposited onto the surface of the substrate.

[0074] An embodiment of method 500 will include a method for depositing a film onto a substrate, the method comprising applying a bias voltage to at least one of a plurality of biasable flux optimizers disposed in a processing region of a processing chamber, the voltage being supplied by a power source. At least one of the plurality of biasable flux optimizers is grounded, and the plurality of biasable flux optimizers are positioned within a processing region between a sputtering target and a substrate support. The process includes sputtering target material from a sputtering target by applying a bias voltage to the target, forming a film on a surface of a substrate disposed on the substrate support.

[0075] As previously discussed, the biasable flux optimizer 490 may include a first biasable flux optimizer 492, which is electrically isolated from and spaced apart from the second biasable flux optimizer 494 by a distance 489. Without being bound by theory, it has been found that the voltage difference applied to the first biasable flux optimizer 492 and the second biasable flux optimizer 494, combined with the gap between the two optimizers (e.g., distance 489), can be used to control and tune the interaction of plasma material (i.e., ions, electrons, and neutral particles) with the substrate surface during processing. More specifically, it has been determined that when the bias voltage applied to the second biasable flux optimizer 494 is greater than the bias voltage applied to the first biasable flux optimizer 492 (e.g., relative to ground correction), a larger ion fraction is present in the plasma closer to the substrate. This aspect is relevant when examining copper sputtering processes. Figure 6 Further exemplification is provided, wherein, as shown, copper ion flux is provided relative to a distance from the substrate, wherein a distance 489 between the first biasable flux optimizer 492 and the second biasable flux optimizer 494 is maintained at a constant nominal distance, while the voltage applied to each of the biasable flux optimizers is systematically varied. For example, it can be... Figure 6 It was observed that in each example where the voltage applied to the second biasable flux optimizer 494 was greater than the voltage applied to the first biasable flux optimizer 492 (e.g., ΔV is a positive value), the ion content in the plasma was greater than the ion content when the same voltage was applied to both biasable flux optimizers (e.g., ΔV is 0).

[0076] Figure 7 The effect of adjusting the distance between the first biasable flux optimizer 492 and the second biasable flux optimizer 494 by incorporating the difference in applied bias voltage is shown. It has been found that increasing the distance between the two biasable flux optimizers exaggerates the same trend of increasing ion content in the plasma previously established by the ion flux generated by the difference in applied bias voltage.

[0077] Although the dual-biased flux optimizer is described in the context of including the first biasable flux optimizer 492 and the second biasable flux optimizer 494, it should not limit the number of biasable flux optimizers that may exist in the biasable flux optimizer 490. For example, the biasable flux optimizer 490 may include multiple individual biasable flux optimizers configured / oriented therein, such as two or more biasable flux optimizers (e.g., the first biasable flux optimizer 492 and the second biasable flux optimizer 494). Figure 8The illustration shows a processing region 801 within a processing chamber 800 (such as processing chamber 200), and the processing region includes a top biasable flux optimizer 802, a middle biasable flux optimizer 804, and a bottom biasable flux optimizer 806. The top biasable flux optimizer 802 may include a first surface 802a and a second surface 802b. The first surface 802a of the top biasable flux optimizer 802 may be adjacent to the sputtering target 232, separated by a distance 808. The second surface 802b of the top biasable flux optimizer 802 may be adjacent to the middle biasable flux optimizer 804. The middle biasable flux optimizer 804 may include a first surface 804a and a second surface 804b. The first surface 804a of the middle biasable flux optimizer 804 may be adjacent to the second surface 802b of the top biasable flux optimizer 802, separated by a distance 810. The second surface 804b of the intermediate biasable flux optimizer 804 may be adjacent to the bottom biasable flux optimizer 806. The bottom biasable flux optimizer 806 may include a first surface 806a and a second surface 806b. The first surface 806a of the bottom biasable flux optimizer 806 may be adjacent to the second surface 804b of the intermediate biasable flux optimizer 804, separated by a distance 812. The second surface 806b of the bottom biasable flux optimizer 806 may be adjacent to the substrate 205, separated by a distance 814.

[0078] The top-biasable flux optimizer 802 can be configured according to any one or more flux optimizer configurations previously described. In at least one embodiment, the top-biasable flux optimizer 802 is configured to be electrically grounded such that no voltage can be applied to it. In at least one embodiment, the top-biasable flux optimizer 802 is electrically biased by applying a voltage relative to ground to it via a power supply 802c. In one or more embodiments, a voltage of about 10 V to about 200 V, such as about 50 V to about 150 V, such as about 70 V to about 120 V, alternatively about 10 V to about 50 V, alternatively about 50 V to about 70 V, alternatively about 70 V to about 100 V, alternatively about 100 V to about 120 V, alternatively about 120 V to about 150 V, alternatively about 150 V to about 200 V can be applied to the top-biasable flux optimizer 802. As discussed above, in some embodiments, an RF bias can be applied to the top-biasable flux optimizer 802.

[0079] In at least one embodiment, the first surface 802a of the top biasable flux optimizer 802 is separated from the sputtering target 232 by a distance 808 of about 800 mm or less, such as about 250 mm or less, such as about 100 mm or less, such as about 10 mm to about 500 mm, such as about 25 mm to about 250 mm, such as about 50 mm to about 100 mm, alternatively about 10 mm to about 25 mm, alternatively about 25 mm to about 50 mm, alternatively about 50 mm to about 75 mm, alternatively about 75 mm to about 100 mm, alternatively about 100 mm to about 250 mm, alternatively about 250 mm to about 500 mm. In at least one embodiment, the second surface 802b of the top biasable flux optimizer 802 is separated from the first surface 804a of the intermediate biasable flux optimizer 804 by a distance 810 of about 500 mm or less, such as about 250 mm or less, such as about 100 mm or less, such as about 10 mm to about 500 mm, such as about 25 mm to about 250 mm, such as about 50 mm to about 100 mm, alternatively about 10 mm to about 25 mm, alternatively about 25 mm to about 50 mm, alternatively about 50 mm to about 75 mm, alternatively about 75 mm to about 100 mm, alternatively about 100 mm to about 250 mm, alternatively about 250 mm to about 500 mm.

[0080] In some embodiments, the intermediate biasable flux optimizer 804 includes a plurality of individual biasable flux optimizers. The plurality of individual biasable flux optimizers may include any number of biasable flux optimizers, such as 1 to 50, 1 to 25, 1 to 10, 1 to 5, or 1 to 2. Each of the plurality of individual biasable flux optimizers of the intermediate biasable flux optimizer 804 may be configured independently according to any one or more flux optimizer configurations previously described. In at least one embodiment, each of the plurality of individual biasable flux optimizers of the intermediate biasable flux optimizer 804 is oriented in a stacked configuration such that ions from the sputtering target flow continuously through each of the biasable flux optimizers (i.e., collimators). In at least one embodiment, each of the plurality of individual biasable flux optimizers of the intermediate biasable flux optimizer 804 is independently separated by a distance of about 500 mm or less, such as about 250 mm or less, such as about 100 mm or less, such as about 10 mm to about 500 mm, such as about 25 mm to about 250 mm, such as about 50 mm to about 100 mm, alternatively about 10 mm to about 25 mm, alternatively about 25 mm to about 50 mm, alternatively about 50 mm to about 75 mm, alternatively about 75 mm to about 100 mm, alternatively about 100 mm to about 250 mm, alternatively about 250 mm to about 500 mm.

[0081] In at least one embodiment, each of the plurality of individual biasable flux optimizers of the intermediate biasable flux optimizer 804 is independently biased by applying a voltage to it via power supply 804c, or electrically grounded such that no voltage can be applied to it. In one or more embodiments, a voltage of about 10 V to about 200 V relative to ground, such as about 50 V to about 150 V, such as about 70 V to about 120 V, alternatively about 10 V to about 50 V, alternatively about 50 V to about 70 V, alternatively about 70 V to about 100 V, alternatively about 100 V to about 120 V, alternatively about 120 V to about 150 V, alternatively about 150 V to about 200 V, can be applied to one or more of the intermediate biasable flux optimizers, as discussed above. In some embodiments, an RF bias may be applied to one or more of the intermediate biasable flux optimizers.

[0082] As previously discussed, the intermediate biasable flux optimizer 804 may include a first surface 804a and a second surface 804b. The first surface 804a of the intermediate biasable flux optimizer 804 may be adjacent to the second surface 802b of the top biasable flux optimizer 802, separated by a distance 810. In at least one embodiment, the first surface 804a of the intermediate biasable flux optimizer 804 is a surface of one of the individual biasable flux optimizers of the intermediate biasable flux optimizer 804 adjacent to the second surface 802b of the top biasable flux optimizer 802. The second surface 804b of the intermediate biasable flux optimizer 804 may be adjacent to the bottom biasable flux optimizer 806. In at least one embodiment, the second surface 804b of the intermediate biasable flux optimizer 804 is the surface of one of the individual biasable flux optimizers adjacent to the bottom biasable flux optimizer 806 and separated by a distance 812 of about 500 mm or less, such as about 250 mm or less, such as about 100 mm or less, such as about 10 mm to about 500 mm, such as about 25 mm to about 250 mm, such as about 50 mm to about 100 mm, alternatively about 10 mm to about 25 mm, alternatively about 25 mm to about 50 mm, alternatively about 50 mm to about 75 mm, alternatively about 75 mm to about 100 mm, alternatively about 100 mm to about 250 mm, alternatively about 250 mm to about 500 mm.

[0083] The top biasable flux optimizer 806 can be configured according to any one or more flux optimizer configurations previously described. In at least one embodiment, the bottom biasable flux optimizer 806 is configured to be electrically grounded such that no voltage can be applied to it. In at least one embodiment, the bottom biasable flux optimizer 806 is electrically biased by applying a relative voltage to it via power supply 806c. In one or more embodiments, a voltage of about 10 V to about 200 V, such as about 50 V to about 150 V, such as about 70 V to about 120 V, alternatively about 10 V to about 50 V, alternatively about 50 V to about 70 V, alternatively about 70 V to about 100 V, alternatively about 100 V to about 120 V, alternatively about 120 V to about 150 V, alternatively about 150 V to about 200 V can be applied to the bottom biasable flux optimizer 806. As discussed above, in some embodiments, an RF bias can be applied to the bottom biasable flux optimizer 806.

[0084] In at least one embodiment, the second surface 806b of the bottom biasable flux optimizer 806 is separated from the substrate 205 by a distance 814 of about 500 mm or less, such as about 250 mm or less, such as about 100 mm or less, such as about 10 mm to about 500 mm, such as about 25 mm to about 250 mm, such as about 50 mm to about 100 mm, alternatively about 10 mm to about 25 mm, alternatively about 25 mm to about 50 mm, alternatively about 50 mm to about 75 mm, alternatively about 75 mm to about 100 mm, alternatively about 100 mm to about 250 mm, alternatively about 250 mm to about 500 mm.

[0085] In some embodiments, processing chamber 800 (such as processing chamber 200) includes a power supply 802c electrically coupled to a top biasable flux optimizer 802, a power supply 804c electrically coupled to an intermediate biasable flux optimizer 804, and a power supply 806c electrically coupled to a bottom biasable flux optimizer 806. Each of the power supplies (e.g., power supplies 802c, 804c, and 806c) can be independently controlled by controller 816 to independently establish a bias applied to one or more biasable flux optimizers (e.g., top biasable flux optimizer 802, intermediate biasable flux optimizer 804, and bottom biasable flux optimizer 806).

[0086] Controller 816 can be any type of controller used in an industrial setting, such as a programmable logic controller (PLC). Controller 816 includes a processor 818, memory 820, and input / output (I / O) circuitry 822. Controller 816 may further include one or more of the following components (not shown): such as one or more power supplies, frequency, communication components (e.g., a network adapter), and a user interface typically found in controllers used in semiconductor devices.

[0087] Memory 820 may include non-transitory memory. Non-transitory memory may be used to store programs and settings as described below. Memory 820 may include one or more readily available types of memory, such as read-only memory (ROM) (e.g., electrically erasable programmable read-only memory (EEPROM)), flash memory, floppy disk, hard disk, or random access memory (RAM) (e.g., non-volatile random access memory (NVRAM)).

[0088] Processor 818 is configured to execute various programs stored in memory 820, such as those configured to execute references. Figure 5The described method 500 is a program. During the execution of these programs, the controller 816 can communicate with the I / O device via I / O circuitry 822. For example, during the execution of these programs and the communication via I / O circuitry 822, the controller 816 can control the output (e.g., independently apply bias voltages to different flux optimizers).

[0089] In summary, this disclosure provides an apparatus including one or more biasable flux optimizers and a method for forming a thin film on the surface of a substrate. Voltage can be independently supplied to one or more biasable flux optimizers from one or more power supplies to maximize the ion fraction within the deposition plasma closer to the substrate during the deposition process. It has been found that the ion content can be maximized by independently varying the bias applied to the biasable flux optimizers and by independently tuning the space between them. Additionally, the space between the sputtering target and an adjacent biasable flux optimizer and / or the space between the substrate and the biasable flux optimizer can also be tuned to further increase the ion fraction within the deposition plasma.

[0090] Although the foregoing relates to embodiments of this disclosure, other and further embodiments of this disclosure may be designed without departing from its essential scope, which is defined by the following claims.

Claims

1. A physical vapor deposition apparatus, the physical vapor deposition apparatus comprising: A substrate support is disposed within the processing area of ​​the processing chamber of the physical vapor deposition apparatus, wherein the substrate support includes a substrate support surface. A first flux optimizer is disposed within the processing region and includes a plurality of orifices extending therethrough, the first flux optimizer being configured to be biased relative to a ground reference. A second flux optimizer is disposed within the processing area and includes a plurality of holes extending therethrough. The second flux optimizer is configured to be biased relative to the ground reference, wherein the second flux optimizer is disposed between the first flux optimizer and the substrate support. A first power supply is coupled to either the first or the second throughput optimizer, the first power supply being configured to supply a voltage to either the first or the second throughput optimizer, wherein the first power supply is configured to generate a bias voltage between the first and the second throughput optimizer.

2. The physical vapor deposition apparatus as described in claim 1, wherein... Each of the plurality of orifices in the first flux optimizer includes an opening extending through the first flux optimizer; Each of the plurality of orifices in the second flux optimizer includes an opening extending through the first flux optimizer, and The plurality of holes in the first flux optimizer and the second flux optimizer are aligned.

3. The physical vapor deposition apparatus of claim 1, wherein the first flux optimizer is biased by supplying a voltage relative to ground from the first power supply to the first flux optimizer.

4. The physical vapor deposition apparatus of claim 3, wherein the second flux optimizer is electrically grounded.

5. The physical vapor deposition apparatus of claim 1, wherein the second flux optimizer is biased by supplying a voltage from the first power source to the second flux optimizer.

6. The physical vapor deposition apparatus of claim 4, wherein the first flux optimizer is electrically grounded.

7. The physical vapor deposition apparatus as described in claim 1, wherein... The first power source is coupled to the first flux optimizer. The second power supply is coupled to the second flux optimizer, and A first bias voltage is applied to the first flux optimizer by supplying a voltage from the first power supply to the first flux optimizer, and a second bias voltage is applied to the second flux optimizer by supplying a voltage from the second power supply to the second flux optimizer.

8. The physical vapor deposition apparatus of claim 6, wherein a negative bias is supplied to the first flux optimizer relative to the second flux optimizer.

9. The physical vapor deposition apparatus of claim 6, wherein a positive bias is supplied to the first flux optimizer relative to the second flux optimizer.

10. A physical vapor deposition apparatus, the physical vapor deposition apparatus comprising: The top flux optimizer is configured to be biased; An intermediate flux optimizer is configured to be biased, wherein the top flux optimizer and the intermediate flux optimizer are separated by a first distance; A bottom flux optimizer is configured to be biased, wherein the bottom flux optimizer and the middle flux optimizer are separated by a second distance; Top power supply, coupled to the top flux optimizer; An intermediate power source is coupled to the intermediate throughput optimizer; and Bottom power supply, coupled to the bottom flux optimizer.

11. The physical vapor deposition apparatus of claim 10, wherein... The first distance and the second distance are between approximately 0.01 cm and 25 cm; The intermediate flux optimizer comprises multiple biasable flux optimizers, which are separated from each other by third distances of approximately 0.01 cm and approximately 25 cm.

12. The physical vapor deposition apparatus of claim 11, wherein at least one of the intermediate flux optimizers is biased by supplying a voltage from the intermediate power supply to the at least one biasable flux optimizer.

13. The physical vapor deposition apparatus of claim 11, wherein the plurality of biasable flux optimizers are independently biasable.

14. The physical vapor deposition apparatus of claim 10, wherein at least one of the top flux optimizer, the intermediate flux optimizer, and the bottom flux optimizer is electrically grounded.

15. The physical vapor deposition apparatus of claim 10, wherein a voltage of about 10 V to about 200 V from the top power supply is supplied to the top flux optimizer.

16. The physical vapor deposition apparatus of claim 10, wherein a voltage of about 10 V to about 200 V from the bottom power supply is supplied to the bottom flux optimizer.

17. A method for depositing a film onto a substrate, the method comprising: A bias voltage is applied to at least one of a plurality of biasable flux optimizers disposed in the processing region of the processing chamber, wherein the voltage is supplied by a power source. At least one of the plurality of biasable flux optimizers is grounded, and The plurality of biasable flux optimizers are positioned within the processing region between the sputtering target and the substrate support; and A film is formed on the surface of a substrate disposed on a substrate support by sputtering target material from the sputtering target by applying a bias voltage to the target.

18. The method of claim 17, wherein the plurality of biasable flux optimizers comprises a first flux optimizer and a second flux optimizer.

19. The method of claim 18, wherein the first flux optimizer is grounded and the second flux optimizer is biased.

20. The method of claim 18, wherein voltages are supplied to both the first throughput optimizer and the second throughput optimizer, and the voltage supplied to the second throughput optimizer is greater than the voltage supplied to the first throughput optimizer.

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