Dual input self-referenced voltage regulator

Abstract

An apparatus for voltage regulation is disclosed. In some implementations, the apparatus includes: a first voltage regulator configured to generate a regulated voltage at an output based on a first supply voltage on a first voltage rail; a second voltage regulator configured to generate the regulated voltage at the output based on a second supply voltage on a second voltage rail; and a control circuit configured to: in response to a first condition, maintain the first voltage regulator and the second voltage regulator to concurrently generate the regulated voltage; and in response to a second condition, prevent cross-coupling of the second supply voltage to the first voltage rail.

Description

Cross-references to related applications

[0001] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 514,440, filed November 20, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This disclosure relates in general to voltage regulators, and more particularly to dual-input self-referenced voltage regulators. Background Technology

[0003] A dual-input voltage regulator can be used to generate a regulated output voltage for a combination of one or more circuits. The first input of the dual-input voltage regulator can receive voltage from a battery. The second input can receive voltage from a battery charger. Managing the regulation of the output voltage based on the presence of one or both of the battery voltage and the charger voltage is of interest. Summary of the Invention

[0004] The following is a simplified overview of one or more specific implementations to provide a basic understanding of such implementations. This overview is not an exhaustive summary of all envisioned implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0005] One aspect of this disclosure relates to an apparatus. The apparatus includes: a first voltage regulator configured to generate an regulated voltage at an output based on a first power supply voltage on a first voltage rail; a second voltage regulator configured to generate the regulated voltage at the output based on a second power supply voltage on a second voltage rail; and a control circuit configured to: maintain simultaneous generation of the regulated voltage by the first voltage regulator and the second voltage regulator in response to a first condition; and prevent cross-coupling of the second power supply voltage to the first voltage rail in response to a second condition.

[0006] Another aspect of this disclosure relates to a method. The method includes: generating an regulated voltage at an output based on a first supply voltage on a first voltage rail, based on a first condition; generating the regulated voltage based on a second supply voltage on a second voltage rail, based on a second condition; and decoupling the first voltage rail from the output in response to a third condition.

[0007] Another aspect of this disclosure relates to an apparatus. The apparatus includes: a first voltage regulator configured to generate an regulated voltage at an output based on a first power supply voltage on a first voltage rail; a second voltage regulator configured to generate the regulated voltage at the output based on a second power supply voltage on a second voltage rail; and a control circuit configured to: simultaneously couple the first voltage rail and the second voltage rail to the output in response to a first condition; and decouple the first voltage rail from the output in response to a second condition.

[0008] Another aspect of this disclosure relates to an apparatus. The apparatus includes: components for generating an regulated voltage at an output terminal based on a first power supply voltage on a first voltage rail, based on a first condition; components for generating the regulated voltage based on a second power supply voltage on a second voltage rail, based on a second condition; and components for decoupling the first voltage rail from the output terminal in response to a third condition.

[0009] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the description of the embodiments is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] Figure 1 A schematic diagram / block diagram of an example dual-input voltage regulator according to one aspect of this disclosure is illustrated.

[0011] Figure 2 A schematic diagram / block diagram of an example dual-input self-reference voltage regulator according to one aspect of this disclosure is illustrated.

[0012] Figure 3 A schematic diagram / block diagram of an example Brokaw cell according to another aspect of this disclosure is illustrated.

[0013] Figure 4 A schematic / block diagram of another example of a dual-input self-reference voltage regulator according to one aspect of this disclosure is illustrated.

[0014] Figure 5 A flowchart illustrating an example method for generating a regulated voltage according to another aspect of this disclosure is provided.

[0015] Figure 6 A block diagram illustrating an example integrated circuit (IC) or system-on-a-chip (SOC) according to another aspect of this disclosure is shown. Detailed Implementation

[0016] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0017] Some integrated circuits (ICs), including systems-on-chips (SoCs), may include some circuitry that still draws power from a battery when in a shutdown mode (e.g., when “on the shelf” for subsequent product distribution). In many cases, such circuitry is implemented at relatively small process nodes, such as 22 nanometers (nm) or 40 nm. Due to the small nature of the devices at such process nodes, the circuitry may not be able to directly accept battery voltages (e.g., 2.7 volts (V) to 4.8V), as this would exceed the reliability limits of the devices used in these circuits. Accordingly, such ICs or SoCs may include integrated voltage regulators to reduce the battery voltage to a level more suitable for such circuitry (e.g., 2.45V).

[0018] Typically, integrated voltage regulators consume some current when performing battery voltage reduction. Integrated voltage regulators can also be dual-input voltage regulators, receiving both the battery voltage and the battery charger voltage (when present). As illustrated in further detail below, the integrated voltage regulator should quickly sense the charger voltage (especially when it is unplugged) so that it can switch from the charger voltage to the battery voltage while preventing the circuit's output regulated voltage from dropping too low. If it drops too low, the circuit may malfunction or be damaged. Therefore, integrated voltage regulators typically utilize fast control circuitry to perform the switching between battery and charger voltages. And, therefore, integrated voltage regulators can consume a significant amount of current (e.g., 1.6 microamps (μA)).

[0019] Figure 1A schematic / block diagram of an example dual-input voltage regulator 100 according to one aspect of this disclosure is illustrated. The voltage regulator 100 includes a first input configured to receive a battery charger voltage VCHG and a second input configured to receive a battery voltage VBAT. The voltage regulator 100 includes a multiplexer 105 comprising a first switching device M11 (e.g., a p-channel field-effect transistor (FET)), a first diode D11, a first resistive device (e.g., a resistor) R11, and a first driver 120. Additionally, the multiplexer 105 includes a second switching device M12 (e.g., a p-channel FET), a second diode D12, a second resistive device (e.g., a resistor) R12, and a second driver 130.

[0020] A first switching device M11 (e.g., drain and source) and a first diode D11 (e.g., in the forward direction or in a pn junction, respectively) are coupled between the charger voltage VCHG input and the output (VMAX) of the multiplexer 105. Similarly, a second switching device M12 (e.g., source and drain) and a second diode D12 (e.g., in the forward direction or in a pn junction, respectively) are coupled between the battery voltage VBAT input and the output of the multiplexer 105. Along a first current path, a first resistor R11 is coupled in series with a first driver 120 between the source of the first switching device M11 and the current sink 150 (e.g., a temperature-per-absolute (PTAT) current sink). Similarly, along a second current path, a second resistor R12 is coupled in series with a second driver 130 between the source of the second switching device M12 and the current sink 150.

[0021] The voltage regulator 100 also includes a comparator 110, which includes a first (e.g., positive) input configured to receive a charger voltage VCHG and a second (e.g., negative) input configured to receive a battery voltage VBAT. The comparator 110 includes an output coupled to a first driver 120 and coupled to a second driver 130 via an inverter 140. The multiplexer 105 is configured to select either the charger voltage VCHG or the battery voltage VBAT as the output voltage VMAX of the multiplexer 105 based on the comparison performed by the comparator 110.

[0022] For example, if the charger voltage VCHG is greater than the battery voltage VBAT, comparator 110 outputs an assertion select (SEL) control signal (e.g., logic 1 (1)), and inverter 140 generates a deassertion select (SEL) control signal (e.g., logic 0 (0)). The assertion SEL signal activates the first driver 120 to draw current from the source of the first switching device M11 via the first resistor R11 to reduce the gate voltage of the first switching device M11; and thereby turns on the first switching device M11. This causes the multiplexer 105 to output the charger voltage VCHG as VMAX. The deassertion SEL signal does not activate the second driver 130, and therefore, the second switching device M12 is turned off.

[0023] Conversely, if the charger voltage VCHG is less than the battery voltage VBAT, comparator 110 outputs a de-assertion select (SEL) control signal (e.g., logic zero (0)), and inverter 140 generates an assertion select (SEL) control signal (e.g., logic one (1)). The assertion SEL signal activates the second driver 130 to draw current from the source of the second switching device M12 via the second resistor R11 to reduce the gate voltage of the second switching device M12; and thereby turn on the second switching device M12. This causes the multiplexer 105 to output the charger voltage VBAT as VMAX. The de-assertion SEL signal does not activate the first driver 120, and therefore, the first switching device M11 is turned off.

[0024] The multiplexer output voltage VMAX is supplied to current sink 150 for operation and to sub-regulator 160 based on threshold voltage Vt. Sub-regulator 160 based on Vt generates a regulated voltage VBR based on the multiplexer output voltage VMAX. The regulated voltage VBR can be supplied to one or more circuits, such as an IC or SOC, which are referred to herein as a capacitive load Cout and a resistive load Rout. As previously discussed, such circuitry can operate in shutdown mode or during shelf life; and therefore, the battery current consumption of the voltage regulator should be kept low to extend product shelf life.

[0025] However, when the charger is disconnected from the voltage regulator 100 (e.g., the charger voltage VCHG is present and then unplugged), a fast response from the voltage regulator 100 is expected; otherwise, the multiplexer output voltage VMAX may drop to a level where the Vt-based sub-regulator 160 may not be able to correctly generate the regulated voltage VBR. Therefore, comparators 110, drivers 120 and 130, and a current sink 150 are implemented to draw a large current to achieve the fast time required to prevent the multiplexer output voltage VMAX from dropping too low. As discussed, this large current can shorten the product's shelf life, which is generally undesirable. As a supplementary note, the first diode D11 and the second diode D12 are used for startup purposes to generate an initial voltage VMAX based on the diode voltage drops from the charger voltage VCHG and the battery voltage VBAT, respectively.

[0026] Figure 2 A schematic / block diagram of an example dual-input self-reference voltage regulator 200 according to one aspect of this disclosure is illustrated. As discussed in more detail, voltage regulator 200 includes two voltage regulators associated with a charger and a battery, which are simultaneously activated or operable for voltage regulation purposes based on certain conditions. For example, both voltage regulators are activated simultaneously when the charger voltage VCHG is greater than the battery voltage VBAT (and the battery voltage VBAT is greater than the regulation voltage VBR, e.g., not in a battery depletion scenario). In this case, if the charger is removed, the battery voltage regulator continues to generate the regulation voltage VBR, which prevents a drop in the regulation voltage VBR, as is the case with voltage regulator 100.

[0027] In response to the removal of the charger from the voltage regulator 200, the charger voltage regulator decouples its voltage rail from the output of the voltage regulator 200 to prevent cross-coupling of the battery voltage VBAT to the charger voltage rail. Additionally, if the charger voltage VCHG is present and the battery is depleted such that the battery voltage VBAT is less than the regulated voltage VBR, the battery voltage regulator decouples its voltage rail from the output of the voltage regulator 200 to prevent cross-coupling of the charger voltage VCHG to the battery voltage rail.

[0028] Specifically, the voltage regulator 200 includes a charger voltage regulator 210, a battery voltage regulator 220, and a control circuit, which includes a first comparator 230 and a second comparator 240.

[0029] Charger voltage regulator 210 includes a first resistive device R21 (e.g., the resistive device may be a resistor or other type of resistive device), a second resistive device R22, and a FET M21 (e.g., an n-channel FET) coupled in series between the charger voltage rail VCHG and a lower voltage rail (e.g., ground). Charger voltage regulator 210 also includes an inverter 215, which includes an input coupled to the output of a first comparator 230 and an output coupled to the gate of FET M21. Charger voltage regulator 210 also includes FETs M23 and M24 (e.g., p-channel FETs) coupled in series between the charger voltage rail VCHG and the lower voltage rail, as well as resistive devices R25 and R26. Additionally, charger voltage regulator 210 includes a first diode D21 and a second diode D22 coupled in parallel with the drain / source of FET M23 and the source / drain of FET M24 in the forward bias direction and the reverse bias direction, respectively.

[0030] The charger voltage regulator 210 additionally includes a FET M22 (e.g., a p-channel FET) comprising a gate coupled to a node between resistive devices R21 and R22, a drain coupled to the gates of FETs M23 and M24, respectively, and a source coupled to the sources of FETs M23 and M24, respectively. Furthermore, the charger voltage regulator 210 includes a Brokaw cell 250 comprising an input coupled to a node between resistive devices R25 and R26, and an output coupled to the gates of FETs M23 and M24, respectively. The Brokaw cell 250 is coupled between the sources of FETs M23 and M24 to receive a bias voltage vmidc therefrom, and is coupled between lower voltage rails.

[0031] The battery voltage regulator 220 is structurally similar to the charger voltage regulator 210. The battery voltage regulator 220 includes a first resistive device R23, a second resistive device R22, and a FET M25 (e.g., an n-channel FET) series coupled between the battery voltage rail VBAT and the lower voltage rail. FET M25 includes a gate coupled to the output of a second comparator 240. The battery voltage regulator 220 also includes FETs M27 and M28 (e.g., p-channel FETs) series coupled between the battery voltage rail VBAT and the lower voltage rail, as well as resistive devices R27 and R28. Additionally, the battery voltage regulator 220 includes a first diode D23 and a second diode D24 coupled in parallel with the drain / source of FET M27 and the source / drain of FET M28 in the forward bias direction and the reverse bias direction, respectively.

[0032] Battery voltage regulator 220 additionally includes FET M26 (e.g., a p-channel FET) including a gate coupled to a node between resistive devices R23 and R24, a drain coupled to the gates of FET M27 and FET M28, respectively, and a source coupled to the sources of FET M27 and FET M28, respectively. Furthermore, battery voltage regulator 220 includes a Brokaw cell 260, which includes an input coupled to a node between resistive devices R27 and R28, and an output coupled to the gates of FET M27 and FET M28, respectively. Brokaw cell 260 is coupled between the sources of FET M27 and FET M28 to receive a bias voltage vmidb therefrom, and is coupled between lower voltage rails.

[0033] Voltage regulator 200 includes an output terminal coupled to the node between FET M24 and FET M28 and resistive devices R25 and R27, respectively. A load (e.g., one or more circuits) represented by capacitive load Cout and resistive load Rout is coupled between the output terminal of voltage regulator 200 and the lower voltage rail.

[0034] The first comparator 230 includes a first (e.g., positive) input configured to receive a charger voltage VCHG and a second (e.g., negative) input configured to receive a battery voltage VBAT. Note that, for ease of explanation, voltage rails and corresponding voltages are referred to by the same term. As mentioned, the output of the first comparator 230 is coupled to the input of the inverter 215 and the enable (EN) input of the second comparator 240. The second comparator 240 then includes a first (e.g., negative) input configured to receive the battery voltage VBAT and a second (e.g., positive) input configured to receive a regulated voltage VBR at the output of the voltage regulator 200. As mentioned, the output of the second comparator 240 is coupled to the gate of the FET M25.

[0035] In operation, both charger voltage regulator 210 and battery voltage regulator 220 are active or operational for voltage regulation purposes when the charger voltage VCHG is greater than the battery voltage VBAT and the battery voltage VBAT is greater than the output regulated voltage VBR, respectively. That is, both Brokaw cells 250 and 260 perform voltage regulation based on feedback voltages vfbc and vfbb at the nodes between resistor devices R25 / R26 and R27 / R28 to control FETs M23 / M24 and M27 / M28 to generate the regulated voltage VBR at the output of voltage regulator 200, respectively. This is because the first comparator 230 generates a logic low voltage at the gate of FET M21 via inverter 215, thereby keeping FET M21 off. This causes FETs M23 and M24 to turn on, as discussed further herein. Similarly, a second comparator 240, enabled by the logic high voltage generated by the first comparator 230, generates a logic low voltage at the gate of FET M25, thereby keeping FET M25 off. This causes FETs M27 and M28 to turn on, as discussed further in this paper.

[0036] More specifically, referring to charger voltage regulator 210, when the charger voltage VCHG is greater than the battery voltage VBAT, the first comparator 230 generates a high logic voltage. Inverter 215 inverts the high logic voltage and applies a low logic voltage to the gate of FET M21 to turn off FET M21. When FET M21 is off, essentially no current flows from the charger voltage rail VCHG to the lower voltage rail via resistors R21 and R22. Accordingly, the gate of FET M22 is essentially at the charger voltage potential, which turns off FET M22. Therefore, FET M22, which is source-gate coupled across FET M23 and FET M24, does not turn off FET M23 and FET M24. And therefore, Brokaw cell 250 is able to perform regulation of the output voltage VBR by controlling FET M23 and FET M24 to continue operating based on the feedback voltage vfbc obtained from the node between resistors R25 and R26.

[0037] Similarly, referring to battery voltage regulator 230, when the battery voltage VBAT is greater than the regulation voltage VBR, the second comparator 240 generates a low logic voltage. This low logic voltage is applied to the gate of FET M25 to turn it off. When FET M25 is off, essentially no current flows from the battery voltage rail VBAT to the lower voltage rail via resistors R23 and R24. Accordingly, the gate of FET M26 is essentially at the battery voltage potential, which turns off FET M26. Therefore, FET M26, which is source-gate coupled across FETs M27 and M28, does not turn off FETs M27 and M28. And thus, Brokaw cell 260 can perform regulation of the output voltage VBR by controlling FETs M27 and M28 to continue operating based on the feedback voltage vfbb obtained from the node between resistors R27 and R28.

[0038] In the second condition (e.g., battery depletion condition) where the charger voltage VCHG is greater than the battery voltage VBAT and the battery voltage VBAT is less than the output regulation voltage VBR, the charger voltage regulator 210 remains active or operational for voltage regulation purposes as previously discussed, while the battery voltage regulator 220 is disabled, preventing cross-coupling of the charger voltage VCHG to the battery voltage rail VBAT. In this case, the second comparator 240 generates a high logic voltage to turn on FET M25. Therefore, a current path from the battery voltage rail VBAT to the lower voltage rail is formed via resistors R23 and R24 and FET M25. This causes a voltage drop at the gate of FET M26, thereby turning on FET M26. The turned-on FET M26 short-circuits the source-gate of FETs M27 and M28, thereby turning off FETs M27 and M28. Therefore, this prevents the charger voltage VCHG from cross-coupling to the battery voltage rail VBAT via the output.

[0039] Under the third condition that the charger voltage VCHG is less than the battery voltage VBAT, the first comparator 230 outputs a logic low voltage. A logic low voltage supplied to the enable input of the second comparator 240 disables the second comparator 240; and thus, FET M25 remains off. In this case, as discussed above, the battery voltage regulator 220 is activated or operational for voltage regulation purposes. Referring to the charger voltage regulator 210, the inverter 215 inverts the logic low voltage to generate a logic high voltage to turn on FET M21. Therefore, a current path is formed from the charger voltage rail VCHG to the lower voltage rail via resistors R21 and R22 and FET M21. This causes a voltage drop at the gate of FET M22; and thus turns on FET M22. The turned-on FET M22 short-circuits the source-gate of FETs M23 and M24; thus turning off FETs M23 and M24. Therefore, this prevents the battery voltage VBAT from being cross-coupled to the charger voltage rail VCHG via the output.

[0040] Resistors R25, R26, R27, and R28 can be configured such that, when both the charger voltage regulator 210 and the battery voltage regulator 220 are active or operational, the feedback voltage vfbc provided to the input of the Brokaw cell 250 is greater than the feedback voltage vfbb provided to the input of the Brokaw cell 260. The higher feedback voltage vfbc allows the Brokaw cell 250 to drive FETs M23 and M24 more strongly than the Brokaw cell 260. This allows the output regulated voltage to be based more on the current from the charger than on the current from the battery, thus conserving battery life.

[0041] As an additional supplementary explanation, during regulator startup, when both charger voltage VCHG and battery voltage VBAT are present, diodes D21 and D23 provide bias voltages vmidc and vmidb to Brokaw cells 250 and 260, respectively. When charger voltage regulator 210 is disabled and battery voltage regulator 220 is enabled, diode D22 provides bias voltage vmidc to Brokaw cell 250 from its output. Similarly, when battery voltage regulator 260 is disabled and charger voltage regulator 210 is enabled, D24 provides bias voltage vmidb to Brokaw cell 260 from its output.

[0042] Figure 3A schematic / block diagram of an example Brokaw cell 300 according to another aspect of this disclosure is illustrated. Brokaw cell 300 may be an example implementation of either Brokaw cells 250 or 260 of voltage regulator 200. Specifically, Brokaw cell 300 includes a first FET Mp1 (e.g., a p-channel FET), a second FET Mphv1 (e.g., a p-channel FET), a third FET Mnhv1 (e.g., an n-channel FET), and a first bipolar junction transistor (BJT) Q1, which are coupled in series via their source / drain-drain / source and collector-emitter connections between node vmid (e.g., the node that generates bias voltages vmidc or vmidb, as previously discussed) and node n1.

[0043] Brokaw cell 300 includes a fourth FET Mp2 (e.g., a p-channel FET), a fifth FET Mphv2 (e.g., a p-channel FET), a sixth FET Mnhv2 (e.g., an n-channel FET), and a second BJT Q2, which are coupled in series between node vmid and node n1 via their source / drain-drain / source and collector-emitter connections (and include a resistive device (e.g., resistor) R33). Brokaw cell 300 also includes another resistive device R34 coupled between node n1 and a lower voltage rail (e.g., ground).

[0044] The gates of FETs Mp1 and Mp2 are coupled together and to the drain of FET Mp1 to form a current mirror, producing substantially the same current in each current branch or path. The gates of FETs Mphv1 and Mphv2 (e.g., having a higher reliability voltage compared to Mp1 / Mp2 to protect BJT Q1 and BJT Q2) are coupled together and to the drain of FET Mphv1. The gates of FETs Mnhv1 and Mnhv2 (also having a higher reliability voltage compared to Mp1 / Mp2) are coupled together via a resistor device R31 and are configured to improve the matching between the collectors of BJT Q1 and BJT Q2 via a cascode voltage vcasc generated at the gate of FET Mnhv1. The bases of BJT Q1 and BJT Q2 are coupled together via a resistor device R32. The size of BJT Q2 can be, for example, N times the size of BJT Q1 (e.g., 14 times, depending on the application). The feedback voltage vfb (e.g., vfbc or vfbb of voltage regulator 200) can be provided to the base of BJT Q1. The output of Brokaw cell 300 is located at the node between the drains of FET Mphv2 and FET Mnhv2, and is connected to the gates of M24 / M23 for VCHG-side regulator 210 and M28 / M27 for VBAT-side regulator 220.

[0045] Figure 4 A schematic / block diagram of another example of a dual-input self-reference voltage regulator 400 according to one aspect of this disclosure is illustrated. The voltage regulator 400 includes a first voltage regulator 410 configured to generate a regulated voltage VBR at an output (which may be coupled to a load (represented as a capacitive load Cout and a resistive load Rout), such as one or more circuits of an IC or SOC) based on a first supply voltage on a first voltage rail VS1. The voltage regulator 400 also includes a second voltage regulator 420 configured to generate the regulated voltage VBR at the output based on a second supply voltage on a second voltage rail VS2.

[0046] Additionally, the voltage regulator 400 includes a control circuit 430 configured to: maintain the first voltage regulator and the second voltage regulator simultaneously generating a regulated voltage in response to a first condition (COND1) received at the first input (e.g., VS1>VS2); and prevent cross-coupling of the second power supply voltage to the first voltage rail in response to a second condition (COND2) received at the second input (e.g., VS2>VS1).

[0047] Figure 5A flowchart illustrating an example method 500 for generating a regulated voltage according to another aspect of this disclosure is shown. Method 500 includes generating a regulated voltage at an output based on a first supply voltage on a first voltage rail, based on a first condition (block 510). Examples of components for generating a regulated voltage at an output based on the first supply voltage on the first voltage rail, based on the first condition, include a first voltage regulator 410; and more specifically, include a Brokaw cell 250, FETs M23 and M24, and resistive devices R21 and R22.

[0048] Method 500 further includes generating a regulated voltage based on a second supply voltage on a second voltage rail, based on a second condition (block 520). Examples of components for generating the regulated voltage based on the second supply voltage on a second voltage rail, based on the second condition, include a second voltage regulator 420; and more specifically, include a Brokaw cell 260, FETs M27 and M28, and resistive devices R25 and R26.

[0049] Furthermore, method 500 includes decoupling the first voltage rail from the output in response to a third condition (block 530). Examples of components for decoupling the first voltage rail from the output in response to the third condition include a first voltage regulator 410, and more specifically, FET M23.

[0050] The following provides an overview of the various aspects of this disclosure: Aspect 1: An apparatus comprising: a first voltage regulator configured to generate an regulated voltage at an output based on a first power supply voltage on a first voltage rail; a second voltage regulator configured to generate the regulated voltage at the output based on a second power supply voltage on a second voltage rail; and a control circuit configured to: maintain simultaneous generation of the regulated voltage by the first voltage regulator and the second voltage regulator in response to a first condition; and prevent cross-coupling of the second power supply voltage to the first voltage rail in response to a second condition.

[0051] Aspect 2: The apparatus according to aspect 1, wherein the first condition includes the first power supply voltage being greater than the second power supply voltage.

[0052] Aspect 3: The apparatus according to aspect 1 or 2, wherein the second condition includes the first power supply voltage being less than the second power supply voltage.

[0053] Aspect 4: The apparatus according to any one of Aspects 1 to 3, wherein the control circuitry includes a first comparator configured to generate a first control signal based on a first power supply voltage and a second power supply voltage, wherein the first voltage regulator includes a field-effect transistor (FET) coupled between the first voltage rail and the output terminal, wherein the FET is configured to turn off based on the first control signal.

[0054] Aspect 5: The apparatus according to aspect 4, wherein the FET is configured to generate the regulated voltage in response to the first control signal indicating that the first power supply voltage is greater than the second power supply voltage.

[0055] Aspect 6: The apparatus according to aspect 4 or 5, wherein the FET is configured to turn off in response to the first control signal indicating that the first power supply voltage is less than the second power supply voltage.

[0056] Aspect 7: The apparatus according to any one of aspects 1 to 6, wherein the control circuit is further configured to prevent cross-coupling of the first power supply voltage to the second voltage rail in response to a third condition.

[0057] Aspect 8: The apparatus according to aspect 7, wherein the third condition includes the second power supply voltage being less than the regulated voltage.

[0058] Aspect 9: The apparatus according to aspect 8, wherein the third condition includes the second power supply voltage being greater than the first power supply voltage.

[0059] Aspect 10: The apparatus according to aspect 9, wherein the control circuitry includes: a first comparator configured to generate a first control signal based on a first power supply voltage and a second power supply voltage; and a second comparator configured to generate a second control signal based on the second power supply voltage and the regulated voltage, wherein the second comparator is configured to be enabled based on the first control signal.

[0060] Aspect 11: The apparatus according to aspect 10, wherein the second comparator is configured to be enabled in response to the first control signal indicating that the first power supply voltage is greater than the second power supply voltage.

[0061] Aspect 12: The apparatus according to aspect 11, wherein the second voltage regulator includes a field-effect transistor (FET) coupled between the second voltage rail and the output terminal, wherein the FET is configured to be turned off based on the second control signal.

[0062] Aspect 13: The apparatus according to aspect 12, wherein the FET is configured to turn off in response to the second control signal indicating that the second power supply voltage is less than the regulated voltage.

[0063] Aspect 14: An apparatus according to any one of Aspects 1 to 13, wherein the first voltage regulator comprises: a first field-effect transistor (FET), a second FET, a first resistive device and a second resistive device, the first field-effect transistor (FET), the second FET, the first resistive device and the second resistive device being coupled in series between a first voltage rail and a third voltage rail, wherein a first node between the second FET and the first resistive device is coupled to the output terminal; and a first Brokaw cell, the first Brokaw cell comprising an input terminal coupled to a second node between the first resistive device and the second resistive device and an output terminal coupled to the gate of the first FET and the gate of the second FET, respectively.

[0064] Aspect 15: The apparatus according to aspect 14, wherein the second voltage regulator comprises: a third FET, a fourth FET, a third resistive device, and a fourth resistive device, the third FET, the fourth FET, the third resistive device, and the fourth resistive device being coupled in series between the second voltage rail and the third voltage rail, wherein a third node between the fourth FET and the third resistive device is coupled to the output terminal; and a second Brokaw cell, the second Brokaw cell comprising an input terminal coupled to the fourth node between the third resistive device and the fourth resistive device and an output terminal respectively coupled to the gate of the third FET and the gate of the fourth FET.

[0065] Aspect 16: The apparatus according to aspect 15, wherein the first resistor device, the second resistor device, the third resistor device and the fourth resistor device are configured to provide a first feedback voltage to the input of the first Brokaw cell, the first feedback voltage being greater than a second feedback voltage provided to the input of the second Brokaw cell.

[0066] Aspect 17: The apparatus according to any one of aspects 1 to 16, wherein at least one of the first voltage regulator or the second voltage regulator comprises a Brokaw cell.

[0067] Aspect 18: The apparatus according to Aspect 17, wherein the Brokaw cell comprises: a first field-effect transistor (FET), a second FET, a third FET, and a first bipolar junction transistor (BJT), the first FET, the second FET, the third FET, and the first BJT being coupled between a first node and a second node; a fourth FET, a fifth FET, a sixth FET, a second BJT, and a first resistive device, the fourth FET, the fifth FET, the sixth FET, the second BJT, and the first resistive device being coupled between the first node and the second node; a second resistive device being coupled between the second node and a third voltage rail; a third resistive device being coupled between the gate of the third FET and the gate of the sixth FET; and a fourth resistive device being coupled between the base of the first BJT and the base of the second BJT; wherein the gates of the first FET and the third FET are coupled together, and the gates of the second FET and the fourth FET are coupled together.

[0068] Aspect 19: The apparatus according to aspect 18, wherein the first FET, the second FET, the fourth FET and the fifth FET are p-channel FETs, and wherein the third FET and the sixth FET are n-channel FETs.

[0069] Aspect 20: The apparatus according to aspect 18 or 19, wherein the size of the second BJT is greater than the size of the first BJT.

[0070] Aspect 21: A method comprising: generating an regulated voltage at an output based on a first supply voltage on a first voltage rail based on a first condition; generating the regulated voltage based on a second supply voltage on a second voltage rail based on a second condition; and decoupling the first voltage rail from the output in response to a third condition.

[0071] Aspect 22: According to the method of aspect 21, the first condition includes the first power supply voltage being greater than the second power supply voltage.

[0072] Aspect 23: The method according to aspect 21 or 22, wherein the second condition includes the first power supply voltage being greater than the second power supply voltage and the second power supply voltage being greater than the regulated voltage.

[0073] Aspect 24: The method according to any one of aspects 21 to 23, wherein the third condition includes the first power supply voltage being less than the second power supply voltage.

[0074] Aspect 25: The method according to any one of aspects 21 to 24, the method further comprising decoupling the second voltage rail from the output terminal in response to a fourth condition.

[0075] Aspect 26: According to the method of aspect 25, the fourth condition includes the second power supply voltage being greater than the first power supply voltage.

[0076] Aspect 27: An apparatus comprising: a first voltage regulator configured to generate an regulated voltage at an output based on a first power supply voltage on a first voltage rail; a second voltage regulator configured to generate the regulated voltage at the output based on a second power supply voltage on a second voltage rail; and control circuitry configured to: simultaneously couple the first voltage rail and the second voltage rail to the output in response to a first condition; and decouple the first voltage rail from the output in response to a second condition.

[0077] Aspect 28: The apparatus according to aspect 27, wherein the first condition includes the first power supply voltage being greater than the second power supply voltage.

[0078] Aspect 29: The apparatus according to aspect 27 or 28, wherein the second condition includes the first power supply voltage being less than the second power supply voltage.

[0079] Aspect 30: An apparatus comprising: means for generating an regulated voltage at an output based on a first power supply voltage on a first voltage rail based on a first condition; means for generating the regulated voltage based on a second power supply voltage on a second voltage rail based on a second condition; and means for decoupling the first voltage rail from the output in response to a third condition.

[0080] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: A first voltage regulator is configured to generate a regulated voltage at its output based on a first supply voltage on a first voltage rail. A second voltage regulator is configured to generate the regulated voltage at the output based on a second power supply voltage on a second voltage rail; and Control circuit, the control circuit being configured to: In response to a first condition, the first voltage regulator and the second voltage regulator simultaneously generate the regulated voltage; and In response to a second condition, cross-coupling of the second power supply voltage to the first voltage rail is prevented.

2. The apparatus according to claim 1, wherein the first condition includes the first power supply voltage being greater than the second power supply voltage.

3. The apparatus of claim 1, wherein the second condition includes the first power supply voltage being less than the second power supply voltage.

4. The apparatus of claim 1, wherein the control circuitry includes a first comparator configured to generate a first control signal based on the first power supply voltage and the second power supply voltage, wherein the first voltage regulator includes a field-effect transistor (FET) coupled between the first voltage rail and the output terminal, wherein the FET is configured to turn off based on the first control signal.

5. The apparatus of claim 4, wherein the FET is configured to generate the regulated voltage in response to the first control signal indicating that the first power supply voltage is greater than the second power supply voltage.

6. The apparatus of claim 4, wherein the FET is configured to turn off in response to the first control signal indicating that the first power supply voltage is less than the second power supply voltage.

7. The apparatus of claim 1, wherein the control circuit is further configured to prevent cross-coupling of the first power supply voltage to the second voltage rail in response to a third condition.

8. The apparatus of claim 7, wherein the third condition includes the second power supply voltage being less than the regulated voltage.

9. The apparatus of claim 8, wherein the third condition includes the second power supply voltage being greater than the first power supply voltage.

10. The apparatus of claim 9, wherein the control circuit comprises: A first comparator is configured to generate a first control signal based on the first power supply voltage and the second power supply voltage; and A second comparator is configured to generate a second control signal based on the second power supply voltage and the regulated voltage, wherein the second comparator is configured to be enabled based on the first control signal.

11. The apparatus of claim 10, wherein the second comparator is configured to be enabled in response to the first control signal indicating that the first power supply voltage is greater than the second power supply voltage.

12. The apparatus of claim 11, wherein the second voltage regulator includes a field-effect transistor (FET) coupled between the second voltage rail and the output terminal, wherein the FET is configured to be turned off based on the second control signal.

13. The apparatus of claim 12, wherein the FET is configured to turn off in response to the second control signal indicating that the second power supply voltage is less than the regulated voltage.

14. The apparatus of claim 1, wherein the first voltage regulator comprises: A first field-effect transistor (FET), a second FET, a first resistive device, and a second resistive device are connected in series between a first voltage rail and a third voltage rail, wherein a first node between the second FET and the first resistive device is coupled to the output terminal; and The first Brokaw cell includes an input terminal coupled to a second node between the first resistive device and the second resistive device, and an output terminal coupled to the gate of the first FET and the gate of the second FET, respectively.

15. The apparatus of claim 14, wherein the second voltage regulator comprises: A third FET, a fourth FET, a third resistor device, and a fourth resistor device are connected in series between the second voltage rail and the third voltage rail, wherein a third node between the fourth FET and the third resistor device is coupled to the output terminal; and The second Brokaw cell includes an input terminal coupled to a fourth node between the third and fourth resistive devices and an output terminal coupled to the gates of the third and fourth FETs, respectively.

16. The apparatus of claim 15, wherein the first resistor device, the second resistor device, the third resistor device, and the fourth resistor device are configured to provide a first feedback voltage to the input of the first Brokaw cell, the first feedback voltage being greater than a second feedback voltage provided to the input of the second Brokaw cell.

17. The apparatus of claim 1, wherein at least one of the first voltage regulator or the second voltage regulator comprises a Brokaw cell.

18. The apparatus of claim 17, wherein the Brokaw cell comprises: A first field-effect transistor (FET), a second FET, a third FET, and a first bipolar junction transistor (BJT) are coupled between a first node and a second node. A fourth FET, a fifth FET, a sixth FET, a second BJT, and a first resistive device, wherein the fourth FET, the fifth FET, the sixth FET, the second BJT, and the first resistive device are coupled between the first node and the second node; A second resistor device is coupled between the second node and the third voltage rail; A third resistive device is coupled between the gate of the third FET and the gate of the sixth FET; and A fourth resistor device is coupled between the base of the first BJT and the base of the second BJT. The gates of the first FET and the third FET are coupled together, and the gates of the second FET and the fourth FET are coupled together.

19. The apparatus of claim 18, wherein the first FET, the second FET, the fourth FET, and the fifth FET are p-channel FETs, and wherein the third FET and the sixth FET are n-channel FETs.

20. The apparatus of claim 18, wherein the size of the second BJT is greater than the size of the first BJT.

21. A method, the method comprising: Based on the first condition, a regulating voltage is generated at the output terminal based on the first power supply voltage on the first voltage rail; The regulating voltage is generated based on the second condition and the second power supply voltage on the second voltage rail. as well as In response to a third condition, the first voltage rail is decoupled from the output terminal.

22. The method of claim 21, wherein the first condition includes the first power supply voltage being greater than the second power supply voltage.

23. The method of claim 21, wherein the second condition includes the first power supply voltage being greater than the second power supply voltage and the second power supply voltage being greater than the regulated voltage.

24. The method of claim 21, wherein the third condition includes the first power supply voltage being less than the second power supply voltage.

25. The method of claim 21, further comprising decoupling the second voltage rail from the output in response to a fourth condition.

26. The method of claim 25, wherein the fourth condition includes the second power supply voltage being greater than the first power supply voltage.

27. An apparatus comprising: A first voltage regulator is configured to generate a regulated voltage at its output based on a first supply voltage on a first voltage rail. A second voltage regulator is configured to generate the regulated voltage at the output based on a second power supply voltage on a second voltage rail; and Control circuit, the control circuit being configured to: In response to a first condition, the first voltage rail and the second voltage rail are simultaneously coupled to the output terminal; and In response to a second condition, the first voltage rail is decoupled from the output terminal.

28. The apparatus of claim 27, wherein the first condition includes the first power supply voltage being greater than the second power supply voltage.

29. The apparatus of claim 27, wherein the second condition includes the first power supply voltage being less than the second power supply voltage.

30. An apparatus comprising: A component for generating a regulated voltage at the output terminal based on a first supply voltage on a first voltage rail, based on a first condition; A component for generating the regulated voltage based on a second condition and a second power supply voltage on a second voltage rail; and A component for decoupling the first voltage rail from the output terminal in response to a third condition.

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