Integrated circuit device with zener diode for reducing leakage and / or increasing breakdown voltage

Abstract

A method (1100) forms an integrated circuit, the steps of which include forming (1104) a polysilicon layer having a first side over a semiconductor substrate having a top surface; forming (1106) a first resist layer over the semiconductor substrate, the first resist layer having a second side spaced apart from the first side; forming (also 1106) a diode well extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type; forming (1108) a second resist layer having a third side over the semiconductor substrate; and forming (also 1108) a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending from the diode well along the top surface.

Description

[0001] The described examples relate to semiconductor integrated circuits (ICs) and their fabrication, and more specifically, but not exclusively, to an IC that includes an integrated Zener diode and other devices, such as metal-oxide-semiconductor (MOS) transistors and / or laterally diffused metal-oxide-semiconductor (LDMOS) transistors. Background Technology

[0002] IC manufacturing typically involves considering and weighing various factors, including one or more of IC size, cost, complexity, performance, and yield. These factors can become more complex when an IC incorporates different device types, as adjusting a factor for one device can sometimes have trade-offs with one or more others. These trade-offs may exist in ICs, for example, those with Zener diodes and other devices, because factors incorporating other devices can adversely affect the target Zener diode's operating parameters, such as breakdown voltage or leakage current. For instance, some ICs may include both a Zener diode and an LDMOS transistor, where the transistor allows for higher power applications and operation, and the Zener diode is coupled to the transistor in a way that allows reverse breakdown of the Zener diode in the event of a voltage rise across the LDMOS transistor, thus preventing potential damage to the transistor's gate oxide. However, some baseline manufacturing methods may inefficiently require additional steps or considerations only for one or the other, such as the LDMOS transistor or the Zener diode.

[0003] While the foregoing may be implemented in various baseline devices, this article provides examples of improvements to certain of the above concepts, as detailed below. Summary of the Invention

[0004] In one example, a method for forming an integrated circuit is described. The method includes: forming a polysilicon layer having a first side over a semiconductor substrate having a top surface; forming a first photoresist layer over the semiconductor substrate, the first photoresist layer having a second side spaced apart from the first side; forming a diode well extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type; forming a second photoresist layer having a third side over the semiconductor substrate; and forming a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending along the top surface from the diode well.

[0005] It also describes and requests protection for other aspects. Attached Figure Description

[0006] Figures 1 to 9This is a partial cross-sectional view showing the continuous manufacturing stages of an IC semiconductor structure and the resulting structure.

[0007] Figure 10 Here is a plan view of another example diode.

[0008] Figure 11 This is a flowchart of an example method for manufacturing semiconductor structures. Detailed Implementation

[0009] Figures 1 to 9 This is a cross-sectional view illustrating the sequential manufacturing stages of a semiconductor structure 100 (e.g., a portion of an IC) and the resulting structure. Ultimately, the semiconductor structure 100 will include IC devices such as LDMOS transistors, MOS transistors, and diodes (e.g., Zener diodes), therefore... Figure 1 The figures also illustrate LDMOS transistor region 102, MOS transistor region 104, and diode region 106, each of the respective devices. As an example, the IC may provide an LDMOS transistor with an operating voltage greater than that associated with the MOS transistor; for example, the LDMOS operates at 10 volts or greater, the MOS transistor operates at 5 volts or less, and the diode may be located close to the MOS or LDMOS transistor, for example, for voltage protection. Furthermore, in addition to the diode, the IC may also include many other devices (not shown) that function in association with the transistor. Such devices may be formed, for example, at the substrate level via field oxide (e.g., using shallow trench isolation (STI) or local silicon oxide (LOCOS) processes) and... Figure 1 The structure shown (and other subsequent diagrams) is isolated and can be interconnected at the interconnect level. Figure 1 The structure shown is connected.

[0010] from Figure 1 Initially, the semiconductor structure 100 includes a semiconductor substrate 108, for example, as part of a silicon wafer, and isolation regions 109 formed between the aforementioned device regions. Such wafers typically contain multiple locations, each corresponding to the same or different ICs on the wafer, therefore... Figure 1The illustrations (and subsequent figures) can be repeated at each wafer IC location. The wafer is typically provided with P-type or N-type semiconductors, and substrate 108 may represent a portion of the bulk wafer or a region (e.g., a well or buried layer) formed in conjunction with the wafer. In the illustrated example, substrate 108 is a P-type epitaxial (e.g., epitaxial) layer. A mask (e.g., resist) layer 110 is formed over selective locations across the upper surface 108US (e.g., using a photolithography process; other masks described below may also use this process). Mask layer 110 includes a first opening 112 and a second opening 114, each located in a corresponding region where implantation is to be performed. Implantation, for example using a P-type dopant, is performed through the first opening 112 in a portion of MOS transistor region 104 and through the second opening 114 in a portion of diode region 106 to form corresponding PWELL regions (or more generally, well regions) 116 and 118. Each of PWELL regions 116 and 118 may have a density of 1e16 / cm². 3 Up to 3e17 / cm 3 The dopant concentration is within the range of 0.5 µm to 1.5 µm, and the maximum depth D1 (shown in the vertical dimension) extending from the upper surface 108US into the substrate 108 is within the range of 0.5 µm to 1.5 µm.

[0011] exist Figure 2 Remove Figure 1 A mask layer 110 is constructed and a mask layer 202 is formed therein, and the mask layer is patterned to form openings 204 therein. Implantation is performed through the openings 204 in a portion of the LDMOS transistor region 102, for example using N-type dopant implantation, to form a corresponding drift region 206 in the substrate 108. The drift region 206 may have a density of 3E15 / cm 3 Up to 1E17 / cm 3 The dopant concentration is within the range of 0.2 µm to 2 µm, and the maximum depth D2 (shown in the vertical dimension) extending from the upper surface 108US into the substrate 108 is within the range of 0.2 µm to 2 µm.

[0012] exist Figure 3 Remove Figure 2A mask layer 202 is formed and a mask layer 302, such as a SiN layer, is formed. The mask layer is patterned to form openings 304 therein. A thick LOCOS structure 306 is formed over the drift region 206 by etching the openings 304 in the mask layer 302. Typically, the LOCOS structure 306 can be formed by oxidizing the portion of the upper surface 108 μm exposed through the openings 304. As shown, the LOCOS structure 306 may include a central portion that has a greater depth in the vertical dimension toward its central region relative to the area surrounding its lateral or peripheral edges, which form a shape sometimes referred to as a "beak".

[0013] exist Figure 4 Remove Figure 3 The mask layer 302, and polysilicon (polysilicon / poly) and related structures have been formed in each of the LDMOS transistor region 102, MOS transistor region 104, and diode region 106 by a polysilicon layer. First, a thin insulating layer is formed, for example, by growing or depositing an insulator (e.g., oxide) over the exposed portion of the upper surface 108US. Figure 4 (Only a portion of it is retained). Next, a polycrystalline silicon layer is formed on top of the insulating layer. Figure 4 (Only a portion of it is retained). The deposited polysilicon layer can be doped in situ or subsequently. The polysilicon layer and the thin insulating layer are patterned and etched to form the resulting polysilicon structures 402, 404, and 406, which are separated from the upper surface 108US by the remaining and corresponding insulating portions 408, 410, and 412, each insulating portion in one of the LDMOS transistor region 102, the MOS transistor region 104, and the diode region 106. Regarding the polysilicon structure 402, one vertical end provides a first sidewall above the LOCOS structure 306, and another vertical end provides a second sidewall positioned laterally beyond the vertical edge of the drift region 206. The combination of the polysilicon structure 402 and the insulating portion 408, combined with the region where the polysilicon structure 402 overlaps with the thick LOCOS structure 306, can serve as the gate and corresponding gate dielectric of the LDMOS transistor. The combination of the polysilicon structure 404 and the insulating portion 410 can serve as the gate and corresponding gate dielectric of the MOS transistor. As further described below, in conjunction with the diode formed in diode region 106, the combination of polysilicon structure 406 and insulator portion 412 can serve as an injection hard mask.

[0014] exist Figure 5In this process, a mask layer 502 is formed above the upper surface 108US, and the mask layer is patterned to form a first opening 504 and a second opening 506 therein, both openings being located within the MOS transistor region 104. A relatively light dopant implantation, commonly referred to as lightly doped drain (LDD) implantation, is performed through the first opening 504 and the second opening 506, resulting in corresponding LDD regions 508 and 510 formed below the upper surface 108US and self-aligned with the insulator portion 410. LDD implantation is typically provided at lower energies than individual (described later) n-type or p-type source / drain implantations, and the dopant type is selected to correspond to the desired conductivity type of the transistor formed in the MOS transistor region 104. For example, for an n-type MOS (NMOS) transistor, LDD implantation uses an n-type dopant (e.g., phosphorus and / or arsenic pocket implantation, and optionally germanium pre-amorphization implantation (PAI)), for example, using phosphorus, at energies in the range of 5 keV to 80 keV and 1e13 to 3e14 atoms / cm². 2 Doses within the range of 10 keV to 100 keV and 1E14 to 1E15 atoms / cm². 2 The dose is within the range of 0 to 35 degrees, and the device is rotated two or four times. As an alternative example, for p-type MOS (PMOS) transistors, LDD implantation uses p-type dopants (e.g., BF2 (boron difluoride), boron and / or indium, and optionally germanium PAI), for example, using BF2, at energies in the range of 5 keV to 50 keV and 5E13 to 5E14 atoms / cm². 2 Doses within the range; using boron, at energies in the range of 2 keV to 20 keV and 5E13 to 5E14 atoms / cm². 2 Doses within the range of 2 keV to 15 keV and 1E13 to 5E14 atoms / cm². 2 Doses within the range; optionally, germanium PAI is used at energies in the range of 5 keV to 20 keV and 1e14 to 5e14 atoms / cm. 2 The dose range is specified. PMOS LDDs may also contain arsenic and / or antimony pocket implantations in the range of 20 keV to 60 keV, with doses in the range of 1E13 to 1E14 atoms / cm². 2 Within the range. During LDD implantation, polysilicon structures 402 and 406 may or may not be masked.

[0015] exist Figure 6 Remove Figure 5A mask layer 502 is formed, and a mask layer 602 (e.g., photoresist) is formed over the upper surface 108US. The mask layer is patterned to form a first opening 604 and a second opening 606 therein, wherein the first opening 604 is in the LDMOS region 102 and the second opening 606 is in the diode region 106. Although the first opening 604 is above a portion of the LDMOS transistor region 102, it is laterally spaced from the drift region 206. Therefore, subsequent implantation through the first opening 604 will provide a DWELL structure at the target location, for example, self-aligned with the vertical edge of the polysilicon structure 402, for operation of the LDMOS transistor. Also in this respect, to allow such a DWELL, the width of the first opening 604 is in the range of 0.5 µm to 1.0 µm. Specifically, the second opening 606 is in the diode region 106, and its exposed upper surface 108US is defined in the region between two different types of structures, namely, provided on one vertical edge by the mask layer 602, and on the other vertical edge by the sidewall of the polysilicon structure 406, such as... Figure 4 As shown, it is formed simultaneously with other polysilicon structures 402 and 404. Furthermore, the width of the second opening between these two vertical edges is shown as w. d And it can be controlled within the range of 30 nm to 300 nm, and can provide important benefits, as further described below. Thereafter, two sets of implantations are performed, for example, sequentially and in any order, through the first opening 604 and the second opening 606, as described below. Therefore, it should be noted that each of these implantations depends in part on the polysilicon structure 406, which acts as an implantation hard mask, within its range through the second opening 606, because the polysilicon structure defines one edge of the second opening 606 (the other edge is provided by the mask layer 602).

[0016] The single implantation performed through both the first opening 604 and the second opening 606 uses the same dopant type as that used for drift region 206 and the opposite dopant type to that used for PWELL region 118. Therefore, in this example where drift region 206 is N-type and PWELL region 118 is P-type, Figure 6 The injection is of the N-type, for example, using arsenic. Furthermore, this... Figure 6 The result of this injection is referred to as a shallow injection zone because the injection energy is lower than that used for the deeper injection to be described, and the injection is also performed through the same openings 604 and 606. For example, Figure 6 The shallow injection dose can be 1.0E14 atoms / cm. 2 Up to 2.0E14 atoms / cm 2 (For example, 1.4E14 atoms / cm) 2The range is within the range of 5 keV to 10 keV (e.g., 8 keV). Shallow implantation forms a shallow well region 608 in substrate 108, generally aligned with the first opening 604, and also forms a shallow well region 610 in substrate 108, generally aligned with the second opening 606. In this example, each of the shallow well regions 608 and 610 is thus formed simultaneously with the same implantation and extends into substrate 108 to a depth D3. Depth D3 is based on the depth D5 of the subsequently formed source / drain (see...). Figure 7 The value of D3 is selected from D5, where D3 is about fifty percent (50%) or less of D5. For example, where D5 is in the range of 60 nm to 200 nm, correspondingly and separately, D3 is in the range of 30 nm to 100 nm.

[0017] Another implantation, performed through both the first opening 604 and the second opening 606, uses the opposite dopant type to that used for drift region 206 and the same dopant type as that used for PWELL region 118, which is P-type in the present example, to form transistor well region 612 and diode well region 614. This implantation uses greater energy than shallow well implantation, causing well regions 612 and 614 to be formed deeper and lower than the corresponding shallow well regions 608 and 610. In various examples, well regions 612 and 614 are double diffused wells (DWELL). The deeper implantation targets a depth D4, which can be in the range of 300 nm to 500 nm. The deeper implantation uses doses and energies consistent with these targets, for example at 1E13 atoms / cm². 2 Up to 6E13 atoms / cm 2 Within the range, and with energies in the range of 20 keV to 50 keV (e.g., 3E13 atoms / cm). 2 (Energy is 32 keV).

[0018] exist Figure 7 The middle part has been removed. Figure 6A mask layer 602 is formed, and a mask layer 702 (e.g., photoresist) is formed over an upper surface 108US. The upper surface is patterned to form first to fifth openings 704, 706, 708, 710, and 712 therein, wherein some of these openings are in each of the LDMOS region 102, the MOS region 104, and the diode region 106. Sidewall spacers 714 have been formed along the sidewalls of polysilicon structure 402, sidewall spacers 716 have been formed along the sidewalls of polysilicon structure 404, and sidewall spacers 718 have been formed along the sidewalls of polysilicon structure 406. Sidewall spacers 714, 716, and 718 may be formed, for example, by forming oxide and / or nitride layers over and along at least the sidewalls of each polysilicon structure, followed by appropriate etching to leave the remaining portions of the oxide and / or nitride as sidewall spacers.

[0019] Figure 7 Source / drain implantation is also illustrated, which uses an N-type dopant in the example described, and is correspondingly referred to as NSD implantation. For example, NSD implantation using arsenic (or phosphorus or antimony) is associated with the source / drain functionality of the LDMOS transistor in LDMOS transistor region 102 and the NMOS transistor in MOS transistor region 104. Implantation forms an N-type region in substrate 108 through each of the first to fifth openings 704, 706, 708, 710, and 712. NSD implantation can be performed at 1.0E15 atoms / cm². 2 Up to 1.6E15 atoms / cm 2 Within the range of 20 keV to 30 keV, dopant is implanted to a depth D5, which, as described above, can be in the range of 60 nm to 200 nm. Therefore, N-type implantation forms the drain 720 and source 724 of the LDMOS transistor, as well as the first source / drain (S / D) region 726 and the second S / D region 728 of the MOS transistor. N-type implantation also forms an N-type region 730. The N-type region 730 (combined with the N-type shallow well region 610) interfaces with or forms a metallurgical interface with the P-type material of the diode well region 614, thereby providing a PN junction 732 between them, wherein the junction is partially indicated by a schematic diode symbol with a dashed outline, located between the diode well region 614 and the N-type region 730. A portion of the N-type region 730 extending along the upper surface 108US away from the shallow well region 610 can be used as the first terminal of the diode 106.

[0020] exist Figure 8 The middle part has been removed. Figure 7A mask layer 702 is formed, and a mask layer 802 is formed above the upper surface 108US. The upper surface is patterned to form a first opening 804 in the LDMOS region 102 and a second opening 806 in the diode region 106. Then, type and Figure 7 Complementary injection; therefore, in Figure 7 When using N-type dopants Figure 8 The injection is P-type, and boron is used, for example. Figure 8 The injection can be referred to as PSD injection, that is, the injection of P-type dopant and the combination of the transistor shown or other transistors that may require P-type source / drain or other regions. Figure 8 The injection rate can reach 1E15 atoms / cm 2 Up to 10E15 atoms / cm 2 Within the range of 5 keV to 10 keV, and also reaching a depth of D5. Figure 8 The P-type injection passes through the first opening 804 and forms a P-type body region 808 in the transistor well region 612. Furthermore, Figure 8 The P-type implantation passes through the second opening 806 and forms a P-type region 810 in the PWELL region 118. The P-type region 810 is spaced apart from the N-type region 730 because the PWELL region 118 extends to the surface 108US between the P-type region 810 and the N-type region 730. The P-type region 810 provides a conductive path 812 of the same dopant type, shown by a dashed line passing through the PWELL region 118 (and possibly a portion of the substrate 108) and reaching the diode well region 614, allowing the P-type region 810 to be electrically contacted as the anode of the PN junction 732. The P-type region 810 can be used as a second terminal of the diode 106.

[0021] exist Figure 9 The middle part has been removed. Figure 8 Mask layer 802. Thereafter, connections can be made to the LDMOS transistors in LDMOS transistor region 102, to the MOS transistors in MOS transistor region 104, and to the diodes in diode region 106; these connections are either between devices or to other devices. To facilitate such connections, for example, in… Figure 9In this configuration, silicide conductive regions 902, 904, 906, 908, 910, 912, 914, 916, and 918 are formed along selected semiconductor surfaces, for example, laterally along the surfaces of the drain 720, source 724, body region 808, S / D region 726, S / D region 728, P-type region 810, N-type region 730, and polysilicon structures 402, 404, and 406, respectively. In this respect, the electrical path through the PN junction 732 can be achieved through electrical contact with the silicide conductive region 914, which serves as the diode anode, and the silicide conductive region 916, which serves as the diode cathode. Along the electrical path, and where the P-type material of the diode well region 614 interfaces with the N-type material of the N-type region 730, an ionization region 920 is presented, representing the location where diode breakdown (or impact ionization) may occur due to the P-type / N-type (PN) junction or interface. Specifically, the formation of diode well region 614 results in a lower P-type dopant concentration compared to the PWELL region 118 formed by diode well region 614. Therefore, in ionization region 920, in the region of ionization 920 at the PN junction 732 from diode well region 614 to N-type region 730, the relatively higher P-type dopant concentration from diode well region 614 creates a region capable of achieving one or more advantageous properties, including increased breakdown voltage and / or reduced leakage current. Thus, either of these properties can be achieved without additional manufacturing steps already performed during the formation of other devices (e.g., the formation of MOS and LDMOS transistors).

[0022] Also in Figure 9 Note that the ionization region 920 appears at approximately depth D5, which is the depth of the PN junction 732 between the N-type region 730 and the P-type diode well region 614. Briefly back to... Figure 6 Recall that the shallow well region 610 and the additional diode well region 614 are formed by a second opening 606, and said opening has a width w d .exist Figure 9 Given that the depth D5 where the ionization region 920 appears has been depicted, it should also be noted that in one instance, Figure 6 Width w d It is approximately equal to depth D5. However, in other instances, w d This can be relative to depth D5 within a certain range, for example, up to approximately 50% greater than D5, or down to approximately 50% less than D5. In this context, "approximately" means ±5%. The example provided above illustrates this width-depth relationship, where it has been stated that 60nm ≤ D5 ≤ 200nm and 30nm ≤ w d ≤300nm, making w d The minimum width is about 50% smaller than the minimum depth of D5, and w dThe maximum width is approximately 50% greater than the maximum depth of D5. Furthermore, in terms of NSD implantation, depth D5 may be related to the depths of other devices in semiconductor structure 100 (e.g., the source 724 of the LDMOS transistor, and the first S / D region 726 and the second S / D region 728 of the MOS transistor), and nominally also establishes a depth for the N-type region 730 used as the diode cathode in diode region 106. This depth may be partially limited by a minimum accurate aperture size achievable in a photolithography process (e.g., in a photoresist), which is typically used to define the implantation opening (e.g., ...). Figure 6 The first opening 604 or Figure 7 The widths of the first to fourth openings (704, 706, 708, and 710). However, in Figure 6 In the middle, it should be noted that the width w of the second opening 606 d This will affect the location of the relatively high dopant concentration provided by the diode well region 614, but the second opening is not limited to this because it is not constrained by the photoresist on both lateral sides, since it is on one side (e.g., Figure 6 On the left side of the mask layer 602, it intersects with the vertical edge of the mask layer 602, while on the opposite side (e.g., on the left side of the mask layer 602), it meets the vertical edge of the mask layer 602. Figure 6 On the right side of the structure, it intersects with the vertical edge of the polycrystalline silicon structure 406. Therefore, in Figure 6 In the baseline DWELL implantation process for other non-diode devices, a relatively narrow width of the diode well region 614 can be achieved by adding a polysilicon hard mask, allowing it to partially self-align with the vertical sidewalls of the hard mask polysilicon structure 404 when the diode well region 614 is formed. Therefore, the width w is partially established by the hard mask polysilicon structure 404. d Correspondingly, the width and dopant concentration depth distribution of the diode well region 614 are adjusted, and these factors support Figure 7 PN junction 732 (and so on) Figure 9 The subsequent formation, positioning, and behavior at the ionization region 920 (shown in the diagram). Furthermore, this is achieved using polysilicon (e.g., polysilicon structure 406) as a hard mask, combined with a conventional (e.g., photoresist) mask used for DWELL implantation in other devices (e.g., LDMOS transistors). Therefore, when as... Figure 7 As shown and further as Figure 9 As shown, when the N-type region 730 is subsequently formed, the PN junction 732 provides a resulting ionization region 920 with a desired relatively high concentration of P-type dopant at the location, thereby increasing the diode breakdown voltage and reducing the diode leakage current.

[0023] Finally, regarding Figure 9 Additional electrical connections can be made, for example, through metal layers and metal vias (not shown), which are typically formed in... Figure 9 It is placed on top of the structure and in contact with the appropriate one in the silicide conductive region.

[0024] Figure 10 This is a plan view of diode 1000, which includes... Figure 9 The diode portion of the semiconductor structure 100. The diode 1000 is generally symmetrical about a polysilicon structure 406, which is shown as rectangular (or square). Therefore, in each linear dimension forming the polysilicon structure 406, a diode well region 614 (spaced from the polysilicon structure 406 by unmentioned sidewall spacers) is shown outwards from said dimension, and an N-type region 730 (cathode) is further shown outwards from the diode well region 614, and a P-type region (anode) 810 is shown even further outwards from the N-type region 730 (cathode). Therefore, Figure 10 Different perspective views of the foregoing are depicted as examples, wherein the N-type region (cathode) 730 completely surrounds the diode well region 614, and the P-type region 810 (cathode) completely surrounds the N-type region (cathode) 730.

[0025] Figure 11 A flowchart summarizing the various steps described above for manufacturing the semiconductor structure 100 is provided, for example, to ultimately provide... Figure 9 and 10 The structure 100 is shown. Method 1100 begins with step 1102, in which the following is obtained: Figure 1 The semiconductor substrate 108. At this stage, the semiconductor substrate 108 may be a bare wafer, or may have one or more semiconductor features already formed thereon. The semiconductor substrate 108 also includes one or more regions, or one or more electrical structures adjacent to these regions, wherein it is desired to form devices comprising semiconductors or silicon, such as diodes, and one or more of LDMOS transistors and MOS transistors. Next, in step 1104, a polysilicon component, such as..., is formed over the surface of the semiconductor substrate 108. Figure 4 The polysilicon structure 406. Next, in step 1106, a portion of the polysilicon component from step 1104 is used as a hard mask to form a PN junction region in the semiconductor substrate 108, for example... Figure 6 The diode well region 614. Next, in step 1108, one of the diode anode or diode cathode is formed in the semiconductor substrate 108, for example... Figure 7 The N-type region 730 (cathode). Thereafter, step 1110 generally means that, after step 1108, additional structures associated with the diode (and possibly other devices and interconnections with these and other devices) associated with the semiconductor substrate 108 of step 1102 can be formed.

[0026] As will be apparent to those skilled in the art, examples provided are for the fabrication of semiconductor ICs, such as ICs comprising Zener diodes and other devices (e.g., MOS transistors and / or LDMOS transistors) formed at least in part using parallel processing steps. Such examples offer a variety of benefits, some of which are described above and still include others. For example, while certain dopant types have been described, complementary (opposite) conductivity types have also been considered, thereby reversing the positions of the diode anode and cathode. Other examples can implement other types of IC structures that provide processes that can be used simultaneously to form the diode structures described herein. Thus, each of the diode breakdown voltage and leakage current can be advantageously tuned without the use of additional masks, for example, for one or the other of these properties. These benefits can be realized for more complex structures, or for multiple devices on the same substrate (and IC), thereby enabling improvements at scale across devices. Additional modifications are possible to the described embodiments, and other embodiments are possible within the scope of the appended claims.

Claims

1. A method for forming an integrated circuit, comprising: A polycrystalline silicon layer having a first side is formed above a semiconductor substrate having a top surface; A first photoresist layer is formed over the semiconductor substrate, the first photoresist layer having a second side spaced apart from the first side; A diode well extending into the semiconductor substrate is formed between the first side and the second side, the diode well having a first conductivity type; A second photoresist layer having a third side is formed over the semiconductor substrate; as well as A diode terminal is formed between the first side and the third side, extending into the semiconductor substrate. The diode terminal has an opposite second conductivity type and extends from the diode well along the top surface.

2. The method of claim 1, wherein the diode terminal is a first diode terminal, and the diode well and the first diode terminal extend into a well region having the first conductivity type, the method further comprising forming a second diode terminal extending into the well region, the second diode terminal being spaced apart from the first diode terminal and having the first conductivity type.

3. The method of claim 1, wherein the diode well is P-type and the diode terminal is N-type.

4. The method of claim 1, further comprising forming a shallow well between the PN junction and the top surface between the first side and the second side, the shallow well overlapping the diode terminal and having the second conductivity type.

5. The method of claim 4, wherein the first depth of the shallow well is approximately half the second depth of the diode terminal.

6. The method of claim 4, wherein the shallow well has a depth approximately equal to half the width between the first side and the second side.

7. The method of claim 1, wherein the width between the first side and the second side is in the range of 30 nm to 300 nm.

8. The method of claim 1, wherein the width between the first side and the second side is approximately equal to the depth of the metallurgical interface between the diode terminal and the diode well.

9. The method of claim 1, wherein the width between the first side and the second side is approximately the depth to which the diode terminal extends into the semiconductor substrate.

10. The method of claim 1, wherein the implantation forming the diode well further forms a transistor extending into the semiconductor substrate.

11. A method for forming an integrated circuit, comprising: An exposed area of ​​the semiconductor substrate is formed between the resist mask and the polysilicon structure mask; N-type and P-type dopants are implanted into the semiconductor substrate through the exposed region, thereby forming a PN junction below the exposed region; as well as A diode terminal is formed in the semiconductor substrate, the diode terminal extending from the PN junction along the top surface of the semiconductor substrate.

12. The method of claim 11, wherein the width between the resist mask and the polysilicon structure mask is approximately equal to the depth of the diode terminal.

13. The method of claim 11, wherein the diode terminal is a first diode terminal having a first conductivity type, and the method further comprises forming a second diode terminal having an opposite second conductivity type, the second diode terminal being spaced apart from the first diode terminal along the top surface.

14. The method of claim 11, wherein the diode terminal has a first conductivity type, and the method further comprises forming a shallow well having the first conductivity type between the PN junction and the top surface.

15. The method of claim 11, further comprising forming a transistor over the semiconductor substrate and extending it into the semiconductor substrate, comprising DWELL using the resist mask to form the transistor.

16. An integrated circuit (IC) comprising: A polycrystalline silicon component located above the surface of a semiconductor substrate; A PN junction, which is located below the surface and self-aligned with the polycrystalline silicon component; as well as Diode contacts extend along the surface away from the PN junction.

17. The IC of claim 16, wherein the diode terminal is a first diode terminal having a first conductivity type, and the IC further includes a second diode terminal having an opposite second conductivity type, the second diode terminal being spaced apart from the first diode terminal along the surface.

18. The IC of claim 17, wherein the DWELL having the second conductivity type extends from the PN junction into the semiconductor substrate.

19. The IC of claim 16, wherein a first DWELL region having a conductivity type extends from the PN junction into the semiconductor substrate, and the IC further includes a MOS transistor extending into the semiconductor substrate, the MOS transistor comprising a second DWELL region having the conductivity type and the same depth as the first DWELL region.

20. The IC of claim 16, wherein the diode terminal having a conductivity type extends into the semiconductor substrate to a first depth, and the IC further includes a MOS transistor comprising a source region and a drain region having the conductivity type and extending into the semiconductor substrate to the same second depth.

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