A growth method for improving pit defects of silicon carbide epitaxial wafer

Abstract

The application discloses a growth method for improving pit defects of a silicon carbide epitaxial wafer, and comprises the following steps: cleaning a silicon carbide substrate and placing the substrate in an epitaxial reaction chamber, introducing hydrogen, and performing high-temperature annealing treatment; increasing the hydrogen flow and the reaction chamber temperature, and performing hydrogen etching; reducing or maintaining the reaction chamber temperature, introducing a carbon source and a silicon source, and growing a buffer layer on the substrate surface; maintaining the gas introduction, increasing the reaction chamber temperature, and growing a gradient layer on the buffer layer; reducing the reaction chamber temperature, simultaneously opening a center gas source and an edge gas source, and growing a base epitaxial layer on the gradient layer; maintaining the reaction chamber temperature, adjusting the edge gas source flow to form a gradient flow, and growing a flat epitaxial layer on the base epitaxial layer. Through the substrate pretreatment-low rate epitaxy-high rate flat epitaxy, combined with the gradient process filling process, the application realizes the step-by-step filling and surface flattening of the pit defects, and effectively reduces the number of Pit defects and the epitaxial thickness uniformity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a growth method for improving pit defects in silicon carbide epitaxial wafers. Background Technology

[0002] Silicon carbide (SiC), as a semiconductor material with superior performance and broad application prospects, has attracted widespread attention and investment globally. Pit defects in SiC are a key factor affecting the performance of SiC substrates and devices, severely restricting the high-quality development of the SiC industry. The presence of pit defects increases the leakage current of SiC devices, reduces breakdown voltage and reverse blocking capability. Lattice distortion and impurity enrichment at the pits can form localized conductive channels, causing abnormal current conduction during device operation, leading to performance degradation or even failure. Therefore, improving pit defects in SiC epitaxial wafers is crucial for improving wafer quality.

[0003] Currently, industry-wide methods for improving pit defects in silicon carbide epitaxial wafers mainly focus on "single process optimization," lacking a systematic solution and resulting in limited defect control effectiveness. Conventional processes include the following steps: hydrogen etching – growth of a buffer layer – high-rate epitaxial layer growth. While hydrogen etching and the buffer layer can improve pit defects to some extent, hydrogen etching alone cannot repair dislocation extension regions within the substrate, and surface dangling bonds are not fully reorganized after etching, resulting in a pit filling rate of less than 50%. Furthermore, directly entering high-rate growth (20-40 μm / h) after the buffer layer growth does not allow sufficient time for Si / C atoms to diffuse and accumulate in the pit region, easily forming "covering growth" on the top of the pit, causing the pit to be "wrapped" rather than "filled." Therefore, a growth method that can further improve pit defects in epitaxial wafers is urgently needed. Summary of the Invention

[0004] Purpose of the invention: To address the above-mentioned shortcomings, this invention provides a growth method for improving pit defects in silicon carbide epitaxial wafers, which can reduce the number of pit defects on the surface of silicon carbide epitaxial wafers, reduce epitaxial thickness uniformity, and improve epitaxial wafer quality.

[0005] Technical solution: To solve the above problems, the present invention employs a growth method for improving pit defects in silicon carbide epitaxial wafers, comprising the following steps:

[0006] S1. Clean the silicon carbide substrate, place the cleaned silicon carbide substrate in the epitaxial reaction chamber, introduce hydrogen gas, and perform high-temperature annealing treatment.

[0007] S2. Increase the hydrogen flow rate and reaction chamber temperature to perform hydrogen etching;

[0008] S3. Lower or maintain the temperature of the reaction chamber, turn on the gas source, and introduce the carbon source and silicon source. Set the carbon-silicon ratio to 0.4-0.6 and the growth rate to 7-10 μm / h to grow a buffer layer on the substrate surface.

[0009] S4. Maintain the gas inlet conditions of step S3, increase the temperature of the reaction chamber, and grow a gradient layer on the buffer layer.

[0010] S5. Reduce the temperature of the reaction chamber, introduce carbon and silicon sources, keep the flow rates of the central and edge gas sources the same, set the carbon-silicon ratio to 0.4-0.6, set the growth rate to 6-8 μm / h, and grow a low-rate epitaxial layer on the gradient layer.

[0011] S6. Keep the reaction chamber temperature constant, increase the carbon source and silicon source flow rate, and adjust the edge gas source flow rate to be 10%-15% higher than the center gas source. Set the carbon-silicon ratio to 0.5-0.7 and the growth rate to 20-40 μm / h. Grow a high-rate epitaxial layer on the base epitaxial layer.

[0012] Furthermore, in step S1, the hydrogen flow rate is 30-50 slm, and a high-temperature annealing treatment is performed at 1200-1300℃ for 10-20 minutes.

[0013] Furthermore, in step S2, the hydrogen flow rate is 100-170 slm, the reaction chamber temperature is 1590-1610℃, and the etching time is 4-8 min.

[0014] Furthermore, in step S3, the reaction temperature is 1580℃, the silicon source flow rate is 60-90 sccm, the carbon source flow rate is 15-25 sccm, and the thickness of the buffer layer is 0.5-1 μm.

[0015] Furthermore, in step S4, the temperature of the reaction chamber is 1600℃, and the temperature ramp-up time is 4-8 minutes.

[0016] Furthermore, in step S5, the reaction temperature is 1560-1600℃, the silicon source flow rate is 60-90 sccm, and the carbon source flow rate is 15-25 sccm.

[0017] Furthermore, the thickness of the base epitaxial layer is 0.5-1 μm.

[0018] Furthermore, in step S6, the flow rate of the silicon source in the central gas source is 300-380 sccm, and the flow rate of the carbon source is 80-120 sccm.

[0019] Furthermore, the thickness of the planar epitaxial layer is 6-10 μm.

[0020] Furthermore, the carbon source is ethylene, and the silicon source is trichlorosilane.

[0021] Beneficial effects: Compared with the prior art, the significant advantage of this invention is that by using substrate pretreatment-low-rate epitaxy-high-rate planarization epitaxy, combined with a gradient process filling flow, it can achieve gradual filling of pit defects and surface planarization, effectively reducing the number of pit defects and reducing the uniformity of epitaxial thickness. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall process of the growth method of the present invention. Detailed Implementation

[0023] Example 1

[0024] like Figure 1 As shown in this embodiment, a growth method for improving pit defects in silicon carbide epitaxial wafers includes the following steps:

[0025] S1. Perform RCA standard cleaning on the silicon carbide substrate (rinsing and drying with two core chemical solutions (SC-1, SC-2) and deionized water). Place the cleaned silicon carbide substrate in the epitaxial reaction chamber, introduce hydrogen gas at a flow rate of 40 slm, raise the temperature in the reaction chamber to 1250℃ and hold for 15 minutes for high-temperature annealing. The reduction effect of hydrogen removes the residual oxide layer on the substrate surface, while the high temperature promotes the recombination of surface dangling bonds, reduces stress concentration at the edges of the original pits, and improves atomic filling efficiency, increasing the original pit filling rate to over 80%.

[0026] S2. Increase the hydrogen flow rate to 120 slm and the reaction chamber temperature to 1610℃ for hydrogen etching for 6 minutes. The high-flow-rate hydrogen forms a strong etching effect at high temperature, eliminating the micro-damage layer on the substrate surface that has not been repaired by annealing, preventing these damages from becoming "seeds" for subsequent epitaxy pits, and reducing the probability of defect generation from the source.

[0027] S3. Lower the reaction chamber temperature to 1580℃, turn on the gas source, and introduce the silicon source trichlorosilane (SiHCl3) and carbon source ethylene (C2H4). The silicon source flow rate is 75 sccm, the carbon source flow rate is 19 sccm, the carbon-silicon ratio is 0.5, the central hydrogen flow rate is 210 sccm, and the growth rate is set to 8 μm / h. Grow a buffer layer with a thickness of 1 μm on the substrate surface. The low carbon-silicon ratio and medium temperature environment can suppress the extension of substrate defects to the epitaxial layer, laying the foundation for a "low-defect substrate" for subsequent growth.

[0028] S4. Maintaining the gas flow conditions of step S3, increase the reaction chamber temperature to 1600℃, with a temperature ramp-up time of 8 minutes, and grow a gradient layer on the buffer layer. Gradual heating avoids atomic deposition imbalance caused by sudden temperature changes, while the gradient layer connects the lattice structure of the buffer layer and the subsequent epitaxial layer, reducing new defects caused by interfacial stress.

[0029] S5. Lower the reaction chamber temperature to 1580℃, introduce carbon and silicon sources, maintaining the same flow rates for the central and edge gas sources. The silicon source flow rate is 75 sccm, the carbon source flow rate is 19 sccm, the carbon-silicon ratio is 0.5, and the growth rate is set to 7.5 μm / h. Grow a low-rate epitaxial layer with a thickness of 0.8 μm on the graded layer. This step involves growing the initial epitaxial layer at a low rate. Under low-rate growth conditions, Si and C atoms have sufficient time to accumulate in the pit areas, preferentially filling the bottom of the pits through atomic diffusion, forming a preliminary flat epitaxial substrate, and preventing the pits from being "covered" during subsequent high-speed growth.

[0030] S6. Keeping the reaction chamber temperature constant, increase the flow rates of the carbon and silicon sources. Increase the edge silicon source flow rate to 360 sccm, the edge carbon source flow rate to 108 sccm, the center silicon source flow rate to 324 sccm, and the center carbon source flow rate to 97.2 sccm. Set the carbon-to-silicon ratio to 0.6 and the growth rate to 33.5 μm / h. Grow a high-rate epitaxial layer with a thickness of 8 μm on the base epitaxial layer. After growth, allow it to cool naturally to room temperature to complete the epitaxial process.

[0031] This step increases the carbon-to-silicon ratio, which facilitates the lateral growth of the epitaxial layer along the surface steps (rather than rapid vertical stacking), effectively smoothing out the edges of tiny pits not fully filled during the initial layer preparation stage. Furthermore, this step improves the growth rate. Typically, the growth rate at the reaction chamber edges may be lower due to airflow disturbances or slightly lower temperatures, leading to pit accumulation. During the high-rate growth stage, by optimizing the gas distribution (using a center-edge gradient gas supply), specifically by adjusting the gas flow rate in different regions (10%-15% higher at the edge than at the center), and matching the slightly lower temperature at the reaction chamber edges, the increased gas flow rate at the edges enhances the atomic deposition rate in that region. This ensures uniform growth of the epitaxial layer from the center to the edge, and also ensures lateral growth along the surface steps, further covering the tiny pits not fully filled during the initial layer preparation stage, ultimately forming a low-defect surface. Simultaneously, by optimizing the gas distribution, the process adjustment window widens, making it easier to optimize the overall thickness uniformity of the epitaxial wafer.

[0032] Example 2

[0033] This embodiment provides a growth method for improving pit defects in silicon carbide epitaxial wafers, comprising the following steps:

[0034] S1. Perform RCA standard cleaning on the silicon carbide substrate. Place the cleaned silicon carbide substrate in the epitaxial reaction chamber, introduce hydrogen gas at a flow rate of 40 slm, raise the temperature in the reaction chamber to 1250℃ and hold for 15 minutes for high-temperature annealing.

[0035] S2. Increase the hydrogen flow rate to 120 slm and the reaction chamber temperature to 1590℃ to perform hydrogen etching for 6 minutes.

[0036] S3. Lower the reaction chamber temperature to 1580℃, turn on the gas source, and introduce silicon source trichlorosilane (SiHCl3) and carbon source ethylene (C2H4). The silicon source flow rate is 60 sccm, the carbon source flow rate is 15 sccm, the carbon-silicon ratio is 0.5, the central hydrogen flow rate is 180 sccm, and the growth rate is set to 10 μm / h. Grow a buffer layer with a thickness of 1 μm on the substrate surface.

[0037] S4. Maintain the gas supply conditions of step S3, increase the temperature of the reaction chamber to 1600℃, and the temperature ramp-up time is 8 minutes to grow a gradient layer on the buffer layer.

[0038] S5. Maintain the reaction chamber temperature at 1600℃, introduce carbon and silicon sources, keep the flow rates of the central and edge gas sources the same, the silicon source flow rate is 60 sccm, the carbon source flow rate is 15 sccm, the carbon-silicon ratio is 0.5, set the growth rate to 6 μm / h, and grow a low-rate epitaxial layer with a thickness of 1 μm on the gradient layer.

[0039] S6. Keeping the reaction chamber temperature constant, increase the flow rates of the carbon and silicon sources. Increase the edge silicon source flow rate to 300 sccm, the edge carbon source flow rate to 80 sccm, the center silicon source flow rate to 270 sccm, and the center carbon source flow rate to 72 sccm. Set the carbon-silicon ratio to 0.53 and the growth rate to 28 μm / h. Grow a high-rate epitaxial layer with a thickness of 8 μm on the base epitaxial layer. After growth, allow it to cool naturally to room temperature to complete the epitaxial process.

[0040] Example 3

[0041] This embodiment provides a growth method for improving pit defects in silicon carbide epitaxial wafers, comprising the following steps:

[0042] S1. Perform RCA standard cleaning on the silicon carbide substrate. Place the cleaned silicon carbide substrate in the epitaxial reaction chamber, introduce hydrogen gas at a flow rate of 40 slm, raise the temperature in the reaction chamber to 1250℃ and hold for 15 minutes for high-temperature annealing.

[0043] S2. Increase the hydrogen flow rate to 120 slm and the reaction chamber temperature to 1600℃ to perform hydrogen etching for 6 minutes.

[0044] S3. Lower the reaction chamber temperature to 1580℃, turn on the gas source, and introduce silicon source trichlorosilane (SiHCl3) and carbon source ethylene (C2H4). The silicon source flow rate is 90 sccm, the carbon source flow rate is 25 sccm, the carbon-silicon ratio is 0.55, the central hydrogen flow rate is 300 sccm, and the growth rate is set to 7 μm / h. Grow a buffer layer with a thickness of 0.5 μm on the substrate surface.

[0045] S4. Maintain the gas supply conditions of step S3, increase the temperature of the reaction chamber to 1600℃, and the temperature ramp-up time is 8 minutes to grow a gradient layer on the buffer layer.

[0046] S5. Maintain the reaction chamber temperature at 1560℃, introduce carbon and silicon sources, keep the flow rates of the central and edge gas sources the same, the silicon source flow rate is 90 sccm, the carbon source flow rate is 25 sccm, the carbon-silicon ratio is 0.55, set the growth rate to 8 μm / h, and grow a low-rate epitaxial layer with a thickness of 1 μm on the gradient layer.

[0047] S6. Keeping the reaction chamber temperature constant, increase the flow rates of the carbon and silicon sources. Increase the edge silicon source flow rate to 380 sccm, the edge carbon source flow rate to 120 sccm, the center silicon source flow rate to 323 sccm, and the center carbon source flow rate to 102 sccm. Set the carbon-to-silicon ratio to 0.63 and the growth rate to 38.5 μm / h. Grow a high-rate epitaxial layer with a thickness of 8 μm on the base epitaxial layer. After growth, allow it to cool naturally to room temperature to complete the epitaxial process.

[0048] Comparative Example 1

[0049] This embodiment describes an unmodified epitaxial process, including the following steps:

[0050] S1. Place the silicon carbide substrate into the epitaxial reaction chamber, introduce hydrogen gas at a flow rate of 120 slm, raise the temperature of the reaction chamber to 1600℃, and perform hydrogen etching for 6 minutes.

[0051] S2. Lower the reaction chamber temperature to 1580℃, turn on the gas source, and introduce silicon source trichlorosilane (SiHCl3) and carbon source ethylene (C2H4). The silicon source flow rate is 90 sccm, the carbon source flow rate is 25 sccm, the carbon-silicon ratio is 0.55, and the central hydrogen flow rate is 300 sccm. Grow a buffer layer with a thickness of 1 μm on the substrate surface.

[0052] S3. Keeping the reaction chamber temperature constant, increase the source flow rate to 380 sccm, the carbon source flow rate to 120 sccm, set the carbon-silicon ratio to 0.63, and set the growth rate to 38.5 μm / h. Grow a smooth epitaxial layer with a thickness of 8 μm on the buffer layer. After growth, allow it to cool naturally to room temperature to complete the epitaxial process.

[0053] The performance of the epitaxial wafers obtained from the three embodiments and the comparative example described above was tested, and the results are shown in the table below:

[0054]

[0055] Compared to existing processes, the pit defect density in all embodiments of the present invention is reduced, controlled to 5 pits / cm². 2 Within this range, the uniformity of the epitaxial layer thickness is improved to a certain extent, achieving the expected results.

Claims

1. A growth method for improving pit defects in silicon carbide epitaxial wafers, characterized in that, Includes the following steps: S1. Clean the silicon carbide substrate, place the cleaned silicon carbide substrate in the epitaxial reaction chamber, introduce hydrogen gas, and perform high-temperature annealing treatment. S2. Increase the hydrogen flow rate and reaction chamber temperature to perform hydrogen etching; S3. Lower or maintain the temperature of the reaction chamber, turn on the gas source, and introduce the carbon source and silicon source. Set the carbon-silicon ratio to 0.4-0.6 and the growth rate to 7-10 μm / h to grow a buffer layer on the substrate surface. S4. Maintain the gas inlet conditions of step S3, increase the temperature of the reaction chamber, and grow a gradient layer on the buffer layer. S5. Reduce the temperature of the reaction chamber, introduce carbon and silicon sources, keep the flow rates of the central and edge gas sources the same, set the carbon-silicon ratio to 0.4-0.6, set the growth rate to 6-8 μm / h, and grow a low-rate epitaxial layer on the gradient layer. S6. Keep the reaction chamber temperature constant, increase the carbon source and silicon source flow rate, and adjust the edge gas source flow rate to be 10%-15% higher than the center gas source. Set the carbon-silicon ratio to 0.5-0.7 and the growth rate to 20-40 μm / h. Grow a high-rate epitaxial layer on the base epitaxial layer.

2. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, In step S1, the hydrogen flow rate is 30-50 slm, and a high-temperature annealing treatment is performed at 1200-1300℃ for 10-20 minutes.

3. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, In step S2, the hydrogen flow rate is 100-170 slm, the reaction chamber temperature is 1590-1610℃, and the etching time is 4-8 min.

4. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, In step S3, the reaction temperature is 1580℃, the silicon source flow rate is 60-90 sccm, the carbon source flow rate is 15-25 sccm, and the thickness of the buffer layer is 0.5-1 μm.

5. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, In step S4, the temperature of the reaction chamber is 1600℃, and the temperature ramp-up time is 4-8 minutes.

6. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, The reaction temperature in step S5 is 1560-1600℃, the silicon source flow rate is 60-90 sccm, and the carbon source flow rate is 15-25 sccm.

7. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, The thickness of the base epitaxial layer is 0.5-1 μm.

8. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, In step S6, the flow rate of the silicon source in the central gas source is 300-380 sccm, and the flow rate of the carbon source is 80-120 sccm.

9. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, The thickness of the flat epitaxial layer is 6-10 μm.

10. The growth method for improving pit defects in silicon carbide epitaxial wafers as described in claim 1, characterized in that, The carbon source is ethylene, and the silicon source is trichlorosilane.

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