Storage device, control method and controller thereof, and distributed storage system

Abstract

This application provides a storage device and its control method and controller, as well as a distributed storage system, relating to the field of storage technology. The controller of the storage device includes: a memory access control module configured to respond to a host's memory access request and write data to or read data from the storage device's memory based on a compute extended connection memory protocol; and a bridging module configured to respond to a host's persistent refresh request and persistently store the data written by the host to the storage device's non-volatile memory. An embodiment of this application provides an NVMe SSD device based on PMEM technology, which can expose the device memory to the host, support host access to the device memory, and allow this memory data to be cached by the host. Furthermore, the data can be quickly flushed to NAND flash memory during power loss, achieving large-capacity persistent data storage.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a control method for a storage device, a controller for a storage device, a storage device, and a distributed storage system. Background Technology

[0002] The emergence of Compute Express Link (CXL) technology provides a viable technical path for implementing cacheable device memory. While CXL devices offer high-speed and low-latency memory access based on their memory semantics interface, they lack data persistence capabilities. For some application scenarios, especially metadata storage for file systems or databases, the data volume is typically not large, but memory semantics support is required to achieve data persistence. Summary of the Invention

[0003] This application provides a control method for a storage device, a controller for a storage device, a storage device, and a distributed storage system to alleviate or solve the technical problems existing in the prior art.

[0004] In a first aspect, embodiments of this application provide a method for controlling a storage device, comprising: obtaining a persistent refresh request from a host for target data, wherein the target data is data written from the host to the device memory of the storage device based on a compute extended connection memory protocol between the host and the storage device; and in response to the persistent refresh request, persistently storing the target data from the device memory to the non-volatile memory of the storage device.

[0005] Secondly, embodiments of this application provide a controller for a storage device, including: a memory access control module configured to respond to a host's memory access request and write data to or read data from the device memory of the storage device based on a compute extended connection memory protocol; and a bridging module configured to respond to a host's persistent refresh request and persistently store the data written by the host to the device memory in the non-volatile memory of the storage device.

[0006] Thirdly, embodiments of this application provide a storage device, including: device memory, non-volatile memory, and any of the controllers described in embodiments of this application, wherein the controller is connected to the device memory and the non-volatile memory respectively.

[0007] Fourthly, embodiments of this application provide a distributed storage system, including: a storage node, comprising a distributed storage server and a plurality of storage devices of any type described in any of the embodiments of this application corresponding to the distributed storage server; and a block storage server, which forwards access requests from a host to the corresponding storage device for processing, wherein the access request includes at least one of a persistent refresh request, a memory access request, and a non-volatile memory access request.

[0008] This application provides a storage device based on persistent memory (PMEM) technology, which can expose the device memory of the storage device to the host, support the host to access the device memory, and this memory data can not only be cached by the host, but also be flushed to non-volatile memory when power is lost, thus realizing persistent storage of host memory data.

[0009] Optionally, during the data flushing (persistent storage) process after power failure, a preset fast programming mode is adopted to shorten the programming time by reducing the consistency of threshold voltage distribution, so as to complete the flushing of large amounts of data faster.

[0010] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this application and should not be construed as limiting the scope of this application.

[0012] Figure 1 This diagram illustrates the structure of a storage device according to one embodiment of this application.

[0013] Figure 2 This illustration shows a schematic diagram of the structure of a storage device according to another embodiment of this application.

[0014] Figure 3 This illustration shows a structural schematic diagram of a storage device according to another embodiment of the present application;

[0015] Figure 4 This diagram illustrates the interaction between the host and the storage device in an embodiment of this application.

[0016] Figure 5A A schematic diagram of the threshold voltage distribution under standard pSLC programming mode is shown;

[0017] Figure 5B This diagram illustrates the threshold voltage distribution under the preset pSLC programming mode provided in the embodiments of this application.

[0018] Figure 6 This illustration shows an example diagram of power-down data brushing in an embodiment of this application;

[0019] Figure 7 A flowchart illustrating the control method for a storage device provided in an embodiment of this application is shown.

[0020] Figure 8 The illustration shows application scenarios of the storage devices according to Embodiment 1 and Embodiment 2 of this application. Detailed Implementation

[0021] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the concept or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0022] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and all of them fall within the protection scope of the embodiments of this application.

[0023] The following terms will be used hereinafter

[0024] Solid State Drive (SSD): A storage device based on flash memory technology that can replace traditional hard disk drives (HDDs), offering faster read and write speeds, lower latency, and greater shock resistance. SSDs primarily use NAND flash memory chips as their storage medium. SSDs are widely used in data centers, personal computers, and mobile devices, serving as a mainstream storage solution for fast data access and storage.

[0025] Non-Volatile Memory Express (NVMe) protocol: A high-efficiency storage interface protocol specifically designed for flash storage devices, aiming to provide higher throughput and lower latency. The NVMe protocol eliminates the bottleneck of traditional hard drive interfaces by optimizing storage access paths, allowing flash drives to fully utilize their high-speed characteristics.

[0026] Controller Memory Buffer (CMB): Provides a memory semantic interface that presents a buffer containing a portion of device memory as part of host memory. In this way, the host can access data in the CMB as if it were accessing main memory.

[0027] Peripheral Component Interconnect Express (PCIe) is a high-speed input / output (I / O) bus protocol used to connect various peripheral devices within a computer, such as graphics cards, network adapters, and storage controllers. PCIe's high bandwidth and low latency make it a primary technology for connecting various devices in modern computers and data centers. PCIe supports multi-channel parallel transmission, enabling extremely high data throughput.

[0028] CXL: A new type of high-speed interconnect technology that provides interconnection between the central processing unit (CPU) and devices, as well as between devices. By supporting features such as shared memory and cache coherency, it enables the CPU, accelerator cards, storage devices, and other components to work together efficiently.

[0029] PMEM is a non-volatile memory technology located on the memory bus. It combines the high speed and byte-addressable access of Dynamic Random Access Memory (DRAM) with the persistence of traditional storage devices such as hard disk drives and solid-state drives. It supports data access like DRAM and can maintain data persistence after power loss.

[0030] Cacheable data refers to data that can be stored in the CPU's cache (such as L1, L2, and L3 caches), thereby speeding up data retrieval. When the CPU needs to access data, it first checks if the data is already in the cache. If it is (a cache hit), the data can be read directly from the cache, avoiding slower main memory access and improving system performance. For non-cacheable data, each access requires reading directly from main memory or other storage media, which typically leads to higher latency.

[0031] Persistence refers to ensuring that data remains unchanged and is not lost even in the event of power failure or other adverse events. In traditional storage architectures, data is typically first written to volatile memory (such as DRAM) and then synchronized to non-volatile storage media (such as HDDs or SSDs) to guarantee data persistence.

[0032] Example One

[0033] NVMe SSD storage devices, supporting the NVMe protocol, are widely used in data centers due to their high bandwidth and low latency. The NVMe protocol is a block device interface protocol suitable for storage scenarios with I / O data larger than 4KB. However, many non-4KB scenarios exist in data center applications, requiring storage devices to provide byte-addressing capabilities. Therefore, in recent years, there has been much exploration of technologies that provide memory semantic access interfaces on top of NVMe SSD devices.

[0034] One typical technical implementation is the CMB (Continuous Memory Buffer) technology in the NVMe protocol. CMB technology allows the DRAM within an NVMe SSD to be presented as part of the host memory, enabling the host to access this memory in memory semantics. However, the memory semantic interface implemented through CMB technology has some limitations, the most important of which is that this memory cannot be uncacheable by the CPU.

[0035] The emergence of CXL technology provides a viable technical path for enabling cacheable device memory. The CXL interface supports multiple protocols running on PCIe, including CXL Input / Output (CXL.io), CXL Memory (CXL.mem), and CXL Cache (CXL.cache). The CXL.io protocol is similar to the PCIe protocol, and can be considered an "enhanced" PCIe protocol, providing an I / O interface for I / O devices. The CXL.mem protocol allows the host to access data using memory semantics (e.g., write or read commands). CXL devices are essentially PCIe devices, and PCIe devices can be divided into three categories based on the specific CXL protocols they support: The first category supports only the CXL.io protocol; the second category supports both CXL.io and CXL.cache protocols; and the third category supports both CXL.io and CXL.mem protocols, and can be used to connect devices with different memory types, expanding memory bandwidth and capacity, and possessing cacheable capabilities.

[0036] Beyond providing a memory semantic interface, data persistence is also a requirement for many applications. For example, while file system metadata and database metadata are relatively small in volume, they require memory semantic support and must also ensure data persistence. If these applications can achieve data persistence while using a memory semantic interface, it will greatly simplify system design and management. Therefore, PMEM technology has become a key research focus in the industry. PMEM technology can be widely applied to scenarios requiring high throughput, low latency, and data persistence, such as databases and log storage.

[0037] One implementation based on PMEM technology uses a novel storage class memory (SCM) medium. However, the technology for generating SCM media is not mature and cannot achieve large-scale mass production.

[0038] Another implementation of PMEM technology is using non-volatile dual in-line memory modules (NV-DIMMs). This implementation requires an external battery for persistent storage of memory data. However, using an external battery consumes internal server space and also presents reliability and security issues. Therefore, NV-DIMMs are not suitable for deployment in data centers.

[0039] Another implementation based on PMEM technology provides an NVMe SSD device with a CMB (Continuous Memory Management) function on its NVMe controller. This allows the NVMe SSD's DRAM to be exposed to the host, while achieving persistence through supercapacitors and data flushing to NAND during power loss. However, as mentioned earlier, the memory presented by the CMB function cannot be cached by the CPU. This leads to a decrease in access performance, especially in applications that require frequent read / write of small data blocks, failing to fully utilize the advantages of CPU caching and impacting overall system performance.

[0040] Given the various shortcomings of current PMEM technology in its implementation, this application aims to provide a storage device based on PMEM technology that supports the CXL.mem protocol, thereby exposing the device memory of the storage device to the host, supporting host access to the device memory, and this memory data can not only be cached by the host, but also be flushed to non-volatile memory when power is lost (i.e., persistently stored from device memory to non-volatile memory), thus realizing persistent storage of host memory data.

[0041] Figure 1 A schematic diagram of the structure of a storage device according to an embodiment of this application is shown. Figure 1As shown, the storage device includes a controller 100, a device memory 200, and a non-volatile memory 300.

[0042] The device memory 200 can be a volatile storage medium, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The non-volatile memory 300 uses NOR or NAND flash memory as the storage medium.

[0043] For example, the non-volatile memory 300 uses NAND flash memory chips as the storage medium, which not only provides large-capacity storage but also offers high bandwidth for data flushing and significantly reduces data flushing time, thereby improving system reliability and response speed. The following description uses NAND flash memory chips as the storage medium, but this is not a limitation on the storage medium of the non-volatile memory 300.

[0044] NAND flash memory chips can be categorized into at least four types based on their chip type: Single Level Cell (SLC) NAND, Multi Level Cell (MLC) NAND, Trinary Level Cell (TLC) NAND, and Quad Level Cell (QLC) NAND. A cell is the smallest storage unit in NAND, responsible for data storage. In SLC NAND, each cell stores 1 bit of data; in MLC NAND, each cell stores 2 bits of data; in TLC NAND, each cell stores 3 bits of data; and in QLC NAND, each cell stores 4 bits of data. For example, the non-volatile memory 300 includes multiple storage cells. These storage cells can be one or more of SLC, TLC, and QLC storage cells.

[0045] The controller 100 includes a memory access control module 101 and a bridging module 102. The memory access control module 101 is configured to respond to a host's memory access request by writing data to or reading data from the storage device's memory 200 based on the Compute Extended Connection (CXL) memory protocol.

[0046] The CXL memory protocol is the CXL.mem protocol. Through the CXL.mem protocol, the host can access the device memory 200 of the remote storage device as if it were local memory, achieving low-latency and high-bandwidth memory access. For example, the memory access control module 101 supports the CXL interface. As a PCIe interface, the CXL interface enables the memory access control module 101 to communicate with the host and semantically interpret the host's memory access requests as write or read commands to the device memory 200, allowing the host to write data to or read data from the device memory 200. Therefore, based on the memory access control module 101, the controller 100 provides a data path between the host and the device memory 200 (see...). Figure 2 and Figure 4 Pathway ② in the middle.

[0047] In one example, the host initiates a memory access request, including the target address. Controller 100 receives this memory access request through the CXL interface, parses it based on the CXL.men protocol, extracts the corresponding access command (write command or read command), and translates the target address in the access request into a physical address in device memory 200. Based on path ②, the data requested by the host is written to or read from that physical address and returned to the host.

[0048] Furthermore, the bridging module 102 is configured to persistently store data written by the host to device memory 200 to non-volatile memory 300 in response to a persistent refresh request from the host. For example, based on a persistent refresh request from the host, the bridging module transfers data from the DRAM medium of device memory 200 to the NAND medium of non-volatile memory 300, ensuring that data is not lost in the event of power failure or system failure.

[0049] In one example, the host sends a persistent refresh request to controller 100, indicating that data in device memory 200 needs to be persistently stored in non-volatile memory 300. Controller 100's CXL interface receives this persistent refresh request, parses it, and extracts the range of data to be persisted and the target address. Controller 100 then converts the persistent refresh request into an NVMe write command, preparing to transfer data from device memory 200 to non-volatile memory 300. This is based on a bridging path (see...). Figure 2 and Figure 4 In the path ③), the bridging module 102 reads the data that needs to be persisted from the device memory 200 and writes the data to a specified address in the non-volatile memory 300.

[0050] For example, the persistent flush request can be a General Persistent Flush (GPF) request. That is, the controller 100 can follow the GPF process under the CXL protocol for power-down protection, thereby further ensuring compatibility with the CXL protocol.

[0051] For example, the controller 100 also includes a supercapacitor and a power management integrated circuit (PMIC). The supercapacitor is a capacitor with extremely high capacitance, capable of storing and releasing large amounts of electrical energy in a short time. During system power loss and the transfer of data from device memory 200 to non-volatile memory 300, the supercapacitor can provide temporary backup power, ensuring the smooth completion of data transmission and storage operations. The PMIC can monitor the power status and manage and allocate power, triggering necessary protection measures during power loss. In this application example, the PMIC can coordinate the charging and discharging process of the supercapacitor to ensure timely switching to backup power and activation of data protection mechanisms during power loss.

[0052] In this embodiment, the memory access control module 101 provides high-bandwidth and low-latency communication capabilities, enabling the host to efficiently access the device memory 200. The bridging module 102 is configured to respond to the host's persistent refresh request, flushing data from DRAM to NAND to ensure that data is not lost during power failure. Therefore, this embodiment provides a storage device based on PMEM technology, which supports the CXL.mem protocol, thereby exposing the device memory of the storage device to the host, supporting host access to the device memory, and this memory data can be cached by the host. Furthermore, the non-volatile memory of this storage device uses NAND flash memory as the storage medium, ensuring that data can be quickly flushed from DRAM to NAND during power failure, achieving large-capacity persistent data storage.

[0053] In the technical solutions of this application embodiment, both DRAM and NAND are storage media suitable for mass production, and there is no external battery occupying the internal space of the server. Therefore, the technical solutions of this application embodiment are suitable for deployment in data centers to improve the reliability and security of data center storage performance.

[0054] Figure 2 This invention provides a schematic diagram of the structure of a storage device according to an embodiment of the present application. Figure 4 This diagram illustrates the interaction between the host and the storage device in an embodiment of this application. Figure 2As shown, the controller 100 also includes a non-volatile memory access control module 103. The non-volatile memory access control module 103 responds to the host's non-volatile memory access request and writes data to or reads data from the non-volatile memory 300 based on the non-volatile memory fast protocol between the host and the storage device.

[0055] Non-volatile memory access requests are NVMe requests, and the Non-volatile Memory Fast Protocol is the NVMe protocol. Therefore, the non-volatile memory access control module 103 supports the NVMe interface. The NVMe protocol is specifically designed for non-volatile storage devices (such as SSDs) and can improve the transmission efficiency of storage devices.

[0056] For example, such as Figure 4 As shown, the host initiates an NVMe request, the controller 100 receives the NVMe request through the NVMe interface, parses the memory access request based on the NVMe protocol, extracts the corresponding access command (write command or read command), and writes the data to the non-volatile memory 300 or reads the data from the non-volatile memory 300 and returns it to the host based on path ①.

[0057] In other words, the non-volatile memory access control module 103 provides a standardized SSD read and write method. This application embodiment combines the CXL interface with traditional NVMe SSD technology to provide an NVMe SSD device that can support PMEM. It implements the NVMe block device path (path ①) and the CXL memory semantic path (path ②) on the same controller, and supports the flow of data between the two paths based on the bridging channel (path ③).

[0058] Figure 3 A schematic diagram of the structure of a storage device according to an embodiment of this application is shown. Figure 3 As shown, the memory access control module 101 has a compute extended connection memory interface (CXL.mem interface) for communicating with the host, and the non-volatile memory access control module 103 has a non-volatile memory fast interface (NVMe interface) for communicating with the host. The CXL.mem interface and the NVMe interface are configured on different data paths.

[0059] The NVMe interface provides high-bandwidth and low-latency data transmission through the PCIe channel. In the CXL protocol, the CXL.io protocol provides basic I / O functions, and the CXL.io interface provides the underlying PCIe communication path. Therefore, logically, the NVMe interface can utilize the PCIe communication path provided by the CXL.io interface to implement specific read and write operations, enabling the non-volatile memory access control module 103 to run in a CXL-compliant system without additional adaptation.

[0060] Furthermore, although the CXL.mem interface and the NVMe interface share the same PCIe infrastructure, they are configured on different data paths to ensure independence and avoid mutual interference. For example, the CXL.mem interface and the NVMe interface can be assigned to different PCIe paths, or an Input-Output Memory Management Unit (IOMMU) can be used to manage the access permissions and address spaces of different I / O streams. This ensures that the memory access requests processed by the CXL.mem interface and the NVMe requests processed by the NVMe interface are independent of each other, making them physically separate and preventing mutual interference.

[0061] Based on this, by isolating the CXL.mem interface and the NVMe interface, the NVMe block device path (path ①) and the CXL memory semantic path (path ②) can be separated so that they do not interfere with each other, thereby ensuring the reliability of data transmission.

[0062] In one embodiment, the bridging module 102 is configured to persistently store data written to the device memory 200 into the storage unit of the non-volatile memory 300 using a preset pseudo single-level cell (pSLC) programming mode, wherein the programming time of the preset pSLC programming mode is less than a preset time.

[0063] In NAND flash memory, data writing (i.e., programming) is achieved by applying a high voltage (typically tens of volts) to the array of memory cells. This high voltage causes electrons to tunnel into the gate of the NAND memory cell, storing the corresponding data. Figure 4 As shown, based on path ③, the data written to the device memory 200 is persistently stored in the storage unit of the non-volatile memory 300, which is a programming process.

[0064] During programming, the voltage is typically increased in steps, requiring precise control of the increment and duration of each voltage step. Accurate control of these parameters ensures that each NAND flash memory cell in the array has a consistent threshold voltage distribution after programming, which is crucial for data reliability. Generally, longer programming times result in a more uniform threshold voltage distribution and higher data reliability. Conversely, shorter programming times reduce the uniformity of the threshold voltage distribution and decrease data reliability.

[0065] Programming modes include TLC, QLC, and pSLC. In TLC programming, each cell of a NAND flash memory can store 3 bits of data, representing 8 different states. Therefore, the voltage of each cell needs to be divided into 8 different ranges, each corresponding to one state. In TLC programming, the voltage is adjusted to the correct range by gradually increasing it (step-wise) to ensure that each cell represents the desired state. In QLC programming, each cell of a NAND flash memory can store 4 bits of data, representing 16 different states. Therefore, the voltage of each cell needs to be divided into 16 different ranges, each corresponding to one state. In QLC programming, voltage control needs to be more precise because the voltage range for each state is very small. pSLC programming is a mode that simulates SLC, where each cell only stores 1 bit of data, thereby improving the speed of data writing and reading.

[0066] During data flushing (persistent storage) after power loss, pSLC programming mode is typically used. This is because pSLC programming mode has a higher energy efficiency ratio compared to TLC or QLC programming modes, and can support larger data flushing volumes. However, this speed may still be insufficient for high-speed write requirements. For example, in the embodiments of this application, the amount of data to be flushed from the device memory 200 to the storage cells of the non-volatile memory 300 is usually very large, possibly reaching tens or even hundreds of gigabytes, which far exceeds the amount of data required for traditional SSD power-loss protection.

[0067] Meanwhile, considering that in this embodiment, it is only necessary to ensure that the data can be reliably stored for a short period of time (e.g., one month), the requirements for data reliability (especially data retention) can be appropriately relaxed, and the lifespan requirements for NAND can also be reduced. Therefore, a preset pSLC programming mode can be customized. The preset pSLC programming mode is a fast programming mode that can reduce the uniformity of threshold voltage distribution and shorten the programming time, so as to complete the brushing of large amounts of data more quickly.

[0068] The programming time in the preset pSLC programming mode is shorter than the preset time. For example, in the standard pSLC programming mode, the consistency requirement for the threshold voltage distribution is high, such as... Figure 5A As shown, its programming time is typically between 100 and 200 microseconds. However, in the preset pSLC programming mode, the consistency requirement for the threshold voltage distribution is lower, such as... Figure 5BAs shown, its programming time can be shorter than that of the standard pSLC programming mode, for example, 50 to 100 microseconds. Experimental data demonstrates that compared to the standard pSLC programming mode, when the programming time is in the range of 50 to 100 microseconds, the write speed can be significantly accelerated, thereby ensuring that large amounts of data can be flushed in a timely manner.

[0069] The following is combined Figure 6 This application provides an example of power-down data flashing in its embodiments. For example... Figure 6 As shown, based on the storage device and its controller provided in the embodiments of this application, the power-down data flushing process includes steps S601 to S606.

[0070] Step S601: The host determines that the target data that needs to be persisted has been transferred to the device memory 200 of the storage device, and then sends a persistence refresh request, such as a GPF request, to the device to instruct the device to perform data persistence operation.

[0071] Step S602: The device responds to the GPF request, for example, by returning the response result of starting the GPF process.

[0072] Step S603: The device will no longer respond to new IO requests, that is, the device will no longer respond to new memory access requests and new NVMe requests, to ensure that the data in the current cache can be successfully persisted to the NAND storage unit.

[0073] Step S604: Write the cached data and metadata in path ① to the NAND storage cell of the non-volatile memory 300 to avoid data loss due to power failure.

[0074] Step S605: Switch to path ③ and flush the target data from path ② into the device memory 200 to the NAND storage cell. The flushing process uses a preset pSLC programming mode, thereby shortening the data flushing time and ensuring more efficient data persistence. For example, the target data can be persistently stored in the superblock of the non-volatile memory 300 to improve data management and storage efficiency.

[0075] Step S606: Data flushing is complete, and the power-down process is marked as finished in the NOR flash memory. For example, a flag bit is reserved at a specified address in the NOR flash memory. When the data flushing is complete, that is, when the target data has been persistently stored in the non-volatile memory 300, a specific value is written to the flag bit to mark the end of the power-down process.

[0076] It should be noted that when storage devices are used in different systems or fields, other components of the storage devices may differ. Other components of the storage devices in the above embodiments can adopt various technical solutions that are now and in the future known to those skilled in the art, and will not be described in detail here.

[0077] Example Two

[0078] Figure 7 A flowchart illustrating a control method for a storage device according to an embodiment of this application is shown. This control method can be applied to a storage device, for example, executed by a controller of the storage device. This controller can be the controller 100 mentioned above, or a processor capable of running software programs. When the controller executes the software program, it can implement the control method of this embodiment. Figure 7 As shown, the control method may include:

[0079] Step S701: Obtain the persistent refresh request from the host for the target data, wherein the target data is the data written from the host to the device memory of the storage device based on the compute extended connection memory protocol between the host and the storage device;

[0080] Step S702: In response to the persistent refresh request, persistently store the target data from the device memory to the non-volatile memory of the storage device.

[0081] In one embodiment, in step S702, persistently storing the target data from the device memory to the non-volatile memory may include: using a preset pseudo-single-layer granular programming mode to persistently store the target data in the storage unit of the non-volatile memory, wherein the programming time of the preset pseudo-single-layer granular programming mode is less than a preset time.

[0082] In one implementation, the programming time for the preset pseudo-single-layer particle programming mode is 50 microseconds to 100 microseconds, and the non-volatile memory uses NAND particles as the storage medium.

[0083] In one implementation, the control method may further include: writing data to or reading data from device memory based on a compute extended connection memory protocol in response to a host memory access request.

[0084] In one embodiment, the control method may further include: in response to a non-volatile memory access request from the host, writing data to or reading data from the non-volatile memory of the storage device based on the Non-volatile Memory Fast Protocol between the host and the storage device.

[0085] The specific implementation methods and technical effects can be found in the relevant description of Embodiment 1, and will not be repeated here. In the above embodiments, implementation can be achieved wholly or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented wholly or partially in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another.

[0086] Corresponding to the method provided in Embodiment 2 of this application, this application also provides a control device for a storage device, used to implement the control method of Embodiment 2. The control device includes: a persistent refresh request acquisition module, used to acquire a persistent refresh request from the host for target data, wherein the target data is data written from the host to the device memory of the storage device based on the Compute Extended Connection Memory Protocol (CEPDM) between the host and the storage device; and a persistent storage module, used to persistently store the target data from the device memory to the non-volatile memory of the storage device in response to the persistent refresh request.

[0087] In one implementation, the persistent storage module is specifically used to: persistently store the target data in the storage unit of the non-volatile memory using a preset pseudo-single-layer granular programming mode, wherein the programming time of the preset pseudo-single-layer granular programming mode is less than a preset time.

[0088] In one implementation, the programming time for the preset pseudo-single-layer particle programming mode is 50 microseconds to 100 microseconds, and the non-volatile memory uses NAND particles as the storage medium.

[0089] In one embodiment, the control device may further include a memory control module for writing data to or reading data from the device memory based on the Compute Extended Connection Memory Protocol in response to a host memory access request.

[0090] In one embodiment, the control method may further include a non-volatile memory control module, configured to write data to or read data from the non-volatile memory of the storage device in response to a non-volatile memory access request from the host, based on the Non-volatile Memory Fast Protocol between the host and the storage device.

[0091] The functions of each module in each device in the embodiments of this application can be found in the corresponding description in the above method, and they have corresponding beneficial effects, which will not be repeated here.

[0092] This application also provides a storage device, including device memory, non-volatile memory, and a controller connected to the device memory and non-volatile memory respectively. When the storage device is used in different systems or fields, other configurations of the storage device may differ. Other configurations of the storage device in the above embodiments can employ various technical solutions now and in the future known to those skilled in the art, and will not be described in detail here.

[0093] Application Scenario

[0094] Figure 8 The diagram illustrates application scenarios of the storage devices according to Embodiments 1 and 2 of this application. Figure 8 As shown, based on this storage device, this application provides a distributed storage system, including storage nodes and a block server. The storage node includes a distributed storage server (Chunk Server) and multiple storage devices corresponding to the Chunk Server. The storage devices are the storage devices of Embodiments 1 and 2 of this application, that is, the storage devices in the distributed storage system are PMEM-based NVMe SSD devices, meaning the device memory of the storage device is PMEM. The Block Server forwards access requests from the host to the corresponding storage device for processing, wherein the access requests include at least one of persistent refresh requests, memory access requests, and non-volatile memory access requests.

[0095] For example, the cloud disk control center distributes host requests to the corresponding Block Server via a Network Interface Controller (NIC). The Block Server's host memory is used to cache and process request data from the cloud disk control center. When the host needs to access PMEM data, the Block Server can directly initiate a memory access request through the CXL channel where the CXL.mem interface of the storage device resides, and directly access the data stored in PMEM using the CXL-mapped memory space. When the host needs to access persistent data (non-volatile memory), the Block Server communicates with the storage device through the NVMe interface of the storage device to complete the exchange of data between non-volatile memory.

[0096] like Figure 8As shown, in the front-end service of the distributed storage system, based on the data path represented by the solid line (writing to the storage device) and the dotted line (reading from the storage device), the host directly accesses the device memory data of the storage device mapped in the memory space through the CXLmem interface. This memory data can be cached by the host, enabling large-capacity persistent data storage in the event of power failure. In the back-end service of the distributed storage system, based on the data path represented by the dashed line, the ChunkServer writes data to the non-volatile memory of the storage device through the NVMe interface.

[0097] exist Figure 8 In the distributed storage system shown, if a PMEM larger than 512GB needs to be configured on the server, low-cost deployment can be achieved using the NVMe SSD devices based on PMEM that come with the Chunk Server itself. Specifically, assuming each NVMe SSD device provides 7.68TB of NAND storage capacity and 128GB of DRAM storage capacity, with 64GB of DRAM having power-loss protection, this 64GB of DRAM can be presented as host memory via the CXL protocol and provides PMEM functionality. In this configuration, a single server can support up to 16 NVMe SSD devices, providing 16 x 64GB = 1TB of PMEM space with high bandwidth performance. Assuming the controller provides 32GB / s bandwidth for the CXL path, and the NVMe block device path (path ①) where the NVMe interface resides and the CXL memory semantic path (path ②) where the CXL.mem interface resides each use 4 PCIe lanes, then 16 NVMe SSD devices can achieve a total CXL memory access bandwidth of 512GB / s.

[0098] It should be noted that the application scenarios or examples provided in this application embodiment are for ease of understanding and are not specifically limited thereto. Furthermore, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. The collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to select, edit, authorize, or refuse.

[0099] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0101] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0102] The logic and / or steps described in the flowchart or otherwise herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0103] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0104] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0105] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope described in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for controlling a storage device, comprising: Obtain a persistent refresh request from the host for target data, wherein the target data is data written from the host to the device memory of the storage device based on the compute extended connection memory protocol between the host and the storage device; In response to the persistent refresh request, the target data is persistently stored from the device memory to the non-volatile memory of the storage device.

2. The method according to claim 1, wherein, Persistently storing the target data from the device memory to the non-volatile memory includes: The target data is persistently stored in the storage unit of the non-volatile memory using a preset pseudo-single-layer granular programming mode, wherein the programming time of the preset pseudo-single-layer granular programming mode is less than the preset time.

3. The method according to claim 2, wherein, The non-volatile memory uses NAND flash memory as the storage medium, and the programming time of the preset pseudo-single-layer flash memory programming mode is 50 microseconds to 100 microseconds.

4. The method according to any one of claims 1 to 3, further comprising: In response to a memory access request from the host, data is written to or read from the device memory based on the Compute Extended Connection Memory Protocol.

5. The method according to any one of claims 1 to 3, further comprising: In response to a non-volatile memory access request from the host, data is written to or read from the non-volatile memory of the storage device based on the Non-volatile Memory Fast Protocol between the host and the storage device.

6. A controller for a storage device, comprising: The memory access control module is configured to respond to a host's memory access request by writing data to or reading data from the device memory of the storage device based on the Compute Extended Connection Memory Protocol. The bridging module is configured to respond to a persistent refresh request from the host by persistently storing the data written by the host to the device memory to the non-volatile memory of the storage device, wherein the non-volatile memory uses NAND flash memory as the storage medium.

7. The controller according to claim 6, wherein, The bridging module is configured to use a preset pseudo-single-layer granular programming mode to persistently store the data written to the device memory into the storage unit of the non-volatile memory, wherein the programming time of the preset pseudo-single-layer granular programming mode is less than a preset time.

8. The controller according to claim 6 or 7, further comprising: The non-volatile memory access control module is configured to respond to a non-volatile memory access request from the host and, based on the non-volatile memory fast protocol between the host and the storage device, write data to or read data from the non-volatile memory.

9. The controller according to claim 8, wherein, The memory access control module has a compute extension connection memory interface that communicates with the host, and the non-volatile memory access control module has a non-volatile memory fast interface that communicates with the host. The compute extension connection memory interface and the non-volatile memory fast interface are configured on different data paths.

10. A storage device, comprising: The device memory, the non-volatile memory, and the controller as described in any one of claims 6 to 9, wherein the controller is connected to the device memory and the non-volatile memory, respectively.

11. A storage device, comprising: The device memory, the non-volatile memory, and the controller for implementing the method of any one of claims 1 to 5, the controller being connected to the device memory and the non-volatile memory, respectively.

12. A distributed storage system, comprising: A storage node includes a distributed storage server and multiple storage devices corresponding to the distributed storage server, wherein the storage devices are as described in claim 10 or 11; A block storage server forwards access requests from a host to the corresponding storage device for processing. The access requests include at least one of persistent refresh requests, memory access requests, and non-volatile memory access requests.

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