Storage device and operating method of storage device

Abstract

A storage device and an operating method thereof are provided. The storage device includes a nonvolatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks, and a storage controller configured to transmit a command and an address to the nonvolatile memory device, communicate first data with the nonvolatile memory device, allocate one of the plurality of sub-blocks to a first area based on first information about a programming speed or an erase speed of the plurality of sub-blocks, and write second data of a write request received from an external host device together with second information into the first area.

Description

Cross-reference of related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0180923, filed on December 6, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some exemplary embodiments of the inventive concept described herein relate to a storage device, and more specifically, to a storage device and / or a method of operating the storage device that performs a clearing operation at an improved speed. Background Technology

[0003] Storage devices refer to devices that store data under the control of host devices such as computers, smartphones, and / or smart tablets. Storage devices include devices that store data on disks (such as hard disk drives (HDDs)) and / or devices that store data in semiconductor memory, particularly in non-volatile memory (such as solid-state drives (SSDs) and / or memory cards).

[0004] Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0005] With advancements in semiconductor manufacturing technology, the operating speed of host devices (such as computers, smartphones, and / or tablets) that communicate with storage devices has improved. Furthermore, the size of content used in both storage devices and their host devices is increasing. Therefore, providing storage devices with improved operating speeds is likely advantageous. Summary of the Invention

[0006] Some exemplary embodiments of the present invention provide a storage device and / or a method of operating the storage device that performs a clearing operation at an improved speed.

[0007] According to some example embodiments, a storage device includes: a non-volatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks; and a storage controller configured to send commands and addresses to the non-volatile memory device, communicate first data with the non-volatile memory device, allocate one of the plurality of sub-blocks to a first region based on first information regarding programming speed or erasure speed of the plurality of sub-blocks, and write second data of a write request to the first region, the write request being received from an external host device along with the second information.

[0008] According to some example embodiments, a storage device includes: a non-volatile memory device including a plurality of memory blocks; and a storage controller configured to send commands and addresses to the non-volatile memory device, communicate first data with the non-volatile memory device, write second data of a first write request received from an external host device along with first information into a first region, read second information from the non-volatile memory device about memory cells allocated to the first region, and write third data of a second write request based on the second information into the first region, the second write request being received from the external host device along with the third information.

[0009] According to some example embodiments, a method of operating a storage device includes a non-volatile memory device and a storage controller. The non-volatile memory device includes a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks. The storage controller is configured to send commands and addresses to the non-volatile memory device and communicate first data with the non-volatile memory device. The method includes: at the storage controller, allocating one of the plurality of sub-blocks to a first region based on first information regarding programming speed or erasure speed of the plurality of sub-blocks; and at the storage controller, writing second data of a write request to the first region, the write request being received from an external host device along with the second information.

[0010] According to some example embodiments, a system may include: a host and a storage device, the storage device including a non-volatile memory device and a storage controller, the non-volatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks, the storage controller being configured to: send commands and addresses to the non-volatile memory device, communicate first data with the non-volatile memory device, allocate one of the plurality of sub-blocks to a first region based on first information about the programming speed or erasure speed of the plurality of sub-blocks, receive a write request and second information from the host, and write the second data of the write request to the first region.

[0011] In some example embodiments, the storage controller is configured to assign a first sub-block of a plurality of sub-blocks to a first region, the first sub-block having a fast programming or erasing speed.

[0012] In some example embodiments, the second information includes a specific logical unit or a specific flow identifier.

[0013] In some example embodiments, the non-volatile memory device includes a substrate and a plurality of cell strings disposed on the substrate along a first direction and a second direction, each of the plurality of cell strings including a plurality of stacks stacked on the substrate along a third direction, and each of the plurality of stacks including a plurality of memory cells stacked along a third direction. Attached Figure Description

[0014] The above and other objects and features of the present invention will become apparent from a detailed description of some exemplary embodiments of the invention with reference to the accompanying drawings.

[0015] Figure 1 A computing device according to some example embodiments is shown.

[0016] Figure 2 This is a block diagram illustrating a non-volatile memory device according to some example embodiments.

[0017] Figure 3 This illustrates some example embodiments. Figure 2 A circuit diagram of an example memory block among the memory blocks.

[0018] Figure 4 A side view of the a memory block according to some example embodiments is shown.

[0019] Figure 5 The operation of a storage device according to some example embodiments is illustrated.

[0020] Figure 6 An example is shown of allocating a first region in the a memory block according to some example embodiments.

[0021] Figure 7 Another example is shown, illustrating the allocation of a first region in the a-th memory block according to some example embodiments.

[0022] Figure 8 An example is shown where a storage device, according to some example embodiments, performs a cleanup operation upon a request from a host.

[0023] Figure 9 Examples of performing an erase operation in a non-volatile memory device according to some example embodiments are shown.

[0024] Figure 10 Examples of performing a secure erase operation in a non-volatile memory device are shown according to some example embodiments.

[0025] Figure 11 An example is shown of allocating a first region across multiple memory blocks according to some example embodiments.

[0026] Figure 12 An example is shown where an RPMB is allocated to the first sub-block of a third memory block, according to some example embodiments.

[0027] Figure 13 An example is shown where some first sub-blocks of a first memory block and some first sub-blocks of a second memory block are allocated together to the RPMB according to some example embodiments.

[0028] Figure 14 An example is shown where a storage controller, according to some example embodiments, assigns a third sub-block of a first memory block to an RPMB.

[0029] Figure 15 The operation of a storage device according to some example embodiments is illustrated.

[0030] Figure 16 An example of priority allocation by a storage controller is shown according to some example embodiments.

[0031] Figure 17 This is a diagram illustrating a system according to some example embodiments. Detailed Implementation

[0032] Below, some exemplary embodiments of the inventive concept will be described in detail and clearly to enable those skilled in the art to readily implement the inventive concept.

[0033] It will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being “on” another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly on” another element, there are no intermediate elements present. It will also be understood that when an element is referred to as being “on” another element, it may be above or below that other element, or adjacent to that other element (e.g., horizontally adjacent).

[0034] It will be understood that elements and / or their properties may be described herein as “the same” or “equivalent” to other elements, and it will also be understood that elements and / or their properties described herein as “the same,” “identical,” or “equivalent” to other elements may be “the same,” “identical,” “equivalent,” “substantially the same,” “substantially identical,” or “substantially equivalent” to those other elements. Elements and / or their properties that are “substantially the same,” “substantially identical,” or “substantially equivalent” to other elements and / or their properties will be understood to include elements and / or their properties that are the same, identical, or equivalent to those other elements and / or their properties within manufacturing tolerances and / or material tolerances. Elements and / or their properties that are the same or substantially the same and / or identical or substantially identical to other elements and / or their properties may be structurally the same or substantially identical, functionally the same or substantially identical, and / or composed of the same or substantially identical.

[0035] Figure 1 A computing device 100 according to some example embodiments is shown. (Refer to...) Figure 1 The computing device 100 may include a storage device 110 and a host (or host device) 120.

[0036] Storage device 110 can operate under the control of host 120. Storage device 110 may include non-volatile memory device 111 and memory controller 112.

[0037] The memory controller 112 can send commands and addresses CA to the non-volatile memory device 111. For example, the memory controller 112 can send a clock signal CLK to the non-volatile memory device 111, and can send commands and addresses CA to the non-volatile memory device 111 synchronously with the clock signal CLK.

[0038] The memory controller 112 can communicate a data strobe signal DQS with the non-volatile memory device 111, and can send and / or issue a read enable signal RE to the non-volatile memory device 111. The memory controller 112 can communicate data DQ with the non-volatile memory device 111 synchronously with the data strobe signal DQS.

[0039] In some example embodiments, when the storage controller 112 sends and / or issues data DQ to the non-volatile memory device 111, the storage controller 112 may send and / or issue a data strobe signal DQS to the non-volatile memory device 111, and may send and / or issue data DQ to the non-volatile memory device 111 synchronously with the data strobe signal DQS.

[0040] In some example embodiments, when the storage controller 112 receives data DQ from the non-volatile memory device 111, the storage controller 112 may send and / or issue a read enable signal RE to the non-volatile memory device 111. The non-volatile memory device 111 may delay the read enable signal RE to generate a data strobe signal DQS. The non-volatile memory device 111 may send and / or issue the data strobe signal DQS to the storage controller 112, and may send and / or issue the data DQ to the storage controller 112 synchronously with the data strobe signal DQS.

[0041] The non-volatile memory device 111 may send and / or issue a ready / busy signal RnB to the memory controller 112. In some example embodiments, when the ready / busy signal RnB is at a first level (e.g., high), the ready / busy signal RnB may indicate that the non-volatile memory device 111 is in a state where it can receive new commands (or alternatively, additional commands) and can perform new access operations (or alternatively, additional access operations) on data written to the non-volatile memory device 111. In some example embodiments, when the ready / busy signal RnB is at a second level (e.g., low), the ready / busy signal RnB may indicate that the non-volatile memory device 111 is in a state where it cannot receive new commands (or alternatively, additional commands) and cannot perform new access operations (or alternatively, additional access operations) on data written to the non-volatile memory device 111.

[0042] The non-volatile memory device 111 may include a memory cell array MCA, a command parser CMDP, an operation controller OPC, a general-purpose internal buffer UIB, and a feature register FR.

[0043] The memory cell array (MCA) may include multiple memory cells. The non-volatile memory device 111 can store data in the memory cells of the memory cell array (MCA). Even when the power to the storage device 110 is turned off, the data stored in the memory cells of the memory cell array (MCA) can be retained.

[0044] The Command Parser (CMDP) can parse commands received from the Storage Controller 112 as commands and addresses (CA). The CMDP can then transmit the parsing results to the Operation Controller (OPC). The OPC can control the operation of the non-volatile memory device 111 based on the parsing results from the CMDP. For example, the OPC can control the non-volatile memory device 111 to perform read, write, and / or erase operations.

[0045] The general-purpose internal buffer (UIB) can store settings associated with various operations of the non-volatile memory device 111. For example, the UIB can store various parameters associated with read, write, and / or erase operations, such as voltage levels and / or the number of voltage applications. In some example embodiments, the UIB can be implemented using an electric fuse. When the memory controller 112 sends and / or issues a specific (or alternatively, desired) command via command and address CA through its first transmitted line, the memory controller 112 can enter a mode for setting the UIB and can set the value of the UIB via data DQ through its second transmitted line. Then, when the memory controller 112 sends and / or issues a specific (or alternatively, desired) command or another (e.g., additional) specific (or alternatively, desired) command via command and address CA through its first transmitted line, the memory controller 112 can terminate the mode for setting the UIB.

[0046] The feature register FR can store various features associated with commands received via the command and address CA through the first line through which they are transmitted. For example, the feature register FR can store information about whether each command is executed in any way. The storage controller 112 can set the feature register FR by sending and / or issuing a set feature command via the command and address CA through the first line through which it is transmitted.

[0047] Storage controller 112 may receive a request REQ from host 120. In response to the request REQ, storage controller 112 may send and / or issue a command and address CA to non-volatile memory device 111 to perform a specific (or alternatively, desired) operation and / or perform internal operations. In some example embodiments, upon completion of the operation according to the request REQ, storage controller 112 may send and / or issue a response RESP to host 120. The response RESP may include information about the request REQ and information about the result of the operation performed according to the request REQ. Storage controller 112 may communicate with host 120 to manage various control signals CTRL of storage device 110.

[0048] Storage controller 112 may include a buffer memory BUF, a queue QUE, and a secure erase controller SEC. Storage controller 112 may use the buffer memory BUF to buffer data to be written from host 120 to non-volatile memory device 111 and data to be read from non-volatile memory device 111 to host 120.

[0049] The storage controller 112 can read a mapping table or a portion thereof from the non-volatile memory device 111 for storage in a buffer memory (BUF). The mapping table may include information about the relationship between logical addresses managed by the host 120 and the physical addresses of the non-volatile memory device 111. The storage controller 112 can generate the mapping table when the host 120 writes data to the non-volatile memory device 111. The storage controller 112 can use the generated mapping table to process read requests from the host 120.

[0050] Storage controller 112 can arrange requests transmitted from host 120 into queue QUE. Storage controller 112 can perform reordering to change the execution order of requests arranged into queue QUE.

[0051] The secure erase controller SEC of storage controller 112 can control secure erase operations. For example, when a erase request is received from host 120, the secure erase controller SEC of storage controller 112 can perform a secure erase operation.

[0052] For example, the non-volatile memory device 111 may include a NAND flash memory device. The non-volatile memory device 111 may not support rewrite operations. In some example embodiments, when the host 120 requests an update to data written to the storage device 110, the storage controller 112 can invalidate the original data present in the non-volatile memory device 111 in a mapping table by marking it as "invalid," and can write the updated data to a free area. By invalidating the data, the storage controller 112 can reduce the number of read, write, and / or erase operations in the non-volatile memory device 111 and can improve the lifespan of the non-volatile memory device 111.

[0053] According to some example embodiments, a portion of the data stored by host 120 in storage device 110 may be secure data, and this portion of data may be advantageous for providing secure data with high security. For example, host 120 may store keys used for data encryption in storage device 110. In some example embodiments, even if the secure data is invalidated in the mapping table of storage device 110, the secure data can still be exposed by means such as hacking. Therefore, host 120 may request the physical erasure of secure data from storage device 110 instead of invalidating the secure data. For example, host 120 may request the physical erasure of data associated with a erase request by sending and / or issuing an erase request to storage device 110.

[0054] In response to a wipe request from host 120, storage controller 112 may physically erase the data associated with the wipe request on non-volatile memory device 111. For example, the secure erase controller SEC of storage controller 112 may control the wipe operation in response to the wipe request. The secure erase controller SEC may control non-volatile memory device 111 such that the data identified by the wipe request is physically erased. In some example embodiments, storage controller 112 may also physically erase invalid copy data when duplicate data of secure data (e.g., invalid copy data of secure data) is present.

[0055] In some example embodiments, host 120 may activate and / or deactivate the cleanup operation based on a cleanup request. In some example embodiments, host 120 may activate and / or deactivate the cleanup operation by using a Universal Flash Query Request (UFS Protocol Information Unit) (UPIU).

[0056] Figure 2 This is a block diagram illustrating a non-volatile memory device 200 according to some example embodiments. (Refer to...) Figure 1 and Figure 2 The non-volatile memory device 200 includes a memory cell array 210, a row decoder block 220, a page buffer block 230, a pass / fail check block (PFC) 240, a data input and output block 250, a data buffer 260, a command and address buffer 270, and a control logic block 280.

[0057] Memory cell array 210 includes multiple memory blocks BLK1 to BLKz. Each of memory blocks BLK1 to BLKz includes multiple memory cells. Each of memory blocks BLK1 to BLKz is connected to line decoder block 220 via at least one ground select line GSL, a word line WL, and at least one string select line SSL. Some of the word lines WL can be used as pseudo-word lines. Each of memory blocks BLK1 to BLKz is connected to page buffer block 230 via multiple bit lines BL. Multiple memory blocks BLK1 to BLKz can be jointly connected to multiple bit lines BL.

[0058] In some example embodiments, each of the plurality of memory blocks BLK1 to BLKz may correspond to a unit of erase operation. Memory cells belonging to each memory block may be erased simultaneously. In some example embodiments, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of erase operation. For example, the unit of erase operation may be the minimum number of sub-blocks that can be erased at once.

[0059] The row decoder block 220 is connected to the memory cell array 210 via the ground select line GSL, the word line WL, and the serial select line SSL. The row decoder block 220 operates under the control of the control logic block 280.

[0060] The row decoder block 220 can decode the row address RA received from the control logic block 280, and can control the voltage to be applied to the serial select line SSL, word line WL and ground select line GSL based on the decoded row address.

[0061] Page buffer block 230 is connected to memory cell array 210 via multiple bit lines BL. Page buffer block 230 is connected to data input and output block 250 via multiple data lines DL. Page buffer block 230 operates under the control of control logic block 280.

[0062] During programming operations, page buffer block 230 can store data to be written to memory cells. Page buffer block 230 can apply voltages to multiple bit lines BL based on the stored data. During read operations or verification read operations performed during programming or erasure operations, page buffer block 230 can sense the voltage of bit lines BL and store the sensing results.

[0063] In a verification read operation associated with a programming or erasing operation, pass / fail detection block 240 can verify the sensing results of page buffer block 230. For example, in a verification read operation performed during a programming operation, pass / fail detection block 240 can count the number of values ​​(e.g., the number of "0") corresponding to conduction cells that have not been programmed to a target threshold voltage or higher.

[0064] In the verification read operation performed during the erase operation, the pass / fail check block 240 may count the number of values ​​(e.g., the number of "1"s) corresponding to cutoff cells that have not been erased to a target threshold voltage or lower. In some example embodiments, when the count result is greater than or equal to the threshold, the pass / fail check block 240 may output a failure signal to the control logic block 280. In some example embodiments, when the count result is less than the threshold, the pass / fail check block 240 may output a pass signal to the control logic block 280. Based on the verification result of the pass / fail check block 240, a programming loop for programming operations may be further executed, and / or an erase loop for erasing operations may be further executed.

[0065] Data input / output block 250 is connected to page buffer block 230 via multiple data lines DL. Data input / output block 250 receives column address CLA from control logic block 280. Data input / output block 250 outputs data DATA read from page buffer block 230 to data buffer 260 based on column address CLA. Data input / output block 250 can also transfer data received from data buffer 260 to page buffer block 230 based on column address CLA.

[0066] Data buffer 260 operates under the control of control logic block 280. Data buffer 260 can receive data DQ from memory controller 112 synchronously with data strobe signal DQS from memory controller 112. Data buffer 260 can receive data strobe signal DQS from command and address buffer 270. Data buffer 260 can output data DQ to memory controller 112 synchronously with data strobe signal DQS received from command and address buffer 270.

[0067] Command and address buffer 270 operates under the control of control logic block 280. Command and address buffer 270 can receive commands and addresses CA synchronously with the clock signal CLK from memory controller 112. Command and address buffer 270 can transmit the received commands and addresses CA to control logic block 280. Command and address buffer 270 can receive a read enable signal RE from memory controller 112. Command and address buffer 270 can delay the read enable signal RE to generate a data strobe signal DQS. Command and address buffer 270 can transmit the generated data strobe signal DQS to data buffer 260.

[0068] Control logic block 280 can receive commands and addresses (CA) from command and address buffer 270. Control logic block 280 can parse the commands and addresses (CA) received from command and address buffer 270, and can control the non-volatile memory device 200 according to the parsed commands. Control logic block 280 can extract the row address (RA) and column address (CLA) by decoding the addresses of the commands and addresses (CA) received from command and address buffer 270. Control logic block 280 can transmit the row address (RA) to row decoder block 220, and can transmit the column address (CLA) to data input and output block 250.

[0069] In some example embodiments, control logic block 280 may include references Figure 1 The command parser CMDP, operation controller OPC, general internal buffer UIB, and feature register FR are described.

[0070] In some example embodiments, the non-volatile memory device 200 can be fabricated using a bonding method. The memory cell array 210 can be fabricated using a first wafer, and the line decoder block 220, page buffer block 230, pass / fail check block 240, data input and output block 250, data buffer 260, command and address buffer 270, and control logic block 280 can be fabricated using a second wafer. The non-volatile memory device 200 can be implemented by coupling the first and second wafers such that the upper surfaces of the first and second wafers face each other.

[0071] According to some example embodiments, a non-volatile memory device 200 can be fabricated using a cell-on-periphery (COP) method. Peripheral circuitry including a row decoder block 220, a page buffer block 230, a pass / fail check block 240, a data input and output block 250, a data buffer 260, a command and address buffer 270, and a control logic block 280 can be implemented on the substrate. A memory cell array 210 can be implemented on the peripheral circuitry. The peripheral circuitry and the memory cell array 210 can be connected using pass-through components.

[0072] Figure 3 This illustrates some example embodiments. Figure 2 A circuit diagram of an example memory block BLKa from memory blocks BLK1 to BLKz. (Refer to...) Figure 3 Multiple cell strings CS11, CS12, CS21, and CS22 can be arranged in rows and columns on the substrate SUB. Each row can extend along a first direction. Each column can extend along a second direction. The multiple cell strings CS11, CS12, CS21, and CS22 can be collectively connected to a common source line CSL formed on (or within) the substrate SUB. Figure 3 In order to better understand the structure of the memory block BLKa according to some example embodiments, the location of the substrate SUB is depicted as an example.

[0073] The cell strings CS11, CS12, CS21, and CS22 of each row can be connected together to the ground select line GSL, and can also be connected to the corresponding select lines among the first select lines SSL1a and SSL1b and the second select lines SSL2a and SSL2b. The string of each column can be connected to the corresponding bit line among the first bit line BL1 and the second bit line BL2.

[0074] Each cell string CS11, CS12, CS21, and CS22 may include at least one ground select transistor GST connected to the ground select line GSL and multiple memory cells MC1 to MC8 connected to multiple word lines WL1 to WL8, respectively. Cell strings CS11 and CS12 in the first row may also include string select transistors SSTa and SSTb connected to the first string select lines SSL1a and SSL1b, respectively. Cell strings CS22 and CS21 in the second row may also include string select transistors SSTa and SSTb connected to the second string select lines SSL2a and SSL2b, respectively.

[0075] In each cell string CS11, CS12, CS21, CS22, the ground selection transistor GST, memory cells MC1 to MC8, and string selection transistors SSTa and SSTb may be connected in series in a direction perpendicular to the substrate SUB (e.g., a third direction), and may be stacked sequentially in this direction. In each of the cell strings CS11, CS12, CS21, and CS22, at least one of the memory cells MC1 to MC8 may be used as a dummy memory cell. The dummy memory cell may not be programmed (e.g., may be disabled for programming) or may be programmed to be different from the other memory cells in the memory cells MC1 to MC8.

[0076] In some example embodiments, memory cells located at the same height and associated with one of the string select lines SSL1a, SSL1b, SSL2a, and SSL2b may constitute a physical page. Memory cells of a physical page may be connected to a subword line. Subword lines of physical pages located at the same height may be connected together to a word line. Hereinafter, the term "word line" may be used to refer to a word line or a subword line and may be interpreted based on the context.

[0077] An example is shown according to some exemplary embodiments, wherein the memory block BLKa includes cell strings CS11, CS12, CS21 and CS22 at the intersection of a first row corresponding to the first string select lines SSL1a and SSL1b, a second row corresponding to the second string select lines SSL2a and SSL2b, a first column corresponding to the first bit line BL1, and a second column corresponding to the second bit line BL2, but the number of rows and columns of cell strings included in the memory block BLKa is not limited thereto.

[0078] Figure 4 A side view of the a memory block BLKa according to some example embodiments is shown. (Refer to...) Figure 1 , Figure 2 , Figure 3 and Figure 4 Each of the a-th cell string CSa and the b-th cell string CSb may include multiple stacks stacked on the substrate. Each stack may indicate a portion of the cell string, and the width of each stack increases with distance from the substrate. For example, each of the a-th cell string CSa and the b-th cell string CSb may include three stacks.

[0079] The storage controller 112 can allocate stacks of each of the a-th cell string CSa and the b-th cell string CSb to sub-blocks. For example, the storage controller 112 can allocate stacks of each of the a-th cell string CSa and the b-th cell string CSb to a first sub-block SBLK1, a second sub-block SBLK2, and a third sub-block SBLK3. Sub-blocks may correspond to units of erase operations. The storage controller 112 can generate erase (ERS) commands for each sub-block SBLK1, SBLK2, and SBLK3.

[0080] In some example embodiments, the capacity of the stacked components included in each of the a-th unit string CSa and the b-th unit string CSb may be different. For example... Figure 4 As shown, in each stack, the dashed lines can be the dividing lines of memory cells. For example, the stack of the first sub-block SBLK1 may include four layers of memory cells. The second sub-block SBLK2 may include seven layers of memory cells. The third sub-block SBLK3 may include six layers of memory cells. However, the number of memory cells included in each stack according to some example embodiments is not limited to this. Memory cells belonging to each layer may be connected to the same word line.

[0081] Simultaneously, among sub-blocks of different sizes, sub-blocks of the same size can form a super sub-block. For example, sub-block SBLK1 of the a-th unit string CSa and sub-block SBLK1 of the b-th unit string CSb can form a first super sub-block. Similarly, sub-block SBLK2 of the a-th unit string CSa and sub-block SBLK2 of the b-th unit string CSb can form a second super sub-block, and sub-block SBLK3 of the a-th unit string CSa and sub-block SBLK3 of the b-th unit string CSb can form a third super sub-block. Furthermore, super sub-blocks can also be extended to sub-blocks belonging to other memory blocks. For example, among sub-blocks belonging to a memory block different from memory block BLKa, a sub-block with the same size as sub-block SBLK1 of the a-th unit string CSa can be considered to belong to the first super sub-block.

[0082] Figure 5 The operation of a storage device 110 according to some example embodiments is illustrated. (Refer to...) Figure 1 and Figure 4 as well as Figure 5 In operation S110, the storage controller 112 may read sub-block (SBLK) information from the non-volatile memory device 111. For example, the sub-block (SBLK) information may be information obtained through test operations during the manufacturing process of the storage device 110 and written into the non-volatile memory device 111. The sub-block (SBLK) information may include programming or erasure information for the first sub-block SBLK1, the second sub-block SBLK2, and the third sub-block SBLK3 of each of the a-th cell string CSa and the b-th cell string CSb, and / or information regarding reliability.

[0083] In operation S120, storage controller 112 may allocate a specific (or alternatively, desired) dataset for a sub-block SBLK corresponding to sub-block (SBLK) information (e.g., a sub-block SBLK assigned to a first region). For example, storage controller 112 may receive a specific (or alternatively, desired) identifier (e.g., information requesting that data with logical unit LU or stream identifier be written to a specific (or alternatively, desired) first region) from host 120. Storage controller 112 may allocate a dataset with a specific (or alternatively, desired) identifier so that it can be written to the specific (or alternatively, desired) first region.

[0084] In operation S130, storage controller 112 may write a specific (or alternatively, desired) dataset with a specific (or alternatively, desired) identifier into a sub-block SBLK allocated to the first region.

[0085] In some example embodiments, a specific (or alternatively, desired) identifier may be a logical unit LU indicating an RPMB (Replay Protection Memory Block). The RPMB may store secure data such as data encryption keys. In some example embodiments, when it is advantageous for host 120 to erase secure data stored in the RPMB, host 120 may send and / or issue a wipe request to storage controller 112 to prevent and / or reduce the possibility of secure data leakage. For example, wipe requests for the RPMB, which is a first area, may be more frequent than for any other area. Because wipe requests may involve physical erasure, processing wipe requests may take longer than invalidating the data.

[0086] The subblock (SBLK) information may include information about subblocks in each of the a-th cell string CSa and the b-th cell string CSb that have relatively fast programming or erasing speeds and have reliability ensured during the testing process of the storage device 110. In some example embodiments, the programming or erasing speed and reliability may be tested during the testing process of the storage device 110. The information of the tested subblocks may be written into the non-volatile memory device 111 as subblock (SBLK) information.

[0087] The storage controller 112 can select sub-blocks to be allocated to the RPMB based on programming or erasing speed and reliability. Allocating sub-blocks with fast programming or erasing speeds and high reliability to the RPMB can improve the speed of executing clear requests to the RPMB.

[0088] In some example embodiments, there may be datasets that host 120 does not write to in the RPMB but have security that host 120 intends to protect by clearing requests. Host 120 may assign a stream identifier to the corresponding dataset and may provide the stream identifier to storage controller 112. Storage controller 112 may select a second region from the remaining regions besides the region assigned to the RPMB, taking into account programming speed or erase speed and reliability, and may write data with the stream identifier specified by host 120 to the second region.

[0089] Figure 6 An example is shown where a memory block BLKa, in which a first region is allocated, is illustrated according to some example embodiments. (Refer to...) Figure 6 In the a-th memory block BLKa, the first sub-block SBLK1 at the top of the a-th cell string CSa and the b-th cell string CSb can be allocated to the first region.

[0090] Figure 7 Another example is shown, in which the first region of memory block BLKa is allocated, according to some example embodiments. (Refer to...) Figure 7 In the a-th memory block BLKa, the third sub-block SBLK3 located at the bottom of the a-th cell string CSa and the b-th cell string CSb can be allocated to the first region.

[0091] In some example embodiments, depending on the processing of the non-volatile memory device 111, the programming or erasing speed and reliability may differ for each sub-block. According to some example embodiments... Figure 6 and Figure 7 The first region shown is provided as an example only and may be allocated according to the actual programming or erasing speed of the sub-blocks of the non-volatile memory device 111 and the actual reliability.

[0092] Figure 8 An example is shown where a storage device 110, according to some example embodiments, performs a cleanup operation upon a request from a host 120. (Refer to...) Figure 1 and Figure 8 In operation S210, the storage controller 112 may receive a wipe request from the host 120. The wipe request may include information for identifying the data to be wiped, such as an address or identifier.

[0093] In operation S220, the storage controller 112 may select the sub-block SBLK that includes the requested data.

[0094] In operation S230, storage controller 112 may migrate unrequested data. For example, storage controller 112 may migrate data from the selected sub-block SBLK that is not the target of the cleanup operation to free space in another first region.

[0095] In operation S240, the storage controller 112 may perform a secure erase (SERS) on the selected sub-block SBLK. For example, the storage controller 112 may physically erase data written to the selected sub-block SBLK.

[0096] Figure 9 An example of performing an erase (ERS) operation in a non-volatile memory device 111 according to some example embodiments is shown. Figure 9 In the diagram, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells.

[0097] Reference Figure 1 , Figure 3 , Figure 4 and Figure 9 When data is written via a write operation, the memory cells of one or more sub-blocks within the first sub-block SBLK1, second sub-block SBLK2, and third sub-block SBLK3 of either the a-th unit string CSa or the b-th unit string CSb can be programmed to fall within different threshold voltage ranges. These different threshold voltage ranges can correspond to different states. For example, the state corresponding to the lowest threshold voltage range could be the erase state. Threshold voltage ranges higher than the erase state can each correspond to different programming states.

[0098] When an erase (ERS) operation is performed, memory cells of a specific (one or more) sub-blocks can be erased to an erase state with a threshold voltage range below the first verification voltage VFY1.

[0099] In some example embodiments, an erase (ERS) operation may be performed to secure a free block and write new data to that free block. In some example embodiments, because data will be written via a write operation after the erase (ERS) operation, errors that could occur when the memory cell is in an erase state alone may not occur. For example, a deep erase where the threshold voltage of the memory cell in an erase state may not become too low may not occur, and the reliability of the data written to the memory cell may not be affected.

[0100] Figure 10 An example of performing a Secure Erase (SERS) operation in a non-volatile memory device 111 according to some example embodiments is shown. Figure 10 In the diagram, the horizontal axis represents the threshold voltage Vth of the memory cell, and the vertical axis represents the number of memory cells.

[0101] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 10When data is written via a write operation, the memory cells of the first memory block BLK1 can be programmed to include different threshold voltage ranges. Different threshold voltage ranges can correspond to different states. For example, the state corresponding to the lowest threshold voltage range can be the erase state. Threshold voltage ranges higher than the erase state can each correspond to different programming states.

[0102] A Secure Erase (SERS) operation may include an Erase (ERS) operation and a Pre-programming (PP) operation. In some example embodiments, the Erase (ERS) operation of a Secure Erase (SERS) operation may be referred to as a shallow erase because the erase is performed relatively small. For example, when performing an Erase (ERS) operation, memory cells of the first memory block BLK1 may be erased to a state where their threshold voltage range is below the second verification voltage VFY2 and above the third verification voltage VFY3. In some example embodiments, the level of the second verification voltage VFY2 used in the Erase (ERS) operation of a Secure Erase (SERS) operation may be higher than that at the reference... Figure 9 The level of the first verification voltage VFY1 used in the described erase (ERS) operation.

[0103] In some example embodiments, when performing a pre-programming (PP) operation, the memory cells of the first memory block BLK1 can be programmed to have a threshold voltage range below the fourth verification voltage VFY4 and above the fifth verification voltage VFY5. In some example embodiments, the level of the fifth verification voltage VFY5 used in the pre-programming (PP) operation of a secure erase (SERS) operation may be higher than the level of the second verification voltage VFY2 used in the erase (ERS) operation of a secure erase (SERS) operation.

[0104] In some example embodiments, the threshold voltage distribution range of the memory cell performing a secure erase (ERS) operation may be wider than the threshold voltage distribution range of an erase state or a programming state when data is written.

[0105] In some example embodiments, a Secure Erase (SERS) operation may be arbitrarily initiated to cause host 120 to erase secure data instead of protecting free blocks and writing new data. Therefore, memory cells may be left alone, and errors that can occur when memory cells are left alone may happen. For example, a deep erase may occur where the threshold voltage of the memory cell becomes low or even lower. A Secure Erase (SERS) operation may be performed to adjust the threshold voltage range of the memory cell to be higher than the threshold voltage range of the erase state. In some example embodiments, even if the threshold voltage of the memory cell becomes lower, the threshold voltage of the memory cell may not become lower than the threshold voltage range of the erase state.

[0106] When the storage controller 112 intends to write data to a memory cell in another specific sub-block after a Secure Erase (SERS) operation has been completed, the storage controller 112 may perform an Erase (ERS) operation on the memory cell in the other specific sub-block, causing the first memory block BLK1 to become a free block, and then the data can be written to the other specific sub-block. Therefore, interference caused when a memory cell is in an erase state alone will not affect the reliability of the data to be written subsequently.

[0107] In some example embodiments, reference is made to Figure 9 The described erase (ERS) operation can be a background operation performed when the storage device 110 is in an idle state. Therefore, refer to Figure 9 The described erase (ERS) operation does not affect the latency of storage device 110.

[0108] In some example embodiments, reference is made to Figure 10 The described Secure Erase (SERS) operation requests the immediate physical erasure of memory cells. Therefore, refer to... Figure 10 The described Secure Erase (SERS) operation may affect the latency of storage device 110.

[0109] According to some example embodiments, the storage device 110 may select sub-blocks to be allocated to the first region, taking into account programming speed or erase speed and reliability. Therefore, the erase (SERS) operation based on the erase request can suppress the increase in latency of the storage device 110.

[0110] Figure 11 Examples of allocating a first region across multiple memory blocks are illustrated according to some example embodiments. In some example embodiments, the first region is assumed to be an RPMB. However, some example embodiments are not limited to RPMBs. In some example embodiments, regions that separately manage purpose-specific data, in addition to RPMBs, may also be allocated to the first region. In some example embodiments, regions configured to perform write / read / erase operations within a given time, rather than typical write / read / erase regions, may be allocated to the first region, which is relatively faster than any other region(s). Furthermore, in some example embodiments, regions that support erase functionality that processes physical erase requests immediately at the time the erase request is generated by the host 120 or storage controller 112 may be allocated to the first region.

[0111] Reference Figure 1 , Figure 2 , Figure 3 and Figure 11The storage controller 112 can allocate the first sub-block SBLK1 of the first memory block BLK1 (e.g., the first sub-block SBLK1 of the eleventh cell string CS11, the first sub-block SBLK1 of the twelfth cell string CS12, the first sub-block SBLK1 of the twenty-first cell string CS21, and the first sub-block SBLK1 of the twenty-second cell string CS22) of the memory cell array 210 to the RPMB.

[0112] In some example embodiments, when the storage capacities of the sub-blocks of each memory block differ from each other, sub-blocks with relatively small sizes or storage capacities consistent with the design purpose of the RPMB may be assigned to the RPMB. In some example embodiments, the sub-blocks of each memory block with the highest programming or erasing speed may be assigned to the RPMB. Sub-blocks of each memory block with small channel dimensions (e.g., sub-blocks at the bottom) may be assigned to the RPMB. Based on the physical structure of the supply operating voltage, sub-blocks of each memory block capable of attempting programming and erasing operations relatively quickly may be assigned to the RPMB. In some example embodiments, sub-blocks of each memory block capable of meeting the required or advantageous time for the RPMB's erase operations may be assigned to the RPMB.

[0113] In some example embodiments, the reliability of the memory cell may decrease as programming and erasing operations are repeated. Therefore, the lifetime of the memory cell can be measured as the number of programming and erasing cycles. Because a Secure Erase (SERS) operation based on a erase request causes data migration, erasure, and programming operations, the lifetime of an RPMB memory cell may be exhausted faster than that of any other memory cell.

[0114] For wear leveling (e.g., balance between programming and erasing cycles), when the wear level of the RPMB becomes higher than or greater than the wear level of any other memory cell (e.g., when the wear level difference is greater than a predetermined first threshold), the memory controller 112 may allocate a sub-block at the same location of another memory block to the first region. Figure 12 An example is shown where, according to some example embodiments, the RPMB is allocated to the first sub-block SBLK1 of the third memory block BLK3.

[0115] In some example embodiments, during the process of allocating the first sub-block SBLK1 of the third memory block BLK3 to the RPMB in place of the first sub-block SBLK1 of the first memory block BLK1, it is possible that some first sub-blocks SBLK1 of the first memory block BLK1 and some first sub-blocks SBLK1 of the third memory block BLK3 may be allocated to the RPMB together. Figure 13 An example is shown where some first sub-blocks SBLK1 of a first memory block BLK1 and some first sub-blocks SBLK1 of a third memory block BLK3 are allocated together to the RPMB according to some example embodiments.

[0116] In some example embodiments, when the wear level of the first sub-block SBLK1 of the first memory block BLK1, the first sub-block SBLK1 of the second memory block BLK2, the first sub-block SBLK1 of the third memory block BLK3, and the first sub-block SBLK1 of the fourth memory block BLK4 is greater than the wear level of any other sub-block (e.g., greater than a second threshold), the memory controller 112 may allocate any other sub-block (e.g., the third sub-block SBLK3 of the first memory block BLK1) to the RPMB. Figure 14 An example is shown where a storage controller 112, according to some example embodiments, assigns a third sub-block SBLK3 of a first memory block BLK1 to an RPMB.

[0117] As described above, based on the wear level, the storage controller 112 can change the sub-blocks that will be allocated to the RPMB within the memory block, and can change the sub-blocks that will be allocated to the RPMB between memory blocks.

[0118] Figure 15 The operation of a storage device 110 according to some example embodiments is illustrated. (Refer to...) Figure 1 , Figure 4 and Figure 15 In operation S310, the memory controller 112 can read word line (WL) information from the non-volatile memory device 111. For example, the word line (WL) information may be information obtained through a test operation in the manufacturing process of the memory device 110 and written into the non-volatile memory device 111. The word line (WL) information may include information about the programming speed or erase speed of each of the first sub-block SBLK1, the second sub-block SBLK2, and the third sub-block SBLK3 included in each of the a-th cell string CSa and the b-th cell string CSb, or information about the amount of energy consumed in their programming or erasing operations.

[0119] In operation S320, the storage controller 112 may assign priority to the sub-block SBLK assigned to the first region based on word line (WL) information.

[0120] In operation S330, storage controller 112 can write a specific dataset to the first region based on priority.

[0121] Figure 16 An example of priority allocation by storage controller 112 according to some example embodiments is shown. For example, suppose storage controller 112 allocates the first sub-block SBLK1 of memory block a to a first region.

[0122] The storage controller 112 can assign a first priority P1 and a second priority P2 to the first subblock SBLK1. The first priority P1 and the second priority P2 can be determined based on information included in the word line (WL) information about the programming speed or erase speed and / or information about the energy available for the programming or erasing operations.

[0123] In some example embodiments, priority can be determined based on the programming speed or the erasure speed when the difference between the programming speed and the erasure speed of the memory cell is greater than or equal to a third threshold.

[0124] Priority can be determined based on the energy available for programming or erasing operations of memory cells when the difference between the energy available for such operations is greater than or equal to a fourth threshold.

[0125] In some example embodiments, the storage controller 112 may prioritize operations by taking into account wear levels, programming or erasing speeds, and the energy available for providing programming or erasing operations.

[0126] Assuming priority is assigned based on word line (WL) information, when a wipe request is generated before the first region is fully filled with data, the data may already be in a state where it has been written to a memory cell with a higher priority. Therefore, wipe requests can be processed with high or higher programming or erasing speeds and / or with low or lower programming or erasing energy.

[0127] In some example embodiments, the non-volatile memory device 111 may be implemented in three or more layers. The peripheral circuitry and memory cell array 210 may be distributed and implemented in three or more layers. The peripheral circuitry may include a line decoder block 220, a page buffer block 230, a pass / fail check block (PFC) 240, a data input and output block 250, a data buffer 260, a command and address buffer 270, and a control logic block 280.

[0128] Three or more layers can be implemented using a first memory cell array on the peripheral circuitry and a second memory cell array on the first memory cell array. In some example embodiments, the memory controller 112 can assign specific sub-blocks of specific memory blocks in the first or second memory cell array to a first region, such as an RPMB.

[0129] Three or more layers can be implemented using a first memory cell array and a second memory cell array on peripheral circuitry. In some example embodiments, the memory controller 112 can assign specific sub-blocks of specific memory blocks in the first or second memory cell array to a first region, such as an RPMB.

[0130] Figure 17 This is a diagram of a system 1000 that utilizes a storage device according to some example embodiments. Figure 17 The system 1000 can essentially be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, and / or an Internet of Things (IoT) device. However, Figure 17 The system 1000 is not limited to mobile systems, and in some example embodiments, Figure 17 The system 1000 can be a PC, laptop computer, server, media player and / or automotive device (e.g., navigation device).

[0131] Reference Figure 17 System 1000 may include a main processor 1100, memory (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). In some example embodiments, system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0132] The main processor 1100 can control all operations of the system 1000, and more specifically, can control the operations of other components included in the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor, etc.

[0133] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and also includes a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130 as dedicated circuitry for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and is implemented as a chip physically separate from other components of the main processor 1100.

[0134] Memory 1200a and 1200b may be used as the main memory device of system 1000. Although each of memory 1200a and 1200b may include volatile memory (such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), each of memory 1200a and 1200b may include non-volatile memory (such as flash memory, phase-change RAM (PRAM) and / or resistive RAM (RRAM)). Memory 1200a and 1200b may be implemented in the same package as main processor 1100.

[0135] Storage devices 1300a and 1300b can be used as non-volatile storage devices configured to store data regardless of power supply, and have a larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may each include storage controllers (STRG CTRL) 1310a and 1310b and NVMs 1320a and 1320b configured to store data via the control of storage controllers 1310a and 1310b. Although NVMs 1320a and 1320b may include flash memory with a two-dimensional (2D) structure and / or a three-dimensional (3D) V-NAND structure, NVMs 1320a and 1320b may also include other types of NVMs, such as PRAM and / or RRAM.

[0136] Storage devices 1300a and 1300b may be physically separate from and included in the main processor 1100, and / or may be implemented in the same package as the main processor 1100. In some example embodiments, storage devices 1300a and 1300b may be of the type of solid-state device (SSD) and / or memory card, and may be removably coupled to other components of the system 1000 via an interface such as connection interface 1480, which will be described later. Storage devices 1300a and 1300b may be, but are not limited to, devices applying standard protocols such as Universal Flash Memory (UFS), embedded multimedia card (eMMC), and / or high-speed non-volatile memory (NVMe).

[0137] Image capture device 1410 can capture still images and / or moving images. Image capture device 1410 may include a camera, video camera, and / or webcam.

[0138] User input device 1420 can receive various types of data input by the user of system 1000, and includes touchpad, keypad, keyboard, mouse and / or microphone, etc.

[0139] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors, etc.

[0140] The communication device 1440 can send and / or transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, transceiver, and / or modem, etc.

[0141] The display 1450 and the speaker 1460 can be used as output devices configured to output visual and auditory information to the user of the system 1000, respectively.

[0142] The power supply unit 1470 can suitably convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0143] The connection interface 1480 provides a connection between the system 1000 and an external device that connects to the system 1000 and is able to send and / or transmit data to and receive data from the system 1000. The connection interface 1480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External Serial ATA (e-SATA), Small Computer Interface (SCSI), Serial Attached SCSI (SAS), External Component Interconnect (PCI), High-Speed ​​PCI (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and / or Compact Flash (CF) card interface.

[0144] In some example embodiments, reference is made to Figures 1 to 16 The described host 120 can be implemented using a main processor 1100. In some example embodiments, reference is made to... Figures 1 to 16 The described storage device 110 can be implemented using one of storage devices 1300a and 1300b. At least one of storage devices 1300a and 1300b can be implemented in an SCA architecture and can allocate RPMBs based on sub-block information. Furthermore, in some example embodiments, at least one of storage devices 1300a and 1300b can set the priority of write data based on word line information.

[0145] In the above example embodiments, components according to some example embodiments are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., are used to distinguish components from each other and do not limit the inventive concept. For example, the terms "first," "second," "third," etc., do not imply any form of order or numerical meaning.

[0146] In the above example embodiments, components according to some example embodiments are referenced by the use of blocks. Blocks may be implemented using various hardware devices such as integrated circuits (ICs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in the hardware device, software such as an application, or a combination of hardware devices and software. In some example embodiments, a block may include circuitry implemented in an integrated circuit using semiconductor elements, or circuitry registered as intellectual property (IP). For example, it will be understood that, as described herein, any device, electronic device, module, unit, and / or any portion thereof according to any of the example embodiments may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry, hardware / software combinations (such as a processor executing software), or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA) and programmable logic units, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory), such as a solid-state drive (SSD), storing a program of instructions, and a processor (e.g., a CPU) configured to execute the instructions to implement the functions and / or methods performed by some or all of any device, electronic device, module, unit, and / or portions thereof according to any example embodiment.

[0147] According to some example embodiments, the storage device can allocate specific regions based on the characteristics of sub-blocks, and can allocate the priority of writing data based on the characteristics of word lines within those specific regions. The speed of the erase operation can be improved by considering both the characteristics of the sub-blocks and the characteristics of the word lines.

[0148] Although the inventive concept has been described with reference to some exemplary embodiments thereof, various changes and modifications may be made thereto by those skilled in the art without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. A storage device, comprising: A non-volatile memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of sub-blocks; as well as The storage controller is configured as follows: Send commands and addresses to the non-volatile memory device. Communicating first data with the non-volatile memory device, Based on first information regarding the programming or erasing speed of the plurality of sub-blocks, one of the sub-blocks is assigned to the first region, and The second data of the write request is written to the first area, and the write request is received from the external host device along with the second information.

2. The storage device as claimed in claim 1, wherein, The storage controller is configured to assign a first sub-block of the plurality of sub-blocks to the first region, the first sub-block having a fast programming or erasing speed.

3. The storage device as claimed in claim 1, wherein, The second information includes a specific logical unit or a specific flow identifier.

4. The storage device as claimed in claim 1, wherein, The non-volatile memory device includes: Substrate; and Multiple unit strings arranged on the substrate along a first direction and a second direction, Each of the plurality of unit strings includes a plurality of stacked elements stacked on the substrate along a third direction, and Each of the plurality of stacks includes a plurality of memory cells stacked along the third direction.

5. The storage device as claimed in claim 4, wherein, Each of the plurality of stacked components corresponds to a different sub-block among the plurality of sub-blocks, and The first sub-block of the first unit string in the plurality of unit strings and the second sub-block of the second unit string in the plurality of unit strings are super sub-blocks.

6. The storage device as claimed in claim 5, wherein, The first sub-block corresponds to the first stacked member in the first plurality of stacked members of the first unit string, and the first stacked member is located at the top of the first unit string. The second sub-block corresponds to the second stack in the second plurality of stacks of the second unit string, which is located at the top of the second unit string.

7. The storage device as claimed in claim 5, wherein, The first sub-block corresponds to the first stacked member in the first plurality of stacked members of the first unit string, and the first stacked member is located at the bottom of the first unit string. The second sub-block corresponds to the second stack in the second plurality of stacks of the second unit string, which is located at the bottom of the second unit string.

8. The storage device as claimed in claim 1, wherein, The first region includes a replay protection memory block.

9. The storage device as claimed in claim 1, wherein, The second information indicates a higher probability of requesting a clearing operation for the second data compared to any other data, and The erasure operation includes the physical erasure of the second data.

10. The storage device of claim 9, wherein, The clearing operation includes: An erase operation that reduces the threshold voltage of the memory cell storing the second data to a first threshold voltage or lower; and The pre-programming operation increases the threshold voltage of the memory cell to a second threshold voltage or higher.

11. The storage device as claimed in claim 1, wherein, The storage controller is configured to allocate a first portion of at least one of the plurality of memory blocks to the first region.

12. The storage device of claim 11, wherein, The storage controller is configured to allocate a second portion of the at least one memory block to the first region in response to an increase in the wear level of the first portion of the at least one memory block.

13. The storage device of claim 11, wherein, The storage controller is configured to allocate a portion of a memory block different from the at least one memory block to the first region in response to an increase in the wear level of the first portion of the at least one memory block.

14. The storage device as claimed in claim 1, wherein, The storage controller is configured as follows: Read third information about the memory cells allocated to the first region from the non-volatile memory device; as well as Based on the third information, the second data of the write request received from the external host device along with the second information is written into the first area.

15. The storage device of claim 14, wherein, The third piece of information includes information about the programming speed or erasing speed of the memory cell.

16. The storage device of claim 15, wherein, The storage device is configured to first write the second data into a first memory cell with a higher programming or erasing speed than the memory cell.

17. The storage device of claim 14, wherein, The third information includes information about the energy consumed during programming or erasing operations on the memory cell.

18. The storage device of claim 17, wherein, The storage device is configured to first write the second data into a first memory cell within the memory cell, where the energy consumed in the programming or erasing operation is lower.

19. A storage device, comprising: A non-volatile memory device comprising multiple memory blocks; as well as The storage controller is configured as follows: Send commands and addresses to the non-volatile memory device. Communicating first data with the non-volatile memory device, Some regions of the plurality of memory blocks are allocated to the first region. The second data of the first write request is written to the first area, and the first write request is received from the external host device along with the first information. Read second information about the memory cells allocated to the first region from the non-volatile memory device, and Based on the second information, the third data of the second write request is written into the first area, and the second write request is received from the external host device together with the third information.

20. A method of operating a storage device, the storage device comprising a non-volatile memory device and a storage controller, the non-volatile memory device comprising a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of sub-blocks, and the storage controller configured to send commands and addresses to the non-volatile memory device and communicate first data with the non-volatile memory device, the method comprising: At the storage controller, based on first information about the programming speed or erasure speed of the plurality of sub-blocks, one of the plurality of sub-blocks is assigned to the first region; as well as At the storage controller, the second data of the write request is written to the first area, and the write request is received from the external host device along with the second information.

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