A microcode splitting method and device for an RVV instruction, electronic equipment and storage medium

Abstract

The present disclosure provides a microcode splitting method and device of RVV instructions, electronic equipment and storage medium, by further introducing a sub-MOP splitting mechanism on the basis of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs, so that the execution unit can gradually complete the target operation by using the intermediate results generated by the previous sub-MOP, thereby realizing the execution of the special vector instruction without greatly modifying the existing execution unit structure. Thus, the hardware modification cost can be effectively reduced, the reuse degree of the existing vector microarchitecture can be improved, the register port pressure can be reduced, and the compatibility and engineering implementation feasibility of the processor for special RISC-V vector instructions can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of processor instruction execution technology, and more specifically, to a method, apparatus, electronic device, and storage medium for microcode splitting of RVV instructions. Background Technology

[0002] As an open reduced instruction set architecture, RISC-V has been widely used in general-purpose computing, edge computing, high-performance computing, and artificial intelligence acceleration due to its advantages such as strong scalability, high modularity, and ease of hardware-software co-design. With the increasing demand for data-parallel computing, RISC-V Vector Extension (RVV) introduces vector registers, vector arithmetic logic operations, and a configurable vector length mechanism, enabling processors to process multiple data elements in parallel with a single instruction, thereby significantly improving data throughput and execution efficiency.

[0003] In existing RISC-V vector processor designs, to accommodate different vector lengths, register set configurations, and execution bandwidths, a vector instruction is typically split into multiple micro-operations (MOPs), which are then computed in batches by the back-end execution unit. This MOP splitting method is suitable for most conventional vector instructions; each MOP only needs to access its corresponding set of source operands and independently complete the corresponding data processing task. Therefore, it can better match the hardware architecture and pipelined execution mechanism of existing vector execution units.

[0004] However, for some special RISC-V vector instructions, the execution process cannot be simply completed by uniformly dividing a vector operation into several independent MOPs. For example, in the execution of some special vector instructions, the generation of a destination register element often depends on multiple source data elements within the same register group, or on the gradual accumulation of previous local computation results. For these special vector instructions, if the existing MOP splitting method for ordinary vector instructions is still used, problems such as an excessive number of source operands required for a single micro-operation, insufficient input resources of the execution unit, excessive pressure on register read ports, and difficulty in directly reusing existing execution paths can easily occur. Summary of the Invention

[0005] This disclosure provides at least one method, apparatus, electronic device, and storage medium for microcode splitting of RVV instructions. By introducing a sub-MOP splitting mechanism on top of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs. This allows the execution unit to gradually complete the target computation using intermediate results generated by preceding sub-MOPs, thereby achieving the execution of special vector instructions without significantly modifying the existing execution unit structure. This effectively reduces hardware modification costs, improves the reusability of existing vector microarchitectures, alleviates register port pressure, and enhances the processor's compatibility with special RISC-V vector instructions and the feasibility of engineering implementation.

[0006] This disclosure provides a microcode decomposition method for RVV instructions, applied to a vector instruction processing circuit in a processor. The method includes: The instruction type of the RVV instruction to be executed is determined to determine whether the RVV instruction to be executed is a special vector instruction; When the RVV instruction to be executed is a non-special vector instruction, the RVV instruction to be executed is split into micro-operations according to the normal MOP splitting method, and the corresponding MOPs are issued and executed sequentially according to the MOP number; When the RVV instruction to be executed is a special vector instruction, the RVV instruction to be executed is split into multiple MOPs according to a preset MOP splitting method, and any MOP is further split into multiple sub-MOPs; Multiple sub-MOPs corresponding to the current MOP are issued sequentially according to the sub-MOP number, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOPs. When it is determined that all sub-MOPs corresponding to the current MOP have been issued, the MOP number is switched to the next MOP and the sub-MOP number is reset; when it is determined that all MOPs corresponding to the current special vector instruction have been issued, the execution of the pending RVV instruction ends.

[0007] In one optional implementation, the RVV instruction to be executed is split into multiple MOPs according to a preset MOP splitting method, specifically including: Based on the instruction information of the RVV instruction to be executed and the register group configuration information in the vector configuration register, determine the total number of MOPs corresponding to the RVV instruction to be executed; The current MOP number is recorded in the MOP number register and incremented by the MOP adder; The MOP comparator compares the current MOP number with the total number of MOPs to determine whether all MOPs corresponding to the current special vector instruction have been issued.

[0008] In one optional implementation, any MOP is further subdivided into multiple sub-MOPs, specifically including: The total number of sub-MOPs corresponding to the current MOP is determined based on the instruction information, register set configuration information, and special vector instruction type corresponding to the current MOP. The current sub-MOP number is recorded in the sub-MOP number register and incremented by the sub-MOP adder; The sub-MOP comparator compares the current sub-MOP number with the total number of sub-MOPs to determine whether all sub-MOPs corresponding to the current MOP have been transmitted.

[0009] In one optional implementation, multiple sub-MOPs corresponding to the current MOP are sequentially issued according to their sub-MOP numbers, so that the execution unit can successively complete the cumulative calculation corresponding to the current MOP based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOPs, specifically including: When the first sub-MOP is launched, the preset initial value and the source operand corresponding to the current sub-MOP are used as the input to the execution unit; When issuing subsequent sub-MOPs, the intermediate results generated by the previous sub-MOP and the source operands corresponding to the current sub-MOP are used as the inputs to the execution unit; The control execution unit executes each sub-MOP sequentially until the target execution result corresponding to the current MOP is obtained; The preset initial value is zero, and the intermediate result is the staged calculation result obtained by writing back or bypassing after the execution of the preceding sub-MOP.

[0010] In an optional implementation, before sequentially transmitting multiple sub-MOPs corresponding to the current MOP according to their sub-MOP numbers, the method further includes: The element quantity calculation module determines the number of elements to be processed corresponding to the micro-operation to be launched. Specifically, when the RVV instruction to be executed is a non-special vector instruction, the element quantity calculation module determines the number of elements to be processed corresponding to the current MOP based on the current MOP number; when the RVV instruction to be executed is a special vector instruction, the element quantity calculation module determines the number of elements to be processed corresponding to the current sub-MOP based on the current sub-MOP number.

[0011] In one optional implementation, when it is determined that all sub-MOPs corresponding to the current MOP have been issued, the MOP number is switched to the next MOP, and the sub-MOP number is reset; when it is determined that all MOPs corresponding to the current special vector instruction have been issued, the execution of the pending RVV instruction is terminated, specifically including: Output the sub-MOP completion flag of the current MOP through the sub-MOP comparator; In response to the sub-MOP completion flag, the control sub-MOP selector sets the sub-MOP number register to zero; The control MOP selector selects the output of the MOP adder as the input to the MOP number register, so that the MOP number switches to the next MOP; The instruction completion flag is output via the MOP comparator; In response to the instruction completion flag, the control MOP number register is cleared, and the control sub-MOP number register is also cleared to prepare for processing the next vector instruction.

[0012] In one optional implementation, the vector instruction processing circuit includes: The MOP number register is used to store the current MOP number; The MOP adder is used to increment the current MOP number; The maximum MOP counter is used to determine the total number of MOPs corresponding to the vector instructions to be executed. The MOP comparator is used to determine whether all MOPs have been emitted. The MOP selector, used to control the input selection of the MOP number register, is configured to select the reset value as the input of the MOP number register when all MOPs have been issued; select the number value incremented by the MOP adder as the input of the MOP number register when all sub-MOPs corresponding to the current MOP have been issued but all MOPs have not been issued; and keep the current MOP number unchanged when not all sub-MOPs corresponding to the current MOP have been issued. The sub-MOP number register is used to store the current sub-MOP number; The sub-MOP adder is used to increment the current sub-MOP number; The maximum sub-MOP counter is used to determine the total number of sub-MOPs corresponding to the current MOP; The sub-MOP comparator is used to determine whether all sub-MOPs of the current MOP have been emitted. The sub-MOP selector, used to control the input selection of the sub-MOP number register, is configured to select the reset value as the input of the sub-MOP number register when all MOPs have been issued; select the reset value as the input of the sub-MOP number register when all sub-MOPs corresponding to the current MOP have been issued; and select the number value incremented by the sub-MOP adder as the input of the sub-MOP number register when the sub-MOPs corresponding to the current MOP have not been issued. The element quantity calculation module is used to determine the number of elements to be processed corresponding to the current micro-operation to be launched; The vector instruction execution module is used to perform corresponding operations based on the currently emitted MOP or sub-MOP.

[0013] This disclosure also provides a microcode splitting device for RVV instructions, applied to a vector instruction processing circuit in a processor, the device comprising: The type determination module is used to determine the instruction type of the RVV instruction to be executed, and to determine whether the RVV instruction to be executed is a special vector instruction. The non-special instruction processing module is used to perform micro-operation splitting on the RVV instruction to be executed according to the ordinary MOP splitting method when the RVV instruction to be executed is a non-special vector instruction, and to issue the corresponding MOPs for execution in sequence according to the MOP number; A special instruction processing module is used to split the RVV instruction to be executed into multiple MOPs according to a preset MOP splitting method when the RVV instruction to be executed is a special vector instruction, and to further split any MOP into multiple sub-MOPs. The MOP launch module is used to launch multiple sub-MOPs corresponding to the current MOP in sequence according to the sub-MOP number, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOPs. The execution determination module is used to switch the MOP number to the next MOP and reset the sub-MOP number when it is determined that multiple sub-MOPs corresponding to the current MOP have been issued; and to end the execution of the RVV instruction to be executed when it is determined that all MOPs corresponding to the current special vector instruction have been issued.

[0014] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the processor performs the steps of the above-described microcode splitting method for RVV instructions, or any possible implementation of the above-described microcode splitting method for RVV instructions.

[0015] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the above-described microcode splitting method for RVV instructions, or any possible implementation of the above-described microcode splitting method for RVV instructions.

[0016] This disclosure also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the microcode splitting method for the RVV instruction described above, or the steps in any possible implementation of the microcode splitting method for the RVV instruction described above.

[0017] This disclosure provides a method, apparatus, electronic device, and storage medium for microcode splitting of RVV instructions. By introducing a sub-MOP splitting mechanism on top of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs. This allows the execution unit to gradually complete the target computation using intermediate results generated by preceding sub-MOPs, thereby achieving the execution of special vector instructions without significantly modifying the existing execution unit structure. This effectively reduces hardware modification costs, improves the reusability of existing vector microarchitectures, alleviates register port pressure, and enhances the processor's compatibility with special RISC-V vector instructions and the feasibility of engineering implementation.

[0018] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a vector instruction processing circuit in a processor provided in an embodiment of the present disclosure is shown; Figure 2 A flowchart of a microcode splitting method for RVV instructions provided in an embodiment of this disclosure is shown; Figure 3A schematic diagram of a microcode splitting device for RVV instructions provided in an embodiment of this disclosure is shown; Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0024] Research has revealed that in existing RISC-V vector processor designs, to adapt to different vector lengths, register set configurations, and execution bandwidths, a vector instruction is typically split into multiple micro-operations (MOPs) before being computed in batches by the back-end execution unit. However, for some special RISC-V vector instructions, the execution process cannot be simply completed by uniformly dividing a vector operation into several independent MOPs. For example, in the execution of certain special vector instructions, the generation of a destination register element often depends on multiple source data elements within the same register set, or on the gradual accumulation of previous local computation results. For these special vector instructions, if the existing MOP splitting method used for ordinary vector instructions is still applied, problems such as an excessive number of source operands required for a single micro-operation, insufficient input resources for the execution unit, excessive pressure on register read ports, and difficulty in directly reusing existing execution paths can easily arise.

[0025] Based on the above research, this disclosure provides a microcode splitting method, apparatus, electronic device, and storage medium for RVV instructions. By introducing a sub-MOP splitting mechanism on top of ordinary MOP splitting, the single MOP corresponding to the special vector instruction is further split into multiple sequentially executed sub-MOPs. This allows the execution unit to gradually complete the target computation using the intermediate results generated by the preceding sub-MOPs, thereby achieving the execution of special vector instructions without significantly modifying the existing execution unit structure. This effectively reduces hardware modification costs, improves the reusability of existing vector microarchitectures, alleviates register port pressure, and enhances the processor's compatibility with special RISC-V vector instructions and the feasibility of engineering implementation.

[0026] To facilitate understanding of this embodiment, a microcode decomposition method for RVV instructions disclosed in this disclosure will first be described in detail. This microcode decomposition method for RVV instructions is applied to the vector instruction processing circuit in a processor. In some possible implementations, this microcode decomposition method for RVV instructions can be implemented by the processor calling computer-readable instructions stored in memory. See also... Figure 1 The diagram shown is a schematic of a vector instruction processing circuit in a processor provided in an embodiment of this disclosure.

[0027] In practical implementation, the vector instruction processing circuit is used to jointly process the input vector instruction decoding information and vector instruction configuration information to determine the micro-operation splitting method, numbering advancement method, element quantity allocation method and mask control information corresponding to the target vector instruction in the execution stage, and output the control parameters corresponding to the micro-operation to be executed to the subsequent execution module to drive the execution module to complete the execution of the target vector instruction.

[0028] Combination Figure 1 As shown, the vector instruction processing circuit includes at least: an MOP number generation path, a sub-MOP number generation path, a maximum MOP counting module, a maximum sub-MOP counting module, an element quantity calculation module, and an execution module.

[0029] The MOP number generation path is used to generate the MOP ID corresponding to the micro-operation to be executed; the sub-MOP number generation path is used to generate the sub-MOP ID corresponding to the sub-micro-operation to be executed in special vector instruction scenarios; the maximum MOP counting module and the maximum sub-MOP counting module are used to determine the maximum number of MOPs and the maximum number of sub-MOPs corresponding to the current instruction based on the vector instruction decoding information and the vector instruction configuration information, respectively; the element quantity calculation module is used to determine the number of elements to be processed corresponding to the current MOP or the current sub-MOP and generate the corresponding MASK signal; the execution module is used to receive the MOP ID, sub-MOP ID, current sub-MOP element quantity and MASK signal, and complete the corresponding vector calculation operation accordingly.

[0030] In this embodiment, the MOP number generation path may include register 1, adder 2, maximum MOP count module 3, comparator 4, and selector 5. Maximum MOP count module 3 receives vector instruction decoding information and vector instruction configuration information, and outputs the maximum MOP count value corresponding to the current vector instruction; comparator 4 compares the current MOP number with the maximum MOP count value to determine whether the current MOP has reached its boundary; register 1 stores the current MOP number; adder 2 performs an increment operation on the current MOP number to generate a candidate value for the next MOP number; selector 5 selects between a reset value, a hold value, and an increment value to control the update method of the MOP number in register 1. Through the above structure, the sequential advancement control of ordinary or special vector instructions at the MOP level can be realized, and the corresponding MOP ID can be output to the execution module.

[0031] Here, the sub-MOP number generation path may include register 9, adder 10, maximum sub-MOP count module 11, comparator 12, and selector 13. Maximum sub-MOP count module 11 also receives vector instruction decoding information and vector instruction configuration information, and when the target instruction is determined to be a special vector instruction, it outputs the maximum sub-MOP count value corresponding to the current MOP. Comparator 12 compares the current sub-MOP number with the maximum sub-MOP count value to determine whether the sub-MOPs within the current MOP have been executed. Register 9 stores the current sub-MOP number. Adder 10 performs an increment operation based on the current sub-MOP number to generate a candidate value for the next sub-MOP number. Selector 13 selects between a reset value, a hold value, and an increment value to control the update method of the sub-MOP number in register 9.

[0032] In this way, through the above structure, a single MOP can be further subdivided into multiple sub-MOPs during the execution of special vector instructions, and the corresponding sub-MOP IDs can be output to the execution module in sequence according to the order of the sub-MOPs.

[0033] Furthermore, OR gate 14 is used to logically combine the completion conditions of the MOP level and the sub-MOP level to coordinate the linkage control between the sub-MOP numbering paths and the MOP numbering paths. That is, when it is detected that the current MOP has ended, or when it is detected that the current sub-MOP sequence has been completed and it is necessary to enter the next MOP, the corresponding selector can be driven by the logic control signal to perform the number clearing, holding, or switching operation, thereby ensuring the correctness of the numbering process under the two-level split structure.

[0034] Here, the element quantity calculation module 6 receives vector instruction decoding information and vector instruction configuration information, which are used to determine the number of elements to be processed corresponding to the current micro-operation to be executed by combining the current MOP number or the current sub-MOP number, and further output the current sub-MOP element quantity and MASK signal.

[0035] The current sub-MOP element quantity is used to characterize the number of valid elements covered by the current micro-operation, and the MASK signal is used to constrain the positions of valid elements involved in the current micro-operation, so that the execution module can complete accurate data processing under different vector lengths, different LMUL configurations and different tail boundary conditions.

[0036] Furthermore, the execution module 7 is connected to the MOP number generation path, the sub-MOP number generation path, and the element quantity calculation module 6. It receives the MOP ID, sub-MOP ID, the current sub-MOP element quantity, and the MASK signal, and determines the execution method based on the current instruction type. For ordinary vector instructions, the execution module 7 can directly execute the corresponding MOP based on the MOP ID. For special vector instructions, the execution module 7 can sequentially execute multiple sub-operations under the same MOP based on different sub-MOP IDs, and gradually complete the target calculation based on the intermediate results generated by the preceding sub-MOPs, thereby realizing the sequential execution of special vector instructions under existing execution resource conditions.

[0037] See Figure 2 The diagram shows a flowchart of a microcode splitting method for RVV instructions provided in an embodiment of this disclosure. The method includes steps S101 to S105, wherein: S101. Determine the instruction type of the RVV instruction to be executed to determine whether the RVV instruction to be executed is a special vector instruction.

[0038] In a specific implementation, after receiving the RVV instruction to be executed, the processor front end can first perform decoding processing on the RVV instruction based on the decoding unit to extract the instruction opcode, function code, source register information, destination register information, vector operation type information, and vector configuration information corresponding to the RVV instruction to be executed.

[0039] The vector configuration information may include parameters such as current vector length configuration, element bit width configuration, register group multiplier configuration, mask enable state, and tail processing method, which are used to characterize the execution context corresponding to the current RVV instruction.

[0040] Furthermore, after obtaining the decoding result of the RVV instruction to be executed, the vector instruction processing circuit can perform type identification on the RVV instruction to be executed according to the preset instruction classification rules to determine whether the instruction belongs to a special vector instruction.

[0041] Here, the preset instruction classification rules can be pre-stored in the decoding control logic, microcode control logic, or instruction type lookup table, and used to distinguish between ordinary vector instructions and special vector instructions.

[0042] Among them, ordinary vector instructions can be instruction types that can be executed directly according to the existing conventional MOP splitting method; special vector instructions can be instruction types that need to associate multiple source data elements, need to utilize the results of previous local operations, or are difficult to complete the target operation independently through a conventional MOP.

[0043] Optionally, when determining the instruction type, the vector instruction processing circuit can match the opcode field of the RVV instruction to be executed with a preset special instruction set. If the matching result indicates that the RVV instruction to be executed belongs to the preset special instruction set, the RVV instruction to be executed is determined to be a special vector instruction. If the matching result indicates that the RVV instruction to be executed does not belong to the preset special instruction set, the RVV instruction to be executed is determined to be a non-special vector instruction. The preset special instruction set can be configured according to the specific processor implementation requirements, and may include, for example, vrgather-type instructions, vcompress-type instructions, and other vector instructions that have cross-element dependencies, cross-group dependencies, or cumulative data organization requirements during execution.

[0044] Furthermore, in some implementations, the determination of whether the RVV instruction to be executed is a special vector instruction is not limited to static identification based solely on the instruction mnemonic or opcode itself, but can also be combined with the current vector configuration state for joint judgment.

[0045] In other words, some instructions can be executed in the normal MOP manner under certain vector configuration conditions, while under other vector configuration conditions, they need to be executed by further splitting them into sub-MOPs. At this time, the vector instruction processing circuit can combine the instruction type information of the RVV instruction to be executed with the current vector configuration information to determine whether the instruction should be classified as a special vector instruction in the current execution context.

[0046] After completing the instruction type determination, the vector instruction processing circuit can output the corresponding instruction type determination result. If the determination result indicates that the RVV instruction to be executed is a non-special vector instruction, then the corresponding MOP number can be generated according to the normal MOP splitting path and the execution module can be driven to execute it; if the determination result indicates that the RVV instruction to be executed is a special vector instruction, then the sub-MOP splitting control path can be entered to further subdivide the MOP corresponding to the current instruction into multiple sub-MOPs to support the sequential execution of special vector instructions.

[0047] In this way, target instructions that require special splitting mechanisms can be identified in advance before the RVV instructions enter the execution phase. This provides a basis for determining whether to use the normal MOP splitting mode or the sub-MOP further splitting mode, ensuring that different types of RVV instructions can be matched with appropriate microcode splitting and execution control methods.

[0048] S102. When the RVV instruction to be executed is a non-special vector instruction, the RVV instruction to be executed is split into micro-operations according to the ordinary MOP splitting method, and the corresponding MOP is issued and executed sequentially according to the MOP number.

[0049] In practical implementation, after the vector instruction processing circuit determines that the RVV instruction to be executed is a non-special vector instruction, it can skip further path splitting by sub-MOPs and directly enter the normal MOP splitting process. At this time, the vector instruction processing circuit can determine the total number of MOPs corresponding to the RVV instruction in the current execution context based on the decoding information of the RVV instruction to be executed and the current vector instruction configuration information, and perform sequential micro-operation splitting on the RVV instruction based on the total number of MOPs.

[0050] The decoding information may include instruction operation type, source register and destination register information, element bit width information, mask enable information, and memory access or operation attribute information, etc.; the vector instruction configuration information may include current vector length, register set multiplier, number of valid elements, tail processing mode, and mask processing mode, etc.

[0051] Here, the vector instruction processing circuit can combine the above information to determine how many MOPs the current RVV instruction needs to be split into under the existing execution bandwidth and register grouping conditions, so that each MOP can undertake the data processing task of a corresponding part of the vector elements.

[0052] In one embodiment, the maximum MOP counting module can calculate and output the maximum MOP count value corresponding to the RVV instruction to be executed based on the decoding information and vector instruction configuration information. This maximum MOP count value represents the upper limit of the number of MOPs that need to be issued sequentially during the current execution of the RVV instruction. Subsequently, the register in the MOP number generation path can store the current MOP number and, in the initial state, set the current MOP number as the starting number, for example, to 0 or other preset starting values.

[0053] During transmission, the vector instruction processing circuit generates a corresponding MOP ID based on the current MOP number and outputs the MOP ID to the execution module. Upon receiving the MOP ID, the execution module performs vector data processing operations corresponding to the current MOP, based on the element range, register fragment range, or data segment range. After the current MOP is transmitted, the adder in the MOP number generation path increments the current MOP number to generate a candidate value for the next MOP number. The selector then controls the writing of this candidate value into the MOP number register, thus initiating the transmission phase of the next MOP.

[0054] Furthermore, during the sequential issuance of each MOP, the comparator compares the current MOP number with the maximum MOP count to determine whether all MOPs have been issued. If the comparison result indicates that the current MOP number has not yet reached the boundary, the next MOP is issued according to the incremented MOP number; if the comparison result indicates that the current MOP number has reached the maximum MOP count range corresponding to the current RVV instruction, the ordinary MOP splitting execution process corresponding to this non-special vector instruction is determined to be over.

[0055] It should be noted that for the non-special vector instructions, there is usually no need to introduce additional sub-MOP cascading split control between each MOP, nor is it necessary to rely on the intermediate cumulative results of the preceding MOP to complete the target operation within a single MOP.

[0056] In other words, each MOP can be viewed as performing relatively independent micro-operations on a subset of elements of the target vector instruction. Therefore, the execution module can directly complete the corresponding calculations based on the current MOP ID, the number of elements corresponding to the current MOP, and the corresponding MASK signal, without needing to additionally enable the sub-MOP number path corresponding to the special vector instruction.

[0057] In some implementations, the element quantity calculation module can also determine the effective element processing quantity corresponding to the current MOP based on the current MOP number, the vector length parameter of the RVV instruction to be executed, and the current configuration information, and output the MASK signal corresponding to the MOP.

[0058] In this way, when the execution module executes the corresponding MOP, it can operate only on the valid elements covered by the current MOP and mask the tail elements that are out of the valid range or the masked elements, thereby ensuring that non-special vector instructions can be executed correctly under different vector lengths and different mask configurations.

[0059] S103. When the RVV instruction to be executed is a special vector instruction, the RVV instruction to be executed is split into multiple MOPs according to the preset MOP splitting method, and any MOP is further split into multiple sub-MOPs.

[0060] In specific implementation, after the vector instruction processing circuit determines that the RVV instruction to be executed is a special vector instruction, it no longer processes it according to the single-level MOP splitting mechanism corresponding to the ordinary vector instruction. Instead, it introduces a sub-MOP splitting mechanism on the basis of MOP splitting to decompose the execution process of the special vector instruction, which is originally difficult to be completed independently by a single MOP, into multiple levels of finer sequential micro-operation processes.

[0061] This approach allows special vector instructions to be executed incrementally within the existing vector execution resources, thereby avoiding hardware implementation difficulties caused by excessive source data involved in a single micro-operation, complex execution dependencies, or excessive register access pressure.

[0062] In this embodiment, the preset MOP splitting method can be to determine the total number of MOPs corresponding to the special vector instruction under the current execution conditions based on the decoding information of the RVV instruction to be executed and the vector instruction configuration information, and split the special vector instruction into multiple MOPs according to the MOP number order.

[0063] The decoding information may include opcode, function code, source register information, destination register information, element bit width information, operand organization method, and mask attribute information, etc.; the vector instruction configuration information may include current vector length, register group multiplier, number of valid elements, tail processing mode, and mask control mode, etc.

[0064] Optionally, the maximum MOP counting module in the vector instruction processing circuit can calculate the maximum MOP count value corresponding to the special vector instruction based on the decoding information of the RVV instruction to be executed and the vector instruction configuration information, and use it as the upper limit of the MOP level split.

[0065] Subsequently, the registers in the MOP number generation path are used to record the current MOP number. Initially, the current MOP number can be set to the starting number, such as 0. As the execution process progresses, the current MOP number is incremented by an adder, and the current MOP number is compared with the maximum MOP count value by a comparator, so as to realize the sequential advancement control of the special vector instruction at the MOP level.

[0066] Unlike non-special vector instructions, for the special vector instructions, a single MOP is usually insufficient to directly complete the corresponding target operation. This is because the operation process within the current MOP may still involve combination relationships, sequential dependencies, or intermediate result passing relationships between multiple source elements, thus requiring further subdivision into multiple sequentially executable subtasks within the current MOP. Based on this, this embodiment further performs sub-MOP splitting processing for any MOP.

[0067] Specifically, the vector instruction processing circuit can, for the current MOP, determine the total number of sub-MOPs corresponding to the current MOP based on the instruction type of the RVV instruction to be executed, the register fragmentation range covered by the current MOP, the element processing range, and the internal operation rules of the special vector instruction, and further divide the current MOP into multiple sub-MOPs. Each sub-MOP can correspond to a local data extraction, local data alignment, local calculation, local accumulation, local rearrangement, or intermediate result update operation within the current MOP.

[0068] In one embodiment, the maximum sub-MOP count module in the sub-MOP number generation path can calculate the maximum sub-MOP count value corresponding to the current MOP based on the decoding information of the RVV instruction to be executed and the vector instruction configuration information, combined with the context information of the current MOP. A register is used to record the current sub-MOP number and is initially set to the starting number, for example, 0. An adder is used to increment the current sub-MOP number, and a comparator is used to compare the current sub-MOP number with the maximum sub-MOP count value to determine whether all sub-MOPs within the current MOP have been split and emitted.

[0069] It should be noted that further splitting any MOP into multiple sub-MOPs does not mean that all MOPs correspond to the same number of sub-MOPs. In actual implementation, different MOPs may have the same or different number of sub-MOPs due to differences in the range of elements they cover, register locations, boundary states, or the internal data organization of special vector instructions.

[0070] For example, a MOP in the middle position can correspond to a relatively complete sequence of sub-MOPs; while for MOPs at the start or end boundaries, a smaller number of sub-MOPs can be configured based on the actual number of valid elements or tail conditions. In other words, the granularity of the sub-MOPs corresponding to the current MOP can be dynamically determined according to actual execution needs, rather than being limited to a fixed splitting pattern.

[0071] Furthermore, after splitting the current special vector instruction into multiple MOPs and further splitting any MOP into multiple sub-MOPs, the vector instruction processing circuit can output the current MOP number and the current sub-MOP number respectively to form a two-layer identifier for the micro-operation to be executed.

[0072] The MOP number represents the execution position of the current special vector instruction at the macro-grouping level, while the sub-MOP number represents the fine-grained execution position within the current MOP. The execution module can determine the specific local operation to be executed based on the MOP number and sub-MOP number, and then progressively complete the target computation of the current MOP according to the sub-MOP sequence before switching to the next MOP to continue execution.

[0073] S104. The multiple sub-MOPs corresponding to the current MOP are sequentially issued according to the sub-MOP number, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOP.

[0074] In practical implementation, for special vector instructions, the target operation within a single MOP usually cannot be completed directly through a single independent micro-operation. Instead, it requires the sequential unfolding of multiple local computation processes involved in the MOP in a predetermined order. Based on this, after determining the multiple sub-MOPs corresponding to the current MOP, the vector instruction processing circuit can control the sub-MOP numbering path to output the identifiers of the currently to be emitted sub-MOPs in the order of their sub-MOP numbers. These sub-MOP identifiers, along with the current MOP identifier, are then sent to the execution unit to instruct the execution unit to perform the local operations of the corresponding stage within the current MOP.

[0075] In this embodiment, the sub-MOP number register can be used to store the current sub-MOP number, which can be initially set to the starting number, such as 0. During execution, the vector instruction processing circuit determines the operation type, source operand range, target data location, and intermediate result usage method corresponding to the sub-MOP to be emitted based on the current sub-MOP number, and controls the execution unit to emit and execute the sub-MOP.

[0076] Here, after the current sub-MOP is transmitted, the sub-MOP adder performs an increment operation on the current sub-MOP number to obtain the candidate value of the next sub-MOP number; if the comparison result shows that all sub-MOPs corresponding to the current MOP have not been transmitted, the candidate value of the next sub-MOP number is written into the sub-MOP number register through the selector, so as to continue transmitting the next sub-MOP.

[0077] Different sub-MOPs can correspond to different stages of data processing tasks within the current MOP. Thus, when processing the first sub-MOP, the execution unit can perform initial local operations based on the source operands corresponding to that sub-MOP to form the initial result of the cumulative operation corresponding to the current MOP. When processing subsequent sub-MOPs, it can receive intermediate results generated by previous sub-MOPs while reading the source operands corresponding to the current sub-MOP, and use these intermediate results as data for computation during the execution of the current sub-MOP, thereby continuing to complete the next stage of local operations based on the previous results.

[0078] In other words, the sub-MOPs are not completely independent of each other, but at least partially related by data transfer. Intermediate results generated after the execution of a preceding sub-MOP can serve as one of the inputs for subsequent sub-MOPs, enabling the gradual accumulation of the overall computational process within the current MOP. These intermediate results can be register-stored results, bypass-pass results, pipeline-level cache results, or results held within the execution unit, and can be specifically configured according to the processor microarchitecture implementation. As long as it can be guaranteed that subsequent sub-MOPs obtain the interim results already formed by the preceding sub-MOPs during execution, they can be considered to fall within the scope of protection of this application.

[0079] In some implementations, for the first sub-MOP corresponding to the current MOP, since there is no intermediate result corresponding to the previous sub-MOP, the execution unit can use a preset initial value and the source operand corresponding to the current sub-MOP to perform calculations to form an initial intermediate result.

[0080] The preset initial value can be zero, null, a default register state value, or a preset initial calculation value corresponding to the current special vector instruction. For the second and subsequent sub-MOPs, the intermediate results generated by the previous sub-MOP or several previous sub-MOPs are used as one of the inputs of the current sub-MOP, and local operations are continued to be performed in combination with the source operands corresponding to the current sub-MOP to update the cumulative result corresponding to the current MOP.

[0081] Furthermore, cumulative operations are not limited to narrow addition, but rather refer to a sequential operation method that relies on previous local results to gradually form the current MOP target result. For example, this can include data concatenation, stepwise rearrangement, updating results after partial filtering, data aggregation under index mapping, multi-stage data migration, and other operations that require continuous correction or supplementation of the current result using results from previous stages. For different types of special vector instructions, the specific operation form corresponding to the current sub-MOP may differ, but all can use this processing mode to gradually complete the overall target operation of the current MOP.

[0082] In one embodiment, after receiving the current MOP identifier and the current sub-MOP identifier, the execution unit can further determine the effective element range actually processed by the current sub-MOP by combining the current sub-MOP element quantity output by the element quantity calculation module and the MASK signal. This ensures that each sub-MOP only performs operations on its corresponding effective elements, and also allows for the masking of invalid elements when the vector length is insufficient to cover the entire set boundary, when tail elements exist, or when masking control is enabled. This guarantees that the sequential accumulation process of each sub-MOP can be correctly executed under different configuration conditions.

[0083] During the sequential issuance and execution of multiple sub-MOPs corresponding to the current MOP in numerical order, the result of the current MOP is not obtained all at once during the issuance of a single sub-MOP, but rather gradually approaches the complete result as the sub-MOP sequence progresses. Once the last sub-MOP has completed execution, the execution unit obtains the target execution result corresponding to the current MOP and uses this result for write-back, buffering, subsequent pipeline propagation, or to provide necessary context for the execution of subsequent MOPs. At this point, it indicates that all local accumulation processes within the current MOP have been completed, and the processing phase of the next MOP can begin.

[0084] S105. When it is determined that all the sub-MOPs corresponding to the current MOP have been issued, the MOP number is switched to the next MOP and the sub-MOP number is reset; when it is determined that all the MOPs corresponding to the current special vector instruction have been issued, the execution of the RVV instruction to be executed is terminated.

[0085] In practical implementation, during the execution of a special vector instruction, the vector instruction processing circuit can simultaneously maintain the execution progress status of both the MOP level and the sub-MOP level. The sub-MOP level represents the fine-grained execution progress within the current MOP, while the MOP level represents the overall segmented execution progress of the current special vector instruction. Therefore, after the current sub-MOP is completed, the vector instruction processing circuit not only needs to determine whether the current sub-MOP is the last sub-MOP corresponding to the current MOP, but also needs to further determine whether the current MOP is the last MOP corresponding to the current special vector instruction after the sub-MOP level is completed. This determines whether to switch to the next MOP to continue execution or directly terminate the execution process of the currently pending RVV instruction.

[0086] In one embodiment, the comparator in the sub-MOP number generation path compares the current sub-MOP number with the maximum sub-MOP count value corresponding to the current MOP to generate a sub-MOP completion determination result. When the comparison result shows that the current sub-MOP number has reached the sub-MOP boundary corresponding to the current MOP, it can be determined that all sub-MOPs corresponding to the current MOP have been launched.

[0087] At this point, it indicates that the local cumulative calculation process within the current MOP, which unfolds sequentially through multiple sub-MOPs, has been completed. The execution unit has obtained the target execution result corresponding to the current MOP, and thus the sub-MOP-level advancement process of the current MOP can be terminated, and preparations can be made to enter the processing stage of the next MOP.

[0088] When it is determined that all sub-MOPs corresponding to the current MOP have been transmitted, the vector instruction processing circuit can control the MOP number generation path to perform an MOP switching operation, and simultaneously control the sub-MOP number generation path to perform a sub-MOP reset operation. Specifically, the adder in the MOP numbering path can increment the current MOP number to obtain a candidate value for the next MOP number, and then write the candidate value for the next MOP number into the MOP number register through the MOP selector, thereby switching the current MOP number to the next MOP number.

[0089] At the same time, a preset reset value, such as 0, can be input into the sub-MOP number register through the sub-MOP selector to return the sub-MOP number to the initial state, thereby establishing the starting numbering condition for the sequential launch of multiple sub-MOPs within the next MOP.

[0090] Furthermore, after all the sub-MOPs corresponding to the current MOP have been issued, the vector instruction processing circuit can also use the comparator in the MOP numbering path to compare the current MOP number or the switched MOP number with the maximum MOP count value corresponding to the special vector instruction, so as to determine whether all the MOPs corresponding to the current special vector instruction have been issued.

[0091] Here, when the comparison result shows that all MOPs have not been completed, it means that there are still subsequent MOPs to be processed for the currently pending RVV instruction. At this time, the vector instruction processing circuit can continue to start the sub-MOP splitting and sequential issuance process corresponding to the next MOP according to the new MOP number and the reset sub-MOP number.

[0092] Here, when the comparison result shows that all MOPs corresponding to the current special vector instruction have been issued, it can be determined that the entire microcode decomposition and execution process of the current RVV instruction to be executed has ended. At this time, the vector instruction processing circuit can output an instruction completion flag to notify the subsequent pipeline control logic, submit the control logic, or write the result back to the control logic, indicating that the current special vector instruction has been executed.

[0093] At the same time, the MOP number register and sub-MOP number register can be cleared, or the initial state value of the next instruction can be maintained or loaded to prepare for the entry and execution of subsequent RVV instructions.

[0094] In some implementations, ending the execution of the pending RVV instruction includes not only stopping the continued issuance of the MOP and sub-MOP corresponding to the current special vector instruction, but also includes: writing the final execution result back to the target vector register; releasing the execution control resources occupied by the current special vector instruction; updating the pipeline status information; and returning a feedback signal that the current instruction has been completed to the front end or scheduling module.

[0095] In other words, as long as it can be shown that all MOPs and their internal sub-MOPs corresponding to the current special vector instruction have been executed and the subsequent micro-operations related to the instruction have been terminated, it can be regarded as the termination of the execution of the RVV instruction to be executed in this embodiment.

[0096] It should also be noted that, in this embodiment, the determination of the completion of sub-MOP execution and the determination of the completion of MOP execution can be two-stage determination processes performed sequentially, or they can be completed collaboratively through logical combination in specific hardware implementations. For example, the MOP switching condition can be triggered first by the sub-MOP comparison result, and then the MOP comparison result can determine whether to continue to the next MOP; alternatively, the instruction end control signal can be directly output when the combinational logic detects that the current sub-MOP is the last sub-MOP of the current MOP and the current MOP is the last MOP of the current instruction. Regardless of the determination and switching timing adopted, as long as the two core control objectives of switching the MOP and resetting the sub-MOP number after all sub-MOPs in the current MOP are completed, and ending the execution of the current instruction after all MOPs are completed, are within the protection scope of this application.

[0097] This disclosure provides a microcode splitting method for RVV instructions. By introducing a sub-MOP splitting mechanism on top of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs. This allows the execution unit to gradually complete the target computation using intermediate results generated by preceding sub-MOPs, thereby achieving the execution of special vector instructions without significantly modifying the existing execution unit structure. This effectively reduces hardware modification costs, improves the reusability of existing vector microarchitectures, alleviates register port pressure, and enhances the processor's compatibility with special RISC-V vector instructions and its engineering feasibility. Those skilled in the art will understand that the order in which the steps are written in the above-described method does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0098] Based on the same inventive concept, this disclosure also provides an RVV instruction microcode splitting device corresponding to the RVV instruction microcode splitting method. Since the principle of the device in this disclosure for solving the problem is similar to the RVV instruction microcode splitting method described above in this disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0099] Please see Figure 3 , Figure 3 This is a schematic diagram of a microcode splitting device for RVV instructions provided in an embodiment of this disclosure. Figure 3 As shown in the figure, the microcode splitting device 300 for RVV instructions provided in this embodiment includes: The type determination module 310 is used to determine the instruction type of the RVV instruction to be executed, and to determine whether the RVV instruction to be executed is a special vector instruction.

[0100] The non-special instruction processing module 320 is used to perform micro-operation splitting on the RVV instruction to be executed according to the ordinary MOP splitting method when the RVV instruction to be executed is a non-special vector instruction, and to issue the corresponding MOPs for execution in sequence according to the MOP number; The special instruction processing module 330 is used to split the RVV instruction to be executed into multiple MOPs according to a preset MOP splitting method when the RVV instruction to be executed is a special vector instruction, and to further split any MOP into multiple sub-MOPs.

[0101] MOP emission module 340 is used to sequentially emit multiple sub-MOPs corresponding to the current MOP according to the sub-MOP number, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOP.

[0102] The execution determination module 350 is used to switch the MOP number to the next MOP and reset the sub-MOP number when it is determined that multiple sub-MOPs corresponding to the current MOP have been issued; and to end the execution of the RVV instruction to be executed when it is determined that all MOPs corresponding to the current special vector instruction have been issued.

[0103] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0104] This disclosure provides a microcode splitting device for RVV instructions. By introducing a sub-MOP splitting mechanism on top of ordinary MOP splitting, a single MOP corresponding to a special vector instruction is further split into multiple sequentially executed sub-MOPs. This allows the execution unit to gradually complete the target computation using intermediate results generated by preceding sub-MOPs, thereby achieving the execution of special vector instructions without significantly modifying the existing execution unit structure. This effectively reduces hardware modification costs, improves the reusability of existing vector microarchitectures, alleviates register port pressure, and enhances the processor's compatibility with special RISC-V vector instructions and the feasibility of engineering implementation. Those skilled in the art will understand that the order in which the steps are written in the above-described method of specific embodiments does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0105] Corresponding to Figure 2 The microcode decomposition method for RVV instructions in this disclosure also provides an electronic device 400, such as... Figure 4 The diagram shown is a structural schematic of an electronic device 400 provided in an embodiment of this disclosure, including: Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including main memory 421 and external memory 422; the main memory 421, also called internal memory, is used to temporarily store the computational data in processor 41, as well as the data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through main memory 421. When the electronic device 400 is running, processor 41 and memory 42 communicate through bus 43, enabling processor 41 to execute... Figure 2 The steps of the microcode splitting method for RVV instructions in the code.

[0106] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the RVV instruction microcode splitting method described in the above method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0107] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the microcode splitting method for RVV instructions described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0108] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0112] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0113] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A method for microcode decomposition of RVV instructions, characterized in that, The method, applied to a vector instruction processing circuit in a processor, includes: The instruction type of the RVV instruction to be executed is determined to determine whether the RVV instruction to be executed is a special vector instruction; When the RVV instruction to be executed is a non-special vector instruction, the RVV instruction to be executed is split into micro-operations according to the normal MOP splitting method, and the corresponding MOPs are issued and executed sequentially according to the MOP number; When the RVV instruction to be executed is a special vector instruction, the RVV instruction to be executed is split into multiple MOPs according to a preset MOP splitting method, and any MOP is further split into multiple sub-MOPs; Multiple sub-MOPs corresponding to the current MOP are issued sequentially according to the sub-MOP number, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOPs. When it is determined that all sub-MOPs corresponding to the current MOP have been issued, the MOP number is switched to the next MOP and the sub-MOP number is reset; when it is determined that all MOPs corresponding to the current special vector instruction have been issued, the execution of the pending RVV instruction ends.

2. The method according to claim 1, characterized in that, The RVV instruction to be executed is split into multiple MOPs according to a preset MOP splitting method, specifically including: Based on the instruction information of the RVV instruction to be executed and the register group configuration information in the vector configuration register, determine the total number of MOPs corresponding to the RVV instruction to be executed; The current MOP number is recorded in the MOP number register and incremented by the MOP adder; The MOP comparator compares the current MOP number with the total number of MOPs to determine whether all MOPs corresponding to the current special vector instruction have been issued.

3. The method according to claim 1, characterized in that, Any MOP can be further subdivided into multiple sub-MOPs, specifically including: The total number of sub-MOPs corresponding to the current MOP is determined based on the instruction information, register set configuration information, and special vector instruction type corresponding to the current MOP. The current sub-MOP number is recorded in the sub-MOP number register and incremented by the sub-MOP adder; The sub-MOP comparator compares the current sub-MOP number with the total number of sub-MOPs to determine whether all sub-MOPs corresponding to the current MOP have been transmitted.

4. The method according to claim 3, characterized in that, Multiple sub-MOPs corresponding to the current MOP are issued sequentially according to their sub-MOP numbers, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOPs. Specifically, this includes: When the first sub-MOP is launched, the preset initial value and the source operand corresponding to the current sub-MOP are used as the input to the execution unit; When issuing subsequent sub-MOPs, the intermediate results generated by the previous sub-MOP and the source operands corresponding to the current sub-MOP are used as the inputs to the execution unit; The control execution unit executes each sub-MOP sequentially until the target execution result corresponding to the current MOP is obtained; The preset initial value is zero, and the intermediate result is the staged calculation result obtained by writing back or bypassing after the execution of the preceding sub-MOP.

5. The method according to claim 1, characterized in that, Before sequentially transmitting multiple sub-MOPs corresponding to the current MOP according to their sub-MOP numbers, the method further includes: The element quantity calculation module determines the number of elements to be processed corresponding to the micro-operation to be launched. Specifically, when the RVV instruction to be executed is a non-special vector instruction, the element quantity calculation module determines the number of elements to be processed corresponding to the current MOP based on the current MOP number; when the RVV instruction to be executed is a special vector instruction, the element quantity calculation module determines the number of elements to be processed corresponding to the current sub-MOP based on the current sub-MOP number.

6. The method according to claim 1, characterized in that, When it is determined that all the sub-MOPs corresponding to the current MOP have been launched, the MOP number is switched to the next MOP and the sub-MOP number is reset. When it is determined that all MOPs corresponding to the current special vector instruction have been issued, the execution of the pending RVV instruction is terminated, specifically including: Output the sub-MOP completion flag of the current MOP through the sub-MOP comparator; In response to the sub-MOP completion flag, the control sub-MOP selector sets the sub-MOP number register to zero; The control MOP selector selects the output of the MOP adder as the input to the MOP number register, so that the MOP number switches to the next MOP; The instruction completion flag is output via the MOP comparator; In response to the instruction completion flag, the control MOP number register is cleared, and the control sub-MOP number register is also cleared to prepare for processing the next vector instruction.

7. The method according to claim 1, characterized in that, The vector instruction processing circuit includes: The MOP number register is used to store the current MOP number; The MOP adder is used to increment the current MOP number; The maximum MOP counter is used to determine the total number of MOPs corresponding to the vector instructions to be executed. The MOP comparator is used to determine whether all MOPs have been emitted. The MOP selector, used to control the input selection of the MOP number register, is configured to select the reset value as the input of the MOP number register when all MOPs have been issued; select the number value incremented by the MOP adder as the input of the MOP number register when all sub-MOPs corresponding to the current MOP have been issued but all MOPs have not been issued; and keep the current MOP number unchanged when not all sub-MOPs corresponding to the current MOP have been issued. The sub-MOP number register is used to store the current sub-MOP number; The sub-MOP adder is used to increment the current sub-MOP number; The maximum sub-MOP counter is used to determine the total number of sub-MOPs corresponding to the current MOP; The sub-MOP comparator is used to determine whether all sub-MOPs of the current MOP have been emitted. The sub-MOP selector, used to control the input selection of the sub-MOP number register, is configured to select the reset value as the input of the sub-MOP number register when all MOPs have been issued; select the reset value as the input of the sub-MOP number register when all sub-MOPs corresponding to the current MOP have been issued; and select the number value incremented by the sub-MOP adder as the input of the sub-MOP number register when the sub-MOPs corresponding to the current MOP have not been issued. The element quantity calculation module is used to determine the number of elements to be processed corresponding to the current micro-operation to be launched; The vector instruction execution module is used to perform corresponding operations based on the currently emitted MOP or sub-MOP.

8. A microcode splitting device for RVV instructions, characterized in that, The apparatus is used in a vector instruction processing circuit in a processor, the apparatus comprising: The type determination module is used to determine the instruction type of the RVV instruction to be executed, and to determine whether the RVV instruction to be executed is a special vector instruction. The non-special instruction processing module is used to perform micro-operation splitting on the RVV instruction to be executed according to the ordinary MOP splitting method when the RVV instruction to be executed is a non-special vector instruction, and to issue the corresponding MOPs for execution in sequence according to the MOP number; A special instruction processing module is used to split the RVV instruction to be executed into multiple MOPs according to a preset MOP splitting method when the RVV instruction to be executed is a special vector instruction, and to further split any MOP into multiple sub-MOPs. The MOP launch module is used to launch multiple sub-MOPs corresponding to the current MOP in sequence according to the sub-MOP number, so that the execution unit can complete the cumulative calculation corresponding to the current MOP one by one based on the source operands corresponding to the current sub-MOP and the intermediate results corresponding to the previous sub-MOPs. The execution determination module is used to switch the MOP number to the next MOP and reset the sub-MOP number when it is determined that multiple sub-MOPs corresponding to the current MOP have been issued; and to end the execution of the RVV instruction to be executed when it is determined that all MOPs corresponding to the current special vector instruction have been issued.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the microcode splitting method for RVV instructions as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the microcode splitting method for RVV instructions as described in any one of claims 1 to 7.

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