Method and circuit for bit read during power-on reset for non-volatile memory

Abstract

The present disclosure relates to methods and circuits for bit reading during power-on reset for non-volatile memory. Embodiments of the present disclosure provide a memory circuit comprising: a non-volatile memory; a one-time programmable memory; a sense amplifier coupled to the non-volatile memory and the one-time programmable memory; a digital register coupled to an output of the sense amplifier to store a reference resistance bit; control logic coupled to an output of the digital register; a decoder coupled to an output of the control logic; and a controller to output control signals to the control logic to select a first reference resistance for the sense amplifier from the decoder to read a bit from the one-time programmable memory and to select a second reference resistance for the sense amplifier from the decoder to read a bit from the non-volatile memory.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to integrated circuits. More specifically, this disclosure provides methods and circuitry for bit reading during a power-on-reset (POR) of a non-volatile memory. Background Technology

[0002] Non-volatile memory (NVM) is a type of memory that retains its stored contents even when power is removed. Electrically erasable programmable read-only memory (EEPROM) and flash memory are two common types of NVM. Specifically, flash memory has become widely used in electronic devices, especially portable electronic devices, due to its ability to provide data storage at low power levels.

[0003] Operating NVM memories typically requires specified, stable reference voltage and current values ​​to ensure proper circuit operation. Due to variations in manufacturing processes, the voltage or current values ​​generated by internal or on-chip reference sources often vary between chips. To set the desired operating point for the internal reference source, adjustments can be performed on the integrated circuit to fine-tune the internal reference source to the desired operating point. This adjustment process, called trimming, is typically performed using trimming bits stored in a portion of the NVM memory to set the desired operating point for the internal reference source.

[0004] In NVM memory, trimming is used not only to adjust the internal analog voltage / current levels to a desired target level, but also to compensate for temperature or enable / disable special internal functions. To save on actual silicon area, NVM memory typically includes a dedicated area for storing trimming data (e.g., one-time programmable (OTP) memory). After the NVM memory is powered on, the trimming data is read from the OTP memory during normal memory read operations and applied to the corresponding circuitry of the NVM memory. However, in some cases, the trimming data may not be correctly read from the NVM memory after power-on and before the analog level adjustments can be applied.

[0005] OTP memory is a type of memory that can be programmed only once to permanently store data, but ideally can be read an unlimited number of times. OTP memory can be used to store trimming data, integrated circuit identification information, firmware (such as BIOS), security data, etc. Trimming data may include, for example, configuration data for integrated circuits and / or data used to compensate for process variability that may occur during integrated circuit manufacturing.

[0006] A portion of the NVM memory can be configured as an OTP memory to store trimming data used to initialize the NVM memory during the POR process. In some cases, the OTP memory may include multiple fuses that have been selectively "blown" to program the trimming data into the OTP memory as trimming bits. Once blown, the final bit in the OTP memory has a much higher resistance than the bit in the NVM memory. In another implementation, the manufactured bit may have very high resistance, and some bits may be programmed to have very low resistance or be short-circuited to store the trimming data into the OTP memory. After programming, the trimming bit can be read from the OTP memory and used to configure the NVM memory during the POR process.

[0007] Data stored in OTP and NVM memories can be read using a sense amplifier. However, the read reference resistor of the sense amplifier is suitable for reading bits from either OTP or NVM memory, but not from both. This is because OTP memory has stricter retention requirements under stress (such as thermal stress) compared to NVM memory, and stress can cause the resistance of a bit to drift over time. Furthermore, the optimal reference resistor for the sense amplifier differs for OTP and NVM memories. Therefore, using a single reference resistor level may result in erroneous data being read from either OTP or NVM memory during a Proof-of-Return (POR) event. Summary of the Invention

[0008] Some aspects of this disclosure provide a memory circuit including: a non-volatile memory; a one-time programmable memory; a sense amplifier coupled to the non-volatile memory and the one-time programmable memory; a digital register coupled to the output of the sense amplifier to store a reference resistor bit; control logic coupled to the output of the digital register; a decoder coupled to the output of the control logic; and a controller for outputting a control signal to the control logic to select a first reference resistor for the sense amplifier from the decoder to read a bit from the one-time programmable memory, and to select a second reference resistor for the sense amplifier from the decoder to read a bit from the non-volatile memory. The selection is based on whether the circuit is in a power-on reset mode (or OTP read mode) or a normal read mode.

[0009] Another aspect of this disclosure includes a method for accessing a memory comprising a non-volatile memory, a one-time programmable memory, and a sense amplifier coupled to the non-volatile memory and the one-time programmable memory, the method comprising: storing reference resistor bits in a digital register; and outputting control signals to control logic to select a first reference resistor for the sense amplifier from a decoder to read bits from the one-time programmable memory, and to select a second reference resistor for the sense amplifier from the decoder to read bits from the non-volatile memory. Attached Figure Description

[0010] Figure 1 A conventional circuit is shown for reading data from one-time programmable (OTP) memory and non-volatile memory (NVM) during a power-on reset (POR) process.

[0011] Figure 2 A circuit is shown according to an embodiment of the present disclosure for reading data from an OTP memory and an NVM memory during a POR process.

[0012] Figure 3 Embodiments according to this disclosure are shown in more detail. Figure 2 The circuit.

[0013] Figure 4 This illustrates an embodiment of the present disclosure showing the process of reading trimmed fuse bits from an OTP memory during a POR process. Figure 3 The circuit.

[0014] Figure 5 This illustrates an embodiment of the present disclosure showing the process of reading NVM data bits from an NVM memory during a POR process. Figure 3 The circuit.

[0015] Figure 6 An additional embodiment of this disclosure illustrates the process of reading trimmed fuse bits from an OTP memory during a POR process. Figure 3 The circuit.

[0016] Figure 7 An additional embodiment of this disclosure illustrates the process of reading data bits from an OTP memory during a POR procedure. Figure 3 The circuit.

[0017] Figure 8 Embodiments according to this disclosure are shown in more detail. Figure 2 The sensing amplifier.

[0018] Please note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0019] In the following description, reference is made to the accompanying drawings, which form a part thereof, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of illustration. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely exemplary.

[0020] Figure 1 A conventional circuit 10 is shown for reading data from a non-volatile memory (NVM) array 12, including main memory 14 and one-time programmable (OTP) memory 16, during a power-on reset (POR) process. The OTP memory 16 may be formed as a portion of the main memory 14. The OTP memory 16 may include multiple fuses (not shown) that have been selectively “blown” to program trimmed data into the OTP memory 16 as trimmed fuse bits 18. After programming, trimmed fuse bits 18 can be read from the OTP memory 16 and used to configure circuit 10 during the POR process.

[0021] After trimming fuse bit 18 is programmed, the OTP control byte can be used to permanently lock the portion of main memory 14 used for OTP memory 16. For example, one or more bits in the OTP control byte can be set to a first state to allow trimming fuse bit 18 to be programmed into OTP memory 16. When the relevant bit in the OTP control byte is set to a second state, opposite to the first state, OTP memory 16 becomes read-only and cannot be reprogrammed. For example, once the relevant bit in the OTP control byte is set to the second state, these data bits cannot be set back to the first state. Therefore, once the relevant bit in the OTP control byte is set to the second state, the entire OTP memory 16 becomes permanently read-only. Thereafter, any programming or erasing cycles applied to OTP memory 16 are rejected.

[0022] Main memory bits 20 stored in main memory 14 and trimming fuse bits 18 stored in OTP memory 16 can be selectively accessed in a conventional manner by row decoders and column decoders for read, program (write), and erase operations. During a read operation, trimming fuse bits 18 stored in OTP memory 16 and main memory bits 20 stored in main memory 14 can be read by sense amplifier 22, which can be configured to measure the current flowing through the cells of main memory 14 and OTP memory 16. In practice, sense amplifier 22 may include a set of sense amplifiers (or sense amplifier circuitry), one sense amplifier for each input / output (I / O) in memory array 12. However, in the following description, the operation of memory array 12 is described with reference to a single sense amplifier 22.

[0023] Sensing amplifier 22 is coupled to digital register 24, which stores trimming fuse bits 18 read from OTP memory 16 by sensing amplifier 22 during the POR process. The trimming fuse bits 18 stored in digital register 24 include reference resistor bits, which are read from digital register 22 by sensing amplifier 22 as reference resistors REF. The reference resistors REF are typically set to a value that is optimal for reading main memory bit 20 from main memory 14 but suboptimal for reading trimming fuse bits 18 from OTP memory 16. For example, to accurately read trimming fuse bits 18 from OTP memory 16 during a POR read, sensing amplifier 22 might need a reference resistor REF much larger than the reference resistor REF required when reading main memory bit 20 from main memory 14. This could result in erroneous data being read from OTP memory 16.

[0024] Figure 2 A circuit 100 is shown according to an embodiment of the present disclosure for reading data from an NVM array 112 including a main memory 114 and an OTP memory 116 during a POR process. Similar to... Figure 1The OTP memory 16 shown can be formed as a portion of the main memory 114 by selectively "fusing" multiple fuses (not shown) to program trimming data into predefined trimming addresses in the OTP memory 116 as trimming fuse bits 118. Alternatively, the OTP memory 116 can be decoupled from the main memory 114. After programming, the trimming fuse bits 118 can be read from the OTP memory 116 and used to configure the circuit 100 during the POR process. However, unlike the conventional circuit 10 described above, the circuit 100 according to embodiments of this disclosure is configured to provide different reference resistors REF to the sense amplifier 122 during the POR process, depending on whether the sense amplifier 122 is currently reading from the OTP memory 116 or the main memory 114.

[0025] Main memory bit 120 stored in main memory 114 and trimming fuse bit 118 stored in OTP memory 116 can be selectively accessed during read, program (write), and erase operations (e.g., via row decoder and column decoder). During a read operation, sense amplifier 122 can be used to read trimming fuse bit 118 stored in OTP memory 116 and main memory bit 120 stored in main memory 114. Sense amplifier 122 can be configured to measure the current flowing through the cells of main memory 114 and OTP memory 116. For example, sense amplifier 122 can compare the current flowing through the memory cells of main memory 114 and OTP memory 116 with a reference current flowing through a reference resistor set according to a reference resistor REF output by decoder 130, and generate a digital reading (readout) for comparison. Although in Figure 2 The NVM array 112 is shown as a single sense amplifier 122, but sense amplifier 122 can be implemented using a set of sense amplifiers (or sense amplifier circuitry), where each sense amplifier is coupled to a corresponding input / output (I / O) of the NVM array 112. However, in the following description, the operation of the NVM array 112 is again described with reference to the single sense amplifier 122.

[0026] An exemplary sense amplifier 122 according to embodiments of the present disclosure is in Figure 8 As shown in the figure, the sensing amplifier 122 may include a variable resistor R set based on a reference resistor REF output from the decoder 130. VAR The sensing amplifier 122 compares the current flowing through the variable resistor R. VAR Current I REF The current I flowing through the memory cells of the main memory 114 and the OTP memory 116 DATA Current I REF With the measured current I DATAThe comparison result is converted into a voltage value, amplified, and output as a digital value.

[0027] Sensing amplifier 122 is coupled to digital register 124, which is configured to store (e.g., during the POR process) trimming fuse bits 118 read from OTP memory 116 by sensing amplifier 122. The trimming fuse bits 118 stored in digital register 124 may include reference resistor REFRES_TRM bits used to select the reference resistor REF from decoder 130. Alternatively, the reference resistor REFRES_TRM bits may be stored in digital register 124 prior to the POR process.

[0028] Decoder 130 is coupled to sense amplifier 122. Decoder 130 is used to select a reference resistor REF from a plurality of reference resistors REF, wherein the selected reference resistor REF is provided to sense amplifier 122. According to embodiments of this disclosure, the reference resistor REF can be selected from resistor R REF, MAIN to resistor R REF, OTP The change, in which the resistance R REF, MAIN It is optimal for reading main memory bit 120 from main memory bit 114, R REF, OTP This is optimal for reading trimmed fuse bit 118 from OPT memory 116, where R REF, MAIN < <R REF, OTP For example, in Figure 2 In the non-restrictive example shown, R REF, MAIN It can be a 16k ohm resistor used to read main memory bit 120 from main memory 114, while R REF, OTP It can be used to read the trimmed fuse bit 118 from the OPT memory 116, which is 160k ohms.

[0029] The output of control logic 132 is coupled to decoder 130. According to an embodiment of this disclosure, control logic 132 is configured to output address SA_TRM to decoder 130 for selecting reference resistor REF for sense amplifier 122 based on the value of signal POR_MODE from controller 136 during the POR process and the reference resistor REFRES_TRM bit stored in digital register 124.

[0030] According to embodiments of this disclosure, such as Figure 3As shown, the control logic may include multiple OR gates 134 (e.g., three OR gates). The first input of each of the multiple OR gates 134 is coupled to the controller 136, and a POR_MODE signal is received from the controller 136. Each bit of the reference resistor REFRES_TRM bit stored in the digital register 124 is coupled to the second input of the corresponding OR gate 134. The outputs of the multiple OR gates 134 provide the address SA_TRM for selecting a reference resistor REF implemented in the decoder 130.

[0031] According to embodiments of this disclosure, each bit of the reference resistor REFRES_TRM bit read into (or otherwise stored in) the digital register 124 can be set to a logic 0 value (e.g., 000). Figure 4 As shown, for example, when controller 136 receives a reset command RESET at the start of the POR process, controller 136 outputs the signal POR_MODE = 1 to the first input of each of the plurality of OR gates 134. The second input of each of the plurality of OR gates 134 is coupled to a corresponding bit in the reference resistor REFRES_TRM bit (000). In this case, the first input of each OR gate 134 is set to a logic 1 value, while the second input of each of the plurality of OR gates 134 is set to a logic 0 value. The output of each of the plurality of OR gates 134 is thus set to a logic 1 value, such that the address SA_TRM output by control logic 132 to decoder 130 is 111.

[0032] Three OR gates 134 in Figure 3 The OR gate 134 is shown as being used to output the three-bit address SA_TRM to decoder 130. However, the number of OR gates 134 can vary depending on the addressing requirements of decoder 130.

[0033] like Figure 4 As shown, when POR_MODE = 1, the three OR gates 134 of control logic 132 output the three-bit address SA_TRM = 111 to decoder 130. In response to the address SA_TRM = 111 provided by the multiple OR gates 134, decoder 130 sets the reference resistor REF = R... REF, OTP (For example, 160k ohms) The output is sent to the sense amplifier 122, and the reference resistor REF = R REF, OTP This is optimal for reading trimmed fuse bit 118 from OPT memory 116. Then, a reference resistor REF = R can be used. REF, OTP The trimming fuse bit 118 is read from the OPT memory 116 by the sensing amplifier 122.

[0034] like Figure 5As shown, after controller 136 determines that all trimming fuse data 118 has been read from the predefined trimming address of OPT memory 116, controller 136 outputs the signal POR_MODE = 0 to the first input of each of the plurality of OR gates 134. In this case, both inputs of each OR gate 134 are set to logic 0. The output of each of the plurality of OR gates 134 is thus set to logic 0, and the three-bit address SA_TRM = 000 is output by the plurality of OR gates 136 to decoder 130.

[0035] In response to the address SA_TRM = 000 output by the multiple OR gates 134 of control logic 132, decoder 130 now references resistor REF = R REF, MAIN (For example, 16k ohms) The output is sent to the sense amplifier 122, and the reference resistor REF = R REF, MAIN This is optimal for reading main memory bit 120 from main memory bit 114. Then, a reference resistor REF = R can be used. REF, MAIN The main memory bit 120 is read by the sensing amplifier 122.

[0036] Summary of circuit 100 operation: When POR_MODE = 1, SA_TRM = 111, REF = R REF, OTP ; and when POR_MODE = 0, SA_TRM = 000, REF = R REF, MAIN Advantageously, different optimal reference resistors REF can be provided to the sense amplifier 122 to read trimmed fuse bit 118 from OTP memory 116 during the POR process and subsequently read main memory bit 120 from main memory 114.

[0037] An additional reference resistor REF = R can be implemented in decoder 130. REF, MAIN And different reference resistors R REF, MAIN It can be selected from decoder 130 and provided to sensing amplifier 122. For example... Figure 6 As shown, this can be achieved, for example, by storing a different set of reference resistor REFRES_TRM bits in digital register 124 so that different addresses SA_TRM are output by multiple OR gates 134. For example, when REFRES_TRM = 001, the reference resistor R stored at address SA_TRM = 001 in decoder 130 is selected when POR_MODE = 0. REF, MAIN = 25k ohms. Different reference resistors R can be selected from the decoder 130 by providing different values ​​for the REFRES_TRM bit. REF, MAIN And provide it to the sensing amplifier 122.

[0038] An additional reference resistor REF = R can also be implemented in decoder 130. REF, OTP So that different reference resistors R REF, OTP It can be selected by decoder 130 and provided to sensing amplifier 122. For example... Figure 7 As shown, this can be achieved, for example, by the controller 136 outputting a multi-bit POR_MODE signal to the first input of a plurality of OR gates 134 in response to a RESET signal. For example, if the controller 136 outputs a POR_MODE = 110 signal to the first input of a plurality of OR gates and assuming REFRS_TRM = 000, then the address SA_TRM = 110 is provided to the decoder 130. As a result, the reference resistor REF = R corresponding to the address SA_TRM = 110... REF, OTP (For example, 130k ohms) is output to the sensing amplifier 122.

[0039] From the above discussion, it should be clear that the address SA_TRM for the decoder 130 can be selectively generated using different combinations of control logic 132, the POR_MODE signal output by controller 136, and the REFRES_TRM bit of the reference resistor stored in digital register 124. For example, control logic 132 may include a NOR gate instead of... Figure 3-7 The OR gate 134 is shown in the diagram. In this case, the controller 136 can output the signal POR_MODE = 0 to the first input of each NOR gate in response to the RESET signal, so that the decoder 130 can select the reference resistor REF = R. REF, OTP Assuming REFRS_TRM = 000, the NOR gate of control logic 132 will output to decoder 130 the value of the reference resistor REF = R. REF, OTP The corresponding address is SA_TRM = 111.

[0040] The methods and structures described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0042] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0043] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A memory circuit, comprising: Non-volatile memory; One-time programmable memory; A sensing amplifier coupled to the non-volatile memory and the one-time programmable memory; A digital register, coupled to the output of the sense amplifier, stores a reference resistor bit; Control logic, which is coupled to the output of the digital register; A decoder, which is coupled to the output of the control logic; as well as A controller is configured to output control signals to the control logic to select a first reference resistor from the decoder for the sense amplifier to read bits from the one-time programmable memory, and to select a second reference resistor from the decoder for the sense amplifier to read bits from the non-volatile memory.

2. The memory circuit according to claim 1, wherein, The first reference resistor is greater than the second reference resistor.

3. The memory circuit according to claim 1, wherein, The non-volatile memory portion includes the one-time programmable memory.

4. The memory circuit according to claim 1, wherein, The controller outputs the control signal to the control logic during the power-on reset process.

5. The memory circuit according to claim 1, wherein, The bits read from the one-time programmable memory include trimmed fuse bits.

6. The memory circuit according to claim 1, wherein, The control logic outputs an address to the decoder for selecting a reference resistor from the decoder.

7. The memory circuit according to claim 1, wherein, The control signal output by the controller has a first value for reading bits from the one-time programmable memory, and wherein the control signal output by the controller has a second value for reading bits from the non-volatile memory.

8. The memory circuit according to claim 1, wherein, The control logic includes a plurality of OR gates, wherein the first input of each of the plurality of OR gates receives the control signal output by the controller.

9. The memory circuit according to claim 8, wherein, The second input of each of the plurality of OR gates receives a corresponding bit from the reference resistor bit stored in the digital register.

10. The memory circuit according to claim 9, wherein, Each of the plurality of OR gates is configured to output a logic 1 value for reading a bit from the one-time programmable memory, and wherein each of the plurality of OR gates is configured to output a logic 0 value for reading a bit from the non-volatile memory.

11. The memory circuit according to claim 10, wherein, The controller receives a reset signal that indicates the controller will output a control signal to the control logic to select the first reference resistor for the sense amplifier from the decoder, in order to read bits from the one-time programmable memory.

12. A method for accessing a memory, the memory comprising a non-volatile memory, a one-time programmable memory, and a sensing amplifier coupled to the non-volatile memory and the one-time programmable memory, the method comprising: Store the reference resistor bit in the digital register; as well as The control signal is output to the control logic to select a first reference resistor from the decoder for the sense amplifier to read bits from the one-time programmable memory, and to select a second reference resistor from the decoder for the sense amplifier to read bits from the non-volatile memory.

13. The method according to claim 12, wherein, The first reference resistor is greater than the second reference resistor.

14. The method according to claim 12, wherein, The bits read from the one-time programmable memory include trimmed fuse bits.

15. The method of claim 12, further comprising: The control logic outputs an address for selecting a reference resistor from the decoder.

16. The method of claim 12, further comprising: The controller outputs the control signal to the control logic during the power-on reset process.

17. The method of claim 15, further comprising: The controller receives a reset signal indicating the start of the power-on reset process; as well as The controller outputs the control signal to the control logic to select the first reference resistor for the sense amplifier from the decoder to read bits from the one-time programmable memory.

18. The method according to claim 16, wherein, The control signal output by the controller has a first value for reading bits from the one-time programmable memory, and wherein the control signal output by the controller has a second value for reading bits from the non-volatile memory.

19. The method according to claim 12, wherein, The control logic includes multiple OR gates, wherein the first input of each of the multiple OR gates receives a control signal output by the controller.

20. The method according to claim 19, wherein, The second input of each of the plurality of OR gates receives a corresponding bit from the reference resistor bit stored in the digital register.

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