Refresh method of non-volatile memory, controller and electronic device
By selecting the appropriate refresh process based on the operating voltage of the previous memory cell and using a hierarchical decision mechanism to quickly filter out cells that do not need to be refreshed, the problem of frequent voltage switching in the refresh process of non-volatile memory is solved, and more efficient and accurate refresh operations are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-09
Smart Images
Figure CN122177190A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the technical field of memory control, and for example to a refresh method, controller, and electronic device for a non-volatile memory. Background Technology
[0002] The core of non-volatile memory (NVMemory) consists of a large number of independent storage cells. Each cell is distinguished by a threshold voltage and stores binary data "0" or "1". Specifically, a cell with a higher threshold voltage (cell0) stores data "0", and a cell with a lower threshold voltage (cell1) stores data "1". Over long-term use, the threshold voltage of cell0 gradually decreases due to factors such as time and changes in ambient temperature. If not addressed promptly, its threshold voltage may fall into the range of cell1, leading to misreading (i.e., a stored "0" is misinterpreted as a "1"), severely impacting the accuracy of stored data and system stability. Therefore, periodically refreshing cell0 with a decaying threshold voltage to restore its normal threshold voltage is essential for ensuring the reliable operation of NVORAM.
[0003] In related technologies, the refresh process of non-volatile memory has formed a fixed execution pattern. Its core is to complete the screening and refresh operation of all memory cells through a fixed cycle of "low-voltage read verification → boost → high-voltage read verification → buck". In this process, regardless of the refresh completion voltage state of the previous memory cell, the next memory cell must start from the initial low voltage and repeat the fixed cycle. This fixed process results in an abnormally frequent switching of operating voltages during the refresh process. The voltage switching process consumes additional charge charging and discharging time and timing stabilization time, directly causing the entire refresh operation to take too long. Furthermore, the fixed refresh process provided by related technologies still strictly executes the complete voltage switching cycle even when no memory cells need to be refreshed, further exacerbating the problem of low refresh efficiency.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0006] This disclosure provides a refresh method, controller, and electronic device for non-volatile memory, which can reduce unnecessary voltage switching steps, avoid the extra time required for charge charging and discharging and timing stability during voltage switching, and thus shorten the overall refresh operation time.
[0007] According to a first aspect of this disclosure, a refresh method for a non-volatile memory is provided. The non-volatile memory includes multiple memory cells, and the refresh method includes: When it is necessary to start the refresh process of the current memory cell, the corresponding refresh process is selected for the current memory cell according to the currently held operating voltage. The operating voltage currently held by the circuit is the default voltage or the operating voltage at the end of the previous memory cell refresh process. The voltage value of the operating voltage includes the lower limit voltage and the upper limit voltage of the refresh determination voltage range. Refresh the current storage unit according to the selected refresh procedure; When the refresh process of the current storage cell ends, maintain the operating voltage at the end of the refresh process.
[0008] In some embodiments, the current storage unit is refreshed according to the selected refresh procedure, including: When the current operating voltage is maintained at the lower limit voltage, the value of the current memory cell is read using the lower limit voltage; If the value of the current storage cell read using the lower limit voltage is 1, it is determined that the current storage cell has no refresh requirement, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the upper limit voltage, and the value of the current memory cell is read using the upper limit voltage. Based on the value of the current memory cell read using the upper limit voltage, the refresh process continues.
[0009] In some embodiments, based on the value of the current memory cell read using the upper limit voltage, the refresh process continues, including: If the value of the current storage cell read using the upper limit voltage is 0, it is determined that there is no need to refresh the current storage cell, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the upper limit voltage is 1, the operating voltage is boosted from the upper limit voltage to the refresh voltage, and the current memory cell is refreshed using the refresh voltage.
[0010] In some embodiments, after refreshing the current memory cell using the refresh voltage, the method further includes: reducing the operating voltage from the refresh voltage to the lower limit voltage to end the refresh process of the current memory cell.
[0011] In some embodiments, the current storage unit is refreshed according to the selected refresh procedure, including: When the current operating voltage is at the upper limit voltage, the value of the current memory cell is read using the upper limit voltage; If the value of the current storage cell read using the upper limit voltage is 0, it is determined that there is no need to refresh the current storage cell, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the upper limit voltage is 1, the operating voltage is reduced from the upper limit voltage to the lower limit voltage, and the value of the current memory cell is read using the lower limit voltage. Based on the value of the current memory cell read using the lower limit voltage, the refresh process continues.
[0012] In some embodiments, based on the value of the current memory cell read using the lower limit voltage, the refresh process continues, including: If the value of the current storage cell read using the lower limit voltage is 1, it is determined that the current storage cell has no refresh requirement, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the lower limit voltage is 0, the operating voltage is increased from the lower limit voltage to the refresh voltage, and the current memory cell is refreshed using the refresh voltage.
[0013] In some embodiments, after refreshing the current memory cell using the refresh voltage, the method further includes: reducing the operating voltage from the refresh voltage to the lower limit voltage to end the refresh process of the current memory cell.
[0014] In some embodiments, when the refresh process corresponding to the current storage cell is selected, the operating voltage is used to read the values of a group of storage cells, including the current storage cell, and when it is determined from the value reading results that none of the storage cells in the group have a refresh requirement, the refresh process of the storage cell group is skipped.
[0015] According to a second aspect of this disclosure, a controller is provided, which is configured to perform a refresh method for non-volatile memory provided in the first aspect of this disclosure.
[0016] According to a third aspect of this disclosure, an electronic device is provided, the electronic device including a non-volatile memory and a controller provided in the second aspect of this disclosure.
[0017] The refresh method, controller, and electronic device for non-volatile memory provided in this disclosure can achieve the following technical effects: A refresh determination voltage range is pre-configured for determining whether a memory cell needs to be refreshed, and the lower and upper limits of the refresh determination voltage range are used as the operating voltage for reading the value of the memory cell. When a memory cell needs to be refreshed, a corresponding refresh process is selected for the current memory cell based on the operating voltage at the end of the previous memory cell refresh, and this currently maintained operating voltage is used as the operating voltage for the first reading of the value of the current memory cell in the refresh process. Specifically, if the latest operating voltage after the previous memory cell refresh is the lower limit voltage, the value of the current memory cell is read for the first time using the lower limit voltage; if it is the upper limit voltage, the value of the current memory cell is read for the first time using the upper limit voltage. This design breaks through the fixed execution mode of "forcing the use of a low voltage (lower limit voltage) as the first reading voltage in the memory cell refresh process," directly reducing meaningless voltage switching steps and avoiding the extra time required for charge charging and discharging and timing stability during voltage switching, thereby shortening the overall refresh operation time. Meanwhile, by selecting a suitable refresh process for the current unit based on the latest operating voltage at the end of the previous unit, the refresh operation of the current unit can be completed efficiently, further shortening the overall refresh time.
[0018] The above general description and the description below are exemplary and illustrative only and are not intended to limit this disclosure. Attached Figure Description
[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a controller provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram illustrating the use of a read storage unit according to an embodiment of this disclosure; Figure 4 This is a flowchart illustrating a refresh method for a non-volatile memory provided in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating another method for refreshing a non-volatile memory provided in an embodiment of this disclosure; Figure 6 This is a flowchart illustrating another method for refreshing a non-volatile memory provided in an embodiment of this disclosure. Detailed Implementation
[0020] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0022] Unless otherwise stated, the term "multiple" means two or more.
[0023] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0024] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0025] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0026] Non-volatile memory (NVMemory) comprises multiple storage cells, each distinguished by a threshold voltage and storing binary data "0" or "1". Storage cells with higher threshold voltages (cell0) store data "0", while those with lower threshold voltages (cell1) store data "1". Over long-term use, the threshold voltage of cell0 gradually decreases due to factors such as time and environmental temperature changes. Without timely intervention, its threshold voltage may fall within the range of cell1, leading to misreading (i.e., a stored "0" is misinterpreted as a "1"), severely impacting the accuracy of stored data and system stability. Therefore, periodically refreshing cell0 with decaying threshold voltages to restore its normal threshold voltage is essential for ensuring the reliable operation of NVORAM.
[0027] To accurately identify storage cells that need to be refreshed, this embodiment sets a refresh determination voltage range and a refresh voltage. The two boundary values of the refresh determination voltage range are defined as a lower limit voltage and an upper limit voltage, respectively. The lower limit voltage is the lowest threshold voltage within the range, and the upper limit voltage is the highest threshold voltage within the range. The upper limit voltage is less than the refresh voltage. Based on these voltages, refresh requirements can be determined by reading the storage cell values: first, a read operation is performed on the storage cell using the lower limit voltage and the upper limit voltage; then, based on the read results, it is accurately determined whether the storage cell needs to be refreshed. If the storage cell is determined to need refresh, a refresh operation is performed on it using the refresh voltage to restore the storage cell to its normal threshold voltage.
[0028] like Figure 1 As shown, this disclosure provides a controller that can be used to execute a refresh method for non-volatile memory. The controller integrates a state machine, a voltage pump module, and a register set. The state machine can schedule the entire refresh process, controlling the voltage pump, reading data from non-volatile memory cells, and writing data to the register set. The voltage pump module can generate three types of operating voltages required for the memory cell refresh process: a lower limit voltage, an upper limit voltage, and a refresh voltage. The voltage pump module can switch the operating voltage between the lower limit voltage, upper limit voltage, and refresh voltage through boost and buck operations. The register set stores the values obtained from reading the memory cell based on the lower limit voltage and upper limit voltage. The register set includes a first register and a second register. The first register stores the value obtained from the first read of the memory cell, and the second register stores the value obtained from the second read of the memory cell.
[0029] like Figure 2 As shown, this disclosure provides an electronic device, which includes a non-volatile memory and a controller provided in the above embodiments. The non-volatile memory may be an ETOX flash memory. The controller, as the execution body of the refresh method, establishes a voltage path and data transmission link with the non-volatile memory through a dedicated memory interface, and is capable of applying voltage to the non-volatile memory and reading and writing data to the non-volatile memory.
[0030] For other types of non-volatile memory, such as NOR Flash, NAND Flash, Phase Change Memory (PCM), and Resistive Random Access Memory (RRAM), the non-volatile memory refresh method provided in this disclosure can be applied when there is a refresh requirement for their memory cells. In specific implementation, key parameters such as the voltage determination range, read voltage threshold, and refresh voltage amplitude in the method can be adjusted according to the working mechanism, numerical representation logic, and threshold parameter characteristics of different types of non-volatile memory to match the hardware characteristics and refresh requirements of different memories, ensuring the universality and effectiveness of the refresh method.
[0031] like Figure 3 As shown, the value of the memory cell can be read first using the lower limit voltage, or the value of the memory cell can be read first using the upper limit voltage. The value of the memory cell read using the lower limit voltage can be 0 or 1, and the value of the memory cell read using the upper limit voltage can also be 0 or 1.
[0032] If the value of a memory cell is read using the lower voltage limit initially, and the value is 0, it means the threshold voltage of this memory cell is greater than the lower voltage limit. Then, the upper voltage limit is used to read the value of the memory cell. If the value is 1, it means the threshold voltage of this memory cell is less than the upper voltage limit. In this case, the memory cell is determined to need to be refreshed.
[0033] If the value of a memory cell is read using the upper limit voltage first, and the value read using the upper limit voltage is 1, then the value read using the lower limit voltage is 2. In this case, the memory cell is determined to need to be refreshed.
[0034] In conjunction with the controller and electronic device provided in the embodiments of this disclosure, the embodiments of this disclosure provide a method for refreshing non-volatile memory. The executing entity of the method for refreshing non-volatile memory is the controller in the electronic device, such as... Figure 4 As shown, the refresh methods for non-volatile memory include: S401, when the controller needs to start the refresh process of the current memory cell, it selects the corresponding refresh process for the current memory cell based on the currently held operating voltage.
[0035] S402, the controller refreshes the current storage unit according to the selected refresh procedure.
[0036] S403, the controller maintains the operating voltage at the end of the refresh process when the current memory cell refresh process ends.
[0037] In this embodiment, when the current memory cell is the first memory cell, the currently held operating voltage is the default voltage; when the current memory cell is one of the remaining memory cells after the first memory cell, the currently held operating voltage is the operating voltage at the end of the refresh process of the previous memory cell. The operating voltage value includes the lower limit voltage and the upper limit voltage of the refresh determination voltage range. During the refresh process, when the currently held operating voltage is the lower limit voltage, the value of the current memory cell is first read using the lower limit voltage, and then subsequent corresponding steps are executed based on the value read result; when the currently held operating voltage is the upper limit voltage, the value of the current memory cell is first read using the upper limit voltage, and then subsequent corresponding steps are executed based on the value read result.
[0038] In this embodiment, the default voltage refers to the operating voltage initially maintained by the circuit when the first memory cell initiates the refresh process. The value of the default voltage must be strictly limited to the two boundary values of the refresh determination voltage range; that is, the default voltage can only be selected from the lower limit voltage or the upper limit voltage of the refresh determination voltage range.
[0039] The refresh method for non-volatile memory provided in this disclosure pre-configures a refresh determination voltage range for determining whether a memory cell needs to be refreshed. The lower and upper limits of the refresh determination voltage range are used as the operating voltages for reading the values of the memory cells. When a memory cell needs to be refreshed, a corresponding refresh process is selected for the current memory cell based on the operating voltage at the end of the previous memory cell refresh. This currently maintained operating voltage is used as the operating voltage for the first reading of the current memory cell's value in that refresh process. Specifically, if the latest operating voltage after the previous memory cell refresh is the lower limit voltage, the current memory cell's value is read for the first time using this lower limit voltage; if it is the upper limit voltage, the current memory cell's value is read for the first time using this upper limit voltage. This design breaks through the fixed execution mode of "forcing the use of a low voltage (lower limit voltage) as the first reading voltage in the memory cell refresh process," directly reducing meaningless voltage switching steps and avoiding the extra time required for charge charging / discharging and timing stability during voltage switching, thereby shortening the overall refresh operation time. Meanwhile, by selecting a suitable refresh process for the current unit based on the latest operating voltage at the end of the previous unit, the refresh operation of the current unit can be completed efficiently, further shortening the overall refresh time.
[0040] In some embodiments, refreshing the current storage cell according to the selected refresh process includes: when the currently maintained operating voltage is the lower limit voltage, reading the value of the current storage cell using the lower limit voltage; if the value of the current storage cell read using the lower limit voltage is 1, determining that the current storage cell has no refresh requirement, and ending the refresh process of the current storage cell; if the value of the current storage cell read using the lower limit voltage is 0, boosting the operating voltage from the lower limit voltage to the upper limit voltage, and reading the value of the current storage cell using the upper limit voltage; and continuing to execute the refresh process based on the value of the current storage cell read using the upper limit voltage.
[0041] The lower limit voltage of the refresh determination voltage range is used as the operating voltage for the first reading of the current memory cell's value. If the read value is 1, it can be directly determined that the current memory cell has no refresh requirement and the process ends. This design can quickly filter out memory cells with a threshold voltage lower than the lower limit voltage, avoiding redundant steps such as subsequent boosting and secondary reading for these cells, directly shortening the average refresh time per cell. The boosting operation is only performed when the initial low-voltage read value is 0 (there is a possibility of a refresh requirement), and the upper limit voltage obtained after boosting is used to continue reading the value of the current memory cell to determine whether the current memory cell has a refresh requirement again. The above scheme significantly reduces the number of meaningless voltage switching operations, avoids the extra time required for charge charging and discharging and timing stabilization during voltage switching, and effectively improves the overall refresh efficiency.
[0042] In some embodiments, refreshing the current storage cell according to the selected refresh process includes: when the currently maintained operating voltage is the upper limit voltage, reading the value of the current storage cell using the upper limit voltage; if the value of the current storage cell read using the upper limit voltage is 0, determining that the current storage cell has no refresh requirement, and ending the refresh process of the current storage cell; if the value of the current storage cell read using the upper limit voltage is 1, reducing the operating voltage from the upper limit voltage to the lower limit voltage, and reading the value of the current storage cell using the lower limit voltage; and continuing to execute the refresh process based on the value of the current storage cell read using the lower limit voltage.
[0043] The upper limit of the refresh determination voltage range is used as the operating voltage for the first reading of the current memory cell's value. If the read value is 0, it can be directly determined that the current memory cell has no refresh requirement and the process ends. This design can quickly filter out memory cells with a threshold voltage higher than the upper limit voltage, avoiding redundant steps such as subsequent voltage boosting and secondary reading for these cells, directly shortening the average refresh time of a single cell. A voltage reduction operation is only performed when the initial low-voltage read value is 1 (indicating a possible refresh requirement), and the lower limit voltage obtained after the voltage reduction is used to continue reading the value of the current memory cell to re-determine whether the current memory cell has a refresh requirement. The above scheme significantly reduces the number of meaningless voltage switching operations, avoids the extra time required for charge charging and discharging and timing stabilization during voltage switching, and effectively improves the overall refresh efficiency.
[0044] like Figure 5 As shown in the embodiments of this disclosure, another method for refreshing non-volatile memory is provided. The method for refreshing non-volatile memory includes: S501: When the controller needs to start the refresh process of the current memory cell, it selects the corresponding refresh process for the current memory cell based on the currently held operating voltage.
[0045] When the currently maintained operating voltage is the lower limit voltage, the first type of refresh procedure is executed, which includes steps S502 to 505; when the currently maintained operating voltage is the upper limit voltage, the second type of refresh procedure is executed, which includes steps S506 to 509.
[0046] S502, the controller uses the lower limit voltage to read the value of the current storage cell.
[0047] In this embodiment of the disclosure, the value of the current storage cell read for the first time using the lower limit voltage is saved to the first register.
[0048] S503: If the value of the current storage cell read by the controller using the lower limit voltage is 1, it determines that there is no need to refresh the current storage cell and ends the refresh process of the current storage cell.
[0049] Understandably, in this case, when it is necessary to start the refresh process of the next memory cell, the lower limit voltage is the operating voltage for the first reading of the memory cell value in the refresh process of the next memory cell.
[0050] S504: When the value of the current memory cell read by the controller using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the upper limit voltage, and the value of the current memory cell is read using the upper limit voltage.
[0051] In this embodiment of the disclosure, the value of the current storage cell read from the upper limit voltage during the second use is saved to the second register.
[0052] S505, the controller continues to execute the refresh process based on the value of the current memory cell read using the upper limit voltage.
[0053] S506, the controller uses the upper limit voltage to read the value of the current storage cell.
[0054] In this embodiment of the disclosure, the value of the current storage cell read for the first time using the upper limit voltage is saved to the first register.
[0055] S507: If the value of the current storage cell read by the controller using the upper limit voltage is 0, it determines that there is no need to refresh the current storage cell and ends the refresh process of the current storage cell.
[0056] Understandably, in this case, when it is necessary to start the refresh process of the next storage cell, the upper limit voltage is the operating voltage for the first reading of the storage cell value in the refresh process of the next storage cell.
[0057] S508: When the value of the current memory cell read from the upper limit voltage is 1, the controller reduces the operating voltage from the upper limit voltage to the lower limit voltage and reads the value of the current memory cell using the lower limit voltage.
[0058] In this embodiment of the disclosure, the value of the current storage cell read by the lower limit voltage is saved to the second register.
[0059] S509, the controller continues to execute the refresh process based on the value of the current memory cell read using the lower limit voltage.
[0060] S510: When the refresh process of the current memory cell ends, the controller maintains the operating voltage at the end of the refresh process.
[0061] In some embodiments, the refresh process continues based on the value of the current storage cell read using the upper limit voltage, including: if the value of the current storage cell read using the upper limit voltage is 0, determining that the current storage cell has no refresh requirement and ending the refresh process of the current storage cell; if the value of the current storage cell read using the upper limit voltage is 1, boosting the operating voltage from the upper limit voltage to the refresh voltage and refreshing the current storage cell using the refresh voltage.
[0062] By using a tiered judgment mechanism that reads the lower voltage limit and the upper voltage limit, only storage cells that simultaneously meet the condition of "lower voltage limit reading is 0 and upper voltage limit reading is 1" will be judged as storage cells that need to be refreshed. This avoids erroneous refreshes of storage cells with threshold voltage higher than upper voltage, improves refresh efficiency, ensures the accuracy of refresh operations, and prevents erroneous operations from affecting the lifespan of storage cells and data stability.
[0063] In some embodiments, when the currently maintained operating voltage is the lower limit voltage, after refreshing the current memory cell using the refresh voltage, the method further includes: reducing the operating voltage from the refresh voltage to the lower limit voltage to end the refresh process of the current memory cell.
[0064] In some embodiments, based on the value of the current storage cell read using the lower limit voltage, the refresh process continues, including: if the value of the current storage cell read using the lower limit voltage is 1, determining that the current storage cell has no refresh requirement and ending the refresh process of the current storage cell; if the value of the current storage cell read using the lower limit voltage is 0, boosting the operating voltage from the lower limit voltage to the refresh voltage and using the refresh voltage to refresh the current storage cell.
[0065] By using a tiered judgment mechanism that reads the upper limit voltage and the lower limit voltage, only storage cells that simultaneously meet the condition of "upper limit voltage reading is 1" and "upper limit voltage reading is 0" will be judged as storage cells that need to be refreshed. This avoids erroneous refreshes of storage cells with threshold voltages higher than the upper limit voltage. While improving refresh efficiency, it also ensures the accuracy of refresh operations and prevents erroneous operations from affecting the lifespan of storage cells and data stability.
[0066] In some embodiments, when the value of the current memory cell read using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the refresh voltage, and the current memory cell is refreshed using the refresh voltage. This includes: when the value of the current memory cell read using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the upper limit voltage, and then the operating voltage is boosted from the upper limit voltage to the refresh voltage, and the current memory cell is refreshed using the refresh voltage.
[0067] The aforementioned graded voltage boosting method, which first boosts to the upper limit voltage and then to the refresh voltage, significantly reduces the magnitude of a single voltage jump compared to the direct boosting from the lower limit voltage to the refresh voltage. This reduces the electrical stress impact of voltage surges on the gate oxide layer and charge storage structure of the memory cell, effectively preventing memory cell damage caused by high-voltage transients and extending the overall lifespan of the non-volatile memory. Furthermore, the boosting process to the upper limit voltage can be considered an intermediate state verification node. Combined with the read judgment logic described earlier, only cells to be refreshed that have been confirmed by both the lower and upper limit voltage reads will continue to be boosted to the refresh voltage for repair operation. This design eliminates misjudgments caused by voltage fluctuations and read interference, avoids invalid refreshes on non-target cells, and ensures the accuracy of the refresh operation.
[0068] In some embodiments, when the currently maintained operating voltage is the upper limit voltage, after refreshing the current memory cell using the refresh voltage, the method further includes: reducing the operating voltage from the refresh voltage to the lower limit voltage to end the refresh process of the current memory cell.
[0069] like Figure 6 As shown in the embodiments of this disclosure, another method for refreshing non-volatile memory is provided. The method for refreshing non-volatile memory includes: S601 When the controller needs to start the refresh process of the current memory cell, it selects the corresponding refresh process for the current memory cell based on the currently held operating voltage.
[0070] When the currently maintained operating voltage is the lower limit voltage, the first type of refresh procedure is executed, which includes steps S602 to 607; when the currently maintained operating voltage is the upper limit voltage, the second type of refresh procedure is executed, which includes steps S608 to 613.
[0071] S602, the controller uses the lower limit voltage to read the value of the current storage cell.
[0072] In this embodiment of the disclosure, the value of the current storage cell read for the first time using the lower limit voltage is saved to the first register.
[0073] S603: If the value of the current storage cell read by the controller using the lower limit voltage is 1, it determines that the current storage cell has no refresh requirement and ends the refresh process of the current storage cell.
[0074] Understandably, in this case, when it is necessary to start the refresh process of the next memory cell, the lower limit voltage is the operating voltage for the first reading of the memory cell value in the refresh process of the next memory cell.
[0075] S604: When the value of the current memory cell read by the controller using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the upper limit voltage, and the value of the current memory cell is read using the upper limit voltage.
[0076] In this embodiment of the disclosure, the value of the current storage cell read from the upper limit voltage during the second use is saved to the second register.
[0077] S605: If the value of the current storage cell read by the controller using the upper limit voltage is 0, it determines that there is no need to refresh the current storage cell and ends the refresh process of the current storage cell.
[0078] Understandably, in this case, when it is necessary to start the refresh process of the next storage cell, the upper limit voltage is the operating voltage for the first reading of the storage cell value in the refresh process of the next storage cell.
[0079] S606: When the value of the current memory cell read by the controller using the upper limit voltage is 1, the operating voltage is boosted from the upper limit voltage to the refresh voltage, and the refresh voltage is used to refresh the current memory cell.
[0080] S607, the controller reduces the operating voltage from the refresh voltage to the lower limit voltage, ending the refresh process of the current memory cell.
[0081] Understandably, in this case, when it is necessary to start the refresh process of the next memory cell, the lower limit voltage is the operating voltage for the first reading of the memory cell value in the refresh process of the next memory cell.
[0082] S608, the controller uses the upper limit voltage to read the value of the current memory cell.
[0083] In this embodiment of the disclosure, the value of the current storage cell read for the first time using the upper limit voltage is saved to the first register.
[0084] S609: If the value of the current storage cell read by the controller using the upper limit voltage is 0, it determines that there is no need to refresh the current storage cell and ends the refresh process of the current storage cell.
[0085] Understandably, in this case, when it is necessary to start the refresh process of the next storage cell, the upper limit voltage is the operating voltage for the first reading of the storage cell value in the refresh process of the next storage cell.
[0086] S610: When the value of the current memory cell read from the upper limit voltage is 1, the controller reduces the operating voltage from the upper limit voltage to the lower limit voltage and reads the value of the current memory cell using the lower limit voltage.
[0087] In this embodiment of the disclosure, the value of the current storage cell read by the lower limit voltage is saved to the second register.
[0088] S611, if the controller reads the value of the current storage cell as 1 using the lower limit voltage, it determines that the current storage cell has no refresh requirement and ends the refresh process of the current storage cell.
[0089] Understandably, in this case, when it is necessary to start the refresh process of the next memory cell, the lower limit voltage is the operating voltage for the first reading of the memory cell value in the refresh process of the next memory cell.
[0090] S612, when the value of the current memory cell read by the controller using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the refresh voltage, and the refresh voltage is used to refresh the current memory cell.
[0091] S613, the controller reduces the operating voltage from the refresh voltage to the lower limit voltage, ending the refresh process of the current memory cell.
[0092] Understandably, in this case, when it is necessary to start the refresh process of the next memory cell, the lower limit voltage is the operating voltage for the first reading of the memory cell value in the refresh process of the next memory cell.
[0093] S614, the controller maintains the operating voltage at the end of the refresh process when the current memory cell refresh process ends.
[0094] In this embodiment, the value of the first register and the second register can be used to determine whether the current storage cell requires a refresh. Specifically, if the operating voltage at the end of the previous storage cell refresh is the lower limit voltage, and the first register is 0 and the second register is 1, then the current storage cell requires a refresh; otherwise, the current storage cell does not require a refresh. If the operating voltage currently maintained after the previous storage cell refresh is the upper limit voltage, and the first register is 1 and the second register is 0, then the current storage cell requires a refresh; otherwise, the current storage cell does not require a refresh.
[0095] In some embodiments, when the operating voltage at the end of the previous memory cell refresh is the upper limit voltage, the value of the current memory cell read using the upper limit voltage and the inverse of the value of the current memory cell read using the lower limit voltage can be stored in the corresponding registers (the value rule is: the inverse of 1 is 0, and the inverse of 0 is 1). At this time, the refresh demand determination rule can be unified as the value of the first register being 0 and the value of the second register being 1. If this condition is met, it is determined that the current memory cell has a refresh demand; otherwise, it is determined that there is no refresh demand.
[0096] In some embodiments, during the refresh process selected for the current storage unit, the operating voltage is used to simultaneously read the values of a group of storage units, including the current storage unit. If the reading results indicate that none of the storage units in the group require a refresh, the refresh process for that group is skipped. This embodiment uses the method of simultaneously reading the values of a group of storage units with the operating voltage, merging the read operation that originally needed to be performed unit by unit into a single parallel read, directly reducing the total number of read operations. The batch read method can significantly improve the read throughput of storage units, and is especially suitable for refresh scenarios of large-scale storage arrays. If the batch read result shows that none of the storage units in the group require a refresh, all subsequent refresh processes such as boosting, bucking, and secondary reading for the entire group are skipped, avoiding redundant operations of performing the determination step for each unit in the group one by one. This design further compresses the processing cycle of units without refresh requirements.
[0097] In this embodiment, when the currently maintained operating voltage is the lower limit voltage, the values of a group of memory cells are read using the lower limit voltage. If all values of the group of memory cells read using the lower limit voltage are 1, it is determined that the group of memory cells has no refresh requirement, and the refresh process for that group of memory cells is skipped. If the values of the group of memory cells read using the lower limit voltage are not all 1, the operating voltage is increased from the lower limit voltage to the upper limit voltage, and the values of the group of memory cells are read using the upper limit voltage. If, when reading the values of the group of memory cells using the upper limit voltage, there is no instance where the lower limit voltage reads 0 and the upper limit voltage reads 1, it is determined that the current memory cell has no refresh requirement, and the refresh process for that group of memory cells is skipped.
[0098] In this embodiment, when the currently maintained operating voltage is the upper limit voltage, the values of a group of memory cells are read using the upper limit voltage. If all the values of the group of memory cells read using the upper limit voltage are 0, it is determined that the group of memory cells has no refresh requirement, and the refresh process for that group of memory cells is skipped. If the values of the group of memory cells read using the upper limit voltage are not all 0, the operating voltage is reduced from the upper limit voltage to the lower limit voltage, and the values of the group of memory cells are read using the lower limit voltage. If, when reading the values of the group of memory cells using the lower limit voltage, there is no instance where the upper limit voltage reads 1 and the lower limit voltage reads 0, it is determined that the current memory cell has no refresh requirement, and the refresh process for that group of memory cells is skipped.
[0099] The technical solutions of this disclosure can be embodied in the form of hardware products or design data. The hardware product can be a manufactured semiconductor chip, which includes the circuit and layout structure of a specific functional module capable of performing all or part of the steps of the methods described in this disclosure. The design data can be a complete set of electronic design data that can be used for semiconductor manufacturing, including but not limited to: register-transfer level hardware description language code, gate-level netlist after logic synthesis, placement and routing information during the physical design stage, and the final GDSII format layout file delivered for manufacturing.
[0100] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
[0101] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0102] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces. The indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0103] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the figures. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the figures, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer commands.
Claims
1. A refresh method for a non-volatile memory, characterized in that, Non-volatile memory comprises multiple memory cells, and refresh methods include: When it is necessary to start the refresh process of the current memory cell, the corresponding refresh process is selected for the current memory cell according to the currently held operating voltage. The operating voltage currently held by the circuit is the default voltage or the operating voltage at the end of the previous memory cell refresh process. The voltage value of the operating voltage includes the lower limit voltage and the upper limit voltage of the refresh determination voltage range. Refresh the current storage unit according to the selected refresh procedure; When the refresh process of the current storage cell ends, maintain the operating voltage at the end of the refresh process.
2. The refresh method for non-volatile memory according to claim 1, characterized in that, The current storage unit is refreshed according to the selected refresh procedure, including: When the current operating voltage is maintained at the lower limit voltage, the value of the current memory cell is read using the lower limit voltage; If the value of the current storage cell read using the lower limit voltage is 1, it is determined that the current storage cell has no refresh requirement, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the lower limit voltage is 0, the operating voltage is boosted from the lower limit voltage to the upper limit voltage, and the value of the current memory cell is read using the upper limit voltage. Based on the value of the current memory cell read using the upper limit voltage, the refresh process continues.
3. The refresh method for non-volatile memory according to claim 2, characterized in that, Based on the value of the current memory cell read using the upper limit voltage, the refresh process continues, including: If the value of the current storage cell read using the upper limit voltage is 0, it is determined that there is no need to refresh the current storage cell, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the upper limit voltage is 1, the operating voltage is boosted from the upper limit voltage to the refresh voltage, and the current memory cell is refreshed using the refresh voltage.
4. The refresh method for non-volatile memory according to claim 3, characterized in that, After refreshing the current memory cell using the refresh voltage, the process also includes: reducing the operating voltage from the refresh voltage to the lower limit voltage to end the refresh process of the current memory cell.
5. The refresh method for non-volatile memory according to claim 1, characterized in that, The current storage unit is refreshed according to the selected refresh procedure, including: When the current operating voltage is at the upper limit voltage, the value of the current memory cell is read using the upper limit voltage; If the value of the current storage cell read using the upper limit voltage is 0, it is determined that there is no need to refresh the current storage cell, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the upper limit voltage is 1, the operating voltage is reduced from the upper limit voltage to the lower limit voltage, and the value of the current memory cell is read using the lower limit voltage. Based on the value of the current memory cell read using the lower limit voltage, the refresh process continues.
6. The refresh method for non-volatile memory according to claim 5, characterized in that, Based on the value of the current memory cell read using the lower limit voltage, the refresh process continues, including: If the value of the current storage cell read using the lower limit voltage is 1, it is determined that the current storage cell has no refresh requirement, and the refresh process of the current storage cell ends. If the value of the current memory cell read using the lower limit voltage is 0, the operating voltage is increased from the lower limit voltage to the refresh voltage, and the current memory cell is refreshed using the refresh voltage.
7. The refresh method for non-volatile memory according to claim 6, characterized in that, After refreshing the current memory cell using the refresh voltage, the process also includes: reducing the operating voltage from the refresh voltage to the lower limit voltage to end the refresh process of the current memory cell.
8. The refresh method for non-volatile memory according to any one of claims 1 to 7, characterized in that, In the current storage cell selection process, the operating voltage is used to read the values of a group of storage cells, including the current storage cell. If it is determined from the value reading results that there is no need to refresh the storage cells in the group, the refresh process of the storage cells in the group is skipped.
9. A controller, characterized in that, The controller is configured to perform a refresh method for the non-volatile memory as described in any one of claims 1 to 8.
10. An electronic device, characterized in that, The electronic device includes a non-volatile memory and a controller as described in claim 9, the controller being communicatively connected to the non-volatile memory.