Medium-high voltage pldmos device and manufacturing method thereof

Abstract

This invention discloses a medium-high voltage PLDMOS device and its manufacturing method. The medium-high voltage PLDMOS device forms an active-end metal field plate. The source-end metal field plate is connected to the source metal and extends from above the source region to above the P-type drift region. The source-end metal field plate and the surface of the P-type drift region are isolated by a dielectric layer. This invention solves the technical problems in the prior art, such as increased surface electric field, uneven electric field distribution, and decreased reliability of the P-type drift region in medium-high voltage PLDMOS devices due to increased epitaxial layer thickness.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a medium- and high-voltage PLDMOS device and its manufacturing method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in power management integrated circuits due to their significant advantages, such as high voltage resistance, high current drive capability, low on-resistance, and compatibility with standard CMOS processes. Based on the type of conductive channel, LDMOS can be divided into two main categories: N-type LDMOS (NLDMOS) and P-type LDMOS (PLDMOS).

[0003] In high-voltage power device design, breakdown voltage (BV) and on-resistance (Ron) are two key electrical parameters for evaluating device performance. For medium- to high-voltage NLDMOS, it is typically necessary to optimize both breakdown voltage and on-resistance simultaneously to achieve the optimal balance (i.e., figure of merit, FOM). However, for medium- to high-voltage PLDMOS, since it is usually used as a high-side switch in circuit applications, the focus is primarily on its breakdown voltage, and the requirements for on-resistance are relatively relaxed. Therefore, in conventional process design, the doping concentration of the P-type drift region of medium- to high-voltage PLDMOS is usually designed to be lower (i.e., "lighter") than that of the N-type drift region of medium- to high-voltage NLDMOS, as long as the breakdown voltage requirement is met, without the need for additional metal field plates to optimize the surface electric field distribution.

[0004] As power management chips evolve towards higher voltage ratings, increasing the epitaxial layer thickness is typically required in process platforms to improve the longitudinal isolation breakdown voltage of medium- and high-voltage NLDMOS. However, in actual production, it has been found that increasing the epitaxial layer thickness has a significant negative impact on the reliability of medium- and high-voltage PLDMOS. The specific reasons are as follows: When the epitaxial layer thickness increases, the width of the deep N-well depletion region beneath the P-type drift region increases accordingly, while the depletion degree of the P-type drift region itself decreases relatively. This leads to an increase in the surface electric field intensity of the P-type drift region and exacerbates the non-uniformity of the electric field distribution. Consequently, early failures occur in reliability tests (such as high-voltage bias lifetime testing, ESD testing, etc.), failing to meet product reliability requirements.

[0005] In existing technologies, the optimization of the surface electric field of LDMOS devices mainly employs a drain-side metal field plate structure, which adjusts the surface electric field distribution through the coupling effect between the drain-side metal field plate and the drift region. However, the drain-side metal field plate primarily affects the electric field distribution near the drain, and its ability to adjust the electric field near the source, especially in the P-type drift region close to the source, is limited. Furthermore, existing technologies have not yet proposed an effective solution to the technical problem of "the decrease in PLDMOS reliability due to thickening the epitaxial layer".

[0006] Therefore, there is an urgent need for a medium-to-high voltage PLDMOS device structure suitable for thickened epitaxial process platforms, which can effectively reduce the peak electric field on the surface of the P-type drift region and improve the uniformity of electric field distribution while maintaining the breakdown voltage, thereby significantly improving device reliability. Summary of the Invention

[0007] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0008] The technical problem to be solved by the present invention is to provide a medium-voltage PLDMOS device and its manufacturing method that can solve the technical problems of increased surface electric field, uneven electric field distribution and decreased reliability of medium-voltage PLDMOS devices caused by increased epitaxial layer thickness.

[0009] To solve the above-mentioned technical problems, the present invention provides a medium-high voltage PLDMOS device, which forms an active end metal field plate 112-2; The source metal field plate 112-2 is connected to the source metal 112-1 and extends from above the source region to above the P-type drift region 106. The source metal field plate 112-2 and the surface of the P-type drift region 106 are isolated by a dielectric layer 113.

[0010] Preferably, the medium-high voltage PLDMOS device is further improved by including: P-type substrate 101; The N-type buried layer 102 is located above the P-type substrate 101; A P-type epitaxial layer is located above the N-type buried layer 102, and the thickness of the P-type epitaxial layer is greater than the thickness of the epitaxial layer of a conventional medium- and high-voltage PLDMOS. N-well deep well 103 is located within the P-type epitaxial layer; Shallow trench isolation region 104 is located within the P-type epitaxial layer; N-well 105 is located within the P-type epitaxial layer and is connected to the N-well deep well 103; P-type drift region 106 is located within the P-type epitaxial layer and is adjacent to N-well 105; Gate oxide layer 107 is located above the P-type epitaxial layer; The gate polysilicon 108 is located above the gate oxide layer 107; The N-type heavily doped region 109 is located within the N-well 105 and constitutes the source region of the device; The P-type heavily doped region 110 is located within the N-well 105 and is adjacent to the N-type heavily doped region 109; Contact hole 111 penetrates dielectric layer 113 to reach the surface of N-type heavily doped region 109, P-type heavily doped region 110 and P-type drift region 106; The metal lead 112 includes a source metal 112-1, a drain metal 112-3, and a gate metal 112-4, which are electrically connected to the corresponding regions through the contact hole 111.

[0011] Preferably, in a further improvement of the medium-high voltage PLDMOS device, the extension length of the source-end metal field plate 112-2 above the P-type drift region 106 is 0.5 μm to 3.0 μm.

[0012] Preferably, in a further improvement of the medium-high voltage PLDMOS device, the thickness of the dielectric layer 113 between the source metal field plate 112-2 and the surface of the P-type drift region 106 is 0.5 μm to 2.0 μm.

[0013] To address the aforementioned technical problems, this invention provides a method for manufacturing medium-to-high voltage PLDMOS devices, comprising the following steps: Step A: N-type impurities are implanted on the P-type substrate 101 to form an N-type buried layer 102, and then a P-type epitaxial layer is grown on the N-type buried layer 102; preferably, the thickness of the P-type epitaxial layer is greater than the epitaxial layer thickness of conventional medium and high voltage PLDMOS. Step B: N-type impurities are implanted into the P-type epitaxial layer to form an N-well deep well 103; Step C: Using active region photolithography, a shallow trench isolation region 104 is formed in the N-well deep well 103; Step D: Photolithography opens the well injection region, N-type impurities are injected into the N-well deep well 103 to form N-well 105, and P-type impurities are injected to form P-type drift region 106. P-type drift region 106 is adjacent to N-well 105. Step E: Fabricate gate oxide layer 107, deposit polysilicon on the gate oxide layer 107 and pattern it to form gate polysilicon 108; Step F involves source and drain ion implantation to form an N-type heavily doped region 109 and a P-type heavily doped region 110 within the N-well 105. The N-type heavily doped region 109 constitutes the source region. Step G: Deposit dielectric layer 113, etch to form contact holes 111, and the contact holes 111 are respectively connected to the surfaces of N-type heavily doped region 109, P-type heavily doped region 110 and P-type drift region 106; Step H: Deposit and pattern a metal layer to form a metal lead 112 and a source metal field plate 112-2. The source metal field plate 112-2 is connected to the source metal 112-1 and extends from above the source region to above the P-type drift region 106.

[0014] Preferably, in the further improved method for manufacturing medium- and high-voltage PLDMOS devices, in step H, the extension length of the source-end metal field plate 112-2 above the P-type drift region 106 is 0.5 μm to 3.0 μm.

[0015] Preferably, in the further improved method for manufacturing medium- and high-voltage PLDMOS devices, in step H, the thickness of the dielectric layer 113 between the source metal field plate 112-2 and the surface of the P-type drift region 106 is 0.5 μm to 2.0 μm.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: 1. This invention introduces a source-side metal field plate into a thickened epitaxial PLDMOS device. Utilizing the capacitive coupling effect between the source-side metal field plate and the P-type drift region, a charge with the opposite doping type to that of the drift region is induced on the surface of the P-type drift region, effectively modulating the potential distribution on the P-type drift region surface. Compared to the drain-side metal field plate, the source-side metal field plate, being directly connected to the source (usually grounded or at a low potential), can form a larger potential difference on the surface of the P-type drift region. This more effectively reduces the peak surface electric field near the source end of the P-type drift region, resulting in a more uniform electric field distribution and effectively solving the reliability degradation problem caused by thickened epitaxy.

[0017] 2. This invention primarily optimizes the lateral electric field distribution on the surface of the P-type drift region without significantly affecting the longitudinal breakdown characteristics of the device. Since the doping concentration and longitudinal structure of the P-type drift region remain unchanged, the device's breakdown voltage can be maintained at the design value without sacrificing its breakdown voltage performance, achieving a balance between improved reliability and maintained breakdown voltage.

[0018] 3. The source-side metal field plate of this invention can be formed simultaneously with conventional CMOS back-end metal interconnect processes without the need for additional photolithography or process steps. It only requires adjusting the mask design during metal layer patterning. Therefore, this invention is fully compatible with standard BCD (Bipolar-CMOS-DMOS) processes, does not increase manufacturing costs, and has good process feasibility and economic efficiency.

[0019] 4. This invention can flexibly adapt to the design requirements of PLDMOS devices with different withstand voltage levels (such as 40V, 60V, 80V, etc.) by adjusting parameters such as the extension length of the source metal field plate above the P-type drift region and the thickness of the dielectric layer, and has a wide range of process platform applicability. Attached Figure Description

[0020] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 This is a schematic cross-sectional view of the high-voltage PLDMOS device in this invention. Figure 2 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 1 .

[0022] Figure 3 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 2 .

[0023] Figure 4 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 3 .

[0024] Figure 5 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 4 .

[0025] Explanation of reference numerals in the attached figures: 101 is a P-type substrate; 102 is an N-type buried layer; 103 is an N-well deep well; 104 is the shallow trench isolation zone; 105 is an N-well; 106 is the P-type drift zone; 107 is the gate oxide layer; 108 is a gate polysilicon; 109 is the heavily doped N-type region; 110 is a heavily p-type doped region; 111 is a contact hole; 112 is a metal lead; 112-1 is the source metal; 112-2 is the source-end metal field plate; 113 is the dielectric layer. Detailed Implementation

[0026] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present invention is thorough and complete, and that the technical solutions of these exemplary embodiments are fully conveyed to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] First embodiment; This embodiment provides a medium-to-high voltage PLDMOS device, which is suitable for thickened epitaxial process platforms and can effectively solve the problem of decreased reliability caused by the increase of epitaxial layer thickness. Compared with the prior art, it adds an active end metal field plate 112-2. The source end metal field plate 112-2 is connected to the source metal 112-1 and extends from above the source region to above the P-type drift region 106. The source end metal field plate 112-2 and the surface of the P-type drift region 106 are isolated by a dielectric layer 113.

[0028] Accordingly, the main improvement of this invention lies in solving the technical problems existing in the prior art through the active end metal field plate. Therefore, other components of the medium and high voltage PLDMOS device are not the improvement points of this invention. In other words, this invention can be applied to any medium and high voltage PLDMOS device in the prior art.

[0029] The source metal field plate 112-2 is integrally formed with the source metal 112-1 and is electrically connected to the source potential. The source metal field plate 112-2 extends laterally from above the source region (N-type heavily doped region 109) to above the P-type drift region 106, with an extension length L of 0.5 μm to 3.0 μm, preferably 1.0 μm to 2.0 μm, above the P-type drift region 106. The source metal field plate 112-2 and the surface of the P-type drift region 106 are isolated by a dielectric layer 113, the thickness d of which is 0.5 μm to 2.0 μm. The source metal field plate 112-2 and the gate polysilicon 108 are also isolated by the dielectric layer 113, with a horizontal spacing S of 0.2 μm to 1.0 μm between them to avoid excessive parasitic capacitance between the source metal field plate 112-2 and the gate polysilicon 108 affecting the device's switching characteristics.

[0030] The source-side metal field plate 112-2 is connected to the source (low potential) and forms a metal-oxide-semiconductor (MOS) capacitor structure with the surface of the P-type drift region 106. When the device is in the off state and a high voltage is applied to the drain, the potential difference between the source-side metal field plate 112-2 and the P-type drift region 106 induces an electron accumulation layer on the surface of the P-type drift region 106. This electron layer effectively shields part of the electric field, reduces the peak surface electric field of the P-type drift region 106 near the source end, and makes the electric field distribution more uniform, thereby avoiding reliability failure caused by excessively high local electric fields.

[0031] For example, such as Figure 1 As shown, the medium-high voltage PLDMOS device includes: P-type substrate 101; The N-type buried layer 102 is located above the P-type substrate 101; A P-type epitaxial layer is located above the N-type buried layer 102, and the thickness of the P-type epitaxial layer is greater than the thickness of the epitaxial layer of a conventional medium- and high-voltage PLDMOS. N-well deep well 103 is located within the P-type epitaxial layer; Shallow trench isolation region 104 is located within the P-type epitaxial layer; N-well 105 is located within the P-type epitaxial layer and is connected to the N-well deep well 103; P-type drift region 106 is located within the P-type epitaxial layer and is adjacent to N-well 105; Gate oxide layer 107 is located above the P-type epitaxial layer; The gate polysilicon 108 is located above the gate oxide layer 107; The N-type heavily doped region 109 is located within the N-well 105 and constitutes the source region of the device; The P-type heavily doped region 110 is located within the N-well 105 and is adjacent to the N-type heavily doped region 109; Contact hole 111 penetrates dielectric layer 113 to reach the surface of N-type heavily doped region 109, P-type heavily doped region 110 and P-type drift region 106; The metal lead 112 includes a source metal 112-1, a drain metal 112-3, and a gate metal 112-4, which are electrically connected to the corresponding regions through the contact hole 111.

[0032] Furthermore, the aforementioned medium- and high-voltage PLDMOS device can be implemented using the following existing technologies: Substrate and Epitaxial Structure: The device uses a P-type substrate 101 as the mechanical support and starting material. An N-type buried layer 102 is formed on top of the P-type substrate 101, and the doping concentration of the N-type buried layer 102 is 1×10¹. 9 cm⁻³ to 5×10¹ 9 The thickness of the buried N-type layer is 1 μm to 3 μm. Above the buried N-type layer 102 is a P-type epitaxial layer with a thickness of 10 μm to 20 μm (significantly larger than the 5 μm to 8 μm epitaxial thickness of conventional medium- and high-voltage PLDMOS), and a resistivity of 5 Ω·cm to 20 Ω·cm. An N-well deep well 103 is formed within the P-type epitaxial layer. The bottom of the N-well deep well 103 contacts the buried N-type layer 102, and the top is 2 μm to 5 μm away from the epitaxial surface. The doping concentration is 1 × 10¹. 6 cm⁻³ to 5×10¹ 7 cm⁻³.

[0033] Active region isolation: A shallow trench isolation region 104 is formed in the P-type epitaxial layer. The shallow trench isolation region 104 is arranged around the active region and has a depth of 0.3μm to 0.6μm to achieve electrical isolation between devices.

[0034] Well and Drift Regions: An N-well 105 and a P-type drift region 106 are formed within the P-type epitaxial layer. The N-well 105 is located at the device source end and is connected to the N-well deep well 103, with a doping concentration of 5 × 10¹. 6 cm⁻³ to 2×10¹ 7 The junction depth is 3 μm to 6 μm, with a diameter of cm⁻³. The P-type drift region 106 is located at the device drain, adjacent to the N-well 105, with a lateral extension length of 5 μm to 15 μm and a doping concentration of 1 × 10¹⁻⁶. 6 cm⁻³ to 5×10¹ 7 The junction depth is 0.5 μm to 2 μm. The lateral boundary between the P-type drift region 106 and the N-well 105 is located below the gate polysilicon 108, forming a lateral channel.

[0035] Gate structure: A gate oxide layer 107 is grown above the P-type epitaxial layer, and the thickness of the gate oxide layer 107 is 15nm to 50nm. A gate polysilicon 108 is deposited above the gate oxide layer 107, and the thickness of the gate polysilicon 108 is 0.2μm to 0.5μm. Low resistivity is achieved by heavy doping with N-type impurities (such as phosphorus or arsenic).

[0036] Source / drain regions: An N-type heavily doped region 109 and a P-type heavily doped region 110 are formed within the N-well 105. The N-type heavily doped region 109 constitutes the source region of the device, with a doping concentration of 1 × 10². 0 cm⁻³ to 5×10² 0 The junction depth is 0.1 μm to 0.3 μm, with a diameter of cm⁻³. The heavily p-doped region 110 and the heavily n-doped region 109 are adjacent, forming a substrate contact region to provide bulk region pull-out. The doping concentration is 1 × 10² cm⁻³. 0 cm⁻³ to 5×10² 0 cm⁻³. An N-type heavily doped drain region is formed within the P-type drift region 106, with a doping concentration comparable to that of the source region.

[0037] Metal interconnects and source-side metal field plates: A dielectric layer 113 (typically borosilicate glass BPSG, with a thickness of 0.5 μm to 1.5 μm) is deposited on the device surface. Contact holes 111 are etched in the dielectric layer 113, exposing the surfaces of the heavily doped N-type region 109, the heavily doped P-type region 110, and the P-type drift region 106, respectively. A metal layer (typically aluminum or an aluminum-copper alloy, with a thickness of 0.5 μm to 2 μm) is deposited and patterned on top of the dielectric layer 113 to form metal leads 112.

[0038] Second embodiment; This invention provides a method for manufacturing medium- and high-voltage PLDMOS devices, with reference to... Figures 2-5 As shown, it includes the following steps: Step A: N-type impurities are implanted on the P-type substrate 101 to form an N-type buried layer 102, and then a P-type epitaxial layer is grown on the N-type buried layer 102; preferably, the thickness of the P-type epitaxial layer is greater than the epitaxial layer thickness of conventional medium and high voltage PLDMOS. More specifically, N-type impurities such as antimony or arsenic are implanted onto the surface of the P-type substrate 101 using an ion implantation process, followed by annealing and bonding to form an N-type buried layer 102. Subsequently, a P-type epitaxial layer is epitaxially grown on top of the N-type buried layer 102. Step B: N-type impurities are implanted into the P-type epitaxial layer to form an N-well deep well 103; More specifically, N-type impurities (such as phosphorus) are implanted into the surface of the P-type epitaxial layer, and then high-temperature push-junction is performed to form an N-well deep well 103; Step C: Using active region photolithography, a shallow trench isolation region 104 is formed in the N-well deep well 103; Active region pattern is defined using active region photolithography, and trenches are etched in the P-type epitaxial layer using dry etching. Then, silicon dioxide is deposited to fill the trenches and chemical mechanical polishing is performed to planarize them, forming shallow trench isolation region 104. Step D: Photolithography opens the well injection region, N-type impurities are injected into the N-well deep well 103 to form N-well 105, and P-type impurities are injected to form P-type drift region 106. P-type drift region 106 is adjacent to N-well 105. More specifically, photolithography opens the N-well implantation region and implants N-type impurities (such as phosphorus) to form N-well 105; photolithography opens the P-type drift region implantation region and implants P-type impurities (such as boron) to form P-type drift region 106; N-well 105 is connected to N-well deep well 103, and P-type drift region 106 is adjacent to N-well 105. Step E: Fabricate gate oxide layer 107, deposit polysilicon on the gate oxide layer 107 and pattern it to form gate polysilicon 108; More specifically, a gate oxide layer 107 is grown by thermal oxidation at an oxidation temperature of 800°C to 950°C. Subsequently, polysilicon is deposited by low-pressure chemical vapor deposition (LPCVD) to a thickness of [thickness missing], and then N-type heavy doping (diffusion or ion implantation) is performed on the polysilicon. Finally, it is patterned by photolithography and dry etching to form the gate polysilicon 108. Step F involves source and drain ion implantation to form an N-type heavily doped region 109 and a P-type heavily doped region 110 within the N-well 105. The N-type heavily doped region 109 constitutes the source region. More specifically, using photoresist masking, N-type source / drain ion implantation (such as arsenic or phosphorus) is performed to form an N-type heavily doped region 109 (source region) in the N-well 105 and an N-type heavily doped drain region in the P-type drift region 106; P-type ion implantation (such as boron or BF2) is performed to form a P-type heavily doped region 110 (substrate contact region) in the N-well 105.

[0039] Step G: Deposit dielectric layer 113, etch to form contact holes 111, and the contact holes 111 are respectively connected to the surfaces of N-type heavily doped region 109, P-type heavily doped region 110 and P-type drift region 106; More specifically, a dielectric layer 113 (such as BPSG) is deposited and planarized by reflow. Using a contact hole photolithography process, the dielectric layer 113 is dry-etched to form contact holes 111, which expose the surfaces of the N-type heavily doped region 109, the P-type heavily doped region 110, and the P-type drift region 106, respectively.

[0040] Step H: Deposit and pattern a metal layer to form a metal lead 112 and a source metal field plate 112-2. The source metal field plate 112-2 is connected to the source metal 112-1 and extends from above the source region to above the P-type drift region 106.

[0041] More specifically, a metal layer (such as an Al-Si-Cu alloy) is sputtered and deposited, and a pattern is defined using a metal layer photolithography process. Metal leads 112 are then formed through dry or wet etching, including a source metal 112-1, a source-end metal field plate 112-2, a drain metal 112-3, and a gate metal 112-4. The source-end metal field plate 112-2 is electrically connected to the source metal 112-1, extending from above the source region to above the P-type drift region 106, with an extension length of 0.5 μm to 3.0 μm, thus completing the device fabrication.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0043] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A medium-to-high voltage PLDMOS device, characterized in that... , which forms an active end metal field plate (112-2). The source metal field plate (112-2) is connected to the source metal (112-1) and extends from above the source region to above the P-type drift region (106). The source metal field plate (112-2) and the surface of the P-type drift region (106) are isolated by a dielectric layer (113).

2. The medium-to-high voltage PLDMOS device as described in claim 1, characterized in that, It includes: P-type substrate (101); An N-type buried layer (102) is located above the P-type substrate (101); A P-type epitaxial layer is located above the N-type buried layer (102), and the thickness of the P-type epitaxial layer is greater than the thickness of the epitaxial layer of a conventional medium-voltage PLDMOS. The N-well deep well (103) is located within the P-type epitaxial layer; Shallow trench isolation region (104) is located within the P-type epitaxial layer; The N-well (105) is located within the P-type epitaxial layer and is connected to the N-well deep well (103); The P-type drift region (106) is located within the P-type epitaxial layer and is adjacent to the N-well (105); Gate oxide layer (107) is located above the P-type epitaxial layer; A gate polysilicon (108) is located above the gate oxide layer (107); The N-type heavily doped region (109) is located within the N-well (105) and constitutes the source region of the device; The P-type heavily doped region (110) is located within the N-well (105) and is adjacent to the N-type heavily doped region (109); The contact hole (111) penetrates the dielectric layer (113) and reaches the surface of the N-type heavily doped region (109), the P-type heavily doped region (110) and the P-type drift region (106); The metal leads (112), including source metal (112-1), drain metal (112-3) and gate metal (112-4), are electrically connected to the corresponding regions through the contact holes (111).

3. The medium-to-high voltage PLDMOS device as described in claim 1, characterized in that: The extension length of the source-end metal field plate (112-2) above the P-type drift region (106) is 0.5 μm to 3.0 μm.

4. The medium-to-high voltage PLDMOS device as described in claim 1, characterized in that: The thickness of the dielectric layer (113) between the source metal field plate (112-2) and the surface of the P-type drift region (106) is 0.5 μm to 2.0 μm.

5. A method for manufacturing a medium-to-high voltage PLDMOS device, characterized in that, Includes the following steps: Step A: An N-type impurity is implanted on a P-type substrate (101) to form an N-type buried layer (102), and then a P-type epitaxial layer is grown on the N-type buried layer (102); Step B: N-type impurities are implanted into the P-type epitaxial layer to form an N-well deep well (103). Step C: Using active region photolithography, a shallow trench isolation region (104) is formed in the N-well deep well (103). Step D: Photolithography opens the well injection region, N-type impurities are injected into the N-well deep well (103) to form an N-well (105), and P-type impurities are injected to form a P-type drift region (106). The P-type drift region (106) is adjacent to the N-well (105). Step E: Fabricate a gate oxide layer (107), deposit polysilicon on the gate oxide layer (107) and pattern it to form a gate polysilicon layer (108). Step F involves source and drain ion implantation to form an N-type heavily doped region (109) and a P-type heavily doped region (110) within the N-well (105). The N-type heavily doped region (109) constitutes the source region. Step G: Deposit dielectric layer (113), etch to form contact holes (111), and the contact holes (111) are connected to the surfaces of N-type heavily doped region (109), P-type heavily doped region (110) and P-type drift region (106), respectively; Step H, deposit a metal layer and pattern it to form a metal lead (112) and a source metal field plate (112-2). The source metal field plate (112-2) is connected to the source metal (112-1) and extends from above the source region to above the P-type drift region (106).

6. The method for manufacturing medium- and high-voltage PLDMOS devices as described in claim 5, characterized in that: In step H, the extension length of the source-end metal field plate (112-2) above the P-type drift region (106) is 0.5 μm to 3.0 μm.

7. The method for manufacturing medium- and high-voltage PLDMOS devices as described in claim 5, characterized in that: In step H, the thickness of the dielectric layer (113) between the source metal field plate (112-2) and the surface of the P-type drift region (106) is 0.5 μm to 2.0 μm.

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