A reset monitoring circuit based on bootstrap RC charging and discharging technology

Abstract

The application discloses a reset monitoring circuit based on bootstrap RC charging and discharging technology, and relates to the technical field of electronic circuit protection, which comprises a watchdog signal preprocessing branch, a bootstrap RC charging and discharging circuit and a power supply control branch. Invalid levels are filtered through the watchdog signal preprocessing branch, and only valid pulse edges are responded. The bootstrap RC charging and discharging circuit and a Schmidt trigger inverter are utilized to form a monitoring logic with a determined time constant. Finally, the on-off of a PMOS power supply switch is controlled through a driving branch. The core effect is that when a microcontroller fails to send a watchdog pulse within a set timeout period, the circuit will automatically cut off the power supply of the microcontroller, realize hard restart and completely eliminate abnormal states. After the discharging is completed, the circuit can automatically restore the power supply to restart the system. The circuit has the beneficial effects of complete reset, strong anti-interference, simple peripheral, adjustable parameters, manual control support and the like, and is suitable for embedded systems with high reliability requirements.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit protection technology, specifically a reset monitoring circuit based on bootstrap RC charging and discharging technology. Background Technology

[0002] In embedded systems, microcontrollers (MCUs) may freeze or crash due to electromagnetic interference, power fluctuations, or software malfunctions. To ensure system reliability, a watchdog circuit is typically required. There are two main traditional methods for implementing watchdogs:

[0003] Dedicated chip solutions, such as the MAX813L, offer high integration but are also costly and have a fixed reset threshold voltage, lacking flexibility.

[0004] Pure software solution: Consumes MCU resources and cannot recover when the MCU completely crashes.

[0005] However, these circuits typically have the following drawbacks:

[0006] The reset time constant is fixed and cannot be flexibly adjusted according to the needs of different systems. The lack of a reset pulse widening design means that an excessively narrow reset signal may cause the MCU to fail to reset reliably.

[0007] The RC parameters are greatly affected by ambient temperature, and drift with temperature may lead to false triggering or failure.

[0008] Therefore, it is of great significance to design a watchdog circuit that is low in cost, has an adjustable reset time, and provides a reliable reset signal. Summary of the Invention

[0009] The purpose of this invention is to provide a reset monitoring circuit based on bootstrap RC charging and discharging technology, and a watchdog circuit built based on capacitor charging and discharging and an inverted logic chip (NOT gate). This circuit has a simple structure, low cost, adjustable reset time, and sufficient reset signal pulse width, so as to solve the problems mentioned in the background art.

[0010] To achieve the above objectives, the present invention provides the following technical solution: a reset monitoring circuit based on bootstrap RC charging and discharging technology, comprising a dog-feeding signal preprocessing branch, a bootstrap RC charging and discharging circuit, and a power control branch:

[0011] The dog-feeding signal preprocessing branch is used to receive the dog-feeding pulse signal, which includes a first-stage NPN transistor Q1; the dog-feeding pulse signal is coupled to the base of the first-stage NPN transistor Q1 via a DC blocking capacitor C1, and the emitter of the first-stage NPN transistor Q1 is grounded.

[0012] A bootstrap RC charging and discharging circuit is used to construct timeout monitoring logic. It includes an inverter U1, a filter capacitor C2, and a feedback resistor R2. The collector of the first-stage NPN transistor Q1 is connected to the signal input terminal of the inverter U1. One end of the filter capacitor C2 is connected to the signal input terminal of the inverter U1, and the other end is grounded. The feedback resistor R2 is connected between the signal input terminal and the signal output terminal of the inverter U1. The output level of the inverter U1 is used to charge the filter capacitor C2 through the feedback resistor R2 to form a closed-loop bootstrap structure.

[0013] The drive and power control branch, used to perform power cut-off action, includes a second-stage NPN transistor Q3 and a PMOS transistor Q2; the signal output terminal of the inverter U1 is connected to the base of the second-stage NPN transistor Q3; the collector of the second-stage NPN transistor Q3 is connected to the gate of the PMOS transistor Q2; the source of the PMOS transistor Q2 is connected to the power supply VCC, and the drain is connected as the power output terminal to the power input terminal of the controlled load;

[0014] When the dog-feeding signal preprocessing branch does not receive the dog-feeding pulse signal within the predetermined time, the bootstrap RC charging and discharging circuit charges the filter capacitor C2 to the flip threshold through the feedback resistor R2, controls the inverter U1 to output a low level to turn off the second-stage NPN transistor Q3, and then drives the PMOS transistor Q2 to turn off to cut off the power supply to the controlled load, thereby realizing power-off reset.

[0015] Preferably, the inverter U1 is a Schmitt trigger inverter; by utilizing the input threshold hysteresis characteristic of the Schmitt trigger inverter, a high-level threshold VTH+ and a low-level threshold VTH- are set to suppress voltage jitter and external noise interference during the charging and discharging process of the filter capacitor C2, and to prevent the PMOS transistor Q2 from oscillating in the critical state.

[0016] As a preferred option, the drive and power control branch also includes a gate current-limiting resistor R5 and a gate-source protection diode D1; the gate current-limiting resistor R5 is connected in series between the collector of the second-stage NPN transistor Q3 and the gate of the PMOS transistor Q2 to limit the drive current; the gate-source protection diode D1 is a Zener diode, connected in parallel between the gate and source of the PMOS transistor Q2, with its cathode connected to the source and its anode connected to the gate, to clamp the gate-source voltage Vgs to prevent overvoltage breakdown.

[0017] As a priority, the timeout reset time T of the bootstrap RC charging and discharging circuit is adjustable, and its value is mainly determined by the resistance value of the feedback resistor R2 and the capacitance value of the filter capacitor C2. The value of the feedback resistor R2 ranges from 10kΩ to 100kΩ, and the value of the filter capacitor C2 ranges from 1nF to 10nF. The corresponding set timeout period range covers 20ms to 500ms to adapt to the startup and dog-feeding cycles of different embedded systems.

[0018] As a preferred feature, the capacitance value of the DC blocking capacitor C1 in the dog-feeding signal preprocessing branch is in the range of 100nF to 1μF; the pull-down resistor R1 is connected between the base of the first-stage NPN transistor Q1 and ground; through the cooperation of the DC blocking capacitor C1 and the pull-down resistor R1, the input continuous high-level or low-level abnormal signals are isolated, and only the edge signal of the dog-feeding pulse is allowed to trigger the first-stage NPN transistor Q1 to conduct.

[0019] As a preferred option, a manual control interface is also included, which includes at least one of a programming mode selection switch S1 or a manual reset switch S2.

[0020] One end of the programming mode selection switch S1 is connected to the base of the first-stage NPN transistor Q1, and the other end is grounded. It is used to force the base level low when closed to disable the watchdog timer.

[0021] One end of the manual reset switch S2 is connected to the base of the second-stage NPN transistor Q3, and the other end is grounded. When the manual reset switch S2 is closed, the base potential of the second-stage NPN transistor Q3 is forcibly pulled low, causing the second-stage NPN transistor Q3 to be turned off, thereby controlling the PMOS transistor Q2 to be turned off to achieve manual power-off reset.

[0022] Preferably, the inverter U1 is selected from any one of SN74AHC1G14, 74LS14, or CD40106; the PMOS transistor Q2 is selected from AO3401 or other P-channel enhancement-type MOS transistors with a turn-on threshold voltage |VTH| less than the power supply voltage; the first-stage NPN transistor Q1 and the second-stage NPN transistor Q3 are both general-purpose small-signal NPN transistors, including the S9013 model.

[0023] Prioritized, under normal watchdog timer conditions: The watchdog pulse saturates and turns on the first-stage NPN transistor Q1, rapidly discharging the charge across the filter capacitor C2 to ground through the collector-emitter path of the first-stage NPN transistor Q1, keeping the input of the inverter U1 at a low level and the output at a high level, thereby keeping the PMOS transistor Q2 on.

[0024] Prioritized, in the timeout power-off state: the first-stage NPN transistor Q1 is turned off, and the power supply charges the filter capacitor C2 through the PMOS transistor Q2, the internal power supply pin of the inverter U1, and the feedback resistor R2; when the voltage of the filter capacitor C2 rises to the high-level threshold VTH+ of the Schmitt trigger inverter, the output of the inverter U1 flips to a low level, causing the second-stage NPN transistor Q3 to turn off, and the gate voltage of the PMOS transistor Q2 is pulled up or left floating to turn off, thus cutting off the load power supply.

[0025] Preferably, the circuit is suitable for embedded microcontroller systems with a supply voltage of 3.3V or 5V. The PMOS transistor Q2 acts as a high-side power switch to directly control the power input pin VCC_MCU of the microcontroller, thereby enabling a hard reboot of the microcontroller.

[0026] In summary, the beneficial effects of this invention are:

[0027] This invention achieves edge-sensitive triggering of the watchdog signal and high noise immunity timeout monitoring through the coordinated design of a bootstrap RC charging and discharging circuit and a Schmitt trigger inverter. It forcibly cuts off the microcontroller power supply (hard reset) when the system crashes, completely clearing the abnormal state and avoiding the residual risks of software reset. At the same time, it supports dynamic adjustment of the watchdog cycle (100ms~1s), 3.3V / 5V wide voltage compatibility, and manual reset / programming mode disabling function, which significantly improves the fault recovery reliability and operational robustness of embedded systems in complex environments. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a reset monitoring circuit based on bootstrap RC charging and discharging technology according to the present invention. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0031] To facilitate understanding of the present invention, a more complete description of the invention will be given below with reference to the accompanying drawings, which illustrate several embodiments of the invention. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the invention will be more thorough and complete.

[0032] All features disclosed in this specification, or steps in all methods or processes disclosed herein, may be combined in any way, except for mutually exclusive features and / or steps.

[0033] Any feature disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by other equivalent or similar features for a similar purpose, unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is merely one example of a series of equivalent or similar features.

[0034] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of at least two elements or the interaction relationship of at least two elements, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] Please see Figure 1 One embodiment of the present invention provides a reset monitoring circuit based on bootstrap RC charging and discharging technology, comprising a dog-feeding signal preprocessing branch, a bootstrap RC charging and discharging circuit, and a power control branch, specifically:

[0036] The dog-feed signal preprocessing branch is used to receive the dog-feed pulse signal, and includes a first-stage NPN transistor Q1. The dog-feed pulse signal is coupled to the base of the first-stage NPN transistor Q1 via a DC blocking capacitor C1. The emitter of the first-stage NPN transistor Q1 is grounded, and the capacitance of the DC blocking capacitor C1 ranges from 100nF to 1μF. A pull-down resistor R1 is connected between the base of the first-stage NPN transistor Q1 and ground. Through the cooperation of the DC blocking capacitor C1 and the pull-down resistor R1, the input continuous high-level or low-level abnormal signals are isolated, and only the edge signal of the dog-feed pulse is allowed to trigger the first-stage NPN transistor Q1 to conduct.

[0037] A bootstrap RC charging / discharging circuit is used to construct timeout monitoring logic. It includes an inverter U1, a filter capacitor C2, and a feedback resistor R2. The collector of the first-stage NPN transistor Q1 is connected to the signal input terminal of the inverter U1. One end of the filter capacitor C2 is connected to the signal input terminal of the inverter U1, and the other end is grounded. The feedback resistor R2 is connected between the signal input and signal output terminals of the inverter U1. The output level of the inverter U1 charges the filter capacitor C2 through the feedback resistor R2 to form a closed-loop bootstrap structure. It should be noted that the inverter U1 is a Schmitt trigger inverter. Utilizing the input threshold hysteresis characteristic of the Schmitt trigger inverter, a high-level threshold VTH+ and a low-level threshold VTH- are set to suppress voltage jitter and external noise interference during the charging and discharging process of the filter capacitor C2, preventing oscillation of the PMOS transistor Q2 in a critical state.

[0038] It is worth mentioning that the bootstrap RC charge and discharge cycle: According to the formula τ=R2×C2 (time constant), combined with the threshold characteristics of the Schmitt inverter, the timeout period T≈2.2τ=2.2×47kΩ×4.7nF≈480ms. The dog feeding cycle requirements of different systems can be adapted by adjusting R2 (10kΩ~100kΩ) or C2 (1nF~10nF).

[0039] The drive and power control branch, used to perform power cut-off actions, includes a second-stage NPN transistor Q3 and a PMOS transistor Q2. The signal output terminal of the inverter U1 is connected to the base of the second-stage NPN transistor Q3, and the collector of the second-stage NPN transistor Q3 is connected to the gate of the PMOS transistor Q2. The source of the PMOS transistor Q2 is connected to the power supply VCC, and the drain serves as the power output terminal connected to the power input terminal of the controlled load. It should be noted that it also includes a gate current-limiting resistor R5 and a gate-source protection diode D1. The gate current-limiting resistor R5 is connected in series between the collector of the second-stage NPN transistor Q3 and the gate of the PMOS transistor Q2 to limit the drive current. The gate-source protection diode D1 is a Zener diode, connected in parallel between the gate and source of the PMOS transistor Q2, with its cathode connected to the source and its anode connected to the gate, to clamp the gate-source voltage Vgs to prevent overvoltage breakdown.

[0040] The inverter U1 is selected from any one of SN74AHC1G14, 74LS14, or CD40106; the PMOS transistor Q2 is selected from AO3401 or other P-channel enhancement-type MOS transistors with a turn-on threshold voltage |VTH| less than the power supply voltage; the first-stage NPN transistor Q1 and the second-stage NPN transistor Q3 are both general-purpose small-signal NPN transistors, including the S9013 model, while the driving conditions for the PMOS transistor Q2 are: the turn-on condition for AO3401 is VS-G≥|VTH| (≥1V), and when the second-stage NPN transistor is turned on, the gate is pulled low to near ground potential, VS-G=VCC≥3.3V, which meets the reliable turn-on requirements.

[0041] Gate current limiting resistor R5 selection: Based on the β value of S9013 (typical value 100), base current IB≈(Uo1-VBE) / R5, inverter output Uo1≈3.3V, VBE≈0.7V, when R3=1kΩ, IB≈2.6mA, collector current IC≈β×IB=260mA, which is sufficient to drive the charging and discharging of the gate capacitor of PMOS transistor Q2.

[0042] When the dog-feeding signal preprocessing branch does not receive the dog-feeding pulse signal within the predetermined time, the bootstrap RC charging and discharging circuit charges the filter capacitor C2 to the flip threshold through the feedback resistor R2, controls the inverter U1 to output a low level to turn off the second-stage NPN transistor Q3, and then drives the PMOS transistor Q2 to turn off to cut off the power supply to the controlled load, thereby realizing power-off reset.

[0043] The circuit is suitable for embedded microcontroller systems with a power supply voltage of 3.3V or 5V. The PMOS transistor Q2 acts as a high-side power switch to directly control the power input pin VCC_MCU of the microcontroller, thereby enabling a hard reboot of the microcontroller.

[0044] Based on circuit parameters and device characteristics, the complete workflow is as follows, covering four stages: power-on initialization, normal watchdog timer feeding, timeout power-off reset, and reset recovery.

[0045] 1. Power-on initialization phase (system startup)

[0046] After the system is powered on, VCC charges the filter capacitor C2 through the feedback resistor R2. Initially, the voltage of C2 is 0V, and the input terminal (IN1) of the inverter U1 is at a low level.

[0047] Due to the Schmitt triggering characteristic of SN74AHC1G14, the output terminal (OUT1) is high when the input is low, and this high level is applied to the base of the second-stage NPN transistor Q3.

[0048] After the base of Q3 is energized, it becomes saturated and conducts. The collector potential is close to the ground potential (≈0V). The gate (G) of PMOS transistor Q2 is pulled low, satisfying the conduction condition VS-G=VCC-0V≥|VTH|, and Q2 is reliably turned on.

[0049] The power supply VCC is output to the load (MCU) through Q2. The load is powered on and initialized, and the entire system enters the standby state. During this stage, C2 continuously charges to near VCC, with a charging time of approximately 3τ≈690ms, ensuring that the circuit stabilizes before entering normal operation.

[0050] 2. Normal dog feeding phase (system running stably)

[0051] After the load MCU is initialized, it enters normal working state and outputs a watchdog pulse signal (active high, pulse width 10ms) through the GPIO port according to the preset period (T_feeddog = 200ms, less than the timeout period of 480ms).

[0052] The dog-feeding pulse is coupled to the base of the first-stage NPN transistor Q1 via the DC blocking capacitor C1. At the same time, the pull-down resistor R1 pulls the base of Q1 low during the pulse gap to prevent false triggering.

[0053] When the dog feed pulse arrives, the base of Q1 receives a forward bias voltage and is saturated and turned on. Its collector potential is close to the ground potential, which causes the input terminal (IN1) of the inverter U1 to be pulled low.

[0054] IN1 low level triggers U1 output (OUT1) high level, Q3 remains on, PMOS transistor Q2 continues to conduct, and the load power supply is stably powered; at the same time, C2 discharges quickly to near 0V through the conducting Q1, completing one dog feed action.

[0055] After the watchdog pulse ends, the base of Q1 is de-energized and cut off. VCC charges C2 again through R2. However, since the next watchdog pulse will arrive within 200ms, the voltage of C2 can never rise to the high-level threshold of SN74AHC1G14 (VTH+≈2V@5V power supply). The circuit maintains a stable state with Q3 and Q2 on, and the load continues to work normally.

[0056] 3. Timeout power-off reset phase (system malfunction)

[0057] When the MCU crashes due to program crashes, electromagnetic interference, or hardware failure, it stops outputting the watchdog pulse, and the first-stage NPN transistor Q1 remains in the off state.

[0058] After Q1 is cut off, VCC continuously charges C2 through R2, and the voltage of C2 rises exponentially. When the voltage reaches the Schmitt high-level threshold VTH+ of SN74AHC1G14, a high level is detected at the input of U1, and the output (OUT1) flips to a low level.

[0059] When the base of Q3 loses its high-level drive and is turned off, its collector potential is pulled up to near VCC by the parasitic resistance (or additional pull-up resistor) of the PMOS gate. At this time, the gate (G) and source (S) potentials of PMOS transistor Q2 are nearly equal (VS-G≈0V<|VTH|), and Q2 is reliably turned off.

[0060] After Q2 is cut off, the power supply to the load (MCU) is completely cut off, realizing "power-off reset" (unlike traditional reset signal triggering, hard power cut-off can completely clear the abnormal state of the MCU, making the reset more reliable).

[0061] 4. Reset and recovery phase (system restart)

[0062] After PMOS transistor Q2 is turned off, the load MCU is powered off, and all abnormal states are cleared; at the same time, the input of inverter U1 remains at a high level, the output remains at a low level, and Q3 remains turned off.

[0063] If manual recovery is required, or automatic recovery can be achieved by C2 discharging the output of U1 through R2 in reverse, the output will be high when the voltage of C2 is lower than the low value of the input of U1. By restarting the power supply or by an external trigger signal, the circuit repeats the "power-on initialization phase" process: VCC recharges C2 through R2, the output of U1 flips, Q3 turns on, Q2 turns on, the load is powered on again, the MCU is reinitialized and resumes normal watchdog feeding, and the system returns to a stable operating state.

[0064] Meanwhile, the circuit supports disabling the watchdog timer and also includes a manual control interface, which includes at least one of a programming mode selection switch S1 or a manual reset switch S2.

[0065] One end of the programming mode selection switch S1 is connected to the base of the first-stage NPN transistor Q1, and the other end is grounded. It is used to force the base level low when closed to disable the watchdog timer.

[0066] One end of the manual reset switch S2 is connected to the base of the second-stage NPN transistor Q3, and the other end is grounded. When the manual reset switch S2 is closed, the base potential of the second-stage NPN transistor Q3 is forcibly pulled low, causing the second-stage NPN transistor Q3 to be turned off, thereby controlling the PMOS transistor Q2 to be turned off to achieve manual power-off reset.

[0067] In summary, this reset monitoring circuit, through the collaborative design of a bootstrap RC charging and discharging circuit and a Schmitt trigger inverter, achieves edge-sensitive triggering of the watchdog signal and high noise immunity timeout monitoring. It forcibly cuts off the microcontroller power supply (hard reset) when the system crashes, completely clearing abnormal states and avoiding the residual risks of software reset. Simultaneously, it supports dynamic adjustment of the watchdog cycle (100ms to 1s), 3.3V / 5V wide voltage compatibility, and a manual reset / programming mode disabling function, significantly improving the reliability and robustness of the embedded system in fault recovery under complex environments.

[0068] The Schmitt triggering characteristic (threshold hysteresis voltage ≈ 0.5V) of SN74AHC1G14, along with the filtering effect of C1 and C2, can suppress spike noise of ≤50ns and achieve a false triggering rate of ≤0.1%.

[0069] After the timeout, the total response time from charging from C2 to the threshold to PMOS cutoff is ≤20μs, and the power-off reset is rapid, avoiding abnormal operation of the load for a long time.

[0070] The two-stage NPN cascaded drive design makes the PMOS on / off state switching more reliable, and it can withstand 1000 consecutive power-on-dog-timeout reset cycles without failure, meeting the long-term stable operation requirements of embedded systems.

[0071] The above description is merely a specific embodiment of the invention, but the scope of protection of the invention is not limited thereto. Any variations or substitutions conceived without inventive effort should be included within the scope of protection of the invention. Therefore, the scope of protection of the invention should be determined by the scope defined in the claims.

Claims

1. A reset monitoring circuit based on bootstrap RC charging and discharging technology, comprising a dog-feeding signal preprocessing branch, a bootstrap RC charging and discharging circuit, and a power control branch, characterized in that: The dog-feeding signal preprocessing branch is used to receive the dog-feeding pulse signal, which includes a first-stage NPN transistor (Q1); the dog-feeding pulse signal is coupled to the base of the first-stage NPN transistor (Q1) via a DC blocking capacitor (C1), and the emitter of the first-stage NPN transistor (Q1) is grounded; The bootstrap RC charging and discharging circuit is used to construct timeout monitoring logic. It includes an inverter (U1), a filter capacitor (C2), and a feedback resistor (R2). The output level of the inverter (U1) is used to charge the filter capacitor (C2) through the feedback resistor (R2) to form a closed-loop bootstrap structure. The power control branch is used to perform the power cut-off action, and it includes a second-stage NPN transistor (Q3) and a PMOS transistor (Q2). When the dog-feeding signal preprocessing branch does not receive the dog-feeding pulse signal within the predetermined time, the bootstrap RC charging and discharging circuit charges the filter capacitor (C2) to the flip threshold through the feedback resistor (R2), controls the inverter (U1) to output a low level, turns off the second-stage NPN transistor (Q3), and then drives the PMOS transistor (Q2) to turn off to cut off the power supply to the controlled load, thereby realizing power-off reset.

2. The reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 1, characterized in that: The collector of the first-stage NPN transistor (Q1) is connected to the signal input terminal of the inverter (U1). One end of the filter capacitor (C2) is connected to the signal input terminal of the inverter (U1), and the other end is grounded. The feedback resistor (R2) is connected between the signal input terminal and the signal output terminal of the inverter (U1).

3. The reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 2, characterized in that: The signal output terminal of the inverter (U1) is connected to the base of the second-stage NPN transistor (Q3); the collector of the second-stage NPN transistor (Q3) is connected to the gate of the PMOS transistor (Q2); the source of the PMOS transistor (Q2) is connected to the power supply (VCC), and the drain is connected to the power input terminal of the controlled load as the power output terminal.

4. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 3, characterized in that: The power control branch also includes a gate current-limiting resistor (R3) and a gate-source protection diode (D1). The gate current-limiting resistor (R3) is connected in series between the collector of the second-stage NPN transistor (Q3) and the gate of the PMOS transistor (Q2) to limit the drive current. The gate-source protection diode (D1) is a Zener diode, connected in parallel between the gate and source of the PMOS transistor (Q2), with its cathode connected to the source and its anode connected to the gate, to clamp the gate-source voltage to prevent overvoltage breakdown.

5. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 1, characterized in that: A pull-down resistor (R1) is connected between the base of the first-stage NPN transistor (Q1) and ground. Through the DC blocking capacitor (C1) and the pull-down resistor (R1), the input continuous high-level or low-level abnormal signals are isolated, and only the edge signal of the dog feed pulse is allowed to trigger the first-stage NPN transistor (Q1) to conduct.

6. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 1, characterized in that: It also includes a manual control interface, which includes at least one of a programming mode selection switch (S1) or a manual reset switch (S2); One end of the programming mode selection switch (S1) is connected to the base of the first-stage NPN transistor (Q1), and the other end is grounded. It is used to force the base level low when closed to disable the watchdog timer. One end of the manual reset switch (S2) is connected to the base of the second-stage NPN transistor (Q3), and the other end is grounded. When the manual reset switch (S2) is closed, the base potential of the second-stage NPN transistor (Q3) is forcibly pulled low, causing the second-stage NPN transistor (Q3) to be turned off, thereby controlling the PMOS transistor (Q2) to be turned off to achieve manual power-off reset.

7. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 6, characterized in that: In normal dog-feeding mode, the dog-feeding pulse causes the first-stage NPN transistor (Q1) to saturate and conduct, rapidly discharging the charge across the filter capacitor (C2) to ground through the collector-emitter path of the first-stage NPN transistor (Q1), keeping the input of the inverter (U1) at a low level and the output at a high level, thereby keeping the PMOS transistor (Q2) on.

8. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 4, characterized in that: The first-stage NPN transistor (Q1) is turned off, and the power supply charges the filter capacitor (C2) through the PMOS transistor (Q2), the internal power supply pin of the inverter (U1), and the feedback resistor (R2). When the voltage of the filter capacitor (C2) rises to the high-level threshold (VTH+) of the Schmitt trigger inverter, the output of the inverter (U1) flips to a low level, causing the second-stage NPN transistor (Q3) to turn off. The gate voltage of the PMOS transistor (Q2) is pulled up or left floating, thus turning it off and cutting off the load power supply.

9. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 2, characterized in that: The timeout reset time of the bootstrap RC charging and discharging circuit is adjustable, and its value is mainly determined by the resistance value of the feedback resistor (R2) and the capacitance value of the filter capacitor (C2). The value of the feedback resistor (R2) ranges from 10kΩ to 100kΩ, and the value of the filter capacitor (C2) ranges from 1nF to 10nF. The corresponding set timeout period range covers 20ms to 500ms to adapt to the startup and dog-feeding cycles of different embedded systems.

10. A reset monitoring circuit based on bootstrap RC charging and discharging technology according to claim 4, characterized in that: The inverter (U1) is a Schmitt trigger inverter. Utilizing the input threshold hysteresis characteristic of the Schmitt trigger inverter, a high-level threshold (VTH+) and a low-level threshold (VTH-) are set to suppress voltage jitter and external noise interference during the charging and discharging process of the filter capacitor (C2) and prevent the PMOS transistor (Q2) from oscillating in the critical state.

Images