Cis probe card space converter and method of making same
By filling the vias of the CIS probe card substrate with ceramic pillars and depositing a seed layer and an electroplated layer, the problems of photoresist chipping at the via edges and poor morphology of electroplated metal were solved, and the functional recovery of the substrate after the redistribution process was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MAXONE SEMICON CO LTD
- Filing Date
- 2026-02-28
- Publication Date
- 2026-06-16
Smart Images
Figure CN122218282A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of probe card technology, specifically a CIS probe card space converter and its preparation method. Background Technology
[0002] A CMOS image sensor (CIS) is a semiconductor device that converts optical images into digital signals. It features high integration, low power consumption, and fast data processing capabilities, and is widely used in consumer electronics, security monitoring, and autonomous driving. Before packaging, CIS wafers require performance testing using probe cards (hereinafter referred to as CIS probe cards).
[0003] CIS probe cards typically have large-diameter (around 10mm) through-holes on their substrates to allow light to pass through, such as the lens mounting holes on ceramic substrates described in Chinese Patent CN120915936A. When redistributing (or rewiring) these substrates with large-diameter through-holes, the following problems are prone to occur: 1. Photoresist chipping at the edges of the large-diameter through-holes; 2. Poor morphology of the PI layer at the edges of the through-holes, such as... Figure 1 3. Poor morphology of the electroplated metal at the edge of the through hole, such as... Figure 2 Since the substrate processing usually involves high temperature, acid and alkali environments, the above-mentioned problems will cause the substrate to be unable to withstand subsequent processing environments such as high temperature (280°C) and acid and alkali environments. Summary of the Invention
[0004] To overcome the deficiencies in the prior art, embodiments of the present invention provide a CIS probe card space converter and its preparation method, which are used to solve at least one of the above-mentioned problems.
[0005] This application discloses a method for preparing a CIS probe card space converter, comprising the following steps:
[0006] Step 1: Provide a substrate, the substrate including a first surface and a second surface disposed opposite to each other, and the substrate having a plurality of through holes that simultaneously penetrate the first surface and the second surface;
[0007] Step 2: Fill multiple fillers into multiple through holes of the substrate, wherein the filler includes a first end near the first surface of the substrate and a second end near the second surface of the substrate;
[0008] Step 3: Deposit a seed layer on the first surface of the substrate and the first ends of all fillers;
[0009] Step 4: Electroplating an electroplating layer on the seed layer corresponding to the first end of the filler, with at least a portion of the electroplating layer located within the through hole to fill the space between the filler and the inner wall of the through hole;
[0010] Step 5: Remove the seed layer on the substrate;
[0011] Step 6: Perform a redistribution process on the substrate obtained in Step 5, and then remove the filler in the area corresponding to the via on the substrate to restore the via and obtain the space converter.
[0012] Specifically, in step 2, before filling the through holes with filler, high-temperature tape is first applied to the second surface of the substrate, covering all through holes. After the filler is filled into the through holes, its second end is bonded to the high-temperature tape.
[0013] Specifically, the filler is a ceramic column.
[0014] Specifically, in step 3, the method for depositing the seed layer includes:
[0015] Step 31: Deposit a titanium layer with a thickness between 30 nm and 50 nm on the first surface of the substrate and the first ends of all fillers;
[0016] Step 32: Deposit a copper layer with a thickness between 900 nm and 1100 nm on the titanium layer.
[0017] Specifically, in step 4, before electroplating on the seed layer, photoresist is first applied to the first surface of the substrate, and the substrate around the via is not covered by the photoresist.
[0018] Specifically, the method of applying photoresist to the first surface of the substrate includes: spraying photoresist onto the first surface of the substrate and the first end of the filler, creating a corresponding pattern, then exposing the photoresist, followed by development, so that the first end of the filler and the area on the substrate around the via that needs to be electroplated are exposed.
[0019] Specifically, in step 5, after removing the seed layer on the substrate, the electroplated metal on the filler is also leveled to be flush with the first surface of the substrate.
[0020] Specifically, in step 6, before performing the redistribution process on the substrate, the substrate is first placed in a chemical plating solution to deposit an Au layer on the surface of the electroplated layer.
[0021] Specifically, in step 6, the method for removing the filler in the area corresponding to the via on the substrate includes: coating the surface of the space converter with photoresist, creating a corresponding pattern, then exposing the photoresist, followed by development to expose the area corresponding to the via, sequentially removing the Au layer electroplating layer and seed layer in the exposed area, then removing the filler from the via, and finally removing the photoresist on the surface of the space converter.
[0022] This application also discloses a CIS probe card space converter, which is prepared using the method described in this embodiment.
[0023] The present invention has at least the following beneficial effects:
[0024] The method for fabricating the CIS probe card spatial converter in this invention is as follows: First, the vias on the substrate are filled with filler material, so that the substrate is in a hole-free state to complete the redistribution process. In this way, problems such as photoresist edge chipping at the via edge, poor PI film morphology, and poor electroplated metal morphology will not occur. After the redistribution process is completed, the filler material and electroplated copper in the vias of the substrate are removed to restore the optical path function of the vias, so that the spatial converter can restore its original function.
[0025] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a morphology image of the PI film at the edge of the through-hole in the existing preparation method;
[0028] Figure 2 This is an electroplating morphology image of the edge of a through hole in an existing preparation method;
[0029] Figure 3 This is a flowchart of the preparation method in the embodiments of the present invention;
[0030] Figure 4 This is a flowchart of filling a through hole in a substrate according to an embodiment of the present invention;
[0031] Figure 5 This is a flowchart illustrating the process of releasing the filler material within the through-hole of the substrate in an embodiment of the present invention.
[0032] The reference numerals in the above figures are as follows: 1. Substrate; 2. Filler; 3. Photoresist; 4. Electroplated layer; 5. Au layer. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "fixing," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.
[0035] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "below," and "over" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0036] In the description of this embodiment, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this application.
[0037] Furthermore, the terms "first" and "second" are used only to distinguish between different terms in description and do not have any special meaning.
[0038] Combination Figures 3 to 5 As shown, the fabrication method of the CIS probe card space converter of the present invention mainly includes the following steps:
[0039] Step 1: Provide a conventional substrate 1 required for fabricating the space converter of the CIS probe card. The substrate 1 includes a first side and a second side disposed opposite to each other. The substrate 1 has a plurality of through holes, each through hole penetrating both the first side and the second side of the substrate 1.
[0040] Step 2: Prepare a number of filler elements 2 equal to the number of through holes. Fill multiple filler elements 2 into multiple through holes of the substrate 1. Each filler element 2 includes a first end and a second end positioned opposite each other. When a filler element 2 is placed into a through hole, its first end is close to the first surface of the substrate 1, and its second end is close to the second surface of the substrate 1. The filler element 2 can be a cylindrical ceramic pillar. Preferably, the size of the ceramic pillar matches the inner diameter of the through hole. However, due to processing tolerances and other reasons, a gap still exists between the outer wall of the ceramic pillar and the inner wall of the through hole, making it difficult to fix the ceramic pillar to the substrate 1.
[0041] Step 3: Deposit a seed layer (not shown) on the first surface of substrate 1 and the first ends of all fillers 2.
[0042] Step 4: Electroplating layer 4 is performed on the portion of the seed layer corresponding to the first end of filler 2. Electroplating layer 4 can be a copper layer or other metal with conductive properties. At least a portion of electroplating layer 4 is located within the through-hole of substrate 1 to fill the space between filler 2 and the inner wall of the through-hole, thereby fixing filler 2 to substrate 1 for subsequent processes.
[0043] Step 5: Remove the seed layer on substrate 1.
[0044] Step 6: Redewire the substrate 1 obtained in Step 5 according to the existing process. Then, remove the filler 2 in the area corresponding to each via on the substrate 1 to restore the vias on the substrate 1 and obtain the space converter.
[0045] By means of the above steps, the preparation method of the CIS probe card spatial converter in this invention is as follows: First, the through holes on the substrate 1 are filled with filler 2 so that the substrate 1 is in a hole-free state to complete the redistribution process. In this way, the problems of photoresist 3 edge chipping at the through hole edge, poor PI film morphology, and poor electroplated metal morphology will not occur. After the redistribution process is completed, the filler 2 and electroplated copper in the through holes of the substrate 1 are removed so that the through holes can restore their optical path function, and the spatial converter can restore its original function.
[0046] In step 2, before filling the through holes with filler 2, high-temperature tape can be applied to the second side of substrate 1, covering all through holes. After filler 2 is filled into the through holes, its second end adheres to the high-temperature tape. This allows for preliminary fixation of substrate 1 and filler 2 before electroplating layer 4, ensuring smooth operation of each process. In step 4, after electroplating layer 4 is completed, since substrate 1 and filler 2 are connected by the electroplated metal, the high-temperature tape can be peeled off substrate 1 and filler 2.
[0047] In step 3, the method for depositing the seed layer includes the following specific steps:
[0048] Step 31: First, deposit a layer of titanium on the first surface of substrate 1 and the first ends of all fillers 2. The thickness of the deposited titanium layer is between 30 nm and 50 nm. The titanium layer can improve...
[0049] Step 32: Deposit a copper layer on the titanium layer, with a thickness between 900 nm and 1100 nm. The titanium layer enhances the bonding force between the copper and the ceramic (filler 2).
[0050] In step 4, before electroplating the electroplated layer 4 on the seed layer, photoresist 3 can be first applied to the first surface of the substrate 1. The photoresist 3 does not cover the portion of the substrate 1 around the via, so that the electroplated layer 4 can also be electroplated on the seed layer around the via. This ensures that the electroplated layer 4 is sufficient to fill the gap between the filler 2 and the inner wall of the via, ensuring the stable connection between the filler 2 and the substrate 1. By applying photoresist 3 to the first surface of the substrate 1 and covering the seed layer that does not require electroplating, the area on the first surface of the substrate 1 to be electroplated with the electroplated layer 4 can be reduced, saving electroplating costs and reducing the difficulty of subsequently removing the electroplated layer 4.
[0051] Specifically, the method for setting photoresist 3 on the first surface of substrate 1 is as follows: Photoresist 3 is sprayed onto the first surface of substrate 1. At this time, photoresist 3 will inevitably be sprayed onto the first end of filler 2 as well. Therefore, in order to improve the spraying efficiency and reduce the spraying difficulty, photoresist 3 can be sprayed directly onto the first surface of substrate 1 and the first end of filler 2, that is, there is no need to distinguish between the sprayed area and the non-sprayed area; the photoresist 3 is exposed on an LDI (Laser Direct Imaging) device and then developed, so that the first ends of all fillers 2 are exposed. At the same time, the areas on substrate 1 that need to be electroplated around the through holes are also exposed.
[0052] In step 5, after removing the seed layer on the substrate 1, the electroplated layer 4 on the filler 2 is also flattened so that the metal on the first end surface of the filler 2 is flush with the first surface of the substrate 1, thereby improving the performance of the subsequent rewiring process.
[0053] In step 6, before performing the redistribution process on substrate 1, substrate 1 can be immersed in a chemical plating solution to form an Au layer 5 (gold layer) on the surface of the electroplated layer 4 (copper layer). The Au layer 5 can protect the electroplated copper layer from being damaged by the subsequent process environment.
[0054] In step 6, the method for removing the filler 2 in the area corresponding to the via on the substrate 1 specifically includes: coating the surface of the space converter with photoresist 3, making a corresponding pattern, and then exposing and developing the photoresist 3 on an LDI device to expose the area corresponding to the via; next, first using IBE (ion milling, also known as ion beam etching) to etch away the electroplated gold layer, and then using a wet method to clean the copper on the surface of the filler 2 and in the gap between it and the via, and removing the filler 2 inside the via; finally, removing the photoresist 3 from the surface of the space converter.
[0055] The preparation method of this embodiment will be described in detail below using Case 1 as an example. The specific steps of Case 1 are as follows:
[0056] 1: Use a ceramic pillar (approximately 10mm in diameter and approximately equal in length to the thickness of the substrate 1) that matches the size of the through hole in the substrate 1 as filler 2. Apply high-temperature adhesive tape to the second side of the substrate 1 and insert the ceramic pillar into the through hole.
[0057] 2: First, a 30nm titanium layer is deposited by PVD on the first surface of substrate 1 and the first ends of multiple ceramic pillars, and then a 1000nm copper layer is deposited as an electroplating seed layer.
[0058] 3: Spray a 10μm thick layer of AZ4620 onto the seed layer surface, create the corresponding pattern, expose it on an LDI, and then develop it with 3038 developer to mark out the area to be electroplated. This area includes the area directly above the through hole and a small area around the through hole.
[0059] 4. Electroplat copper (electroplated layer 4) according to the actual situation of the gap filling. The electroplated copper should fill the gap between the ceramic pillar and the through hole. Then peel off the photoresist 3 and high-temperature tape on both sides of the substrate 1.
[0060] 5: CMP treatment of the seed layer on the surface of substrate 1 and the electroplated layer 4 on the surface of the ceramic pillars to ensure that the flatness of substrate 1 meets the process requirements. After this step, the copper and titanium layers contained in the seed layer in the non-through-hole area are removed, the copper in the gap between the ceramic pillar and the through-hole is retained, and the copper on the first end face of the ceramic pillar (if the first end face is lower than the first surface of substrate 1, the first end face will be covered with an electroplated copper layer) is retained.
[0061] 6: Place substrate 1 into the electroplating solution and plate a layer of gold onto the electroplated copper surface.
[0062] 7: Perform a redistribution process on substrate 1 to obtain a space converter without openings.
[0063] 8: Spray a 10μm thick layer of AZ4620 onto the surface of the un-drilled space converter, and make the corresponding drawings (at this time, the design of the drawings should take care to protect the structure already made around the vias, and should accurately only drill the area where the vias are located to avoid damage to the structure of substrate 1 during the subsequent release process), expose on an LDI, and then develop with 3038 developer to drill the via area.
[0064] 9: Use IBE to etch away the electroplated gold layer.
[0065] 10: Use a wet method to corrode the copper (including electroplated copper and seed layer copper) and titanium from the surface of the ceramic column and the gap between it and the through hole, and then remove the ceramic column from the through hole.
[0066] 11: Use acetone to remove AZ4620 from the surface.
[0067] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.
Claims
1. A method for fabricating a space converter for a CIS probe card, characterized in that, Includes the following steps: Step 1: Provide a substrate, the substrate including a first surface and a second surface disposed opposite to each other, and the substrate having a plurality of through holes that simultaneously penetrate the first surface and the second surface; Step 2: Fill multiple fillers into multiple through holes of the substrate, wherein the filler includes a first end near the first surface of the substrate and a second end near the second surface of the substrate; Step 3: Deposit a seed layer on the first surface of the substrate and the first ends of all fillers; Step 4: Electroplating an electroplating layer on the seed layer corresponding to the first end of the filler, with at least a portion of the electroplating layer located within the through hole to fill the space between the filler and the inner wall of the through hole; Step 5: Remove the seed layer on the substrate; Step 6: Perform a redistribution process on the substrate obtained in Step 5, and then remove the filler in the area corresponding to the via on the substrate to restore the via and obtain the space converter.
2. The method for preparing a CIS probe card space converter according to claim 1, characterized in that, In step 2, before filling the through holes with filler, high-temperature tape is first applied to the second surface of the substrate, covering all through holes. After the filler is filled into the through holes, its second end is bonded to the high-temperature tape.
3. The method for preparing a CIS probe card space converter according to claim 1, characterized in that, The filler is a ceramic column.
4. The method for preparing a CIS probe card space converter according to claim 1, characterized in that, In step 3, the method for depositing the seed layer includes: Step 31: Deposit a titanium layer with a thickness between 30 nm and 50 nm on the first surface of the substrate and the first ends of all fillers; Step 32: Deposit a copper layer with a thickness between 900 nm and 1100 nm on the titanium layer.
5. The method for preparing a CIS probe card space converter according to claim 1, characterized in that, In step 4, before electroplating on the seed layer, photoresist is first applied to the first surface of the substrate, and the substrate around the via is not covered by the photoresist.
6. The method for preparing a CIS probe card space converter according to claim 5, characterized in that, The method of applying photoresist to the first surface of the substrate includes: spraying photoresist onto the first surface of the substrate and the first end of the filler, creating a corresponding pattern, then exposing the photoresist, followed by development, so that the first end of the filler and the area on the substrate around the via that needs to be electroplated are exposed.
7. The method for preparing a CIS probe card space converter according to claim 1, characterized in that, In step 5, after removing the seed layer on the substrate, the electroplated metal on the filler is also leveled to be flush with the first surface of the substrate.
8. The method for preparing a CIS probe card space converter according to claim 1, characterized in that, In step 6, before performing the redistribution process on the substrate, the substrate is first placed in a chemical plating solution to deposit an Au layer on the surface of the electroplated layer.
9. The method for preparing a CIS probe card space converter according to claim 8, characterized in that, In step 6, the method for removing the filler in the area corresponding to the via on the substrate includes: coating the surface of the space converter with photoresist, making a corresponding pattern, then exposing the photoresist, followed by development to expose the area corresponding to the via, sequentially removing the Au layer, electroplating layer and seed layer in the exposed area, then removing the filler from the via, and finally removing the photoresist from the surface of the space converter.
10. A CIS probe card space converter, characterized in that, Prepared using the method described in any one of claims 1 to 9.