Intelligent semiconductor defect analysis method and apparatus

Abstract

A method and apparatus for intelligent semiconductor defect analysis, relating to the semiconductor manufacturing field, are disclosed. This invention acquires a design layout, inspection images obtained from an inspection machine, and corresponding re-inspection images obtained from a re-inspection machine, and aligns them using coordinates. Based on the coordinate alignment results, a defect pattern template is generated. The defect pattern template includes defect regions extracted from the re-inspection images, the corresponding positions of the defect regions in the design layout, and the surrounding design environment information of the corresponding positions in the design layout. A hierarchical search is performed using a geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the entire chip's design layout. Precise defect statistics are performed, matching the potential defect locations with the full defect list provided by the inspection machine to determine the total number of specific defect types on the entire wafer. This invention achieves a transformation from sampling analysis to comprehensive intelligent diagnosis, greatly improving the efficiency and accuracy of semiconductor manufacturing process monitoring.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method and apparatus for intelligent analysis of semiconductor defects. Background Technology

[0002] In semiconductor manufacturing, defect detection and analysis are crucial for ensuring product yield and reliability. Currently, the industry commonly uses sampling analysis during the defect review stage, randomly selecting a small number (typically only 1%) of the tens of thousands of defects detected by the scanning machine. 10% of samples were re-examined using scanning electron microscopy (SEM). This method is inefficient, and due to the randomness of sampling, it is difficult to systematically identify and evaluate hotspot defects that have a greater impact on yield, resulting in biased analysis results and slow process root cause localization.

[0003] Existing technologies still have the following significant limitations in semiconductor defect analysis: 1) Analysis mode is limited by sampling: mainstream methods either rely on random sampling or are limited to enhanced detection of preset areas, neither of which can achieve accurate global statistics and intelligent analysis of defects across the entire wafer.

[0004] 2) Insufficient intelligence and adaptive capabilities: Defect identification and classification still rely on human experience, fixed rules or predefined models, and have failed to achieve automatic matching, identification and judgment based on deep integration of image and design information.

[0005] 3) Limited analytical dimensions and lack of closed-loop feedback: Most analyses focus on defect detection and location, failing to systematically link electrical test data, making it impossible to accurately assess the lethality of defects and their actual impact on product yield, and making it even more difficult to achieve rapid and automatic tracing from defects to process root causes.

[0006] Therefore, there is an urgent need in this field for a defect analysis solution that can achieve a fundamental shift from sampling analysis to comprehensive intelligent diagnosis. Summary of the Invention

[0007] This invention provides a semiconductor defect intelligent analysis scheme, aiming to realize the transformation from sampling analysis to full-domain intelligent diagnosis, and improve the efficiency and accuracy of semiconductor manufacturing process monitoring.

[0008] The first aspect of this invention provides a semiconductor defect intelligent analysis method, comprising: acquiring a design layout, an inspection image obtained from an inspection machine, and a corresponding re-inspection image obtained from a re-inspection machine, and performing coordinate alignment; generating a defect pattern template based on the coordinate alignment result, the defect pattern template including a defect region extracted from the re-inspection image, the corresponding position of the defect region in the design layout, and surrounding design environment information of the corresponding position of the defect region in the design layout; performing a hierarchical search based on a geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the design layout of the entire chip; performing precise defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine, and determining the total amount of a specific defect type on the entire wafer.

[0009] According to the intelligent semiconductor defect analysis method provided by the present invention, the coordinate alignment includes: extracting common alignment features from the design layout and the detection image and matching them; calculating the optimal transformation matrix based on the matching point pairs using a spatial transformation model to realize the mapping from the detection machine coordinate system to the design layout coordinate system.

[0010] According to the present invention, a semiconductor defect intelligent analysis method is provided, wherein generating a defect pattern template includes: performing image segmentation and extraction on a defect region in a coordinate-aligned review image; determining the position of the defect region in the design layout based on the coordinate alignment result; acquiring the surrounding design environment information of the position; the image of the defect region, the corresponding position, and the surrounding design environment information together form the defect pattern template; wherein the surrounding design environment information includes at least the neighboring layout graphics within a preset range centered on the position.

[0011] According to the intelligent semiconductor defect analysis method provided by the present invention, the hierarchical search based on the geometric hash algorithm includes two stages: offline database construction and online query. The offline database construction stage includes: traversing and extracting feature points in the design layout; for each feature point, constructing a local coordinate system based on other feature points in its neighboring area to generate a corresponding hash key; storing the global coordinates and associated attribute information of each feature point as association values ​​in a global hash table to complete the index construction. The online query stage includes: performing the same feature point extraction and hash key generation operations on adjacent layout graphics in the defect pattern template to obtain a set of query hash keys; using the global hash table for fast matching and voting to obtain candidate positions; accurately verifying the candidate positions and outputting the list of potential defect positions.

[0012] According to the intelligent semiconductor defect analysis method provided by the present invention, the method of using a global hash table for fast matching and voting includes: searching for each query hash key in the global hash table to obtain a set of design layout feature point locations with the same hash key; voting based on the matching results of multiple query hash keys in the defect pattern template through geometric consistency verification; and filtering the design layout locations that receive more than a preset threshold of votes as candidate locations.

[0013] According to the intelligent semiconductor defect analysis method provided by the present invention, the step of generating a corresponding hash key for each feature point includes: transforming the coordinates of other feature points in the vicinity of the feature point to the local coordinate system, quantizing them using absolute physical coordinates, and combining the feature point type to jointly generate the hash key.

[0014] According to the intelligent semiconductor defect analysis method provided by the present invention, the auxiliary attribute information includes the layout layer information where the feature point is located.

[0015] According to the intelligent semiconductor defect analysis method provided by the present invention, the extraction of feature points in the design layout includes extracting all vertices of a polygonal graphic, the midpoints of each side segment, and the geometric center of a specific graphic, wherein the specific graphic is a contact hole, a through hole, an arc-shaped graphic, an optical proximity correction auxiliary graphic, an alignment mark, or a test structure.

[0016] According to the present invention, a semiconductor defect intelligent analysis method is provided, wherein the precise defect statistics include: matching the potential defect location list with the full defect list in a unified coordinate system; if the Euclidean distance between the two is less than a preset matching tolerance, they are determined to be the same defect; and counting the number of successful matches to obtain the precise total number of a specific defect type on the entire wafer.

[0017] The semiconductor defect intelligent analysis method provided by the present invention further includes: extracting feature vectors from the defect pattern template; calculating the defect fatality rate based on coordinate association, including associating the located defects with the corresponding chip units, counting the total number of chip units with this type of defect, and the number of chip units whose electrical test results are failures, and calculating the fatality rate accordingly; inferring the process root cause through feature comparison, including comparing the feature vectors with a process failure knowledge base, automatically inferring the process steps and parameter anomalies that cause the defects, and generating a structured analysis report.

[0018] The semiconductor defect intelligent analysis method provided by the present invention further includes: the feature vector includes design environment features extracted from the surrounding design environment information contained in the defect pattern template, and process effect features calculated by a process simulation model based on the surrounding design environment information.

[0019] A second aspect of the present invention provides a semiconductor defect intelligent analysis device, comprising: The data fusion and alignment module is used to acquire the design layout, the detection images obtained from the testing machine, and the corresponding re-examination images obtained from the re-examination machine, and perform coordinate alignment. The template generation module is used to generate a defect pattern template based on the coordinate alignment result. The defect pattern template includes the defect area extracted from the review image, the corresponding position of the defect area in the design layout, and the surrounding design environment information of the corresponding position of the defect area in the design layout. The hierarchical search module is used to perform hierarchical search based on the geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the full chip design layout. The defect statistics module is used to perform accurate defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

[0020] The intelligent semiconductor defect analysis scheme provided by this invention achieves the following significant technical effects compared to existing technologies: 1) Achieving a fundamental breakthrough from sampling analysis to intelligent diagnosis across the entire domain. By intelligently associating defect images with design layouts and combining them with hierarchical search technology, high-speed and automated scanning and matching of the entire wafer can be performed, completely eliminating the reliance on random sampling or local hot spot sampling, and achieving full coverage detection and accurate statistics of all potential defect locations on the wafer surface.

[0021] 2) Significantly improves the accuracy and efficiency of defect identification and location. By integrating multi-source data and sub-pixel-level coordinate alignment, combined with a hierarchical search architecture based on improved geometric hashing, it is possible to quickly and accurately locate graphic positions that are highly similar to defect templates in massive map data, significantly improving the accuracy and speed of defect search and matching, and reducing human intervention and misjudgment.

[0022] 3) Achieve quantitative assessment of defect fatality rates and intelligent traceability of process root causes. By correlating electrical test data, the lethality rate of different types of defects can be accurately calculated, and the abnormal process links and parameters that may cause the defect can be automatically inferred based on the built-in process knowledge base. This forms a complete diagnostic closed loop from defect discovery to lethality analysis and root cause localization, which greatly shortens the process optimization cycle.

[0023] 4) Enhance the comprehensiveness, timeliness, and foresight of process monitoring. It can not only detect and count defects in real time, but also identify recurring and emerging defect types based on historical data and pattern matching results, providing early warning of systemic process risks and data-driven decision support for process stability control and continuous yield improvement.

[0024] 5) Develop a reusable and scalable intelligent defect analysis architecture. Through modular design, it can support flexible access to various testing and review equipment, adapt to different process nodes and product types. Its core search algorithm and feature extraction method have good scalability and adaptability, providing a reliable technical foundation for the intelligent upgrading of semiconductor manufacturing.

[0025] In summary, this invention achieves significant advancements in improving defect detection coverage, analysis accuracy, response speed, and diagnostic depth, providing a powerful technical tool for refined monitoring and rapid closed-loop optimization of semiconductor manufacturing processes. This invention has achieved unexpected technical results: by organically combining intelligent association between defect images and design layouts with improved geometric hash layered search technology, it achieves, for the first time, a second-level, sub-micron precision full-domain search of the entire chip layout, transforming traditional sampling inference into precise comprehensive investigation; by abandoning scale invariance, using absolute physical coordinates, and embedding layer information in the hash key construction method, it significantly improves matching efficiency while achieving high-precision retrieval of complex design patterns across layers; by constructing a composite template containing the defect ontology and its design environment, and associating it with electrical test data and a process knowledge base, it achieves intelligent closed-loop diagnosis from massive defect phenomena to key process root causes, thus realizing a fundamental leap in the field of semiconductor defect analysis from sampling estimation and reliance on human experience to comprehensive intelligent traceability. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating the intelligent semiconductor defect analysis provided by the present invention; Figure 2 This is a schematic diagram comparing the process of intelligent semiconductor defect analysis provided by the present invention with that of existing technologies; Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] Example 1 This invention provides a method for intelligent analysis of semiconductor defects, comprising: Acquire the design layout, the test images obtained from the testing machine, and the corresponding review images obtained from the review machine, and perform coordinate alignment; Based on the coordinate alignment results, a defect pattern template is generated. The defect pattern template includes the defect area extracted from the review image, the corresponding position of the defect area in the design layout, and the surrounding design environment information of the corresponding position of the defect area in the design layout. A hierarchical search based on the geometric hash algorithm is used to locate potential defect locations similar to the defect pattern template in the full chip design layout. Accurate defect statistics are performed by matching the locations of potential defects with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

[0030] Through the above steps, the method provided in this embodiment achieves accurate quantity statistics of defects of a specific type across the entire wafer, which in principle overcomes the inherent bias of traditional statistical inference methods that rely on random sampling, and provides a direct and reliable data foundation for process evaluation and control.

[0031] In one possible embodiment, the method can be further extended to extract feature vectors from the defect pattern template; calculate the defect fatality rate based on coordinate correlation; and infer the root cause of the process through feature comparison, thereby achieving a closed-loop intelligent diagnosis. Specifically, this includes: Extract feature vectors from the defect pattern template; The defect fatality rate is calculated based on coordinate association, which includes associating the located defects with the corresponding chip units, counting the total number of chip units with this type of defect, and the number of chip units whose electrical test results are failures; and then calculating the fatality rate. Inferring the root cause of a process defect through feature comparison includes comparing the feature vector with a process failure knowledge base, automatically inferring the process steps and parameter anomalies that lead to the defect, and generating a structured analysis report.

[0032] Example 2 The following is combined with Figures 1 to 3 This invention introduces a semiconductor defect intelligent analysis method provided by an embodiment of the present invention, comprising: Step 101 involves multi-source data fusion and high-precision coordinate alignment, including acquiring the detection images obtained from the detection machine, the corresponding review images obtained from the review machine, and the design layout.

[0033] This step first obtains the defect coordinates and patch images from the inspection machine, obtains the corresponding SEM images and their coordinates from the re-inspection machine, and obtains the chip design layout. Then, high-precision coordinate alignment is performed on the multi-source data.

[0034] In one feasible implementation, the data acquired from the inspection equipment is a defect report file conforming to the KLARF (KLA-Tencor Logand Results File; where "KLA-Tencor" is the official Chinese name of KLA-Tencor) format. This file records the coordinate information of each suspected defect and its corresponding patch image. The patch image refers to a local optical image captured by the inspection equipment at the specified coordinate location when an anomaly is detected; it is used for preliminary identification and classification of defects.

[0035] In one feasible implementation, for defects initially marked by the inspection equipment, a scanning electron microscope is driven to its corresponding coordinate area in the re-inspection equipment to perform high-resolution imaging, thereby obtaining the SEM image of the defect and the positioning coordinates of the SEM image recorded by the re-inspection equipment, and the SEM image is saved as a re-inspection image.

[0036] In one feasible implementation, the design layout, such as design layout data conforming to the GDSII (Graphic Data System II) stream format, contains geometric information such as polygons and paths that define the graphics of each process layer of the chip, as well as their hierarchical relationships.

[0037] In practice, the defect coordinates and patch images can be obtained from the inspection machine first, and the corresponding SEM images and their coordinates can be obtained from the re-inspection machine. The chip design layout data can be input into the processing system together, and then the high-precision coordinate alignment of multi-source data and subsequent steps can be performed in the processing system.

[0038] When achieving high-precision coordinate alignment of multi-source data, those skilled in the art may consider various technical approaches, such as registration based on full image mutual information optimization or matching based on universal feature points (e.g., SIFT, scale-invariant feature transform). However, these methods may have shortcomings in the specific semiconductor defect analysis scenario addressed in this invention: they may be computationally inefficient and impractical, or they may lack robustness in matching heterogeneous data pairs composed of layout graphics and SEM images.

[0039] To this end, the present invention further proposes to achieve sub-pixel-level precise alignment between the inspection machine coordinate system and the design layout coordinate system by extracting common features such as chip boundaries and alignment marks, and calculating a spatial transformation matrix. Since the inspection machine is usually positioned based on the coordinates provided by the inspection machine, the above alignment can achieve the unification of all data sources in the design layout coordinate system.

[0040] The core of achieving coordinate system alignment lies in extracting and matching common geometric features from different data sources, solving for the optimal spatial transformation model, and thus unifying the coordinate systems. Specific steps include: First, common feature extraction: Pre-defined common alignment features are extracted from the chip design layout and patch images obtained from the testing equipment. These features are geometric structures with clear physical meaning that can be clearly identified in different data sources, including but not limited to: the physical boundaries of the chip or standard cell, and specially designed optical alignment marks.

[0041] Second, feature matching and point pair generation: using image recognition and template matching technology, the image coordinates (pixel coordinates) of the feature points identified in the patch image are accurately associated and paired with the corresponding theoretical coordinates (physical coordinates, usually in nanometers) in the design layout data to form multiple sets of reliable coordinate corresponding point pairs.

[0042] Third, transformation model solution and coordinate unification: Based on the multiple sets of corresponding coordinate point pairs, a spatial transformation model (e.g., an affine transformation model) is used to establish the mapping relationship from the inspection machine image coordinate system to the design layout coordinate system, and the optimal spatial transformation matrix is ​​solved using an optimization algorithm (e.g., the least squares method). Applying this matrix, all original defect coordinates reported by the inspection machine can be uniformly transformed to the design layout coordinate system.

[0043] In one feasible implementation, the center coordinates of common features such as alignment marks extracted from optical patch images can achieve sub-pixel accuracy through algorithms such as sub-pixel edge detection. These image coordinates (accuracy up to 0.1 pixels) are matched with the corresponding theoretical physical coordinates (accuracy up to 1 nanometer) in the design layout to form point pairs. The affine transformation matrix is ​​optimized using the least squares method. This process minimizes the projection error between all point pairs, thereby obtaining a transformation relationship that continuously and accurately maps the coordinate system of the inspection machine to the coordinate system of the design layout, ultimately achieving global alignment accuracy better than that of a single pixel (i.e., sub-pixel level).

[0044] Optionally, the spatial transformation matrix can be verified or locally refined using clearer features in the scanning electron microscope (SEM) images obtained by the review machine to further improve alignment accuracy.

[0045] Step 102, Defect pattern template generation and feature quantization, wherein the defect pattern template includes the defect area extracted from the review image, the corresponding position of the defect area in the design layout, and the surrounding design environment information of the corresponding position of the defect area in the design layout.

[0046] Traditional defect analysis typically focuses only on the image morphology of the defect itself, neglecting the design context in which it occurs. However, defects in semiconductor manufacturing (especially pattern defects) are often closely related to specific layout patterns and their local environment. Defects of the same type, appearing alongside patterns of different densities and linewidths, can have drastically different causes and impacts on electrical performance. Therefore, to achieve intelligent identification, accurate classification, and root cause tracing of defects, this invention proposes that for confirmed defects, such as pattern failures, image segmentation technology be used to extract the defect region from the SEM image and map it to the corresponding layout location. Combined with surrounding design environment information, the combination of "defect + surrounding design environment information" is defined as a defect pattern template.

[0047] Optionally, key attribute features of each defect pattern template can be extracted, such as graphic density, line width, optical features, and defect morphology and texture, and quantized into feature vectors.

[0048] In this invention, the construction of defect pattern templates and feature quantization can adopt two configuration paths based on the required diagnostic depth: Configuration 1 (Basic / Efficient Path): Focuses on fast and accurate defect search and statistics. Under this path, the surrounding design environment information mainly includes neighboring layout graphics within a preset range centered on the location of the defect in the design layout.

[0049] Configuration 2 (Preferred / Deep Diagnostic Path): Building upon Configuration 1, this path further supports precise physical root cause tracing. In this path, the surrounding design environment information includes not only the neighboring layout graphics but also process effect characteristics calculated based on the neighboring layout graphics using process simulation models (such as the Optical Proximity Correction (OPC) model or the Chemical Mechanical Polishing (CMP) model), such as optical imaging features or surface morphology features.

[0050] In this embodiment, the preferred defect pattern template generation and quantization process is as follows: First, a defect pattern template is generated. For SEM images that have undergone coordinate alignment in step 101 and are confirmed as pattern-type defects, image segmentation techniques (such as thresholding, edge detection, or deep learning-based segmentation networks) are used to accurately extract the defect region. Then, based on the aligned coordinates, the extracted defect region image is positioned at its precise location within the design layout (GDSII). Next, the surrounding design environment information is obtained, primarily including: extracting all neighboring layout graphics within a preset physical range centered on this location; and, under the configured two-path approach, in addition to obtaining the neighboring layout graphics, calculating the corresponding process effect characteristics based on these graphics using a process simulation model. Finally, the defect region image, its layout location coordinates, and the surrounding design environment information are fused to form the defect pattern template.

[0051] In one feasible implementation, neighboring pattern elements within a preset range can be obtained by defining a square region with fixed side lengths (e.g., 1 or 2 micrometers). In other implementations, this range can also be adaptively determined, for example, extending beyond defect boundaries until encountering a specific type of pattern boundary (such as an adjacent metal line), to ensure that the most relevant design context is captured.

[0052] Then, feature quantization is performed on the defect pattern template to extract feature vectors. To facilitate efficient matching, retrieval, classification, and diagnosis by the computer, the defect pattern template needs to be quantized into numerical feature vectors. The extracted features include: Design environment features: Features directly extracted from the adjacent graphic layout, such as local graphic density, average width and spacing distribution of dominant lines, etc.

[0053] Defect ontology features: Features extracted from the defect region image, such as morphological and textural features like area, perimeter, and texture contrast.

[0054] Relational features: Features that describe the spatial relationship between defects and the design environment, such as the Euclidean distance from the defect to the nearest graphic edge.

[0055] Process effect characteristics (configuration two paths): characteristics calculated by process simulation model based on the adjacent layout pattern, such as optical imaging contrast obtained by OPC simulation, local thickness predicted by CMP model, etc.

[0056] In a feasible implementation, the feature quantization process can be expressed as: Feature_Vector = [Density, Avg_Line_Width, Optical_Contrast, Defect_Area, Defect_Perimeter, Distance_to_Edge,…]. Wherein, Feature_Vector is the feature vector characterizing the defect pattern template; Density is the layout graphic density of the local region where the defect is located; Avg_Line_Width is the average linewidth of the layout graphics adjacent to the defect, representing a design environment feature; Optical_Contrast is the optical imaging contrast at the location obtained through optical proximity correction simulation, representing a process effect feature; Defect_Area is the physical area of ​​the defect region; Defect_Perimeter is the perimeter of the defect region's outline, representing a defect ontology feature; and Distance_to_Edge is the Euclidean distance from the defect to the nearest layout graphic edge, representing an association feature.

[0057] Through the above quantization, the defect pattern template is transformed into a numerical feature vector that can be used for calculation, matching, and classification.

[0058] Step 102 transforms the approach from viewing defects in isolation to systematically analyzing defect scenarios. This context-aware modeling approach enables a deeper understanding of the essence of defects, a crucial prerequisite for subsequent high-precision full-chip pattern search and intelligent root cause diagnosis. An unexpected technical benefit is that, based on the features of such templates, the accuracy of automatic defect classification is significantly improved, and the recall rate for searching similar defects is greatly increased, effectively reducing false positives and false negatives caused by neglecting the design environment.

[0059] Step 103: Perform a hierarchical search based on the geometric hash algorithm to efficiently locate potential defect locations similar to the defect pattern template in the full chip design layout.

[0060] Traditional full-chip layout search requires pixel-level or image-level full-image comparison, and its computational load increases exponentially with the layout size, which cannot meet the timeliness requirements in actual production. General image recognition algorithms (such as feature point-based matching) also suffer from low efficiency and insufficient matching accuracy when applied to layout data composed of precise polygons.

[0061] To address the aforementioned challenges, this invention proposes a geometric hash algorithm that systematically improves upon the characteristics of semiconductor layout data structures. Combined with a hierarchical architecture that first performs rapid filtering and then precise verification, it achieves high-speed and accurate searching of massive datasets. The specific implementation steps of this process include: The first step is to perform an offline database construction phase, building a global hash index. This phase preprocesses the entire chip design layout, laying the foundation for fast online queries. Its core lies in extracting the essential geometric features of the layout and building an efficient index. Specific steps include: First, defining and extracting layout feature points: Traditional geometric hashing algorithms are often used for detecting corners or key points in natural images, which is not suitable for semiconductor layouts composed of polygons. This invention does not process every point in the design layout (GDSII), nor does it differ from traditional geometric hashing algorithms. Instead, it directly extracts highly discriminative feature points, typically including: vertices of polygonal shapes, midpoints of line segments, and the geometric centers of specific shapes. These feature points provide geometric determinism.

[0062] Specifically, the specific pattern can be a contact hole, a via, an arc shape, an optical proximity correction auxiliary pattern, an alignment mark, or a test structure. Second, a local coordinate system is constructed and a hash key is generated: For each extracted feature point, using it as the origin, several of the most significant other feature points within its neighborhood (e.g., within a radius of 1 micrometer) are selected to form a local geometry, and a local coordinate system is established accordingly. For example, within the neighborhood of feature point P_i, N of the most significant other feature points are found to form a local geometry. Typically, N=2 or 3 to form a stable base. With feature point P_i as the origin, the direction from feature point P_i to another feature point P_j within the local geometry is the x-axis, and its normal direction is the y-axis. Then, the coordinates of all other feature points within the neighborhood are transformed to this new local coordinate system. This transformed coordinate system is invariant to translation and rotation. The coordinates of all neighboring feature points within this local coordinate system are quantized with a certain precision (e.g., 5 nanometers), and combined with the feature point type (e.g., vertex, hole center, etc.) to generate a unique hash key. For example, a hash key can be represented as ("Vertex", 15, -7), where Vertex indicates that the feature point type is a vertex, and (15, -7) are the quantized coordinates.

[0063] It is worth noting that scale invariance is a crucial characteristic in general object recognition. However, in the semiconductor manufacturing environment, layout graphics have fixed design dimensions, and any unexpected scaling implies serious manufacturing defects. Therefore, this invention intentionally abandons scale invariance. When constructing the local coordinate system and quantizing coordinates, no transformation to scale-invariant space is used; instead, the absolute physical coordinates of the layout are used directly for quantization. This approach brings two major advantages: first, it greatly improves matching accuracy, avoiding mismatches introduced by scale normalization; second, it significantly improves the efficiency of index construction and querying because it eliminates the calculation and search of the scale dimension.

[0064] Third, populate the global hash table to complete index construction: Each generated hash key is used as an index key, and the global coordinates of that feature point (i.e., its actual location within the entire chip) and its associated attribute information (e.g., cell name, layer number) are stored as the associated value in a global hash table. After traversing and processing all extracted feature points in the design layout, a complete global hash table is constructed. This table contains an index of the local geometric information of all feature points in the entire layout under the algorithm's definition, laying the foundation for subsequent millisecond-level queries. This hash table is an efficient local structure index, rather than a direct list of defect locations.

[0065] Semiconductor designs typically consist of dozens of layered process data. The relative positions of the graphics in different layers (such as the alignment of metal lines and vias) are crucial for identifying critical defect patterns. This invention innovatively incorporates layer information as part of the association value when constructing hash keys. This allows the algorithm to accurately retrieve complex patterns across layers, such as the relative positions of vias and metal lines across layers, avoiding the limitations of single-layer searches.

[0066] In one feasible implementation, the two nearest neighboring feature points can be selected from among the most prominent other feature points to form a stable and easily computed local coordinate system basis. In another implementation, the number of neighboring points and the distance threshold can be adaptively selected based on the density of the graph.

[0067] Then, the online query phase proceeds, locating similar positions through hierarchical search. This phase utilizes a pre-built offline index to efficiently search individual defect pattern templates, divided into two levels: rapid filtering and precise verification. First layer, fast filtering (based on hash matching and consensus voting): First, for the defect pattern template generated in step 102, the same feature point extraction and hash key generation operations as in the offline database building stage are performed on the neighboring map graphics. This results in a set of query hash keys. This also includes the process of constructing a local coordinate system, that is, taking a certain feature point (such as a vertex) of a neighboring map graphics in the defect pattern template as the origin, and combining it with other feature points in its neighboring area to form a local geometric structure, thus establishing a local coordinate system.

[0068] Subsequently, for each query hash key, all matching entries are searched in the global hash table obtained during the offline database construction phase. Each matching entry means that a certain location P_i on the chip has a local geometry highly similar to the local geometry of a point Q_m in the defect pattern template. At this point, a vote is cast for this location P_i. Simultaneously, the transformation parameters from the local coordinate system of the defect pattern template to the global coordinate system are recorded. Due to the high repetition of the layout, a single query hash key typically matches hundreds or even thousands of layout locations. After all voting is completed, global locations with more than a preset threshold of votes are initially listed as high-confidence candidate regions. This process is equivalent to an efficient consensus matching mechanism, capable of narrowing the search range from billions of possibilities to hundreds of candidates within milliseconds.

[0069] In practice, the preset threshold can be set based on the number of feature points in the defect pattern template and the required matching confidence level. In a preferred embodiment, the preset threshold is set to a proportion (e.g., 50% to 70%) of the total number of valid feature points in the defect pattern template. In another embodiment, an empirically determined minimum number of votes (e.g., 4 or 5 votes) can be used as the threshold. Those skilled in the art can determine the optimal value of the preset threshold through limited experiments based on specific requirements for retrieval precision and recall.

[0070] Furthermore, this invention proposes that transformation parameters be stored together with candidate positions while voting for them. This design enables consistency verification of multiple transformation parameters accumulated for the same candidate position in subsequent processing, thereby filtering out true candidates that are highly consistent in geometric transformation and represent overall pattern matching, effectively filtering out false matches caused by accidental similarity of local structures.

[0071] The second layer, precise verification: For the small number of candidate locations generated by rapid screening, according to the same preset physical range as when generating the defect pattern template in step 102, the actual layout graphics surrounding the location are extracted from the full chip design layout. A more computationally intensive but more accurate similarity matching algorithm is then activated for verification. The defect pattern template (containing the defect area extracted from the review image and the neighboring layout graphics from the surrounding design environment information) is compared with the candidate areas in a refined manner. Finally, a list of high-confidence potential defect locations with similarity scores exceeding the confidence threshold is output.

[0072] In one implementation, the similarity matching algorithm uses polygon Boolean operations to calculate the coverage ratio between neighboring map graphics and candidate region graphics in the defect pattern template.

[0073] For example, the defect pattern template for bridging defects includes a small redundant polygon connecting two adjacent metal lines. In the candidate region, the algorithm extracts the design metal line polygon near the location and performs an AND operation with the template polygon. If the ratio of the intersection area to the template area is greater than 95%, it is confirmed as a bridging defect. The defect pattern template for missing graphics includes a contact hole polygon that should be present but is missing (i.e., a "hole"). The algorithm performs an XOR operation between the template (hole) and the design graphics of the candidate region. If the result shows that the location is completely filled with material (no hole), a missing graphics defect is confirmed.

[0074] In another implementation, the candidate region's layout is rapidly simulated using optical or physical methods. The generated simulated image is then compared with the image portion in the defect template using mutual information calculation or histogram of oriented gradient features to obtain a similarity score.

[0075] The unexpected technical effect of this step is that, by embedding layer information into hash keys, the system achieves efficient retrieval of cross-layer composite design patterns for the first time, which is difficult to achieve with traditional single-layer search or image matching methods. Simultaneously, by intentionally abandoning scale invariance, which has no physical significance for semiconductor manufacturing, and adopting a hierarchical processing architecture, while ensuring sub-micron level search accuracy, the time required for searching the entire chip (containing billions of patterns) is reduced from a theoretically infeasible order of magnitude to a practically acceptable range of seconds. This makes it possible to perform global statistical analysis of massive defects based on the design layout a reality.

[0076] Step 104, accurate defect statistics: match the potential defect locations with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

[0077] Traditional defect counting relies heavily on sampling-based inference, which involves randomly selecting a small subset (typically 1%–10%) from tens of thousands of scanned defects for re-examination and using the proportion of defect types in this sample to estimate the total number of defects on the entire wafer. This method has inherent statistical bias and cannot provide the exact quantity and spatial distribution of a specific type of defect on the entire wafer, resulting in unreliable basic data for yield analysis and difficulty in supporting precise process control.

[0078] To address the aforementioned issues, this step aims to leverage the intelligent search results from the preceding steps to achieve a fundamental shift from estimation to comprehensive survey. Its core lies in precisely associating the verified list of potential defect locations output in step 103 with the original full defect list provided by the defect scanning machine, thereby completing a global count of specific defect patterns. Specifically, by matching the coordinates of the searched potential defect locations with the full defect list of the inspection machine and counting the number of successful matches, the precise total number of defects of that type on the entire wafer can be obtained without sampling inference. Since step 101 has unified all defect scanning coordinates to the design layout coordinate system, and the potential defect locations searched in step 103 are also located in the same coordinate system, precise location matching can be performed within this unified space.

[0079] For example, for a potential defect location obtained from the search list (coordinates are...) If there is a defect point (coordinates) in the full defect list ), making the Euclidean distance between the two If the error is less than the preset matching tolerance, the scan defect is considered to have been successfully identified as this type of defect.

[0080] In one feasible implementation, the matching tolerance can be adaptively set based on the repeatability of different testing equipment and the residual error of coordinate alignment.

[0081] This step enables, for the first time, the absolute number of defects related to a specific design to be statistically analyzed, providing a reliable data foundation for calculating the true lethality rate and assessing process fluctuations. Its technical effect is unmatched by sampling methods.

[0082] Step 105, Mortality Calculation and Root Cause Diagnosis In semiconductor manufacturing, finding defects is not the ultimate goal; the key is to assess their actual impact (lethality) on chip functionality and quickly pinpoint the process steps that caused the defect. In traditional methods, electrical test data and physical defect analysis are often disconnected, the lethality assessment of defects relies on engineers' experience, and tracing the root cause of process defects requires lengthy experimental investigations, which is inefficient and costly.

[0083] This step aims to establish an automated analysis closed loop. By correlating design coordinates, defect characteristics, and chip test results, it can not only quantify the destructive power of defects but also intelligently infer their causes. This invention realizes a transformation from sampling analysis to comprehensive intelligent diagnosis, supporting a priority focus on hotspot defects that pose the greatest threat to yield.

[0084] In one implementation, firstly, the defect fatality rate is calculated based on coordinate correlation. Using the coordinate mapping relationship established in step 101, each precisely located and classified defect can be associated with its specific chip cell in the chip array. Subsequently, the electrical test results of these chip cells are retrieved, and the total number N of chip cells whose electrical test results are failed due to a certain type of defect is counted. fail Then count the number N chips that have this type of defect. affected (Regardless of the number of similar defects in a chip, only one is counted). Therefore, the lethality rate of this type of defect can be calculated as: KR = N fail / N affected The resulting lethality rate is a precise statistical value based on full-wafer survey data, rather than a sample estimate. It directly quantifies the average destructive impact of this type of defect on product yield, providing an objective basis for determining the severity level of defects.

[0085] Secondly, the root cause of the process can be automatically inferred based on feature comparison. In specific implementation, a process failure knowledge base can be pre-set, which stores the defect feature patterns corresponding to various typical process anomalies (such as lithography defocusing, etching micro-loading, CMP disc pits, etc.).

[0086] As a preferred embodiment of the present invention, in order to achieve high-precision physical root cause tracing, the core of the defect feature patterns stored in the process failure knowledge base are: 1. The design environment characteristics in which it is prone to occur (such as specific pattern density, specific linewidth). 2. Key process effect characteristics (i.e., the characteristic values ​​that this type of process anomaly is expected to exhibit through the process simulation model under the design environment, such as the specific optical contrast reduction mode corresponding to lithography defocus, or the specific thickness change curve corresponding to CMP disc pit).

[0087] The corresponding root cause diagnosis process is as follows: The feature vector of the current defect mode extracted in step 102 (which preferably includes design environment features and process effect features) is compared with the records in the knowledge base. The system automatically matches one or more most likely process root cause hypotheses through algorithms (such as calculating feature space distance or similarity). When the feature vector contains process effect features, this comparison can be directly associated with specific physical process deviations, thereby achieving accurate diagnosis from defect phenomena to abnormal process parameters.

[0088] Even when the feature vector only contains design environment and defect ontology features, the system can still perform comparisons. Its inference results are more related to design patterns that are prone to problems, providing important directions for process troubleshooting.

[0089] Finally, the system generates a structured analysis report. The report may include: defect type, precise quantity, spatial distribution, calculated lethality rate, and the most likely process step and specific abnormal parameter direction.

[0090] like Figure 2 As shown, the existing defect analysis process first performs an optical scan of the wafer and generates a defect coordinate report (usually a Klarf format file). Then, a small number of samples are randomly selected from a massive number of defects. Next, high-resolution images of the samples are acquired using a scanning electron microscope, and defects are classified based on image features. Finally, the distribution and total number of defect types across the entire wafer are calculated based on the statistical results of the sampled data. This result relies on sample representativeness and cannot be correlated with design information, representing a global estimation method based on local sampling. In contrast, this invention, through the above process, first constructs a defect pattern template based on the design layout, original defect data (patch images + coordinates), and corresponding review images. Then, through the core step of searching for the defect pattern template in the layout data, the obtained potential defect locations are matched with a full defect list provided by the inspection machine, containing the coordinates of all original defects. Finally, the total number of a certain defect type is directly output, obtaining accurate results, achieving a fundamental shift from sampling inference to precise global diagnosis.

[0091] This invention compresses the traditional, lengthy open-loop process of defect detection, electrical testing, and process experimentation into an intelligent closed loop with automatic diagnosis and real-time reporting. It not only shortens root cause analysis time from days or weeks to near real-time, but more importantly, the analysis conclusions directly provide specific design hotspots and process parameters, offering engineers clear and actionable directions for process optimization, thereby significantly accelerating the improvement of process stability and yield.

[0092] The intelligent semiconductor defect analysis device provided by the present invention is described below. The intelligent semiconductor defect analysis device described below can be referred to in correspondence with the intelligent semiconductor defect analysis method described above.

[0093] The present invention provides a semiconductor defect intelligent analysis device, comprising: The data fusion and alignment module is used to acquire the design layout, the detection images obtained from the testing machine, and the corresponding re-examination images obtained from the re-examination machine, and perform coordinate alignment. The template generation module is used to generate a defect pattern template based on the coordinate alignment result. The defect pattern template includes the defect area extracted from the review image, the corresponding position of the defect area in the design layout, and the surrounding design environment information of the corresponding position of the defect area in the design layout. The hierarchical search module is used to perform hierarchical search based on the geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the full chip design layout. The defect statistics module is used to perform accurate defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

[0094] In one specific embodiment, it also includes: The feature extraction module is used to extract feature vectors from the defect pattern template; The lethality calculation module is used to calculate the defect lethality rate based on coordinate association, including associating the located defects with the corresponding chip units, counting the total number of chip units with this type of defect, and the number of chip units whose electrical test results are failures; and calculating the lethality rate accordingly. The diagnostic module is used to infer the root cause of the process through feature comparison, including comparing the feature vector with the process failure knowledge base, automatically inferring the process links and parameter anomalies that lead to the defect, and generating a structured analysis report.

[0095] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3 As shown, the electronic device may include a processor 310, a communications interface 320, a memory 330, and a communication bus 340. The processor 310, communications interface 320, and memory 330 communicate with each other via the communication bus 340. The processor 310 can call logical instructions in the memory 330 to execute a semiconductor defect intelligent analysis method. This method includes: acquiring a design layout, inspection images obtained from an inspection machine, and corresponding re-inspection images obtained from a re-inspection machine, and performing coordinate alignment; generating a defect pattern template based on the coordinate alignment results, the defect pattern template including defect regions extracted from the re-inspection images, the corresponding positions of the defect regions in the design layout, and the surrounding design environment information of the corresponding positions of the defect regions in the design layout; performing a hierarchical search based on a geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the entire chip's design layout; performing precise defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

[0096] Furthermore, the logical instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0097] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the semiconductor defect intelligent analysis method provided by the above methods. The method includes: acquiring a design layout, a detection image obtained by an inspection machine, and a corresponding re-inspection image obtained by a re-inspection machine, and performing coordinate alignment; generating a defect pattern template based on the coordinate alignment result, the defect pattern template including a defect region extracted from the re-inspection image, the corresponding position of the defect region in the design layout, and the surrounding design environment information of the corresponding position of the defect region in the design layout; performing a hierarchical search based on a geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the design layout of the entire chip; performing precise defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine, and determining the total amount of a specific defect type on the entire wafer.

[0098] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the semiconductor defect intelligent analysis method provided by the above methods. The method includes: acquiring a design layout, a detection image obtained by an inspection machine, and a corresponding re-inspection image obtained by a re-inspection machine, and performing coordinate alignment; generating a defect pattern template based on the coordinate alignment result, the defect pattern template including a defect region extracted from the re-inspection image, the corresponding position of the defect region in the design layout, and the surrounding design environment information of the corresponding position of the defect region in the design layout; performing a hierarchical search based on a geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the design layout of the entire chip; performing precise defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine, and determining the total amount of a specific defect type on the entire wafer.

[0099] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0100] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of intelligent analysis of semiconductor defects, characterized in that, include: Acquire the design layout, the test images obtained from the testing machine, and the corresponding review images obtained from the review machine, and perform coordinate alignment; Based on the coordinate alignment results, a defect pattern template is generated. The defect pattern template includes the defect area extracted from the review image, the corresponding position of the defect area in the design layout, and the surrounding design environment information of the corresponding position of the defect area in the design layout. A hierarchical search based on the geometric hash algorithm is used to locate potential defect locations similar to the defect pattern template in the full chip design layout. Accurate defect statistics are performed by matching the locations of potential defects with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

2. The semiconductor defect intelligent analysis method of claim 1, wherein, The coordinate alignment includes: Extract common alignment features between the design layout and the detected image; The image coordinates of the alignment features identified in the detected image are matched with the corresponding theoretical coordinates in the design layout to form multiple sets of coordinate-corresponding point pairs; Based on the multiple sets of corresponding coordinate point pairs, the optimal spatial transformation matrix is ​​calculated using a spatial transformation model to achieve the mapping from the detection machine coordinate system to the design layout coordinate system.

3. The semiconductor defect intelligent analysis method of claim 1, wherein, The generated defect pattern template includes: Image segmentation and extraction are performed on the defective regions in the coordinate-aligned review images; Based on the coordinate alignment results, determine the location of the defective area in the design layout. Obtain information about the surrounding design environment of the location; The image of the defective area, its corresponding location, and the surrounding design environment information together form the defect pattern template. The surrounding design environment information includes at least the adjacent map graphics within a preset range centered on the location.

4. The semiconductor defect intelligent analysis method of claim 1, wherein, The hierarchical search based on the geometric hash algorithm includes an offline database construction stage and an online query stage. The offline database construction stage includes: traversing and extracting feature points from the design layout; for each feature point, constructing a local coordinate system based on other feature points in its neighboring area and generating a corresponding hash key; storing the global coordinates and associated attribute information of each feature point as associated values ​​in a global hash table to complete the index construction. The online query stage includes: performing the same feature point extraction and hash key generation operations on adjacent map graphics in the defect pattern template to obtain a set of query hash keys; using a global hash table for fast matching and voting to obtain candidate positions; performing precise verification of the candidate positions and outputting the list of potential defect positions.

5. The semiconductor defect intelligent analysis method of claim 4, wherein, The method of using a global hash table for fast matching and voting filtering includes: Each query hash key is searched in the global hash table to obtain the set of all design layout feature point locations with the same hash key; Based on the matching results of multiple query hash keys in the defect pattern template, voting is performed through geometric consistency verification; The design layout locations that receive more votes than a preset threshold are selected as candidate locations.

6. The semiconductor defect intelligent analysis method of claim 4, wherein, The step of generating a corresponding hash key for each feature point includes: transforming the coordinates of other feature points in the vicinity of the feature point to the local coordinate system, quantizing them using absolute physical coordinates, and combining the feature point type to generate the hash key. The associated attribute information includes the map layer information where the feature point is located; Traverse and extract feature points from the design layout, including extracting all vertices of polygonal graphics, the midpoints of each edge segment, and the geometric center of a specific graphic, such as a contact hole, through hole, arc shape, optical proximity correction auxiliary graphic, alignment mark, or test structure.

7. The semiconductor defect intelligent analysis method of claim 1, wherein, The accurate defect statistics include: Under a unified coordinate system, the list of potential defect locations is matched with the list of all defects. If the Euclidean distance between the two is less than the preset matching tolerance, they are determined to be the same defect; The number of successful matches is counted to obtain the precise total number of specific defect types on the entire wafer.

8. The method of claim 1, wherein the step of analyzing the defect data comprises the step of: Also includes: ​ Extract feature vectors from the defect pattern template; The defect fatality rate is calculated based on coordinate association, which includes associating the located defects with the corresponding chip units, counting the total number of chip units with this type of defect, and the number of chip units whose electrical test results are failures; and then calculating the fatality rate. Inferring the root cause of a process defect through feature comparison includes comparing the feature vector with a process failure knowledge base, automatically inferring the process steps and parameter anomalies that lead to the defect, and generating a structured analysis report.

9. The method of claim 8, wherein: The feature vector includes design environment features extracted from the surrounding design environment information contained in the defect pattern template, and process effect features calculated by the process simulation model based on the surrounding design environment information.

10. A semiconductor defect intelligent analysis apparatus characterized by comprising: include: The data fusion and alignment module is used to acquire the design layout, the detection images obtained from the testing machine, and the corresponding re-examination images obtained from the re-examination machine, and perform coordinate alignment. The template generation module is used to generate a defect pattern template based on the coordinate alignment result. The defect pattern template includes the defect area extracted from the review image, the corresponding position of the defect area in the design layout, and the surrounding design environment information of the corresponding position of the defect area in the design layout. The hierarchical search module is used to perform hierarchical search based on the geometric hash algorithm to locate potential defect locations similar to the defect pattern template in the full chip design layout. The defect statistics module is used to perform accurate defect statistics, matching the potential defect locations with the full defect list provided by the inspection machine to determine the total amount of a specific defect type on the entire wafer.

Images