A method and system for calibrating a multiphase quadrature clock

Abstract

This application provides a calibration method and system for a multiphase quadrature clock, relating to the technical field of clock calibration. Each phase of the multiphase quadrature clock is passed through a first low-pass filter to obtain a first DC voltage. Based on a comparison between the first DC voltage and a first reference voltage, the rise time and / or fall time control word of the buffer for that phase clock is adjusted until the first DC voltage equals the first reference voltage. Then, the clock edges of two adjacent phases are sequentially input to a logic gate module to generate pulse signals. These pulse signals are passed through a second low-pass filter to obtain a second DC voltage. Based on a comparison between the second DC voltage and a second reference voltage, the delay control word of the buffer for at least one of the two clock edges is adjusted until the second DC voltage equals the second reference voltage, thereby achieving phase deviation calibration between the clock edges of adjacent phases. The solution provided in this application has the advantage of achieving accurate calibration.

Description

Technical Field

[0001] This application relates to the technical field of clock calibration, and more specifically, to a calibration method and system for a multiphase quadrature clock. Background Technology

[0002] With the rapid development of communication technology, the transmission rate of high-speed serial interfaces is constantly increasing, and the requirements for the accuracy of clock signals are becoming increasingly stringent. For example, in the PCIe (Peripheral Component Interconnect Express) protocol, the uncertainty of the total jitter at the transmitter (T) is crucial. TX-UDJDD The jitter requirement has been reduced from 3.125ps for PCIe 5.0 to 0.75ps for PCIe 7.0. In transmitter designs using a quarter-rate parallel-to-serial (P2S) architecture, precise calibration of the duty cycle distortion (DCD) and quadrature phase skew (IQ skew) of the quadrature clock is required to meet such stringent jitter requirements.

[0003] Traditional clock calibration schemes typically employ differential calibration, first performing differential duty cycle calibration and then differential quadrature phase deviation calibration. The principle of differential duty cycle calibration is as follows: the differential output clock is filtered through a low-pass filter to obtain a DC voltage representing the differential clock duty cycle. These two DC voltages are compared using a comparator, and the digital state machine adjusts the control word based on the comparison result to ensure the differential clock duty cycles are equal. The principle of differential quadrature phase deviation calibration is as follows: a four-phase quadrature clock is input to a 4:1 parallel-to-serial converter. The input data "1010" is converted from parallel to serial, and the output clock code's duty cycle represents the magnitude of the quadrature phase deviation. This output clock code is then filtered through a low-pass filter and compared with half of the power supply voltage. The quadrature phase deviation is adjusted based on the comparison result.

[0004] However, the above calibration scheme has the following drawbacks: First, differential duty cycle calibration can only ensure that the duty cycles between differential clocks are equal, but cannot guarantee that the duty cycle of each phase clock is 50%, resulting in poor single-ended clock quality; Second, differential quadrature phase deviation calibration can only ensure that the phase deviation between two specific pairs of clock edges is symmetrical, but cannot calibrate the phase deviation between four phase clocks to zero, making it difficult to meet the stringent clock accuracy requirements of high-speed protocols such as PCIe 7.0.

[0005] Therefore, how to accurately calibrate the duty cycle and phase deviation of multiphase quadrature clocks has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this application is to provide a calibration method and system for multiphase quadrature clocks to solve the problem of low accuracy in duty cycle and phase deviation of multiphase quadrature clocks in the prior art.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: On one hand, embodiments of this application provide a calibration method for a multiphase quadrature clock, the method comprising: Each phase clock in the multi-phase quadrature clock is passed through a first low-pass filter to obtain a first DC voltage. Based on the comparison result of the first DC voltage and the first reference voltage, the rise time and / or fall time control word of the buffer of the phase clock is adjusted until the first DC voltage is equal to the first reference voltage, so as to achieve duty cycle calibration of each phase clock. The clock edges of two adjacent phases are sequentially input to the logic gate module to generate a pulse signal. The pulse signal is passed through a second low-pass filter to obtain a second DC voltage. Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted until the second DC voltage is equal to the second reference voltage, so as to achieve phase deviation calibration between the clock edges of adjacent phases.

[0008] Optionally, the step of adjusting the rise time and / or fall time control word of the buffer of the phase clock according to the comparison result of the first DC voltage and the first reference voltage until the first DC voltage is equal to the first reference voltage includes: Based on the comparison result between the first DC voltage and the first reference voltage, the rise time and / or fall time control word of the buffer of the phase clock are adjusted according to the set first step length until the comparison result is flipped.

[0009] Optionally, when time-division multiplexing the same hardware module to achieve phase deviation calibration between the clock edges of every two adjacent phases, the step of adjusting the delay control word of the buffer of at least one of the two clock edges until the second DC voltage is equal to the second reference voltage, based on the comparison result of the second DC voltage and the second reference voltage, includes: Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted by a set second step size until the comparison result flips.

[0010] Optionally, each pair of adjacent clocks includes a preceding clock and a following clock. The step of adjusting the delay control word of the buffer for at least one of the two clock edges according to a set second step size includes: Adjust the delay control word of the buffer for the preceding clock in the two clock edges according to the set second step size; or Adjust the delay control word of the buffer for the subsequent clock between the two clock edges according to the set second step size.

[0011] Optionally, when multiple hardware modules are used, and each hardware module is used to implement phase deviation calibration between a pair of adjacent phase clock edges, the step of adjusting the delay control word of the buffer of at least one of the two clock edges until the second DC voltage is equal to the second reference voltage, based on the comparison result of the second DC voltage and the second reference voltage, includes: Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted by a set second step size until the comparison result is flipped. After each comparison result is flipped, the step of adjusting the delay control word of the buffer of at least one of the two clock edges in reverse by a set second step size based on the comparison result of the second DC voltage and the second reference voltage is repeated.

[0012] Optionally, the step of adjusting the delay control word of the buffer for at least one of the two clock edges according to the set second step size includes: Adjust the delay control word of the buffer for at least one of the two clock edges according to the first sub-step size until the comparison result flips; The delay control word of the buffer for at least one of the two clock edges is adjusted in reverse according to the second sub-step size until the comparison result flips again; wherein the first sub-step size is greater than the second sub-step size.

[0013] On the other hand, embodiments of this application also provide a calibration system for a multiphase quadrature clock, the system comprising: The duty cycle calibration unit is used to pass each phase clock in the multi-phase quadrature clock through a first low-pass filter to obtain a first DC voltage, and adjust the rise time and / or fall time control word of the buffer of the phase clock according to the comparison result of the first DC voltage and the first reference voltage, until the first DC voltage is equal to the first reference voltage, so as to realize the duty cycle calibration of each phase clock. The phase deviation calibration unit is used to sequentially input the clock edges of two adjacent phases to the logic gate module to generate a pulse signal after the duty cycle calibration is completed. The pulse signal is passed through a second low-pass filter to obtain a second DC voltage. Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted until the second DC voltage is equal to the second reference voltage, so as to realize the phase deviation calibration between the clock edges of adjacent phases.

[0014] Optionally, the duty cycle calibration unit includes: A first low-pass filter is used to convert each phase clock signal into a first DC voltage; The first comparator has its non-inverting input connected to the first low-pass filter and is used to compare the first DC voltage with the first reference voltage and output a first comparison result. The first digital state machine is connected to the output of the first comparator and the buffer of each clock phase, and is used to adjust the rise time and / or fall time control word of the buffer of the clock phase according to the first comparison result.

[0015] Optionally, the phase deviation calibration unit includes: The logic gate module is used to receive the rising edge of one clock and the falling edge of the other clock from two adjacent phases and generate a pulse signal. A second low-pass filter is connected to the logic gate module and is used to convert the pulse signal into a second DC voltage; The second comparator, whose non-inverting input is connected to the second low-pass filter, is used to compare the second DC voltage with one-quarter of the power supply voltage and output the second comparison result. The second digital state machine is connected to the buffers of two adjacent clock phases and the comparator, and is used to adjust the delay control word of one of the clock buffers according to the second comparison result.

[0016] Optionally, the duty cycle calibration unit and the phase deviation calibration unit share the same low-pass filter, comparator, and digital state machine.

[0017] Compared with the prior art, this application has the following advantages: This application provides a calibration method and system for a multiphase quadrature clock. First, each phase of the multiphase quadrature clock is passed through a first low-pass filter to obtain a first DC voltage. Based on the comparison between the first DC voltage and a first reference voltage, the rise time and / or fall time control word of the buffer of that phase clock is adjusted until the first DC voltage is equal to the first reference voltage, thereby achieving duty cycle calibration for each phase clock. Then, the clock edges of two adjacent phases are sequentially input to a logic gate module to generate pulse signals. The pulse signals are passed through a second low-pass filter to obtain a second DC voltage. Based on the comparison between the second DC voltage and a second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted until the second DC voltage is equal to the second reference voltage, thereby achieving phase deviation calibration between the clock edges of adjacent phases.

[0018] Because this application calibrates each phase clock separately during the calibration process, it ensures that each phase clock meets the standard requirements. After the duty cycle calibration is completed, the phase deviation between multiple clocks is calibrated, ensuring that the phase deviation is equal to 0, thus achieving more accurate calibration.

[0019] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the architecture of the duty cycle calibration unit provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the architecture of the phase deviation calibration unit provided in an embodiment of this application.

[0023] Figure 3 A timing diagram of the output waveform of the logic gate module provided in the embodiments of this application.

[0024] Figure 4 An exemplary flowchart of a calibration method for a multiphase quadrature clock provided in an embodiment of this application.

[0025] In the picture: 111-First low-pass filter; 112-First comparator; 113-First digital state machine; 121-Second low-pass filter; 122-Second comparator; 123-Second digital state machine; 124-Logic gate module. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0028] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in the embodiments of this invention can be combined with each other. It should also be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0030] As described in the background section, current clock calibration schemes using differential calibration can only guarantee that the duty cycle distortion (DCD) between differential clocks is equal, but not equal to 50%. Similarly, when calibrating phase skew, it can only guarantee that the skew between two clocks is equal to the skew between the other two clocks, but cannot guarantee that the skew is zero, resulting in insufficient calibration accuracy.

[0031] In view of this, to solve the above problems, this application provides a calibration system for multi-phase quadrature clocks. By calibrating the duty cycle of multiple clocks separately, each clock can achieve accurate duty cycle calibration. Simultaneously, by calibrating the phase deviation between each pair of adjacent clocks separately, it can be ensured that the phase deviation between the multiple clocks is calibrated to 0.

[0032] The calibration system for the multiphase quadrature clock provided in this application is illustrated below: In one implementation, the system includes a duty cycle calibration unit, used to pass each phase clock of the multi-phase quadrature clock through a first low-pass filter 111 to obtain a first DC voltage, and adjust the rise time and / or fall time control word of the buffer of the phase clock according to the comparison result of the first DC voltage and the first reference voltage, until the first DC voltage is equal to the first reference voltage, so as to achieve duty cycle calibration of each phase clock; and a phase deviation calibration unit, used to input the clock edges of two adjacent phases sequentially to the logic gate module 124 to generate a pulse signal after the duty cycle calibration is completed, pass the pulse signal through a second low-pass filter 121 to obtain a second DC voltage, and adjust the delay control word of the buffer of at least one of the two clock edges according to the comparison result of the second DC voltage and the second reference voltage, until the second DC voltage is equal to the second reference voltage, so as to achieve phase deviation calibration between the clock edges of adjacent phases.

[0033] Understandably, this application first performs single-ended duty cycle calibration independently for each phase clock, and then performs skew calibration independently for each pair of adjacent phase edge combinations, thus achieving accurate calibration.

[0034] Specifically, in the duty cycle calibration stage, each phase of the multi-phase quadrature clock is filtered by a first low-pass filter (LPF) 111, thereby converting the waveform of that phase clock into a DC voltage (i.e., a first DC voltage) characterizing its duty cycle. This first DC voltage is compared with a first reference voltage. Then, based on the comparison result, the rise time control word and / or fall time control word of the buffer through which the phase clock passes are dynamically adjusted, thereby changing the ratio of the high-level duration to the low-level duration of that phase clock. When the first DC voltage obtained by filtering the phase clock is equal to the first reference voltage, it indicates that its high and low level durations are strictly equal, that is, the accurate calibration of the duty cycle is achieved. This process is applied independently to each phase clock sequentially, thereby ensuring that the duty cycle of each phase clock is calibrated to the standard value, rather than just maintaining the symmetry within the differential pair.

[0035] In this process, the phase deviation calibration stage further performs independent closed-loop adjustment on two edges with a defined phase relationship between adjacent phases: for example, the rising edge of one clock and the falling edge of another clock are used as a pair of calibration targets and input together into the logic gate module 124. For example, the logic gate module 124 can be an AND gate, so that it outputs a high level when both signals are simultaneously high, and a low level at other times. The pulse signal output by the logic gate module 124 is filtered by the second low-pass filter 121 to generate a second DC voltage characterizing the proportion of its high level; this second DC voltage is compared with a second reference voltage, and at least one clock (such as the delay control word of the buffer it passes through) is adjusted accordingly until the second DC voltage is stably equal to the second reference voltage, i.e., the phase deviation between them is calibrated to 0. Similarly, this method sequentially completes the phase deviation calibration of any other two adjacent clock phases, thereby ensuring that all clocks achieve global zero deviation at the edge alignment level.

[0036] Therefore, the calibration method provided in this application fundamentally overcomes the inherent systematic deviation defects of traditional differential calibration methods: on the one hand, by individually calibrating the duty cycle of each phase clock to the standard value, it avoids even-order harmonic distortion and static power consumption offset caused by the overall deviation of the duty cycle within the differential pair from the standard value, even though the duty cycles are equal. On the other hand, by performing absolute zero-deviation calibration on each pair of adjacent edges with functional coupling, it significantly compresses the sampling uncertainty window in the parallel-to-serial conversion process, directly reducing the timing jitter of the output data stream, thereby meeting the stringent limit requirements for transmitter jitter of next-generation high-speed interfaces such as PCIe 7.0.

[0037] It should be noted that this application does not limit the number of phases of the multiphase quadrature clock; it can be 4 phases or 8 phases. Furthermore, the first DC voltage described in this application can be set to half the power supply voltage, i.e., Vdd / 2, so that when calibrating the duty cycle of each clock, the duty cycle of each clock is calibrated to 50%. Moreover, the second DC voltage can be adjusted according to the number of phases of the quadrature clock. For example, when it is a 4-phase quadrature clock, the second DC voltage is set to one-quarter of the power supply voltage, i.e., Vdd / 4; when it is an 8-phase quadrature clock, the second DC voltage is set to one-eighth of the power supply voltage, i.e., Vdd / 8.

[0038] Taking a 4-phase quadrature clock as an example, the 4 phases are clkouti, clkoutib, clkoutq, and clkoutqb. Theoretically, the delay between the rising and falling edges of any two adjacent clocks should differ by 90°. For example, the delay between the rising edge of clkouti and the falling edge of clkoutqb is equal to 90°. During calibration, the duty cycle calibration unit is first used to perform single-ended DCD calibration of the 4-phase quadrature clocks, calibrating the DCD of clkouti, clkoutib, clkoutq, and clkoutqb to 50%. Then, the phase deviation calibration unit is used to sequentially perform skew calibration between the rising edge of clkouti and the falling edge of clkoutqb, between the rising edge of clkoutq and the falling edge of clkouti, between the rising edge of clkoutib and the falling edge of clkoutq, and between the rising edge of clkoutqb and the falling edge of clkoutib, ensuring that the phase deviation between any two adjacent clock phases is calibrated to 0.

[0039] In one implementation, please refer to Figure 1 The duty cycle calibration unit includes a first low-pass filter 111, a first comparator 112, and a first digital state machine 113. The non-inverting input of the first comparator 112 is connected to the first low-pass filter 111, the inverting input receives Vdd / 2, and the output is connected to the first digital state machine 113. The first digital state machine 113 is also connected to the buffer for each phase clock, and the buffer for each phase clock is also connected to the first low-pass filter 111. The first low-pass filter 111 is used to convert each phase clock signal into a first DC voltage; the first comparator 112 compares the first DC voltage with a first reference voltage and outputs a first comparison result; the first digital state machine 113 is used to adjust the rise time and / or fall time control word of the buffer for that phase clock according to the first comparison result.

[0040] Understandably, this application converts each phase clock signal into a DC voltage corresponding to its duty cycle distortion level, compares the DC voltage with a reference voltage, and then dynamically adjusts the rise time and / or fall time control word of the buffer through which the phase clock signal passes based on the comparison result, thereby gradually correcting the duty cycle distortion of the phase clock signal until it achieves the ideal 50% duty cycle.

[0041] Specifically, each phase clock signal can be filtered by a first low-pass filter 111. This first low-pass filter 111 can filter out the rapidly changing AC components in the clock signal, retaining only the DC component related to its average level. The voltage value of this DC component can characterize the duty cycle distortion of the phase clock signal. Subsequently, this DC voltage can be input to the non-inverting input of the first comparator 112 and compared with a first reference voltage. Here, the first reference voltage is defined as half of the power supply voltage Vdd, i.e., Vdd / 2. The first comparator 112 can output a first comparison result in the form of a high or low level based on the relative magnitude of the two voltages. The first digital state machine 113 is connected to the output of the first comparator 112 and the buffer corresponding to the phase clock signal. Therefore, based on the first comparison result, the rise time control word and / or fall time control word of the buffer can be selectively adjusted to change the edge transition characteristics of the phase clock signal, thereby adjusting the duration ratio of its high and low levels. For example, you can adjust the rise time control word of the buffer individually, or adjust the fall time control word of the buffer individually, or adjust both the rise time control word and the fall time control word of the buffer simultaneously.

[0042] During this process, when the DC voltage obtained by the phase clock signal after passing through the first low-pass filter 111 approaches Vdd / 2, it indicates that its duty cycle distortion has been basically eliminated, that is, the duty cycle of the phase clock signal approaches 50%. Therefore, the duty cycle calibration unit can sequentially repeat the above calibration process for each phase clock signal, including in-phase clock signals, out-of-phase clock signals, quadrature-phase clock signals, and quadrature-out-of-phase clock signals, thereby achieving systematic calibration of the overall duty cycle distortion of the multi-phase clock system.

[0043] In practical applications, the comparison result can be flipped as a benchmark for determining whether the duty cycle calibration is complete. For example, if the duty cycle of clock clkouti is less than 50%, then after passing through the first low-pass filter 111, its first DC voltage output is less than vdd / 2. Therefore, the first comparator 112 outputs a low level. Based on this, after receiving the low level, the first digital state machine 113 adjusts the fall time control word by a step length, increasing the duty cycle of clock clkouti. As the adjustment continues, the duty cycle of clock clkouti gradually increases until the result of the first comparator 112 jumps from a low output level to a high output level. This indicates that the duty cycle of clock clkouti was slightly lower than 50% in the previous adjustment, and after increasing by a step length, it jumps to slightly higher than 50%. Since the step length is generally set to the minimum scale, the difference between the duty cycle of clock clkouti at this point and 50% is negligible and can be considered precisely equal.

[0044] Similarly, if the duty cycle of clock clkouti is greater than 50%, then after passing through the first low-pass filter 111, its output DC voltage is greater than vdd / 2. Therefore, the first comparator 112 outputs a high level. Based on this, after receiving the high level, the first digital state machine 113 adjusts the fall time control word in reverse order of the first step length, so that the duty cycle of clock clkouti is reduced. When the result of the first comparator 112 changes from output high level to output low level, it means that the duty cycle of clock clkouti is equal to 50%.

[0045] It should be noted that, for a 4-phase quadrature clock, when only one duty cycle calibration unit is set, a time-division multiplexing method can be used to perform DCD calibration on the 4 clocks; when there are multiple duty cycle calibration units, such as 4, the 4 clocks can be synchronously calibrated simultaneously, improving calibration efficiency.

[0046] As one implementation method, please refer to Figure 2 The phase deviation calibration unit includes: a logic gate module 124, used to receive the rising edge of one clock and the falling edge of the other clock in two adjacent phases and generate a pulse signal; a second low-pass filter 121, connected to the logic gate module 124, used to convert the pulse signal into a second DC voltage; a second comparator 122, whose non-inverting input is connected to the second low-pass filter 121, used to compare the second DC voltage with one-quarter of the power supply voltage and output a second comparison result; and a second digital state machine 123, connected to the buffers and comparators of the clocks in two adjacent phases respectively, used to adjust the delay control word of the buffer of one clock according to the second comparison result.

[0047] Understandably, in a multiphase quadrature clock system, even if the duty cycle of each phase clock is accurately calibrated, a tiny time deviation between the clock edges of any two adjacent phases can still cause misalignment of subsequent circuits during sampling or switching, leading to data misjudgment, signal aliasing, or system malfunction.

[0048] To address this issue, in this embodiment, the logic gate module 124 only stably outputs a pulse signal with a fixed duty cycle when the rising edge of one clock and the falling edge of the other clock are aligned in time to the ideal position in two adjacent phases. This pulse signal is then converted into a DC voltage that strictly corresponds to its duty cycle through a low-pass filter, and compared with one-quarter of the power supply voltage as an absolute reference. This converts the time deviation into a voltage deviation signal, and finally, the time deviation is accurately zeroed by dynamically adjusting the delay control word of the buffer.

[0049] Specifically, the phase deviation calibration unit can begin phase deviation calibration after the duty cycle calibration of the multiphase quadrature clock is completed. At this time, two adjacent phase clocks can be selected, and the rising edge of one clock and the falling edge of the other clock can be input to the logic gate module 124. The logic gate module 124 provided in this application is a digital logic circuit that can be configured as an AND gate, that is, it outputs a high level only when both input signals are at a high level simultaneously, and outputs a low level at other times. Since the multiphase quadrature clock has a fixed phase relationship between the edges of each phase under ideal conditions, when the clock skew between the two is zero, the high level duration of the pulse signal output by the logic gate module 124 will roughly correspond to one-quarter of the entire cycle, that is, its high level ratio is basically 25%. If the time deviation between the two clock edges increases, the high level ratio will be greater than 25%; if the time deviation decreases, the high level ratio will be less than 25%. This pulse signal can be input to the second low-pass filter 121 to filter out its fast transition components and obtain a second DC voltage characterizing its high level ratio.

[0050] The second DC voltage can be input to the non-inverting input of the second comparator 122 and compared with the second reference voltage. The second reference voltage is defined as one-quarter of the power supply voltage Vdd, i.e., Vdd / 4. The second comparator 122 can output a second comparison result in the form of a high level or a low level based on the relative magnitude of the two voltages. The second digital state machine 123 can be connected to the output of the second comparator 122 and the buffers corresponding to the two clocks respectively. Based on the second comparison result, the delay control word of the buffer of at least one clock can be selectively adjusted to fine-tune the timing of its edge occurrence, thereby changing the high-level proportion of the output pulse of the logic gate module 124. During this process, when the second DC voltage approaches Vdd / 4, it indicates that the high-level proportion of the pulse signal has approached 25%, i.e., the time deviation between the edges of the two clocks has approached zero. Furthermore, the phase deviation calibration unit can sequentially repeat the above calibration process for all adjacent phase pairs in the multiphase quadrature clock, thereby ensuring that the time deviation between the clock edges of any two adjacent phases in the entire multiphase quadrature clock system approaches zero, significantly improving the timing consistency and operational reliability of the system in high-speed signal processing scenarios.

[0051] It should be noted that in one implementation, if the same hardware module is time-division multiplexed to calibrate the phase deviation between the clock edges of every two adjacent phases during phase deviation calibration (i.e., the system contains only one phase deviation calibration unit), the flipping of the comparison result can still be used as a marker that the phase deviation calibration is complete. For example, please refer to [link to relevant documentation]. Figure 3For clocks clkoutqb and clkoutqb, since the rising edges of clkoutqb differ by 270°, the high-level percentage of the pulse signal clkoutqb output by logic gate module 124 is 25% when skew is 0. If the delay between the rising edge of clkoutqb and the falling edge of clkoutqb is greater than 90°, the high-level percentage of the pulse signal output by logic gate module 124 is greater than 25%; conversely, if the delay between the rising edge of clkoutqb and the falling edge of clkoutqb is less than 90°, the high-level percentage of the pulse signal output by logic gate module 124 is less than 25%. The pulse signal output from logic gate module 124 is filtered by the second low-pass filter 121 to obtain a second DC voltage representing the high-level percentage of the pulse signal. This DC voltage and Vdd / 4 are compared by the second comparator 122. If the second comparator 122 outputs a high level, it indicates that the high-level percentage of the pulse signal is greater than 25%. The second digital state machine 123 will adjust the delay control word of at least one clock buffer according to the second step size. As the adjustment continues, the high level of the pulse signal gradually decreases. If the output of the second comparator 122 flips, it indicates that the duty cycle of the pulse signal is now equal to 25%. Similarly, if the second comparator 122 outputs a low level, the delay control word of at least one clock buffer needs to be adjusted in reverse according to the second step size until the output of the second comparator 122 changes from low to high.

[0052] As another implementation, continuous phase deviation calibration can be achieved when multiple hardware modules are used, each module calibrating the phase deviation between a pair of adjacent clock edges (i.e., the system includes multiple phase deviation calibration units). Specifically, based on the comparison result of the second DC voltage and the second reference voltage, the delay control word of the buffer for at least one of the two clock edges is adjusted by a set second step size until the comparison result flips. Furthermore, after each comparison result flip, the step of adjusting the delay control word of the buffer for at least one of the two clock edges in reverse order by a set second step size based on the comparison result of the second DC voltage and the second reference voltage is repeated.

[0053] For example, if the second comparator 122 outputs a high level, the second digital state machine 123 adjusts, and the duty cycle of the pulse signal output by the logic gate module 124 gradually decreases until the output of the second comparator 122 flips, changing from a high level to a low level. At this point, the second digital state machine 123 continues to adjust, causing the duty cycle of the pulse signal output by the logic gate module 124 to gradually increase until the output of the second comparator 122 flips again. The second digital state machine 123 then repeats this adjustment process continuously, ensuring that the phase deviation remains zero throughout the entire application.

[0054] It should be noted that during adjustment, since the delay control word of the buffer for the first clock path can be adjusted, as can the delay control word of the buffer for the second clock path, the adjustment will be relatively chaotic if the adjustment position of each pair of clocks is not fixed. Multiple rounds of adjustment are required to achieve zero phase deviation for the multi-phase quadrature clocks. Therefore, to achieve more precise adjustment, for each pair of adjacent clocks, a preceding clock and a following clock are defined. When the second digital state machine 123 performs adjustment, the delay control word of the buffer for the preceding clock in the two clock edges is adjusted by a set second step size; or the delay control word of the buffer for the following clock in the two clock edges is adjusted by a set second step size.

[0055] For example, in a four-phase quadrature clock system clkouti, clkoutib, clkoutq, and clkoutqb, when calibrating the phase deviation between clkouti and clkoutib, clkouti is defined as the preceding clock and clkoutib as the following clock. When the second digital state machine 123 is adjusted, only the delay control word of the following clock buffer is adjusted. Similarly, when calibrating the phase deviation between clkoutib and clkoutq, clkoutib is defined as the preceding clock and clkoutq as the following clock. When the second digital state machine 123 is adjusted, only the delay control word of the following clock buffer is adjusted, and so on. This configuration ensures that when the phase deviation of one pair of clocks is calibrated to 0, it will not affect the phase deviation of the next or previous pair of clocks, resulting in higher adjustment accuracy.

[0056] It should also be noted that the first step size can be equal to the second step size, and both are the smallest adjustment units. Based on this, if adjustments are fixed at either the first or second step size, each adjustment only increases or decreases the size by one step, thus consuming a significant amount of time per adjustment. Therefore, this application utilizes a combination of coarse and fine adjustments to achieve rapid calibration of the phase deviation.

[0057] Specifically, firstly, the delay control word of the buffer for at least one of the two clock edges is adjusted by a first sub-step, where the first sub-step is the increment of the value of the delay control word changed by one adjustment. The adjustment process continues until the comparison result generated by the two clock edges flips. Then, the delay control word of the buffer for at least one of the two clock edges is adjusted in the opposite direction by a second sub-step, where the second sub-step is the decrement of the value of the delay control word changed by one adjustment, and the value of the second sub-step is less than the value of the aforementioned first sub-step. The adjustment process continues until the comparison result flips again.

[0058] A bidirectional probing mechanism with a first substep size greater than the second substep size is employed. This allows for rapid traversal of larger deviation ranges and enables higher-resolution positioning near the synchronization point, thereby improving the final phase alignment accuracy while maintaining calibration efficiency. Alternatively, a binary adjustment method can be introduced for coarse adjustment. In this method, the first substep size is not customized; adjustments are made using a binary approach each time. After multiple rounds of adjustments, the approximate range where the phase deviation is calibrated to 0 can be quickly identified. Then, the second substep size, the smallest adjustment unit, is used for step-by-step adjustments, allowing for precise calibration of the phase deviation to 0.

[0059] Furthermore, to save on hardware costs, the duty cycle calibration unit and the phase deviation calibration unit can share the same low-pass filter, comparator, and digital state machine. That is, during duty cycle calibration, the hardware architecture of the state machine, comparator, and low-pass filter is first used to adjust each clock path. After duty cycle calibration is completed, the same hardware architecture of the state machine, comparator, and low-pass filter is then used to perform phase deviation calibration.

[0060] Based on the above implementation, this application also provides a calibration method for a multiphase quadrature clock. This calibration method corresponds to the aforementioned calibration system for a multiphase quadrature clock. Please refer to [link to relevant documentation]. Figure 4 The method includes: S102, each phase clock in the multi-phase quadrature clock is passed through the first low-pass filter 111 to obtain the first DC voltage, and the rise time and / or fall time control word of the buffer of the phase clock is adjusted according to the comparison result of the first DC voltage and the first reference voltage until the first DC voltage is equal to the first reference voltage, so as to realize the duty cycle calibration of each phase clock.

[0061] S104, the clock edges of two adjacent phases are sequentially input to the logic gate module 124 to generate pulse signals. The pulse signals are passed through the second low-pass filter 121 to obtain the second DC voltage. Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted until the second DC voltage is equal to the second reference voltage, so as to realize the phase deviation calibration between the clock edges of adjacent phases.

[0062] The step of adjusting the rise time and / or fall time control word of the phase clock buffer according to the comparison result of the first DC voltage and the first reference voltage until the first DC voltage is equal to the first reference voltage includes: Based on the comparison result between the first DC voltage and the first reference voltage, the rise time and / or fall time control word of the buffer of the phase clock are adjusted according to the set first step length until the comparison result flips.

[0063] In one implementation, when the same hardware module is time-division multiplexed to calibrate the phase deviation between the clock edges of every two adjacent phases, the step of adjusting the delay control word of the buffer of at least one of the two clock edges until the second DC voltage is equal to the second reference voltage, based on the comparison result of the second DC voltage and the second reference voltage, includes: Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted by a set second step size until the comparison result flips.

[0064] Each pair of adjacent clocks includes a preceding clock and a following clock. The steps for adjusting the delay control word of the buffer for at least one of the two clock edges according to the set second step size include: Adjust the delay control word of the buffer for the preceding clock in the two clock edges according to the set second step size; or Adjust the delay control word of the buffer for the subsequent clock between the two clock edges according to the set second step size.

[0065] In another implementation, when multiple hardware modules are used, and each hardware module is used to calibrate the phase deviation between a pair of adjacent clock edges, the step of adjusting the delay control word of the buffer of at least one of the two clock edges until the second DC voltage is equal to the second reference voltage, based on the comparison result of the second DC voltage and the second reference voltage, includes: Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted by a set second step size until the comparison result flips. After each comparison result flips, the step of adjusting the delay control word of the buffer of at least one of the two clock edges in reverse according to the comparison result of the second DC voltage and the second reference voltage by a set second step size is repeated.

[0066] Furthermore, in order to achieve rapid phase deviation calibration, the step of adjusting the delay control word of the buffer for at least one of the two clock edges according to the set second step size includes: Adjust the delay control word of the buffer for at least one of the two clock edges according to the first sub-step size until the comparison result flips; Adjust the delay control word of the buffer for at least one of the two clock edges in reverse order of the second substep size until the comparison result flips again; wherein the first substep size is greater than the second substep size.

[0067] In summary, this application provides a calibration method and system for multi-phase quadrature clocks. First, each phase of the multi-phase quadrature clock is passed through a first low-pass filter to obtain a first DC voltage. Based on the comparison between the first DC voltage and a first reference voltage, the rise time and / or fall time control word of the buffer for that phase clock is adjusted until the first DC voltage equals the first reference voltage, thus achieving duty cycle calibration for each phase clock. Then, the clock edges of two adjacent phases are sequentially input to a logic gate module to generate pulse signals. These pulse signals are passed through a second low-pass filter to obtain a second DC voltage. Based on the comparison between the second DC voltage and a second reference voltage, the delay control word of the buffer for at least one of the two clock edges is adjusted until the second DC voltage equals the second reference voltage, thus achieving phase deviation calibration between adjacent phase clock edges. Because this application calibrates each phase clock separately first, it ensures that each phase clock meets the standard requirements. After duty cycle calibration, phase deviation calibration between multiple clocks is performed, ensuring that the phase deviation is equal to 0, achieving more accurate calibration.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0069] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A calibration method for a multiphase quadrature clock, characterized in that, The method includes: Each phase clock in the multi-phase quadrature clock is passed through a first low-pass filter to obtain a first DC voltage. Based on the comparison result of the first DC voltage and the first reference voltage, the rise time and / or fall time control word of the buffer of the phase clock is adjusted until the first DC voltage is equal to the first reference voltage, so as to achieve duty cycle calibration of each phase clock. The clock edges of two adjacent phases are sequentially input to the logic gate module to generate a pulse signal. The pulse signal is passed through a second low-pass filter to obtain a second DC voltage. Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted until the second DC voltage is equal to the second reference voltage, so as to achieve phase deviation calibration between the clock edges of adjacent phases.

2. The calibration method for a multiphase quadrature clock according to claim 1, characterized in that, The step of adjusting the rise time and / or fall time control word of the buffer of the phase clock according to the comparison result of the first DC voltage and the first reference voltage until the first DC voltage is equal to the first reference voltage includes: Based on the comparison result between the first DC voltage and the first reference voltage, the rise time and / or fall time control word of the buffer of the phase clock are adjusted according to the set first step length until the comparison result is flipped.

3. The calibration method for a multiphase quadrature clock according to claim 1, characterized in that, When time-division multiplexing the same hardware module to calibrate the phase deviation between the clock edges of every two adjacent phases, the step of adjusting the delay control word of the buffer of at least one of the two clock edges until the second DC voltage is equal to the second reference voltage, based on the comparison result of the second DC voltage and the second reference voltage, includes: Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted by a set second step size until the comparison result flips.

4. The calibration method for a multiphase quadrature clock according to claim 3, characterized in that, Each pair of adjacent clocks includes a preceding clock and a following clock. The steps for adjusting the delay control word of the buffer for at least one of the two clock edges according to the set second step size include: Adjust the delay control word of the buffer for the preceding clock in the two clock edges according to the set second step size; or Adjust the delay control word of the buffer for the subsequent clock between the two clock edges according to the set second step size.

5. The calibration method for a multiphase quadrature clock according to claim 1, characterized in that, When multiple hardware modules are used, and each hardware module is used to implement phase deviation calibration between a pair of adjacent clock edges, the step of adjusting the delay control word of the buffer of at least one of the two clock edges until the second DC voltage is equal to the second reference voltage, based on the comparison result of the second DC voltage and the second reference voltage, includes: Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted by a set second step size until the comparison result is flipped. After each comparison result is flipped, the step of adjusting the delay control word of the buffer of at least one of the two clock edges in reverse by a set second step size based on the comparison result of the second DC voltage and the second reference voltage is repeated.

6. The calibration method for a multiphase quadrature clock according to any one of claims 3-5, characterized in that, The steps for adjusting the delay control word of the buffer for at least one of the two clock edges according to the set second step size include: Adjust the delay control word of the buffer for at least one of the two clock edges according to the first sub-step size until the comparison result flips; The delay control word of the buffer for at least one of the two clock edges is adjusted in reverse according to the second sub-step size until the comparison result flips again; wherein the first sub-step size is greater than the second sub-step size.

7. A calibration system for a multiphase quadrature clock, characterized in that, The system includes: The duty cycle calibration unit is used to pass each phase clock in the multi-phase quadrature clock through a first low-pass filter to obtain a first DC voltage, and adjust the rise time and / or fall time control word of the buffer of the phase clock according to the comparison result of the first DC voltage and the first reference voltage, until the first DC voltage is equal to the first reference voltage, so as to realize the duty cycle calibration of each phase clock. The phase deviation calibration unit is used to sequentially input the clock edges of two adjacent phases to the logic gate module to generate a pulse signal after the duty cycle calibration is completed. The pulse signal is passed through a second low-pass filter to obtain a second DC voltage. Based on the comparison result between the second DC voltage and the second reference voltage, the delay control word of the buffer of at least one of the two clock edges is adjusted until the second DC voltage is equal to the second reference voltage, so as to realize the phase deviation calibration between the clock edges of adjacent phases.

8. The calibration system for a multiphase quadrature clock according to claim 7, characterized in that, The duty cycle calibration unit includes: A first low-pass filter is used to convert each phase clock signal into a first DC voltage; The first comparator has its non-inverting input connected to the first low-pass filter and is used to compare the first DC voltage with the first reference voltage and output a first comparison result. The first digital state machine is connected to the output of the first comparator and the buffer of each clock phase, and is used to adjust the rise time and / or fall time control word of the buffer of the clock phase according to the first comparison result.

9. The calibration system for a multiphase quadrature clock according to claim 7, characterized in that, The phase deviation calibration unit includes: The logic gate module is used to receive the rising edge of one clock and the falling edge of the other clock from two adjacent phases and generate a pulse signal. A second low-pass filter is connected to the logic gate module and is used to convert the pulse signal into a second DC voltage; The second comparator, whose non-inverting input is connected to the second low-pass filter, is used to compare the second DC voltage with one-quarter of the power supply voltage and output the second comparison result. The second digital state machine is connected to the buffers of two adjacent clock phases and the comparator, and is used to adjust the delay control word of one of the clock buffers according to the second comparison result.

10. The calibration system for a multiphase quadrature clock according to claim 7, characterized in that, The duty cycle calibration unit and the phase deviation calibration unit share the same low-pass filter, comparator, and digital state machine.

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