Deposition mask, method of manufacturing the deposition mask, display panel manufactured by using the deposition mask, and electronic device manufactured by using the deposition mask

Abstract

A deposition mask, a method for manufacturing the deposition mask, a display panel, and an electronic device are provided. The deposition mask can include a mask base having a cell opening, a film on (e.g., disposed on) the mask base and having a pixel opening in communication with the cell opening, and a mask alignment key on (e.g., disposed on) the mask base. The mask alignment key can include a pattern region and a peripheral region around (e.g., surrounding) the pattern region, and the pattern region can include a surface modification region having a greater surface roughness than the peripheral region.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0194116, filed on December 23, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a deposition mask, a method for manufacturing the deposition mask, a deposition apparatus including the deposition mask, a display panel manufactured using the deposition mask, and an electronic device manufactured using the deposition mask. Background Technology

[0003] Wearable devices in the form of glasses or helmets have been developed that focus images at a short distance in front of the user's eyes. For example, such wearable devices may include head-mounted displays (HMDs) and / or augmented reality (AR) glasses. These devices can provide users with augmented reality (AR) and / or virtual reality (VR) visual experiences.

[0004] To enable users to comfortably use wearable devices such as HMDs or AR glasses for extended periods without experiencing dizziness, a display resolution of approximately 3000 pixels per inch (PPI) or higher is desired or even required. To meet this demand, organic light-emitting diodes on silicon (OLEDoS) technology has emerged as a promising solution. OLEDoS involves forming organic light-emitting diodes (OLEDs) on a semiconductor silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) elements.

[0005] To manufacture display panels with a resolution of approximately 3000 PPI or higher, a high-resolution deposition mask is desired or even required. For example, such a deposition mask can be manufactured by forming a film with multiple pixel openings on a substrate such as a silicon wafer and then partially removing the substrate to form cell openings that expose the pixel openings.

[0006] During the deposition process for forming the light-emitting layer of a display panel, a backplane substrate can be arranged or positioned on a deposition mask. Then, vapor-deposited material from a deposition source can be deposited onto the backplane substrate through pixel openings in the deposition mask. Substrate alignment bonds can be formed on the backplane substrate, and mask alignment bonds can be formed on the deposition mask. A camera can be used to obtain positional information of the substrate alignment bonds and mask alignment bonds, and the backplane substrate can be aligned with the deposition mask based on this information. Summary of the Invention

[0007] One or more aspects of this disclosure relate to a deposition mask, a method of manufacturing the deposition mask, a deposition apparatus including the deposition mask, a display panel manufactured using the deposition mask, and an electronic device manufactured using the deposition mask, the deposition mask including a mask alignment key that improves its recognition rate.

[0008] However, one or more embodiments of this disclosure are not limited to those set forth herein. One or more embodiments of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description thereof.

[0009] In one or more embodiments of this disclosure, the deposition mask may include: a mask substrate having cell openings; a film disposed on the mask substrate and having pixel openings communicating with the cell openings; and a mask alignment key disposed on the mask substrate. The mask alignment key may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, and the patterned region may include a surface-modified region having a larger surface roughness than the peripheral region.

[0010] In one or more embodiments, the patterned region may have a recess formed in a surface portion of the mask substrate, and the surface modification region may be formed in a bottom surface portion of the recess.

[0011] In one or more embodiments, the recess may have a width that gradually decreases from the surface of the mask substrate toward the surface modification region.

[0012] In one or more embodiments, the deposition mask may further include an intermediate inorganic membrane disposed between the mask substrate and the film. The intermediate inorganic membrane may have bond openings that expose the patterned regions.

[0013] In one or more embodiments, the surface roughness of the surface-modified region can be in the range of about 50 nm to about 1 μm.

[0014] According to some embodiments, the membrane may include passivation regions disposed on the patterned area.

[0015] In one or more embodiments, the deposition mask may further include a passivation film disposed on the mask substrate and the mask alignment bond. The film may be disposed on the passivation film.

[0016] In one or more embodiments, the mask substrate may have key openings that expose the mask alignment keys.

[0017] In one or more embodiments, the mask alignment key may include a surface layer of a mask substrate, the surface layer including a patterned region and a peripheral region, and the key opening may be configured to expose the surface layer.

[0018] In one or more embodiments, the surface layer may include an etch stop region having an area larger than the bond opening, and the bond opening may be configured to expose the etch stop region.

[0019] In one or more embodiments, the etch stop region may include one or more group III impurities.

[0020] In one or more embodiments of this disclosure, the deposition mask may further include an intermediate inorganic film disposed between the mask substrate and the film. The patterned region may have a recess formed in a surface portion of the intermediate inorganic film, and the surface-modified region may be formed in a bottom surface portion of the recess.

[0021] In one or more embodiments, the deposition mask may further include etch stop regions formed in a surface layer of the mask substrate. The mask substrate may have key openings that expose the etch stop regions.

[0022] In one or more embodiments, the patterned region may have a recess formed in a surface portion of the film, and the surface-modified region may be formed in a bottom surface portion of the recess.

[0023] In one or more embodiments, the deposition mask may further include a passivation film disposed on the film and the mask alignment bond.

[0024] In one or more embodiments, the mask substrate may have key openings that expose the mask alignment keys.

[0025] In one or more other embodiments of this disclosure, the deposition mask may include: a mask substrate having cell openings; a film disposed on the mask substrate and having pixel openings communicating with the cell openings; and a mask alignment key disposed on the mask substrate. The mask alignment key may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, the patterned region having at least one recess formed in a surface portion of the mask substrate, and said at least one recess may be defined by inclined inner surfaces connected to each other.

[0026] In one or more other embodiments of this disclosure, a method of manufacturing a deposition mask may include: forming mask alignment keys on a mask substrate; forming a film on the mask substrate, the film having pixel openings; and forming cell openings through the mask substrate, the cell openings communicating with the pixel openings. The mask alignment keys may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, and the patterned region may include a surface-modified region having a larger surface roughness than the peripheral region.

[0027] In one or more embodiments, the step of forming a mask alignment key may include forming a patterned region in a surface portion of a mask substrate. The step of forming the patterned region may include: forming a recess in a surface portion of the mask substrate; and forming a surface modification region in a bottom surface portion of the recess.

[0028] In one or more embodiments, the recessed and surface-modified regions can be formed by a reactive ion etching process.

[0029] In one or more embodiments, the reactive ion etching process may include the steps of: forming a polymer layer by using a passivation gas; partially removing the polymer layer by using a sputtering gas; and removing a surface portion of the mask substrate by using a reactive gas.

[0030] In one or more embodiments, the step of partially removing the polymer layer can be performed in a shorter time than the steps of forming the polymer layer and removing the surface portion of the mask substrate.

[0031] In one or more embodiments, a step of partially removing the polymer layer may be performed to partially retain the polymer layer on the patterned area.

[0032] In one or more embodiments, the recessed and surface-modified regions can be formed by a metal-assisted chemical etching process.

[0033] In one or more embodiments, a metal-assisted chemical etching process can be performed by utilizing an etchant comprising metal catalyst particles.

[0034] In one or more embodiments, the recess may be formed with a width that gradually decreases from the surface of the mask substrate toward the surface modification region.

[0035] In one or more embodiments, the method may further include: forming an intermediate inorganic film on a mask substrate; and forming bond openings by partially removing the intermediate inorganic film, the bond openings exposing the patterned regions.

[0036] In one or more embodiments, the patterned region may have a recess formed in a surface portion of the mask substrate, the surface-modified region may be formed in a bottom surface portion of the recess, and the recess and the surface-modified region may be formed by a metal-assisted chemical etching process using an intermediate inorganic film as an etching mask.

[0037] In one or more embodiments, the membrane may include a passivation region on the mask alignment key.

[0038] In one or more embodiments, the method may further include forming a passivation film on a mask substrate and a mask alignment key, and the film may be on the passivation film.

[0039] In one or more embodiments, the method may further include forming a key opening by partially removing a mask substrate, the key opening aligning the mask with the exposed key.

[0040] In one or more embodiments, the mask alignment key may include a surface layer of a mask substrate, the surface layer including a patterned region and a peripheral region, and the key opening may be formed to expose the surface layer.

[0041] In one or more embodiments, the method may further include forming an etch stop region in the surface layer, the etch stop region having an area larger than the bond opening, and the bond opening being formed to expose the etch stop region.

[0042] In one or more embodiments, the etch stop region may be formed by an ion implantation process and may include one or more group III impurities.

[0043] In one or more embodiments, the method may further include forming an intermediate inorganic film on a mask substrate, and the step of forming mask alignment bonds may include forming a surface-modified region by partially removing the intermediate inorganic film.

[0044] In one or more embodiments, the method may further include: forming an etch stop region in a surface layer of a mask substrate, the etch stop region overlapping a mask alignment bond; and forming a bond opening by partially removing the mask substrate, the bond opening exposing the etch stop region.

[0045] In one or more embodiments, the step of forming mask alignment keys may include forming surface-modified regions by partially removing the film.

[0046] In one or more embodiments, the method may further include forming a passivation film on the film and mask alignment bond.

[0047] In one or more other embodiments of this disclosure, a method may include: forming a mask alignment key on a mask substrate; forming a film on the mask substrate having pixel openings; and forming a cell opening through the mask substrate, the cell opening communicating with the pixel opening. The mask alignment key may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, the patterned region having at least one recess formed in a surface portion of the mask substrate, and said at least one recess may be defined by inclined inner surfaces connected to each other. The method may be a method for manufacturing a deposition mask.

[0048] In one or more other embodiments of this disclosure, a deposition apparatus may include: a deposition source for providing deposition material; a substrate chuck for supporting a substrate facing the deposition source; and a mask chuck disposed between the deposition source and the substrate chuck and supporting a deposition mask facing the substrate. The deposition mask may include: a mask substrate having cell openings; a film disposed on the mask substrate and having pixel openings communicating with the cell openings; and a mask alignment key disposed on the mask substrate. The mask alignment key may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, and the patterned region may include a surface-modified region having a larger surface roughness than the peripheral region.

[0049] In one or more embodiments, the deposition apparatus may further include: an illumination section that provides light capable of being transmitted through the substrate and the deposition mask; and a camera that detects the light transmitted through the substrate and the deposition mask.

[0050] In one or more embodiments, the deposition apparatus may further include: an illumination section for providing light through a deposition mask to a substrate; and a camera for detecting light reflected from the substrate and transmitted through the deposition mask.

[0051] In one or more other embodiments of this disclosure, the display panel may include: a substrate; and a plurality of light-emitting layers deposited on the substrate using a deposition mask. The deposition mask may include: a mask substrate having cell openings; a film disposed on the mask substrate and having pixel openings communicating with the cell openings; and a mask alignment key disposed on the mask substrate. The mask alignment key may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, and the patterned region may include a surface-modified region having a larger surface roughness than the peripheral region.

[0052] In one or more other embodiments of this disclosure, the electronic device may include a display panel. The display panel may include: a substrate; and a plurality of light-emitting layers deposited on the substrate using a deposition mask. The deposition mask may include: a mask substrate having cell openings; a film disposed on the mask substrate and having pixel openings communicating with the cell openings; and mask alignment keys disposed on the mask substrate. The mask alignment keys may include a patterned region and a peripheral region surrounding (e.g., around) the patterned region, and the patterned region may include a surface-modified region having a larger surface roughness than the peripheral region.

[0053] In one or more embodiments, the electronic device may also include at least one selected from processor, memory, and power module (e.g., power supply).

[0054] According to one or more embodiments of the present disclosure as described above, a mask alignment key may include a surface-modified region formed by an etching process. Light incident on the surface-modified region can be scattered and / or refracted by the surface-modified region, thus the surface-modified region can be more clearly displayed in an image of the mask alignment key obtained by a camera. As a result, the recognition rate of the mask alignment key can be significantly improved. For example, by utilizing a metal-assisted chemical etching process in conjunction with an intermediate inorganic film as an etching mask to form the surface-modified region, the resulting surface topology can be precisely controlled to achieve enhanced optical scattering properties. This makes it possible to enhance the contrast between the patterned region and the surrounding peripheral region when imaging under various illumination conditions, such as backlighting and / or reflected illumination. Therefore, the alignment accuracy between the deposited mask and the substrate during the deposition process can be improved, thereby contributing to higher resolution and yield in the manufacture of display panels, such as display panels requiring ultra-fine pixel arrangements, such as OLEDoS-type microdisplays.

[0055] Other features and embodiments may be apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0056] The above and other aspects and features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in more detail, in which: Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure; Figure 2 This is a schematic diagram of an electronic device according to one or more suitable embodiments of the present disclosure; Figure 3 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure; Figure 4 It is shown Figure 3 Block diagram of the display device shown; Figure 5 It is shown Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown; Figure 6 It is shown Figure 3 A schematic floor plan of an example of a display panel shown; Figure 7 It is shown Figure 6 A schematic enlarged plan view of an example of the display area shown; Figure 8 It is shown Figure 6 A schematic enlarged plan view of another example of the display area shown; Figure 9 It shows along Figure 7A schematic cross-sectional view of an example display panel, shown by line I1-I1'. Figure 10 It shows along Figure 7 A schematic cross-sectional view of another example of a display panel, shown by line I1-I1'. Figure 11 It shows along Figure 7 A schematic cross-sectional view of another example of a display panel, as shown by line I1-I1'. Figure 12 This is a schematic perspective view showing an example of a head-mounted display; Figure 13 It is shown Figure 12 A schematic exploded perspective view of the head-mounted display shown; Figure 14 This is a schematic perspective view showing another example of a head-mounted display; Figure 15 This is a schematic diagram illustrating a deposition apparatus according to one or more embodiments of the present disclosure; Figure 16 It is used to describe Figure 15 A schematic bottom view of the backplate base shown; Figure 17 It is used to describe Figure 15 A schematic plan view of the deposition mask shown; Figure 18 It is used to describe Figure 17 A schematic enlarged plan view of the mask unit region shown; Figure 19 It is along Figure 18 A schematic cross-sectional view taken by line I2-I2' shown; Figure 20 It is used to describe Figure 15 A schematic front view of the base chuck and mask chuck shown; Figure 21 It is used to describe Figure 16 A schematic bottom view of the base alignment key shown; Figure 22 It is used to describe Figure 17 A schematic cross-sectional view of the mask alignment key shown; Figure 23 It is used to describe Figure 17 A schematic plan view of the mask alignment key shown; Figure 24 It is used to describe Figure 15 A schematic cross-sectional view of the camera and lighting components shown; Figure 25 It is used to describe by Figure 24A schematic diagram of an image obtained by the camera shown; Figure 26 It is used to describe Figure 22 A schematic enlarged cross-sectional view of the patterned area shown; Figures 27 to 29 It is used to describe the formation Figure 26 A schematic enlarged cross-sectional view of the method for depicting the recessed and surface-modified regions shown; Figure 30 It is used to describe Figure 26 A schematic enlarged cross-sectional view of another example of the patterned area shown; Figure 31 It is used to describe Figure 26 A schematic enlarged cross-sectional view of another example of the patterned area shown; Figure 32 It is used to describe Figure 26 A schematic enlarged cross-sectional view of another example of the patterned area shown; Figure 33 It is used to describe Figure 22 A schematic cross-sectional view of another example of the deposition mask shown; Figure 34 It is used to describe Figure 22 A schematic cross-sectional view of another example of the deposition mask shown; Figure 35 It is used to describe Figure 22 A schematic cross-sectional view of another example of the deposition mask shown; Figure 36 It is used to describe Figure 24 A schematic cross-sectional view of another example of the camera and lighting components shown; Figure 37 It is used to describe Figure 22 A schematic cross-sectional view of another example of a mask alignment key shown; Figure 38 It is used to describe Figure 22 A schematic cross-sectional view of another example of the mask alignment key shown; and Figures 39 to 45 This is a schematic cross-sectional view used to describe a method of manufacturing a deposition mask according to one or more embodiments of the present disclosure. Detailed Implementation

[0057] This disclosure will now be described more fully below with reference to the accompanying drawings, in which one or more suitable embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0058] It will also be understood that if a component (e.g., element, region, layer, part, section and / or area, etc.) is referred to as "on" another component, "formed on" another component, "disposed on" another component, "connected to" another component, "connected to" another component, or "integrated into" another component (e.g., when a component (e.g., element, region, layer, part, section and / or area, etc.) is referred to as "on" another component, "formed on" another component, "disposed on" another component, "connected to" another component, "connected to" another component, or "integrated into" another component), then the component may be directly on the other component, directly formed on the other component, directly disposed on the other component, directly connected to the other component, directly connected to the other component, or directly integrated into the other component, and / or indirectly on the other component, indirectly formed on the other component, indirectly disposed on the other component, indirectly connected to the other component, indirectly connected to the other component, or indirectly integrated into the other component with an intermediary component therebetween. For example, in the specification, if a component is electrically connected to another component (e.g., when a component is electrically connected to another component), then the component may be directly electrically connected to the other component and / or indirectly electrically connected to the other component with an intermediary component in between. However, "directly connected / directly coupled" means that one component is directly connected to or directly coupled to another component without any intermediate component. Similarly, other expressions describing relationships between components (such as "between," "immediately between," "adjacent to," and "directly adjacent to") can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers. Throughout the specification, the same reference numerals denote the same components.

[0059] It will be understood that although the terms “first” and / or “second” may be used herein to describe one or more suitable elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the publicly stated teachings, the first element under discussion may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended (e.g., simultaneously) to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” can include any and all combinations of one or more of the associated listed items. It will also be understood that, if used in this specification (e.g., when used in this specification), the terms “comprising / including / having” and variations thereof indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0061] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used here to describe the relationship of one element relative to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device besides those depicted in the figures. For example, if the device in one of the figures is flipped, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, depending on the specific orientation of the figure, the term “below” may (e.g., simultaneously) include both “below” and “above” orientations. Similarly, if the device in one of the figures is flipped, an element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the term “below” or “under” may (e.g., simultaneously) include both “above” and “below” orientations.

[0062] Features of each of the disclosed one or more suitable embodiments may be combined in part or in whole with each other and may be technically interlocked with each other, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0063] As used herein, taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), “about” or “approximately” includes the stated value and refers to a range of acceptable deviations from the particular value as determined by a person skilled in the art. For example, “about” may refer to one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, it should be understood that even if the terms “about,” “approximately,” or “basically” are not expressly stated in a given claim element, the scope of such claim element is intended to include non-substantial variations or variations as understood by a person skilled in the art. For example, the numerical values ​​and ranges provided herein are intended to include tolerances and measurement uncertainties that would be recognized by a person skilled in the art, and the claims should be interpreted accordingly to cover such equivalents.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and in this disclosure, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0065] Example embodiments are described herein with reference to cross-sectional views as idealized embodiments. Therefore, variations in the shapes shown in the illustrations will be expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, due to manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the given claims and their equivalents.

[0066] The term “may” will be understood to mean “one or more embodiments of this disclosure,” some of which include the described elements, and some of which exclude the described elements and / or include alternative elements. Similarly, alternative terms such as “or” all include “one or more embodiments of this disclosure” for the corresponding listed items.

[0067] In this document, “consisting essentially of” means that any additional components will not substantially affect the chemical, physical, optical, or electrical properties of the semiconductor film.

[0068] Furthermore, in this specification, the phrase "in a plane" or "plan view" refers to a view of the target portion from the top, and the phrase "in a cross-section" refers to a view of the cross-section formed by vertically cutting the target portion from the side.

[0069] In this disclosure, the term "combination thereof" may refer to mixtures, stacks, complexes, copolymers, alloys, blends and / or reaction products.

[0070] In the following description, embodiments will be described in more detail with reference to the accompanying drawings.

[0071] The display device according to one or more embodiments of the present disclosure can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments of the present disclosure may include the aforementioned display device, and in addition to the display device, may also include modules and / or devices with additional functions.

[0072] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0073] Reference Figure 1 An electronic device 10 according to one or more embodiments of the present disclosure may include a display module 11 (e.g., a display), a processor 12, a memory 13, and a power module 14 (e.g., a power supply).

[0074] The processor 12 may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0075] The memory 13 can store data information for the operation of the processor 12 or the display module 11 (e.g., data information that may be needed to operate the processor 12 or the display module 11). If the processor 12 executes an application stored in the memory 13 (e.g., when the processor 12 executes an application stored in the memory 13), image data signals and / or input control signals can be sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0076] The power module 14 may include a power supply device / module (such as a power adapter or battery) and a power conversion device / module that converts the power supplied by the power supply device / module to generate power for the operation of the electronic device 10 (e.g., the power that may be needed to operate the electronic device 10).

[0077] At least one component selected from one or more embodiments of the present disclosure of the electronic device 10 may be included in the display device 20 according to one or more embodiments of the present disclosure (see Figure 3 Furthermore, some devices / modules that are functionally included in a single device / module may be included in the display device 20, while other devices / modules may be disposed separately from the display device 20. For example, the display device 20 may include a display module 11, and the processor 12, memory 13, and / or power module 14 may be disposed in the electronic device 10 as other devices rather than the display device 20.

[0078] Figure 2 This is a schematic diagram of an electronic device according to one or more suitable embodiments of the present disclosure.

[0079] Reference Figure 2 The display device 20 according to one or more embodiments of the present disclosure can include not only image display electronics (such as smartphones 10_1a, tablet PCs (personal computers) 10_1b, laptop computers 10_1c, TVs 10_1d and / or desktop monitors 10_1e), but also wearable electronics (such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c) that include display devices / modules (circuitets) and / or automotive electronics 10_3 that include display devices / modules (such as CIDs (central information displays) and / or interior mirror displays arranged on the dashboard, central instrument panel and / or instrument panel of a car).

[0080] Figure 3 This is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure. Figure 4 It is shown Figure 3 Block diagram of the display device shown.

[0081] Reference Figure 3 and Figure 4The display device 20 according to one or more embodiments can be a device for displaying moving images and / or still images. The display device 20 according to one or more embodiments can be used as an electronic device 10 or a display module 11 of an electronic device 10. For example, the display device 20 according to one or more embodiments can be applied to portable electronic devices (such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs), etc.). The display device 20 according to one or more embodiments can be applied as a display module 11 of an electronic device 10, such as a television, laptop computer, monitor, billboard, and / or Internet of Things (IoT) terminal. The display device 20 according to one or more embodiments can be applied to an electronic device 10 (such as a smartwatch, watch phone, and / or a head-mounted display (HMD) for realizing virtual reality and augmented reality, etc.).

[0082] The display device 20 according to one or more embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (or timing controller) 400 and / or a power supply circuit (or power supply unit) 500.

[0083] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral, having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or a circle with a set or predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 20 may be consistent with the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0084] Display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, scan driver 610, emission driver 620, and / or data driver 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0085] Multiple pixels (PX) can be arranged in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix along a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and be arranged along the first direction (DR1).

[0086] Multiple scan lines SL may include multiple write scan lines GWL, multiple control scan lines GCL, and / or multiple bias scan lines GBL. Multiple emit control lines EL may include multiple first emit control lines ECL1 and / or multiple second emit control lines ECL2.

[0087] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 5 The multiple pixel transistors shown can be formed and arranged on a semiconductor substrate SSUB using semiconductor processes (see...). Figure 9 For example, the multiple pixel transistors of a pixel PX may include complementary metal-oxide-semiconductor (CMOS) (e.g., formed of complementary metal-oxide-semiconductor (CMOS)), but this disclosure is not limited thereto.

[0088] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and / or a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and may emit light from the light-emitting element according to the data voltage.

[0089] The scan driver 610, the transmit driver 620, and / or the data driver 700 may be arranged in the non-display area NDA.

[0090] Scan driver 610 may include multiple scan transistors, and emitter driver 620 may include multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be fabricated on a semiconductor substrate SSUB (see [link to semiconductor diagram]) using semiconductor processes. Figure 9 On (for example, it can be done through semiconductor processes on a semiconductor substrate SSUB (see...) Figure 9 (A plurality of scanning transistors and a plurality of light-emitting transistors are formed on the CMOS). For example, the plurality of scanning transistors and the plurality of light-emitting transistors may include CMOS (e.g., formed by CMOS), but this disclosure is not limited thereto.

[0091] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and / or a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0092] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 may generate a first transmit control signal based on the transmit timing control signal ECS and output them sequentially to a first transmit control line ECL1. The second transmit control driver 622 may generate a second transmit control signal based on the transmit timing control signal ECS and output them sequentially to a second transmit control line ECL2.

[0093] The data driver 700 may include multiple data transistors, and the multiple data transistors can be fabricated on a semiconductor substrate SSUB using semiconductor processes (see [link to SSUB]). Figure 9 On (for example, it can be done through semiconductor processes on a semiconductor substrate SSUB (see...) Figure 9 (Multiple data transistors are formed on the CMOS). For example, the multiple data transistors may include CMOS (e.g., formed by CMOS), but this disclosure is not limited thereto.

[0094] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 can convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS and output the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0095] The heat dissipation layer 200 may be stacked on the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 may be used to dissipate or reduce the heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity, such as silver (Ag), copper (Cu), and / or aluminum (Al), or may be made of graphite.

[0096] Circuit board 300 can be electrically connected to the first pad (also known as solder pad or solder pad) portion of display panel 100 PDA1 (see [link to PDA1]) using conductive adhesive components such as anisotropic conductive film. Figure 6 Multiple first pads PD1 (see) Figure 6 Circuit board 300 may be a flexible printed circuit board and / or a flexible film with flexible materials. Although circuit board 300 is in Figure 3 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the first pad portion PDA1 of the display panel 100 (see [reference]) using conductive adhesive members. Figure 6 Multiple first pads PD1 (see) Figure 6 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0097] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source (e.g., an external source). The timing control circuit 400 can be used to generate a scan timing control signal SCS, a transmit timing control signal ECS, and / or a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 400 can be used to output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also be used to output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0098] The power supply circuit 500 can be used to generate multiple panel drive voltages based on a power supply voltage from an external source (e.g., an external power source). For example, the power supply circuit 500 can be used to generate a first drive voltage VSS, a second drive voltage VDD, and / or a third drive voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 5 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0099] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and / or data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and / or the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0100] In one or more embodiments, similar to scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be arranged in the non-display area NDA of display panel 100. In this case, timing control circuit 400 may include multiple timing transistors, and power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be fabricated on a semiconductor substrate SSUB (see [link to semiconductor designation]) using semiconductor processes. Figure 9 On (for example, it can be done through semiconductor processes on a semiconductor substrate SSUB (see...) Figure 9 Multiple timing transistors and multiple power transistors are formed on the data driver 700. For example, the multiple timing transistors and multiple power transistors may include CMOS (e.g., formed by CMOS), but this disclosure is not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 may be arranged on the data driver 700 and the first pad portion PDA1 (see...). Figure 6 )between.

[0101] Figure 5 It is shown Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown.

[0102] Reference Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and / or the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, the second drive voltage line VDL, and the third drive voltage line VIL. A first drive voltage VSS, corresponding to a low potential voltage, is applied to the first drive voltage line VSL; a second drive voltage VDD, corresponding to a high potential voltage, is applied to the second drive voltage line VDL; and a third drive voltage VINT, corresponding to the initialization voltage, is applied to the third drive voltage line VIL.

[0103] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and / or a second capacitor CP2.

[0104] The light-emitting element (LE) can be used to emit light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element (LE) can be proportional to the drive current. The first electrode of the light-emitting element (LE) can be an anode electrode, and the second electrode of the light-emitting element (LE) can be a cathode electrode. The light-emitting element (LE) can be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element (LE) can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element (LE) can be a micro-LED.

[0105] The first transistor T1 may be a driving transistor that controls the source-drain current (hereinafter referred to as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode.

[0106] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by the write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1.

[0107] The third transistor T3 can be arranged between the first node N1 and the second node N2. The third transistor T3 can be turned on by the control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this purpose, if the gate electrode and source electrode of the first transistor T1 are connected (e.g., when the gate electrode and source electrode of the first transistor T1 are connected), the first transistor T1 can operate like a diode.

[0108] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 can be turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0109] The sixth transistor T6 can be arranged between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 can be turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0110] The first capacitor CP1 can be formed between the first node N1 and the drain electrode of the second transistor T2. The second capacitor CP2 can be formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0111] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 may be a P-type (P-class) MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 may be an N-type (N-class) MOSFET. In one or more embodiments, at least some of the first transistors T1 to the sixth transistor T6 may be P-type (P-class) MOSFETs, and each of the remaining transistors may be an N-type (N-class) MOSFET.

[0112] Despite Figure 5 The diagram shows that the first sub-pixel SP1 may include six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 5 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 5 The quantities shown.

[0113] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 5 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be repeated in this disclosure.

[0114] Figure 6 It is shown Figure 3 A schematic floor plan of an example of a display panel shown.

[0115] Reference Figure 6The display area DAA of the display panel 100 according to one or more embodiments may include a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments may include a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1 and / or a second pad portion PDA2.

[0116] The scan driver 610 may be arranged on a first side of the display area DAA, and the transmit driver 620 may be arranged on a second side of the display area DAA. For example, the scan driver 610 may be arranged on one side of the display area DAA in a first direction DR1, and the transmit driver 620 may be arranged on the other side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and the scan driver 610 and the transmit driver 620 may be arranged (e.g., simultaneously) on both the first and second sides of the display area DAA.

[0117] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by conductive adhesive members. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed on the second direction DR2 outside the data driver 700.

[0118] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to fixtures and / or probes during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board comprising a rigid material (e.g., made of a rigid material) or a flexible printed circuit board comprising a flexible material (e.g., made of a flexible material).

[0119] The second pad portion PDA2 can be arranged on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be arranged on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be arranged outside the second distribution circuit 720 on the second direction DR2.

[0120] The first distribution circuit 710 can be used to distribute the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of multiple first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2.

[0121] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2.

[0122] The cathode connection (CCA) can be the display element layer (EML) (see...). Figure 9 The second electrode CAT (see) Figure 9 The region connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection CCA may be disposed outside at least one side of the display area DAA. For example, the cathode connection CCA may be disposed outside at least one of the left, right, upper, and lower sides of the display area DAA. In one or more embodiments, as... Figure 6 As shown, the cathode connection CCA can be arranged around the display area DAA to minimize or reduce the deviation of the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA.

[0123] Figure 7 It is shown Figure 6 A schematic enlarged plan view of an example of the display area shown. Figure 8 It is shown Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0124] Reference Figure 7 and Figure 8Each of the pixels PX may include a first emission region EA1, a second emission region EA2, a third emission region EA3 and / or a fourth emission region EA4. The first emission region EA1 may be the emission region of the first sub-pixel SP1, the second emission region EA2 may be the emission region of the second sub-pixel SP2, the third emission region EA3 may be the emission region of the third sub-pixel SP3, and the fourth emission region EA4 may be the emission region of the second sub-pixel SP2.

[0125] The first launch area EA1, the second launch area EA2, the third launch area EA3, and / or the fourth launch area EA4 can be arranged as follows in the plan view: Figure 7 and Figure 8 The quadrilateral or hexagonal shape shown is not the only one described herein. The first emission region EA1, the second emission region EA2, the third emission region EA3 and / or the fourth emission region EA4 may have polygonal shapes, circular shapes, elliptical shapes or irregular shapes other than quadrilaterals or hexagons in the plan view.

[0126] like Figure 7 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0127] In one or more embodiments, such as Figure 8 As shown, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. In this case, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent in the second direction DR2. Additionally, the first emission region EA1 and the second emission region EA2 can be adjacent in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second diagonal direction DD2. Furthermore, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0128] The first sub-pixel SP1 can be used to emit a first light, the second sub-pixel SP2 can be used to emit a second light, and the third sub-pixel SP3 can be used to emit a third light. Here, the first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to 460 nm (e.g., the wavelength of the blue band can be approximately 370 nm to approximately 460 nm), the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to 560 nm (e.g., the wavelength of the green band can be approximately 480 nm to approximately 560 nm), and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to 750 nm (e.g., the wavelength of the red band can be approximately 600 nm to approximately 750 nm).

[0129] Each of the multiple pixels in PX can be like Figure 7 The area shown includes three launch zones, EA1, EA2, and EA3, or it can be as follows: Figure 8 The area shown includes four emission regions EA1, EA2, EA3, and EA4. In this case, the fourth emission region EA4 can be used to emit a second beam that is substantially the same as that of the second emission region EA2, but this disclosure is not limited thereto.

[0130] The emission regions of multiple pixels PX can be arranged in a stripe structure where the emission regions are arranged in the first direction DR1, and the emission regions EA1, EA2, EA3 and EA4 can be arranged as follows: Figure 8 The diamond-shaped PenTile shown ® Structures (e.g., RGBG matrix, RGBG structure, and / or RGBG matrix structure) or hexagonal structures in which the emission regions are arranged in a hexagonal shape, but this disclosure is not limited thereto. PenTile ® It is an officially registered trademark of Samsung Display Co., Ltd.

[0131] Figure 9 It shows along Figure 7 The schematic cross-sectional view of an example display panel shown is taken by line I1-I1'.

[0132] Reference Figure 9 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0133] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and / or multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs), respectively. The multiple pixel transistors (PTRs) may be referenced. Figure 5 The first transistor T1 to the sixth transistor T6 are described.

[0134] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a type 1 (class 1) impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a type 2 (class 2) impurity. The type 2 (class 2) impurity can be different from the type 1 (class 1) impurity. For example, if the type 1 (class 1) impurity is a P-type (class P) impurity (e.g., when the type 1 (class 1) impurity is a P-type (class P) impurity), then the type 2 (class 2) impurity can be an N-type (class N) impurity. In one or more embodiments, if the type 1 (class 1) impurity is an N-type (class N) impurity (e.g., when the type 1 (class 1) impurity is an N-type (class N) impurity), then the type 2 (class 2) impurity can be a P-type (class P) impurity.

[0135] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0136] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0137] Each of the source region SA and drain region DA can be a region doped with type I (class I) impurities. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third-direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can be stacked with the gate electrode GE on the third-direction DR3. The source region SA can be arranged on one side of the gate electrode GE, and the drain region DA can be arranged on the other side of the gate electrode GE.

[0138] Each of the plurality of well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA and / or a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, thereby increasing the length of the channel region CH of each of the pixel transistors PTR.

[0139] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0140] Multiple contact terminals (CTEs) can be arranged on a second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to at least one of the gate electrode (GE), source region (SA), and drain region (DA) selected from each of the pixel transistors (PTRs) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can include at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed of an alloy selected from at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd).

[0141] The third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed without being covered by the third semiconductor insulating film (SINS3).

[0142] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 may include silicon carbonitride (SiCN) and / or silicon oxide (SiO2). x Inorganic films based on silicon carbonitride (SiCN) and / or silicon oxide (SiO2) x (The formation of inorganic membranes), but this disclosure is not limited thereto.

[0143] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0144] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple interlayer insulating films INS1 to INS9.

[0145] Interlayer insulating films INS1 to INS9 can be used to insulate first conductive layers ML1 to eighth conductive layers ML8. First conductive layers ML1 to eighth conductive layers ML8 can be used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 5 The circuit of the first sub-pixel SP1 shown.

[0146] For example, transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the connection between transistors T1 to T6 and the first capacitor CP1 and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0147] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise substantially the same material (e.g., formed of substantially the same material). The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). The first interlayer insulating films INS1 to INS8 may comprise substantially the same material (e.g., made of substantially the same material). The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may include silicon oxide (SiO2). x Inorganic layers based on silicon oxide (SiO2)x (The inorganic layer is formed), but this disclosure is not limited thereto.

[0148] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) (e.g., those made of silicon dioxide (SiO2)) x (The formation of inorganic membranes), but this disclosure is not limited thereto.

[0149] Each of the ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed of an alloy selected from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd).

[0150] The display element layer (EML) can be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0151] The reflective electrodes RL can be disposed on the ninth interlayer insulating film INS9. Each of the reflective electrodes RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, each of the reflective electrodes RL may include, for example,... Figure 9 The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 are shown in the figure.

[0152] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be disposed on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be disposed on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be disposed on its corresponding third reflective electrode RL3.

[0153] Because the second reflective electrode RL2 is the electrode that primarily reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0154] The first reflective electrode RL1 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). For example, the first reflective electrode RL1 may contain titanium nitride (TiN), the second reflective electrode RL2 may contain aluminum (Al), the third reflective electrode RL3 may contain titanium nitride (TiN), and the fourth reflective electrode RL4 may include titanium (Ti).

[0155] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to flatten the step portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0156] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) (e.g., those made of silicon dioxide (SiO2)) x (The formation of inorganic membranes), but this disclosure is not limited thereto.

[0157] The eleventh interlayer insulating film INS11 can be an optical auxiliary layer for adjusting the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can vary among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant peak wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0158] For example, such as Figure 9 As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0159] Each of the tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and connect to the exposed fourth reflective electrode RL4. The tenth via VA10 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed of an alloy selected from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0160] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE may comprise at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or an alloy selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). For example, the first electrode AND of each of the light-emitting elements LE may be titanium nitride (e.g., TiN).

[0161] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a region of the light-emitting element (LE) on which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are disposed.

[0162] The first emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0163] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs). The second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may comprise silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) (e.g., those made of silicon dioxide (SiO2)) x (Formation of an inorganic film based on silicon nitride). In one or more embodiments, the first pixel defining film PDL1 and the third pixel defining film PDL3 may include silicon nitride (SiN). x Inorganic films based on silicon nitride (e.g., silicon nitride (SiN)) x (The second pixel defining film PDL2 may include silicon oxide (SiO2)). x Inorganic films based on silicon dioxide (SiO2) (e.g., those made of silicon dioxide (SiO2)) x (Based on inorganic film formation). The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have a thickness of approximately 500 Å.

[0164] To reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0165] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. The eleventh interlayer insulating film INS11 can be partially recessed at each of the multiple trench TRCs.

[0166] At least one trench TRC can be arranged between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 Two trench TRCs are shown arranged between adjacent sub-pixels SP1, SP2 and SP3, but this disclosure is not limited thereto.

[0167] The light-emitting stack IL can include multiple stacked layers IL1, IL2 and IL3. Figure 9 The illustration shows a light-emitting stack IL having a three-tiered structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, as Figure 10 As shown, the light-emitting stack IL can have a dual-tandem structure comprising two stacked layers.

[0168] In a three-tiered structure, the light-emitting stack IL can have a tiered structure comprising multiple stacked layers IL1, IL2, and IL3 for emitting different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 for emitting a first light, a second stacked layer IL2 for emitting a second light, and a third stacked layer IL3 for emitting a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0169] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer for emitting first light, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer for emitting second light, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer for emitting third light, and a third electron transport layer are sequentially stacked.

[0170] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type (N-class) charge generation layer that supplies electrons to the first stacked layer IL1 and a P-type (P-class) charge generation layer that supplies holes to the second stacked layer IL2. The N-type (N-class) charge generation layer may include a dopant of a metallic material.

[0171] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type (N-class) charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type (P-class) charge generation layer that supplies holes to the third stacked layer IL3.

[0172] A first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL, and a residual film RIL disposed on the bottom surface of each trench TRC may comprise substantially the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 may be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 may be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS and / or empty space may be disposed in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 may be disposed on the second stacked layer IL2. The third stacked layer IL3 may not be cut by the trench TRC and may be arranged to cover the second stacked layer IL2 in each of the trench TRCs.

[0173] In a three-series structure, each of the plurality of trench TRCs can be a structure for cutting off the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. Additionally, in a two-series structure, each of the plurality of trench TRCs can be a structure for cutting off the charge generation layer disposed between the lower and upper stacked layers, as well as the lower stacked layer itself.

[0174] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel-defining film PDL. The height of each of the plurality of trench TRCs can refer to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel-defining film PDL can refer to the length of the pixel-defining film PDL in the third direction DR3. To cut the charge generation layer and hole transport layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, different structures can exist instead of trench TRCs. For example, inverted conical partition walls can be arranged on the pixel-defining film PDL instead of trench TRCs.

[0175] in addition, Figure 9The illustration shows a light-emitting stack IL arranged in a first emission region EA1, a second emission region EA2, and a third emission region EA3, but the present disclosure is not limited thereto. For example, instead of the light-emitting stack IL, a first light-emitting layer may be arranged in the first emission region EA1, and may not be arranged in the second emission regions EA2 and the third emission region EA3. Furthermore, a second light-emitting layer may be arranged in the second emission region EA2, and may not be arranged in the first emission region EA1 and the third emission region EA3. Furthermore, a third light-emitting layer may be arranged in the third emission region EA3, and may not be arranged in the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may not be provided.

[0176] The second electrode CAT can be disposed on the light-emitting stack IL. For example, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can include a transparent conductive material (TCO) that transmits light, such as ITO and / or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag (e.g., formed of a transparent conductive material (TCO) that transmits light, such as ITO and / or IZO, or a semi-transmissive conductive material, such as an alloy of magnesium (Mg), silver (Ag), and / or Mg and Ag). If the second electrode CAT includes a semi-transmissive conductive material (e.g., formed of a semi-transmissive conductive material) (e.g., when the second electrode CAT includes a semi-transmissive conductive material (e.g., formed of a semi-transmissive conductive material)), then due to the microcavity effect, the luminous efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved.

[0177] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and / or TFE3 to prevent or reduce the penetration of oxygen or moisture into the display element layer EML. The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 may be disposed on top of the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may include multiple layers (e.g., formed of multiple layers), among which silicon nitride (e.g., SiN) is included. x ) layer, silicon oxynitride (e.g., SiON) layer, silicon oxide (e.g., SiO) layer x ) layer, titanium oxide (e.g., TiO2) x ) layer and / or alumina (e.g., AlO) x One or more inorganic membranes can be stacked alternately.

[0178] Furthermore, the encapsulation layer TFE may include at least one organic film TFE2 to protect the display element layer EML from foreign matter such as dust. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be an organic film made of monomers. In one or more embodiments, the encapsulation organic film TFE2 may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0179] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Alternatively, the adhesive layer ADL can be a transparent adhesive component such as a transparent adhesive and / or a transparent adhesive resin.

[0180] The optical layer OPL may include multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged on the adhesive layer ADL.

[0181] A first color filter CF1 can be stacked with a first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can be used to transmit light of a first color, for example, light in the blue band. The blue band can be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 can be used to transmit light of a first color emitted from the first emission region EA1.

[0182] The second color filter CF2 can be stacked with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can be used to transmit light of a second color, such as light in the green band. The green band can be from about 480 nm to about 560 nm. Therefore, the second color filter CF2 can be used to transmit light of a second color emitted from the second emission region EA2.

[0183] The third color filter CF3 can be stacked with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can be used to transmit light of a third color, such as light in the red band. The red band can be from approximately 600 nm to approximately 750 nm. Therefore, the third color filter CF3 can be used to transmit light of a third color emitted from the third emission region EA3.

[0184] Multiple lenses LNS can be arranged on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed to the front of the display device 20. Each of the multiple lenses LNS can have a cross-sectional shape that can convex in the upward direction.

[0185] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a set or predetermined refractive index such that light travels in the third direction (DR3) at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0186] A capping CVL can be disposed on a filler layer FIL. The capping CVL can be a glass substrate and / or a polymeric resin. If the capping CVL is a glass substrate (e.g., when the capping CVL is a glass substrate), the capping CVL can be attached to the filler layer FIL. In this case, the filler layer FIL can bond to the capping CVL. If the capping CVL is a glass substrate (e.g., when the capping CVL is a glass substrate), the capping CVL can be used as an encapsulation substrate. If the capping CVL is a polymeric resin (e.g., when the capping CVL is a polymeric resin), the capping CVL can be applied directly to the filler layer FIL.

[0187] A polarizing plate (POL) can be disposed on one surface of the capping layer CVL. The polarizing plate POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and / or a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (e.g., a quarter-wave plate), but this disclosure is not limited thereto. However, if the visibility degradation caused by reflection of external light can be sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3 (e.g., when the visibility degradation caused by reflection of external light can be sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3), then a polarizing plate POL may not be necessary.

[0188] Figure 10 It shows along Figure 7 The schematic cross-sectional view of another example of a display panel, shown by line I1-I1'.

[0189] Figure 10 Implementation examples and Figure 9 The difference in the embodiments may be that the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation examples and Figure 9 The embodiments may also differ in that: the trench TRC may not be provided, and alternatively, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 may have an eaves-shaped or mushroom-shaped cross-sectional structure. Figure 10 In this embodiment, the already provided Figure 9 Redundant descriptions of parts described in the embodiments.

[0190] Reference Figure 10 Multiple connecting electrodes ANC can be respectively arranged on the first portion AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be arranged on its corresponding first portion AA1 of the ninth interlayer insulating film INS9. The multiple connecting electrodes ANC may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), including alloys and / or transparent conductive oxides selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), including alloys and / or transparent conductive oxides selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). For example, multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (e.g., TiN), indium tin oxide (e.g., ITO), and / or indium zinc oxide (e.g., IZO), but this disclosure is not limited thereto.

[0191] Multiple reflective electrodes RL can be arranged on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be arranged on its corresponding connecting electrode ANC. The multiple reflective electrodes RL may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed from an alloy selected from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or include an alloy selected from at least one selected from Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). For example, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity.

[0192] Multiple optical auxiliary films (OALs) can be disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on its corresponding reflective electrode (RL). The multiple optical auxiliary films (OALs) may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) (e.g., those made of silicon dioxide (SiO2)) x (The formation of inorganic membranes), but this disclosure is not limited thereto.

[0193] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be disposed on the reflective electrode RL, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. The thickness of the optical auxiliary film OAL can be substantially the same in the first emission region EA1, the second emission region EA2, and / or the third emission region EA3.

[0194] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first emission region EA1 and the third emission region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be determined by considering the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0195] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0196] The first electrode AND of each of the light-emitting elements LE can be disposed on its corresponding optical auxiliary film OAL. Because the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each of the light-emitting elements LE can be disposed on the top and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Therefore, the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to if the first electrode AND of each of the light-emitting elements LE is connected to the reflective electrode RL exposed through a through-hole penetrating the optical auxiliary film OAL (e.g., when the first electrode AND of each of the light-emitting elements LE is connected to the reflective electrode RL exposed through a through-hole penetrating the optical auxiliary film OAL), the number of mask processes can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0197] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connection electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0198] The ninth interlayer insulating film INS9 may include a first portion AA1 that is superimposed on the third-direction DR3 with the connecting electrode ANC and a second portion AA2 that is not superimposed on the third-direction DR3 with the connecting electrode ANC. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same.

[0199] In one or more embodiments, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 may be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this case, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 may be exposed, and the first electrode AND of each of the light-emitting elements LE may be arranged on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0200] The first electrode AND of each of the light-emitting elements LE may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), including alloys and / or transparent conductive oxides selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd (e.g., formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), including alloys and / or transparent conductive oxides selected from at least one of Cu, Al, W, Mo, Cr, Au, Ti, Ni, and Nd). For example, the first electrode AND of each of the light-emitting elements LE may include titanium (Ti), titanium nitride (e.g., TiN), indium tin oxide (e.g., ITO), and / or indium zinc oxide (e.g., IZO), but this disclosure is not limited thereto.

[0201] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0202] The pixel-limiting film (PDL) may include a first pixel-limiting film (PDL1), a second pixel-limiting film (PDL2), a third pixel-limiting film (PDL3), and a fourth pixel-limiting film (PDL4).

[0203] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the light-emitting elements LE. For example, the first pixel defining film PDL1 can cover a portion of the top surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0204] The planarization film PNS is a film used to planarize the stepped portions caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0205] The planarization film PNS can be disposed on the first pixel defining film PDL1, which covers the side surface of the first electrode AND, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can also be disposed on the first pixel defining film PDL1, which is disposed on the second part AA2 of the ninth interlayer insulating film INS9.

[0206] The planarization film PNS can be disposed between adjacent connecting electrodes ANC on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL on the first direction DR1 or the second direction DR2.

[0207] There is no step layer STPL in the second emission region EA2, but there is a step layer STPL in each of the first emission region EA1 and the third emission region EA3. Therefore, the height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emission region EA2 can be less than the height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 arranged on the top surface of the first electrode AND arranged in the second emission region EA2.

[0208] Conversely, the top surface of the planarization film PNS can be flatly connected to the top surface of the first electrode AND arranged in the first emission region EA1 and the third emission region EA3. For example, the planarization film PNS may not cover the top surface of the first electrode AND arranged in each of the first emission region EA1 and the third emission region EA3.

[0209] The second pixel defining film PDL2 can be disposed on the first pixel defining film PDL1 and the planarization film PNS, the third pixel defining film PDL3 can be disposed on the second pixel defining film PDL2, and the fourth pixel defining film PDL4 can be disposed on the third pixel defining film PDL3. The first pixel defining film PDL1 and the third pixel defining film PDL3 may include silicon nitride (SiN). x Inorganic films based on silicon nitride (e.g., silicon nitride (SiN)) x (Based on inorganic film formation), while the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) (e.g., those made of silicon dioxide (SiO2)) x (Based on inorganic film formation). The first pixel defining film PDL1 may include a material different from the material of the planarization film PNS (e.g., formed from a material different from the material of the planarization film PNS), and can therefore be used as a stop element in the chemical mechanical polishing process for the planarization film PNS.

[0210] If both the planarization film PNS and the second pixel defining film PDL2 are formed (e.g., simultaneously) as silicon oxide (SiO2) x Inorganic films (e.g., when the planarization film PNS and the second pixel defining film PDL2 are both (e.g., simultaneously) formed as silicon oxide (SiO2) x When the base is an inorganic film, the planarization film PNS and the second pixel-defining film PDL2 can be formed as a single film.

[0211] Because the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, the bottom surface of the fourth pixel defining film PDL4 can be exposed without being covered by the third pixel defining film PDL3. For example, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have an eaves-shaped or mushroom-shaped cross-sectional structure.

[0212] A light-emitting stack IL can be disposed on a first electrode AND and a pixel-defining film PDL. The light-emitting stack IL may include a first stacked layer IL1 and a second stacked layer IL2 that emit different lights. If the light-emitting stack IL has a dual-series structure (e.g., when the light-emitting stack IL has a dual-series structure), one of the first stacked layer IL1 and the second stacked layer IL2 can be used to emit light in a wavelength range that may include at least one selected from a first light, a second light, and a third light, and the other can be used to emit light in a wavelength range that may include two other light sources. For example, the first stacked layer IL1 can be used to emit light that may include the wavelength range of the first light and the wavelength range of the third light, and the second stacked layer IL2 can be used to emit light that may include the wavelength range of the second light. Here, the first light may be blue light, the second light may be green light, and the third light may be red light.

[0213] A charge-generating layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge-generating layer may include an N-type (N-class) charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type (P-class) charge-generating layer that supplies holes to the second stacked layer IL2. The N-type (N-class) charge-generating layer may include a dopant of a metallic material.

[0214] The first stacked layer IL1 may not be on (e.g., formed on) the bottom surface of the fourth pixel defining film PDL4 that is exposed and not covered by the third pixel defining film PDL3, and therefore can be cut by the eaves-shaped or mushroom-shaped cross-sectional structure of the third pixel defining film PDL3 and the fourth pixel defining film PDL4. In this case, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be cut. Furthermore, although Figure 10 The second stacked layer IL2 is shown to be connected without being disconnected; however, the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, leakage current can be prevented or reduced from flowing through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer between adjacent emission regions EA1, EA2, and EA3. Therefore, the emission of light other than the initially intended light by the light-emitting stack IL due to the aforementioned current in adjacent emission regions EA1, EA2, and EA3 can be prevented or reduced.

[0215] although Figure 10 The illustration shows a dual-tandem structure in which the light-emitting stack IL may include two stacked layers IL1 and IL2, but this disclosure is not limited thereto. For example, as Figure 9As shown, the light-emitting stack IL can have a triple-tandem structure comprising three stacked layers. In this case, it can be designed such that the charge-generating layer between the first stacked layer IL1 and the second stacked layer IL2, and the charge-generating layer between the second stacked layer IL2 and the third stacked layer IL3, can be cut off by adjusting the height of the third pixel defining film PDL3. In one or more embodiments, as Figure 9 As shown, a trench TRC that penetrates the first pixel-defining film PDL1, the planarization film PNS, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can be added. In this case, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but this disclosure is not limited thereto.

[0216] Figure 11 It shows along Figure 7 The schematic cross-sectional view shown is another example of a display panel, cut off by line I1-I1'.

[0217] Figure 11 Implementation examples and Figure 10 The difference in this embodiment is that the light-emitting element (LE) has a single stacked structure. Figure 11 In this embodiment, the already provided Figure 10 Redundant descriptions of parts described in the embodiments.

[0218] Reference Figure 11 The pixel defining film (PDL) can be disposed on the ninth interlayer insulating film (INS9) and the first electrode (AND), and the planarization film (PNS) can be disposed on the pixel defining film (PDL). The planarization film (PNS) and the pixel defining film (PDL) can have openings exposing the first electrode (AND), and the light-emitting stack (IL) can be disposed on the first electrode (AND). For example, the pixel defining film (PDL) can have openings exposing the first electrode (AND) in the first emission region (EA1), the second emission region (EA2), and the third emission region (EA3), and the planarization film (PNS) can have an opening exposing the first electrode (AND) in the second emission region (EA2). For example, the light-emitting stack (IL) can include a first stacked layer (IL1_1), a second stacked layer (IL1_2), and a third stacked layer (IL1_3).

[0219] The first stacked layer IL1_1 may be disposed in the first emission region EA1 on the first electrode AND exposed by the pixel-defining film PDL. The first stacked layer IL1_1 may also be disposed on a portion of the pixel-defining film PDL. For example, the first stacked layer IL1_1 may include a hole injection layer, a hole transport layer, a first light-emitting layer, an electron transport layer, and an electron injection layer.

[0220] The second stacked layer IL1_2 can be disposed in the second emission region EA2 on the first electrode AND exposed by the planarization film PNS and the pixel defining film PDL. The second stacked layer IL1_2 can also be disposed on a portion of the planarization film PNS. For example, the second stacked layer IL1_2 may include a hole injection layer, a hole transport layer, a second light-emitting layer, an electron transport layer, and an electron injection layer.

[0221] The third stacked layer IL1_3 can be disposed in the third emission region EA3 on the first electrode AND exposed by the pixel-defining film PDL. The third stacked layer IL1_3 can also be disposed on a portion of the pixel-defining film PDL. For example, the third stacked layer IL1_3 may include a hole injection layer, a hole transport layer, a third light-emitting layer, an electron transport layer, and an electron injection layer.

[0222] The first stacked layer IL1_1, the second stacked layer IL1_2, and the third stacked layer IL1_3 can be spaced apart and / or separated from each other (e.g., spaced apart or separated), so it is not necessary to set up a method for making Figure 10 In the embodiments, the light-emitting stack IL is separated into a second pixel defining film PDL2, a third pixel defining film PDL3, and a fourth pixel defining film PDL4.

[0223] The first stacked layer IL1_1 of the first emission region EA1 can be used to emit the first light, the second stacked layer IL1_2 of the second emission region EA2 can be used to emit the second light, and the third stacked layer IL1_3 of the third emission region EA3 can be used to emit the third light. Therefore, it is not necessary to provide [the following]. Figure 9 The embodiments utilize an optical layer OPL with a first color filter CF1, a second color filter CF2 and a third color filter CF3, multiple lenses LNS and a filling layer FIL.

[0224] Figure 12 This is a schematic perspective view showing an example of a head-mounted display. Figure 13 It is shown Figure 12 The schematic exploded perspective view of the head-mounted display shown.

[0225] Reference Figure 12 and Figure 13 The head-mounted display 1000 according to one or more embodiments may include a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0226] The first display device 20_1 can provide an image to the user's left eye, and the second display device 20_2 can provide an image to the user's right eye. This is because each of the first display device 20_1 and the second display device 20_2 can be combined with... Figures 3 to 11 The display devices 20 described are basically the same, so the descriptions of the first display device 20_1 and the second display device 20_2 will not be provided.

[0227] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0228] The intermediate frame 1400 can be arranged between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 can be used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0229] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can be used to convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 20_1 and the second display device 20_2 via connectors.

[0230] The control circuit board 1600 can be used to transmit digital video data DATA corresponding to a left-eye image that is improved or optimized for the user's left eye to a first display device 20_1, and can be used to transmit digital video data DATA corresponding to a right-eye image that is improved or optimized for the user's right eye to a second display device 20_2. In one or more embodiments, the control circuit board 1600 can be used to transmit substantially the same digital video data DATA to the first display device 20_1 and the second display device 20_2.

[0231] The display device housing 1100 can be used to house a first display device 20_1, a second display device 20_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned thereon for the user's left eye and a second eyepiece 1220 positioned thereon for the user's right eye. Figure 12 and Figure 13 The first eyepiece 1210 and the second eyepiece 1220 are shown arranged separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0232] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0233] The headband 1300 can be used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. If the display device housing 1100 is implemented in a lightweight and compact manner (e.g., when the display device housing 1100 is implemented in a lightweight and compact manner), the head-mounted display 1000 can be configured as follows: Figure 14 The eyeglasses frame shown is not the headband 1300.

[0234] Figure 14 This is a schematic perspective view showing another example of a head-mounted display.

[0235] Reference Figure 14 The head-mounted display 1000_1 according to one or more embodiments can be an eyeglass-type (eyeglasses-like) display device, wherein the display device housing 1100_1 can be implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path changing component 1070, and a display device housing 1100_1.

[0236] The display device housing 1100_1 can accommodate the display device 20_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 20_3 with the real image seen through the right eye lens 1020.

[0237] Figure 14The display device housing 1100_1 is shown positioned at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1100_1 may be positioned at the left end of the support frame 1030, and in this case, the image displayed on the display device 20_3 may be provided to the user's left eye. In one or more embodiments, the display device housing 1100_1 may be positioned (e.g., simultaneously) at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 20_3 (e.g., simultaneously) through both the left and right eyes.

[0238] Figure 15 This is a schematic diagram illustrating a deposition apparatus according to one or more embodiments of the present disclosure.

[0239] Reference Figure 15 The deposition apparatus 2000 according to one or more embodiments can be used to form a deposition material layer on a substrate. For example, the deposition apparatus 2000 according to one or more embodiments can be used on a display panel 100 (see...) Figure 3 In the manufacturing process of [the device], a light-emitting layer is formed on the backplane substrate 3000 (or display substrate). For example, such as... Figure 11 As shown, a semiconductor backplane (SBP) and a light-emitting element backplane (EBP) can be disposed on a backplane substrate 3000, and an electrode pattern (such as a first electrode AND serving as an anode electrode) and a pixel-defining film (PDL) having an opening exposing the first electrode AND can be disposed on the light-emitting element backplane EBP. As an example, a deposition apparatus 2000 can be used to form a first light-emitting layer on the first electrode AND of a first emission region EA1. As another example, a deposition apparatus 2000 can be used to form a second light-emitting layer on the first electrode AND of a second emission region EA2. As yet another example, a deposition apparatus 2000 can be used to form a third light-emitting layer on the first electrode AND of a third emission region EA3.

[0240] The deposition apparatus 2000 may include: a deposition source 2200 for providing vapor deposition material onto a backing substrate 3000; a substrate chuck 2300 for supporting the backing substrate 3000 such that the backing substrate 3000 faces the deposition source 2200; and a mask chuck 2400 disposed between the deposition source 2200 and the substrate chuck 2300 and supporting a deposition mask 4000 such that the deposition mask 4000 faces the backing substrate 3000. The deposition source 2200, the substrate chuck 2300, and the mask chuck 2400 may be disposed in a process chamber (or evaporation chamber) 2100.

[0241] The process chamber 2100 may include an internal space, and a deposition process for forming a layer of deposited material on a backplane substrate 3000 can be performed within the internal space of the process chamber 2100. The process chamber 2100 may be connected to a vacuum pump, and a vacuum atmosphere may be generated within the internal space of the process chamber 2100 by the vacuum pump. An opening for entry and exit of the backplane substrate 3000 and the deposition mask 4000 may be provided in a side wall of the process chamber 2100 and may be opened and closed by a gate valve.

[0242] Deposition source 2200 can be arranged inside process chamber 2100, and deposition material can be contained inside deposition source 2200. Deposition source 2200 can be used to evaporate deposition material such as organic material, inorganic material, and / or conductive material toward backplane substrate 3000, and the evaporated deposition material can be deposited on backplane substrate 3000 through deposition mask 4000. For example, deposition source 2200 can be used to evaporate organic light-emitting material for forming a light-emitting layer on backplane substrate 3000, and can include a heater for evaporating organic light-emitting material. The evaporated organic light-emitting material can be deposited on electrode patterns on backplane substrate 3000 through deposition mask 4000, so that a light-emitting layer can be (e.g., formed on) the electrode patterns on backplane substrate 3000. Figure 15 It has been shown that the deposition source 2200 can be arranged on the central portion of the bottom surface of the process chamber 2100, but the deposition source 2200 can also be configured to be horizontally movable by a separate actuator.

[0243] The substrate chuck 2300 can be disposed on the deposition source 2200 and can be used to support the backplate substrate 3000 such that the backplate substrate 3000 faces the deposition source 2200. For example, the substrate chuck 2300 can be an electrostatic chuck that clamps the rear surface of the backplate substrate 3000 using electrostatic force. For example, an electrode pattern such as a first electrode AND can be disposed on the front surface of the backplate substrate 3000, and the substrate chuck 2300 can be used to clamp the rear surface of the backplate substrate 3000 such that the front surface of the backplate substrate 3000 faces downward, for example, towards the deposition source 2200.

[0244] Multiple lifting fingers 2350 for loading the backplane substrate 3000 onto the substrate chuck 2300 can be arranged in the process chamber 2100. The lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved vertically by finger actuators 2360. For example, three or four lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved in the third direction DR3 by the finger actuators 2360.

[0245] The backplate substrate 3000 can be transported into the process chamber 2100 by a transfer robot and then transferred from the transfer robot to the lifting finger 2350 below the base chuck 2300. In this case, the rear surface of the backplate substrate 3000 can face the lower surface of the base chuck 2300, and the lifting finger 2350 can be used to support the edge portion of the front surface of the backplate substrate 3000. The finger actuator 2360 can be used to raise the lifting finger 2350 so that the backplate substrate 3000 can be adjacent to the lower surface of the base chuck 2300, and the rear surface of the backplate substrate 3000 can be clamped to the lower surface of the base chuck 2300 by electrostatic force.

[0246] The finger actuator 2360 can be disposed on the upper cover of the process chamber 2100 and can be connected to the lifting finger 2350 via a drive shaft 2362 extending vertically through the upper cover of the process chamber 2100. The finger actuator 2360 can be used to move the lifting finger 2350 in the vertical direction to load or unload the backplate substrate 3000. Furthermore, the finger actuator 2360 can be used to rotate the lifting finger 2350 based on the drive shaft 2362. For example, the finger actuator 2360 can be used to rotate the lifting finger 2350 such that the end of the lifting finger 2350 does not overlap with the substrate chuck 2300 and the mask chuck 2400, thus enabling vertical movement of the lifting finger 2350. Additionally, the finger actuator 2360 can be used to rotate the lifting finger 2350 such that the end of the lifting finger 2350 overlaps with the edge portion of the backplate substrate 3000 to support the edge portion of the backplate substrate 3000.

[0247] The deposition mask 4000 can be transported into the process chamber 2100 by a transfer robot and can be transferred to the lifting finger 2350 on the mask chuck 2400. The edge portion of the deposition mask 4000 can be placed on the end of the lifting finger 2350, and the finger actuator 2360 can be used to lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. In this case, the edge portion of the mask chuck 2400 can be provided with a recess, the end of the lifting finger 2350 can be inserted into the recess, and the finger actuator 2360 can be used to rotate the lifting finger 2350 such that after the deposition mask 4000 is loaded onto the mask chuck 2400, the lifting finger 2350 does not overlap with the mask chuck 2400.

[0248] The mask chuck 2400 can be used to support the edge portion of the deposition mask 4000. For example, the mask chuck 2400 can be an electrostatic chuck that clamps the edge portion of the deposition mask 4000 using electrostatic force. For example, the mask chuck 2400 can have a circular opening, such that the deposition mask 4000 is exposed toward the deposition source 2200. For example, the mask chuck 2400 can have a disk shape or a rectangular plate shape (e.g., a plate with a circular opening) with a circular opening.

[0249] The deposition apparatus 2000 may include a chuck drive unit (e.g., a chuck driver) for adjusting the position and orientation of the backplane substrate 3000 and the deposition mask 4000. For example, the deposition apparatus 2000 may include a substrate chuck drive unit 2500 (e.g., a substrate chuck driver) for moving the substrate chuck 2300 and a mask chuck drive unit 2600 (e.g., a mask chuck driver) for moving the mask chuck 2400.

[0250] For example, the base chuck drive unit 2500 can be used to move the base chuck 2300 in a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplate base 3000. In this case, the first direction DR1 can be a first horizontal direction, the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1, and the third direction DR3 can be a vertical direction. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0251] The base chuck drive unit 2500 can be used to rotate the base chuck 2300 about the Z-axis to adjust the azimuth angle of the backplate base 3000 (e.g., the angle at which the backplate base 3000 can be clamped on the lower surface of the base chuck 2300). Additionally, the base chuck drive unit 2500 can be used to rotate the base chuck 2300 about the X-axis and about the Y-axis to adjust the tilt of the backplate base 3000. For example, the base chuck drive unit 2500 may include a hexapod actuator 2510 that provides six degrees of freedom of motion (e.g., X, Y, Z, θx, θy, and θz).

[0252] The base chuck drive unit 2500 may include: a base stage 2520, on which a hexapod actuator 2510 may be mounted; and a second actuator 2530 connected to the base stage 2520. The base stage 2520 may be arranged horizontally within a process chamber 2100, and the second actuator 2530 may be arranged on top of the process chamber 2100. The second actuator 2530 may be connected to the base stage 2520 via a plurality of drive shafts 2532 extending through the top cover of the process chamber 2100 in a third direction DR3 (e.g., vertical direction, e.g., Z-axis direction), and may be used to move the base stage 2520 in the direction of the central axis of the hexapod actuator 2510 (e.g., vertical direction). For example, the second actuator 2530 may be constructed using a brushless DC motor, a linear motor, and / or a direct drive (DD) motor, etc., and the height of the base chuck 2300 may be adjusted to load or unload the backplate base 3000.

[0253] The hexapod actuator 2510 may include a first platform connected to the base chuck 2300, a second platform mounted on the base stage 2520, and six sub-actuators arranged between the first and second platforms. For example, the six sub-actuators may each be constructed using a brushless DC motor, a voice coil linear motor, a stepper motor, a DD motor, and / or a servo motor, and may be used to move and rotate the first platform to adjust the position of the backplate base 3000 in the horizontal direction, the position of the backplate base 3000 in the vertical direction, the azimuth angle of the backplate base 3000, and the tilt angle of the backplate base 3000.

[0254] The mask chuck drive unit 2600 can be used to move and rotate the mask chuck 2400 to adjust the position of the deposition mask 4000 in the horizontal direction and the azimuth angle of the deposition mask 4000 (e.g., the angle at which the deposition mask 4000 can be positioned on the mask chuck 2400). The mask chuck drive unit 2600 can also be used to move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and to rotate the mask chuck 2400 about its central axis. For example, the mask chuck drive unit 2600 can be used to move the mask chuck 2400 in a first direction DR1 (e.g., the X-axis direction) and a second direction DR2 (e.g., the Y-axis direction), and can also be used to rotate the mask chuck 2400 about a third direction DR3 (e.g., the Z-axis direction).

[0255] The mask chuck drive unit 2600 may include, for example, a piezoelectric actuator 2610 that provides motion in three degrees of freedom (e.g., X, Y, and θz). The piezoelectric actuator 2610 may have an opening that can communicate with a circular opening of the mask chuck 2400. The mask chuck 2400 may be spaced and / or separated (e.g., spaced apart or separated) from the piezoelectric actuator 2610 in an upward direction by a selected gap. For example, a plurality of support members 2612 may be arranged on the piezoelectric actuator 2610, and the mask chuck 2400 may be arranged on the plurality of support members 2612.

[0256] The mask chuck drive unit 2600 may include a mask stage 2620, which is horizontally arranged within the process chamber 2100 and supports the piezoelectric actuator 2610. For example, the mask stage 2620 may have an opening communicating with the opening of the piezoelectric actuator 2610, and may be supported by a plurality of pillars 2622 connected to the top cover of the process chamber 2100.

[0257] Figure 16 It is used to describe Figure 15 A schematic bottom view of the backplate base shown.

[0258] Reference Figure 16 The back panel base 3000 may include multiple display unit areas 3010 and scribed areas 3020 arranged between the display unit areas 3010. The display unit areas 3010 may be as follows: Figure 16 The panels shown are arranged in a matrix along the first direction DR1 and the second direction DR2, and can be divided into multiple display panels 100 by a cutting process after the display manufacturing process is completed (see...). Figure 3 For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. Additionally, each of the display unit regions 3010 can have, for example, as shown in the example... Figure 16 The rectangular shape shown.

[0259] For example, each of the display unit areas 3010 may include, for example, Figure 11 The diagram shows a semiconductor backplane SBP and a light-emitting element backplane EBP disposed on the semiconductor backplane SBP. Additionally, each of the display unit regions 3010 may include multiple electrode patterns (such as multiple first electrodes AND) disposed on the light-emitting element backplane EBP and a pixel defining film PDL disposed on the light-emitting element backplane EBP and the first electrodes AND. In this case, the electrode patterns of the display unit region 3010 may be disposed on the front surface of the backplane substrate 3000, and the substrate chuck 2300 may be used to clamp the rear surface of the backplane substrate 3000 such that the electrode patterns of the display unit region 3010 face downwards, for example, towards the deposition source 2200.

[0260] Figure 17 It is used to describe Figure 15 A schematic plan view of the deposition mask shown. Figure 18 It is used to describe Figure 17 A schematic enlarged plan view of the mask unit region shown. Figure 19 It is along Figure 18 The schematic cross-sectional view shown is taken by line I2-I2'.

[0261] Reference Figures 17 to 19 The deposition mask 4000 may include mask unit regions 4310 corresponding to display unit regions 3010 of the backplane substrate 3000 and grid regions 4320 corresponding to scribing regions 3020 of the backplane substrate 3000. Each of the mask unit regions 4310 may have a plurality of pixel openings 4312 that expose the first electrode AND of the backplane substrate 3000 during the deposition process. For example, the deposition mask 4000 may include a mask substrate 4100, an intermediate inorganic film 4200 disposed on the mask substrate 4100, and a film 4300 disposed on the intermediate inorganic film 4200. In this case, the film 4300 may include a plurality of mask unit regions 4310 and grid regions 4320 surrounding (e.g., around) the mask unit regions 4310, and each of the mask unit regions 4310 may have a plurality of pixel openings 4312.

[0262] The mask substrate 4100 may have cell openings 4110 corresponding to the mask cell regions 4310 respectively, and may include rib regions 4120 defining the cell openings 4110. The intermediate inorganic film 4200 may have intermediate openings 4210 respectively arranged on the cell openings 4110. In this case, the mask cell regions 4310 of the film 4300 may be located on the intermediate openings 4210 respectively, and the pixel openings 4312 of the film 4300 may be connected to the cell openings 4110 through the intermediate openings 4210.

[0263] According to one or more embodiments, the mask unit region 4310 of the film 4300 can be exposed toward the deposition source 2200 through the unit opening 4110 of the mask substrate 4100 and the intermediate opening 4210 of the intermediate inorganic film 4200, and the pixel opening 4312 can be formed to penetrate the mask unit region 4310. In this case, during the period in which the deposition process is performed, the vapor-deposited material provided from the deposition source 2200 can be deposited on the first electrode AND of the backplane substrate 3000 through the unit opening 4110, the intermediate opening 4210, and the pixel opening 4312.

[0264] like Figure 17As shown, the mask unit regions 4310 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. The mask unit regions 4310 can have, for example, as shown in the diagram. Figure 17 The rectangular shape shown, and the pixel opening 4312 can be arranged to correspond to the first electrode AND selected from at least one of the first emission region EA1, the second emission region EA2 and the third emission region EA3.

[0265] According to one or more embodiments, if the backplane substrate 3000 is positioned on the deposition mask 4000 during the deposition process (e.g., when the backplane substrate 3000 is positioned on the deposition mask 4000 during the deposition process), an electrode pattern of the backplane substrate 3000, such as a first electrode AND, can be positioned on the pixel opening 4312 of the deposition mask 4000. Therefore, the electrode pattern of the backplane substrate 3000 can face the deposition source 2200 through the pixel opening 4312. Subsequently, vapor-phase deposition material can be provided from the deposition source 2200 to the electrode pattern of the backplane substrate 3000 through the pixel opening 4312 of the deposition mask 4000. Therefore, a deposition material layer can be formed on the electrode pattern of the backplane substrate 3000 (e.g., a deposition material layer can be formed on the electrode pattern of the backplane substrate 3000).

[0266] The mask substrate 4100 may include monocrystalline silicon (e.g., made of monocrystalline silicon). For example, a monocrystalline silicon substrate having a thickness of about 700 μm to about 800 μm (e.g., about 775 μm) may be used as the mask substrate 4100.

[0267] Intermediate inorganic films 4200 and 4300 can be disposed on the front surface of mask substrate 4100, and second intermediate inorganic film 4400 and rear inorganic film 4500 can be disposed on the rear surface of mask substrate 4100. For example, second intermediate inorganic film 4400 can be disposed on the rear surface of mask substrate 4100, and rear inorganic film 4500 can be disposed on second intermediate inorganic film 4400. Second intermediate inorganic film 4400 and rear inorganic film 4500 can respectively have a second intermediate opening 4410 and a rear opening 4510 that can communicate with cell opening 4110, and the rear inorganic film 4500 can be used as an etching mask in the etching process for forming cell opening 4110. In this case, mask cell region 4310 can be exposed toward deposition source 2200 through intermediate opening 4210, cell opening 4110, second intermediate opening 4410 and rear opening 4510.

[0268] According to one or more embodiments, the film 4300 may comprise a material having etch selectivity relative to the intermediate inorganic film 4200 and the mask substrate 4100 (e.g., made of a material having etch selectivity relative to the intermediate inorganic film 4200 and the mask substrate 4100). For example, the intermediate inorganic film 4200 may comprise silicon oxide (e.g., SiO2). x (For example, made of silicon oxide (e.g., SiO2) x (made of), and the film 4300 may include silicon nitride (e.g., SiN). x (For example, silicon nitride (e.g., SiN) x According to one or more embodiments, the intermediate inorganic film 4200 may comprise a material substantially the same as that of the second intermediate inorganic film 4400 (e.g., made of a material substantially the same as that of the second intermediate inorganic film 4400), and the film 4300 may comprise a material substantially the same as that of the post-inorganic film 4500 (e.g., made of a material substantially the same as that of the post-inorganic film 4500). For example, the intermediate inorganic film 4200 and the second intermediate inorganic film 4400 may be formed concurrently (e.g., simultaneously) by a thermal oxidation process, and the film 4300 and the post-inorganic film 4500 may be formed concurrently (e.g., simultaneously) by a chemical vapor deposition (CVD) process.

[0269] The pixel opening 4312 of the film 4300 can be formed by an anisotropic etching process such as reactive ion etching (RIE). For example, the pixel opening 4312 exposing the intermediate inorganic film 4200 can be formed by the following steps: forming a photoresist pattern on the film 4300 that exposes the portion where the pixel opening 4312 is to be formed, and then performing the RIE process using the photoresist pattern as an etching mask. In this case, the pixel opening 4312 can be formed as a penetrating film 4300, and the intermediate inorganic film 4200 can be used as an etch stop film in the RIE process.

[0270] The second intermediate opening 4410 and the rear opening 4510 can be formed by an anisotropic etching process such as RIE. For example, the second intermediate opening 4410 and the rear opening 4510 that expose the rear surface of the mask substrate 4100 can be formed by the following steps: forming a photoresist pattern on the rear inorganic film 4500 that exposes the portion where the rear opening 4510 is to be formed, and then performing the RIE process using the photoresist pattern as an etching mask.

[0271] Using the second intermediate inorganic film 4400 and the post-inorganic film 4500 as etching masks, an anisotropic etching process can be used to form unit openings 4110 in the mask substrate 4100, allowing the intermediate inorganic film 4200 to be exposed. For example, a single-crystal silicon substrate can be used as the mask substrate 4100, and the unit openings 4110 can be formed using an etchant such as tetramethylammonium hydroxide (TMAH) solution and / or potassium hydroxide (KOH) solution via a wet etching process. In this case, the single-crystal silicon substrate used as the mask substrate 4100... <100> The crystal orientation can be a third-party DR3, therefore, each of the cell openings 4110 can have a width that gradually decreases from the rear surface of the mask substrate 4100 toward the front surface of the mask substrate 4100 via a wet etching process. For example, the inner surface of the cell opening 4110 can have a tilt angle of approximately 54.7° relative to the rear surface of the mask substrate 4100. In the context of this disclosure, unless otherwise defined, the term "gradually" means that the cell opening 4110 narrows continuously and uniformly from the rear surface of the mask substrate 4100 toward the front surface. This tapering effect is achieved by applying a wet anisotropic etching process (such as a wet anisotropic etching process using tetramethylammonium hydroxide (TMAH) and / or potassium hydroxide (KOH)) to the single-crystal silicon substrate. When the single-crystal silicon substrate has <100> During crystal orientation, the etching process utilizes the different etching rates of various crystal planes—specifically, relative to… <100> surface, etching <111> The process is relatively slow. As a result, the inner surface of the cell opening 4110 is formed at an angle of approximately 54.7° relative to the rear surface of the mask substrate 4100. This angle corresponds to the angle in the silicon crystal structure. <100> Face and <111> The geometric relationship between the surfaces. The result is a smooth, sloping profile in which the width of each cell opening 4110 decreases in a consistent and gradual manner as etching proceeds from the back surface to the front surface, rather than forming an abrupt or step-like transition.

[0272] The intermediate opening 4210 of the intermediate inorganic film 4200 can be formed by a wet etching process after the cell opening 4110 of the mask substrate 4100 is formed. For example, if the intermediate inorganic film 4200 includes silicon oxide (e.g., SiO2), the intermediate opening 4210 of the intermediate inorganic film 4200 can be formed by a wet etching process. x (For example, made of silicon oxide (e.g., SiO2) x (Formed as, for example, when the intermediate inorganic film 4200 includes silicon oxide (e.g., SiO2)) x (For example, made of silicon oxide (e.g., SiO2) xWhen the film is made, the intermediate opening 4210 can be formed by wet etching using an etchant such as buffer oxide etchant (BOE) or diluted hydrofluoric acid (diluted HF). Therefore, the pixel opening 4312 of the film 4300 can be connected to the unit opening 4110 of the mask substrate 4100 through the intermediate opening 4210 of the intermediate inorganic film 4200.

[0273] As another example, the second intermediate inorganic film 4400 may not be provided. In this case, the rear inorganic film 4500 may be disposed on the rear surface of the mask substrate 4100. Alternatively, the intermediate inorganic film 4200 may be formed by a thermal oxidation process or a CVD process, and the rear inorganic film 4500 may be formed in parallel (e.g., simultaneously) with the film 4300 or separately from the film 4300. As another example, both the intermediate inorganic film 4200 and the second intermediate inorganic film 4400 may not be provided (e.g., simultaneously). In this case, the film 4300 may be disposed on the front surface of the mask substrate 4100, and the rear inorganic film 4500 may be disposed on the rear surface of the mask substrate 4100. Alternatively, the rear inorganic film 4500 may be formed in parallel (e.g., simultaneously) with the film 4300 or separately from the film 4300.

[0274] Figure 20 It is used to describe Figure 15 A schematic front view of the base chuck and mask chuck shown.

[0275] Reference Figure 20 After the backplate substrate 3000 and the deposition mask 4000 are loaded onto the substrate chuck 2300 and the mask chuck 2400, respectively, the substrate chuck drive unit 2500 can be used to position the backplate substrate 3000 on the deposition mask 4000. For example, the second actuator 2530 can be used to lower the substrate chuck 2300 so that the backplate substrate 3000 is adjacent to the deposition mask 4000. The hexapod actuator 2510 can adjust the gap between the backplate substrate 3000 and the deposition mask 4000, and can adjust the tilt of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400.

[0276] According to one or more embodiments, the deposition apparatus 2000 may include a plurality of gap sensors 2700 for measuring the gap between the substrate chuck 2300 and the mask chuck 2400. For example, the plurality of gap sensors 2700 for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 may be arranged on an edge portion of the substrate chuck 2300, and the distance to the mask chuck 2400 may be measured through a through-hole 2310 penetrating the edge portion of the substrate chuck 2300.

[0277] The hexapod actuator 2510 can adjust the parallelism between the base chuck 2300 and the mask chuck 2400 based on measurements from the gap sensor 2700. For example, the hexapod actuator 2510 can adjust the height of the base chuck 2300 to a first height such that the gap between the backplate substrate 3000 and the deposition mask 4000 can be several hundred micrometers (e.g., about 100 μm to about 200 μm), and then adjust the tilt of the base chuck 2300 based on measurements from the gap sensor 2700. For example, a capacitive proximity sensor and / or a confocal sensor can be used as the gap sensor 2700, and the hexapod actuator 2510 can adjust the parallelism between the base chuck 2300 and the mask chuck 2400 by adjusting the tilt of the base chuck 2300. As a result, the parallelism between the backplate substrate 3000 supported by the base chuck 2300 and the deposition mask 4000 supported by the mask chuck 2400 can be adjusted.

[0278] According to one or more embodiments, after adjusting the parallelism between the base chuck 2300 and the mask chuck 2400, the hexapod actuator 2510 can adjust the height of the base chuck 2300 to a second height, such that the gap between the backplate substrate 3000 and the deposition mask 4000 can be tens of micrometers (e.g., about 10 μm to about 50 μm).

[0279] According to one or more embodiments, after the height of the base chuck 2300 is adjusted to the second height, the parallelism between the base chuck 2300 and the mask chuck 2400 can be adjusted a second time. For example, although not in Figure 20 As shown, however, multiple second gap sensors can be arranged on the edge portion of the base chuck 2300, and the distance to the mask chuck 2400 can be measured through the through-hole 2310 penetrating the edge portion of the base chuck 2300. The hexapod actuator 2510 can adjust the tilt of the base chuck 2300 based on the measurements of the second gap sensors, thus allowing for secondary adjustment of the parallelism between the base chuck 2300 and the mask chuck 2400. In this case, the second gap sensors can have a higher resolution than the gap sensor 2700. For example, a capacitive proximity sensor can be used as the gap sensor 2700, and a confocal sensor can be used as the second gap sensor. By secondary adjustment of the parallelism between the base chuck 2300 and the mask chuck 2400 as described above, the parallelism between the backing substrate 3000 and the deposition mask 4000 can be adjusted more precisely.

[0280] After adjusting the parallelism between the backplane substrate 3000 and the deposition mask 4000, alignment between the backplane substrate 3000 and the deposition mask 4000 can be performed. According to one or more embodiments, the backplane substrate 3000 may include a substrate alignment key 3100 for alignment with the deposition mask 4000. For example, as... Figure 16 As shown, multiple substrate alignment keys 3100 can be arranged on the edge portion of the backplate substrate 3000. Figure 16 As shown in the previous version, the backplate substrate 3000 may include two substrate alignment keys 3100, but the number of substrate alignment keys 3100 may be appropriately varied. Therefore, the scope of this disclosure is not limited by the number of substrate alignment keys 3100.

[0281] Figure 21 It is used to describe Figure 16 A schematic bottom view of the base alignment key shown.

[0282] Reference Figure 21 According to one or more embodiments, the substrate alignment bond 3100 may include a bond region 3110 and a bond pattern 3120 formed in or on the bond region 3110. For example, a pixel-defined film (PDL) may include the bond region 3110, and the bond pattern 3120 may have an approximately rectangular shape in a planar view. Alternatively, for example, the bond pattern 3120 may include metals such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd).

[0283] According to one or more embodiments, the deposition mask 4000 may include mask alignment keys 4600 for alignment with the backplane substrate 3000. For example, as Figure 17 As shown, multiple mask alignment keys 4600 can be arranged on the edge portions of the deposition mask 4000. Figure 17 As shown in the present invention, the deposition mask 4000 may include two mask alignment keys 4600, but the number of mask alignment keys 4600 may be appropriately varied, and therefore the scope of this disclosure is not limited by the number of mask alignment keys 4600.

[0284] Figure 22 It is used to describe Figure 17 A schematic cross-sectional view of the mask alignment key shown. Figure 23 It is used to describe Figure 17 A schematic plan view of the mask alignment key shown.

[0285] Reference Figure 22 and Figure 23The mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. The patterned region 4620 may include a surface-modified region 4640 having a larger surface roughness than the peripheral region 4610. According to one or more embodiments, the patterned region 4620 may be formed on a surface portion (e.g., a front surface portion) of the mask substrate 4100. In this case, the surface portion of the mask substrate 4100 surrounding (e.g., around) the patterned region 4620 may serve as the peripheral region 4610 of the mask alignment key 4600. For example, the patterned region 4620 may have a recess 4630 formed in the surface portion of the mask substrate 4100 (see...). Figure 26 Furthermore, the surface-modified region 4640 can be formed in the bottom surface portion of the recess 4630. Additionally, for example, the patterned region 4620 can have an approximately rectangular shape, and the recess 4630 can have a rectangular shape in a plan view that is substantially the same as that of the patterned region 4620.

[0286] According to one or more embodiments, the patterned region 4620 of the mask alignment key 4600 can be formed by an anisotropic etching process. For example, the patterned region 4620 of the mask alignment key 4600 can be formed by a RIE process such as the Bosch process. For example, a key opening 4220 can be formed through the intermediate inorganic film 4200 to expose a surface portion of the mask substrate 4100 (e.g., the portion where the patterned region 4620 will be formed) (see...) Figure 26 Furthermore, the recess 4630 and the surface modification region 4640 can be formed by removing the surface portion of the mask substrate 4100 exposed through the key opening 4220 via the RIE process.

[0287] This can be achieved by utilizing polymer layer 4604 (see...) Figure 27 The passivation gases (such as CF4, C2F6, C3F6, C4F6 and / or C4F8), sputtering gases (such as Ar, He, Ne, Xe and / or O2) for anisotropically etching the polymer layer 4604 and the mask substrate 4100, and reactive gases (such as SF6, CHF3, CH3F, CH2F2, CBrF3, CCl4, O2 and / or H2) for isotropically etching the mask substrate 4100 are used to perform the RIE process for forming the recess 4630 and the surface modification region 4640.

[0288] Refer again Figure 15The deposition apparatus 2000 may include a camera 2800 for detecting substrate alignment keys 3100 and mask alignment keys 4600. For example, the deposition apparatus 2000 may include multiple cameras 2800 for detecting substrate alignment keys 3100 and mask alignment keys 4600. Figure 15 The deposition apparatus 2000 has been shown to include two cameras 2800, but the number of cameras 2800 can vary depending on the number of substrate alignment keys 3100 and mask alignment keys 4600. Therefore, the scope of this disclosure is not limited by the number of cameras 2800.

[0289] Figure 24 It is used to describe Figure 15 A schematic cross-sectional view of the camera and lighting components shown.

[0290] Reference Figure 24 A camera 2800 for detecting the substrate alignment key 3100 and the mask alignment key 4600 can be arranged on one side of the mask chuck 2400. According to one or more embodiments, the deposition apparatus 2000 may include: an illumination section 2810 that provides light that can be transmitted through the backplane substrate 3000 and the deposition mask 4000; and a camera 2800 that can be used to detect the light transmitted through the backplane substrate 3000 and the deposition mask 4000. For example, light provided from the illumination section 2810 can be transmitted through the substrate alignment key 3100 and the mask alignment key 4600, and the light transmitted through the substrate alignment key 3100 and the mask alignment key 4600 can be detected by the camera 2800.

[0291] The illumination portion 2810 may be disposed within an edge portion of the lower surface of the substrate chuck 2300 and may be used to provide infrared light that can be transmitted through the backplane substrate 3000 and the deposition mask 4000. For example, the illumination portion 2810 may include an infrared lamp in the substrate chuck 2300 (e.g., mounted in the substrate chuck 2300), and a through-hole 2820 may be provided at the edge portion of the mask chuck 2400 through which light transmitted through the backplane substrate 3000 and the deposition mask 4000 passes. The infrared lamp may be used to provide near-infrared (NIR) light or short-wave infrared (SWIR) light, and the light transmitted through the backplane substrate 3000 and the deposition mask 4000 may be guided to the camera 2800 via an optical unit 2830 (or prism unit) disposed below the mask chuck 2400. For example, the infrared lamp may be used to provide infrared light with a wavelength of about 1000 nm to about 1200 nm.

[0292] Optical unit 2830 may include reflectors 2832 and 2834 for guiding light transmitted through backplane substrate 3000 and deposition mask 4000 to camera 2800, and camera 2800 may obtain image information from the light guided by optical unit 2830. For example, image information may include position information of substrate alignment key 3100 and mask alignment key 4600, and substrate chuck drive unit 2500 and / or mask chuck drive unit 2600 may be used to move and / or rotate substrate chuck 2300 and / or mask chuck 2400 based on image information obtained by camera 2800 to align backplane substrate 3000 and deposition mask 4000 with each other.

[0293] According to one or more embodiments, alignment between the backplate substrate 3000 and the deposition mask 4000 can be performed after adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400. As an example, the camera 2800 can acquire image information including the substrate alignment key 3100 and the mask alignment key 4600, and the hexapod actuator 2510 of the substrate chuck drive unit 2500 can be used to move the substrate chuck 2300 in a first direction DR1 and a second direction DR2 and to rotate the substrate chuck 2300 in a third direction DR3 based on the image information. As another example, the piezoelectric actuator 2610 of the mask chuck drive unit 2600 can be used to move the mask chuck 2400 in the first direction DR1 and the second direction DR2 and to rotate the mask chuck 2400 in a third direction DR3 based on the image information.

[0294] According to one or more embodiments, after aligning the backplate substrate 3000 with the deposition mask 4000, the backplate substrate 3000 can be positioned on the deposition mask 4000. As an example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 such that the gap between the backplate substrate 3000 and the deposition mask 4000 becomes a selected gap, for example, a gap of about a few micrometers. As another example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 such that the backplate substrate 3000 contacts the deposition mask 4000.

[0295] After positioning the backplane substrate 3000 on the deposition mask 4000, the deposition source 2200 can provide vapor-phase deposited material onto the backplane substrate 3000 through the deposition mask 4000, thus a deposited material layer can be formed on the backplane substrate 3000 (e.g., a deposited material layer can be formed on the backplane substrate 3000). For example, by aligning the backplane substrate 3000 with the deposition mask 4000, the first electrode AND of the backplane substrate 3000 can be positioned on the pixel opening 4312 of the deposition mask 4000. Subsequently, the deposition source 2200 can be used to evaporate organic material used to form a light-emitting layer on the first electrode AND of the backplane substrate 3000. The evaporated organic material can be provided onto the first electrode AND of the backplane substrate 3000 through the pixel opening 4312 of the deposition mask 4000, thus a light-emitting layer can be formed on the first electrode AND of the backplane substrate 3000 (e.g., a light-emitting layer can be formed on the first electrode AND of the backplane substrate 3000).

[0296] Figure 25 It is used to describe by Figure 24 The image shown is a schematic diagram of an image obtained by the camera.

[0297] Reference Figure 25 The camera 2800 can detect light transmitted through the substrate alignment key 3100 and the mask alignment key 4600. The image 2900 detected by the camera 2800 may include a key pattern image 2920 of the substrate alignment key 3100 and a surface modification region image 2930 of the mask alignment key 4600. In this case, light incident on the key pattern 3120 of the substrate alignment key 3100 can be reflected by the key pattern 3120, therefore, the key pattern 3120 of the substrate alignment key 3100 can be displayed relatively darkly in the detected image 2900.

[0298] According to one or more embodiments, light incident on the surface-modified region 4640 can be scattered and / or refracted by the surface-modified region 4640, so that the surface-modified region 4640 of the mask alignment key 4600 can be displayed relatively darkly in the detected image 2900. Additionally, light transmitted through the bond region 3110 of the substrate alignment key 3100 and the peripheral region 4610 of the mask alignment key 4600 can be detected by the camera 2800, and the bond region 3110 of the substrate alignment key 3100 and the peripheral region 4610 of the mask alignment key 4600 can be displayed in the detected image 2900 as a peripheral image 2910 surrounding (e.g., around) the bond pattern image 2920 and the surface-modified region image 2930. In this case, the peripheral image 2910 can be displayed as brighter than the bond pattern image 2920 and the surface-modified region image 2930.

[0299] According to one or more embodiments, in order to improve the recognition rate of the mask alignment key 4600 (e.g., the recognition rate of the surface modification region 4640) from the detected image 2900, the contrast (C) between the peripheral image 2910 and the surface modification region image 2930 can be about 0.4 or greater. For example, the contrast (C) between the peripheral image 2910 and the surface modification region image 2930 can be calculated by the following equation.

[0300]

[0301] In the equation above, GL MAX This can refer to the maximum gray level of the outer image (2910), and GL MIN This refers to the smallest gray level in the 2930-pixel image of the surface-modified region. For example, GL MAX It can refer to the gray level of the brightest pixel among the 2910 pixels of the outer image, and GL MIN It can refer to the gray level of the darkest pixel in the 2930 pixels of the surface-modified region image.

[0302] Figure 26 It is used to describe Figure 22 A schematic enlarged cross-sectional view of the patterned area shown. Figures 27 to 29 It is used to describe the formation Figure 26 A schematic enlarged cross-sectional view of the method for creating the recessed and surface-modified regions shown.

[0303] Reference Figure 26 A bond opening 4220, exposing a surface portion of the mask substrate 4100 (e.g., a portion where the patterned region 4620 may be formed), can be formed through the intermediate inorganic film 4200, and a recess 4630 and a surface-modified region 4640 can be formed in the surface portion of the mask substrate 4100 exposed by the bond opening 4220. According to one or more embodiments, the surface-modified region 4640 may have relatively low reflectivity, relatively high absorptivity, and relatively low transmittance to increase the contrast between the peripheral image 2910 and the surface-modified region image 2930. According to one or more embodiments, the surface-modified region 4640 may have a larger surface roughness than the peripheral region 4610. For example, the peripheral region 4610 may have an arithmetic mean roughness (Ra) of about 10 Å or less (e.g., about 1 Å to about 10 Å), and the surface-modified region 4640 may have an arithmetic mean roughness (Ra) of about 50 nm to about 1 μm. Therefore, the surface-modified region 4640 can have lower reflectivity, higher absorptivity, and lower transmittance than the peripheral region 4610. As a result, the contrast between the peripheral image 2910 and the surface-modified region image 2930 can be increased, thus significantly improving the recognition rate of the patterned region 4620.

[0304] According to one or more embodiments, the RIE process for forming the surface-modified region 4640 may include forming a polymer layer 4604 by utilizing a passivation gas (see...). Figure 27 The process includes a first step (e.g., an action or task), a second step (e.g., an action or task) by partially removing the polymer layer 4604 using sputtering gas and reactive gas, and a third step (e.g., an action or task) by removing the surface portion of the mask substrate 4100 using reactive gas. The first step (e.g., an action or task), the second step (e.g., an action or task), and the third step (e.g., an action or task) can be repeated.

[0305] For example, such as Figure 27 As shown, a photoresist pattern 4602 that exposes the portion of the bond opening 4220 to be formed can be formed on an intermediate inorganic film 4200 (e.g., a photoresist pattern 4602 that exposes the portion of the bond opening 4220 to be formed can be formed on the intermediate inorganic film 4200), and the bond opening 4220 exposing the surface portion of the mask substrate 4100 can be formed by using the photoresist pattern 4602 as an etching mask through an anisotropic etching process (e.g., RIE process). Subsequently, a polymer layer 4604 can be formed on the surface portion of the mask substrate 4100 using a passivating gas (e.g., a polymer layer 4604 can be formed on the surface portion of the mask substrate 4100 using a passivating gas). Carbon-containing gases such as CF4, C2F6, C3F6, C4F6 and / or C4F8 can be used as passivating gases, and the polymer layer 4604 can be made of, for example, CF4. x Free radical formation. Although not shown, the etching apparatus for performing the RIE process may include a chuck on which a mask substrate 4100 can be placed and a plasma source for forming the process gas into a plasma state.

[0306] Reference Figure 28A second step (e.g., an action or task) can be performed such that the surface of the mask substrate 4100 and / or the bottom surface of the recess 4630 can be partially exposed. According to one or more embodiments, the polymer layer 4604 can be partially removed by utilizing sputtering gases such as Ar, He, Ne, Xe, and / or O2, and reactive gases such as SF6, CHF3, CH3F, CH2F2, CBrF3, CCl4, O2, and / or H2. For example, the polymer layer 4604 can be irregularly removed by ion bombardment, and thus, a portion 4606 of the polymer layer 4604 can be partially and irregularly retained on the patterned region 4620. The second step (e.g., an action or task) can be performed in a shorter time than the first step (e.g., an action or task), and bias power can be applied to a chuck on which the mask substrate 4100 can be placed. For example, the first step (e.g., an action or task) can be performed for approximately 1.5 to 3.5 seconds, and the second step (e.g., an action or task) can be performed for approximately 0.5 to approximately 1 second. Additionally, during the period when the first step (e.g., an action or task) can be performed, bias power may not be applied to the chuck on which the mask substrate 4100 can be placed, while during the period when the second step (e.g., an action or task) is performed, bias power of approximately 100W to approximately 400W may be applied to the chuck on which the mask substrate 4100 can be placed.

[0307] Reference Figure 29 The surface portion of the mask substrate 4100 can be removed using a reactive gas. In this case, the remaining portion 4606 of the polymer layer 4604 can be used as an etch stop pattern in a third step (e.g., an action or task) and can be removed together with the surface portion of the mask substrate 4100. The surface portion of the mask substrate 4100 can be isotropically etched, for example, by fluorine radicals. For example, the third step (e.g., an action or task) can be performed for about 3 to about 4 seconds, and a bias power of about 10W to 20W can be applied to a chuck on which the mask substrate 4100 can be placed.

[0308] The remaining portion 4606 of the polymer layer 4604 may have an irregular shape, and therefore, irregular pillars 4608 or protrusions may be formed (e.g., on) the patterned area 4620. As a result, during the periods in which the first step (e.g., an action or task), the second step (e.g., an action or task), and the third step (e.g., an action or task) are repeatedly performed, the recess 4630 may be as follows: Figure 26 As shown, the surface modification region 4640, which includes irregular pillars 4608 or protrusions, may be formed in the patterned region 4620 on the bottom surface of the recess 4630 (e.g., formed on the bottom surface of the recess 4630).

[0309] After forming the recesses 4630 and surface-modified regions 4640 as described above, the photoresist pattern 4602 can be removed by ashing and / or stripping processes, and as... Figure 26 As shown, film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620 (e.g., film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620). In this case, film 4300 can be used as a passivation layer for protecting the patterned region 4620. For example, film 4300 may include passivation regions 4330 disposed on the patterned region 4620 (e.g., surface-modified region 4640).

[0310] Figure 30 It is used to describe Figure 26 A schematic enlarged cross-sectional view of another example of the patterned area shown.

[0311] Reference Figure 30 The patterned area 4620 may have a plurality of recesses 4632 extending parallel to each other, and may include a surface-modified area 4642 disposed on the bottom surface of the recesses 4632. Figure 30 It has been shown that five recesses 4632 and five surface modification regions 4642 can be provided, but the number of recesses 4632 and surface modification regions 4642 can be changed. Therefore, the scope of this disclosure is not limited by the number of recesses 4632 and surface modification regions 4642. Furthermore, in Figure 30 It has been shown that the recess 4632 can extend in the second direction DR2, but the direction of extension of the recess 4632 can be changed, and the scope of this disclosure is not limited by the direction of extension of the recess 4632.

[0312] According to one or more embodiments, the recess 4632 and the surface-modified region 4642 can be formed by a RIE process, and each of the surface-modified regions 4642 may include a plurality of irregular pillars 4608 or protrusions. Furthermore, the intermediate inorganic film 4200 may have a plurality of bond openings 4222, and the film 4300 may include passivation regions 4332 disposed on the patterned region 4620. The method for forming the recess 4632 and the surface-modified region 4642 can be the same as described above. Figure 27-29 The methods used are basically the same, so a detailed description is not required.

[0313] According to one or more embodiments, light incident on the surface-modified region 4642 can be scattered and / or refracted by the surface-modified region 4642. Therefore, the surface-modified region 4642 can be displayed as relatively dark stripes in the image 2900 obtained by the camera 2800.

[0314] Figure 31 It is used to describe Figure 26A schematic enlarged cross-sectional view of another example of the patterned area shown.

[0315] Reference Figure 31 The patterned region 4620 may have an approximately rectangular shape in a planar view and may have a recess 4634 formed in a surface portion of the mask substrate 4100. Additionally, the patterned region 4620 may include a surface-modified region 4644 formed in a bottom surface portion of the recess 4634, and the surface-modified region 4644 may have an approximately rectangular shape. According to one or more embodiments, the recess 4634 and the surface-modified region 4644 may be formed by a wet etching process. For example, the intermediate inorganic film 4200 may have bond openings 4224 that expose the patterned region 4620, and the recess 4634 and the surface-modified region 4644 may be formed by a metal-assisted chemical etching (MACE) process using the intermediate inorganic film 4200 as an etching mask.

[0316] According to one or more embodiments, the recess 4634 and the surface-modified region 4644 can be formed by a MACE process using an etchant comprising metal catalyst particles and a TMAH solution and / or a KOH solution. For example, the metal catalyst particles may include metals such as gold (Au), platinum (Pt), palladium (Pd), silver (Ag), iron (Fe), nickel (Ni), copper (Cu), and / or aluminum (Al), and the etchant may include about 10 wt% to about 40 wt% of a TMAH solution and / or about 10% to about 40% of a KOH solution based on the total weight (100 wt%) of the etchant. Additionally, for example, if a TMAH solution is used (e.g., when using a TMAH solution), the MACE process can be performed at a temperature of about 70°C to about 90°C, and if a KOH solution is used (e.g., when using a KOH solution), the MACE process can be performed at a temperature of about 50°C to about 80°C.

[0317] During the MACE process, the surface portion of the mask substrate 4100 can be removed using a TMAH solution or a KOH solution. In this case, the single-crystal silicon substrate used as the mask substrate 4100... <100> The crystal orientation can be a third orientation DR3, therefore, the recess 4634 can be formed by a MACE process to have a width that gradually decreases from the surface of the mask substrate 4100 (e.g., the front surface of the mask substrate 4100) toward the surface modification region 4644. For example, the inner surface 4634s of the recess 4634 can have a tilt angle of about 54.7° relative to the front surface of the mask substrate 4100.

[0318] According to one or more embodiments, the metal catalyst particles can have a size of about 5 nm to about 50 nm. During the period in which the MACE process can be performed, the bottom surface portion of the recess 4634 can be irregularly etched by the metal catalyst particles, thus forming a surface-modified region 4644 including pillars 4608 or protrusions with irregular shapes at the bottom surface portion of the recess 4634. Additionally, after the recess 4634 and the surface-modified region 4644 can be formed, a film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620 (e.g., the film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620). In this case, the film 4300 can include a passivation region 4334 on the patterned region 4620.

[0319] According to one or more embodiments, the patterned region 4620 may include an inner surface 4634s of a recess 4634 and a surface-modified region 4644. In this case, light incident on the inner surface 4634s of the recess 4634 can be refracted by the inner surface 4634s of the recess 4634, and light incident on the surface-modified region 4644 can be scattered and / or refracted by the surface-modified region 4644. As a result, the patterned region 4620 can be displayed relatively darkly in the image 2900 obtained by the camera 2800, thus significantly improving the recognition rate of the patterned region 4620.

[0320] Figure 32 It is used to describe Figure 26 A schematic enlarged cross-sectional view of another example of the patterned area shown.

[0321] Reference Figure 32 The patterned area 4620 may have multiple recesses 4636 extending parallel to each other. Figure 32 It has been shown that pattern area 4620 can have five recesses 4636, but the number of recesses 4636 can be varied; therefore, the scope of this disclosure is not limited by the number of recesses 4636. Additionally, in Figure 32 It has been shown that the recess 4636 can extend in the second direction DR2, but the direction of extension of the recess 4636 can be changed, and the scope of this disclosure is not limited by the direction of extension of the recess 4636.

[0322] According to one or more embodiments, the recess 4636 can be formed by a wet etching process. For example, the intermediate inorganic film 4200 may have a plurality of bond openings 4226 extending in a direction parallel to the recess 4636, and the intermediate inorganic film 4200 can be used as an etching mask to form the recess 4636 by a wet etching process. According to one or more embodiments, each of the recesses 4636 may be defined by inclined inner surfaces 4636s connected to each other, and each of the inclined inner surfaces 4636s may extend in a direction parallel to the recess 4636. For example, the recess 4636 can be formed by a wet etching process using an etchant such as a TMAH solution and / or a KOH solution. In this case, the single-crystal silicon substrate used as the mask substrate 4100 <100> The crystal orientation can be a third orientation DR3, so the inner surfaces 4636s of the recess 4636 can be formed by a wet etching process to have an inclination angle of about 54.7° relative to the front surface of the mask substrate 4100, and can be connected to each other at the bottom portion of each of the recesses 4636.

[0323] According to one or more embodiments, light incident on the inner surface 4636s of the recess 4636 can be refracted by the inner surface 4636s of the recess 4636. Therefore, the recess 4636 can be displayed as relatively dark stripes in the image 2900 obtained by the camera 2800. Additionally, according to one or more embodiments, after forming the recess 4636, a film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620 (e.g., the film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620), and may include a passivation region 4336 disposed on the patterned region 4620.

[0324] Figure 33 It is used to describe Figure 22 A schematic cross-sectional view of another example of the deposition mask shown.

[0325] Reference Figure 33 The deposition mask 4000 may include a mask substrate 4100, a film 4300 disposed on the mask substrate 4100, and a mask alignment key 4600 disposed on the mask substrate 4100. The mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. Additionally, the deposition mask 4000 may include an intermediate inorganic film 4200, a second intermediate inorganic film 4400, and / or a post-inorganic film 4500. As an example, the patterned region 4620 may have, for example, a... Figure 26 The recess 4630 shown may include a surface-modified region 4640 formed in the bottom surface portion of the recess 4630. As another example, the patterned region 4620 may have, for instance... Figure 30 The recess 4632 shown may include a surface-modified region 4642 formed in the bottom surface portion of the recess 4632. As another example, the patterned region 4620 may have, for instance... Figure 31 The recess 4634 shown may include a surface-modified region 4644 formed in the bottom surface portion of the recess 4634. As another example, the patterned region 4620 may have, for instance... Figure 32 The depression shown is 4636.

[0326] In one or more embodiments, the mask substrate 4100, the intermediate inorganic film 4200, the film 4300, the second intermediate inorganic film 4400, the rear inorganic film 4500, and the mask alignment key 4600 may be as described above. Figures 17 to 32 The mask substrate 4100, intermediate inorganic film 4200, film 4300, second intermediate inorganic film 4400, rear inorganic film 4500 and mask alignment key 4600 are basically the same, so their detailed description is not required.

[0327] According to one or more embodiments, the deposition mask 4000 may further include a passivation film 4250 disposed on the mask substrate 4100 and the mask alignment bond 4600. For example, the deposition mask 4000 may further include a passivation film 4250 disposed on the patterned region 4620 and the intermediate inorganic film 4200. The passivation film 4250 may be used to protect the patterned region 4620, and a film 4300 may be disposed on the passivation film 4250. For example, the passivation film 4250 may include silicon oxide (e.g., SiO2). x It can be formed with a thickness of about 0.5 μm to about 1 μm by CVD process.

[0328] According to one or more embodiments, the passivation film 4250 may have a third intermediate opening 4252, allowing the mask unit region 4310 to be exposed toward the deposition source 2200. For example, after forming the unit opening 4110, the intermediate inorganic film 4200 and the passivation film 4250 may be partially removed by a wet etching process using an etchant such as BOE or diluted hydrofluoric acid, thus forming the intermediate opening 4210 and the third intermediate opening 4252. The intermediate opening 4210 and the third intermediate opening 4252 can connect the pixel opening 4312 and the unit opening 4110 to each other, and during the period in which the deposition process is performed, vapor-deposited material can be provided onto the backplane substrate 3000 through the rear opening 4510, the second intermediate opening 4410, the unit opening 4110, the intermediate opening 4210, the third intermediate opening 4252, and the pixel opening 4312.

[0329] Figure 34 It is used to describe Figure 22A schematic cross-sectional view of another example of the deposition mask shown.

[0330] Reference Figure 34 The deposition mask 4000 may include a mask substrate 4100, a film 4300 disposed on the mask substrate 4100, and a mask alignment key 4600 disposed on the mask substrate 4100. The mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. Additionally, the deposition mask 4000 may include an intermediate inorganic film 4200, a second intermediate inorganic film 4400, and a post-inorganic film 4500. In one or more embodiments, the mask substrate 4100, the intermediate inorganic film 4200, the film 4300, the second intermediate inorganic film 4400, the post-inorganic film 4500, and the mask alignment key 4600 may be as described above. Figures 17 to 32 The mask substrate 4100, intermediate inorganic film 4200, film 4300, second intermediate inorganic film 4400, rear inorganic film 4500 and mask alignment key 4600 are basically the same, so their detailed description is not required.

[0331] According to one or more embodiments, a patterned region 4620 may be formed on a surface portion of the intermediate inorganic film 4200. In this case, a portion of the intermediate inorganic film 4200 surrounding (e.g., around) the patterned region 4620 may serve as a peripheral region 4610 of the mask alignment key 4600. For example, the patterned region 4620 may have a recess 4638 formed in the surface portion of the intermediate inorganic film 4200, and a surface-modified region 4648 may be formed in the bottom surface portion of the recess 4638. The recess 4638 and the surface-modified region 4648 may be formed by an anisotropic etching process (e.g., RIE process). For example, the RIE process can be performed using passivation gases (such as CF4, C2F6, C3F6, C4F6 and / or C4F8) for forming the polymer layer 4604, sputtering gases (such as Ar, He, Ne, Xe and / or O2) for anisotropically etching the polymer layer 4604 and the intermediate inorganic film 4200, and reactive gases (such as SF6, CHF3, CH3F, CH2F2 and / or O2) for isotropically etching the intermediate inorganic film 4200. In one or more embodiments, the method for forming the recess 4638 and the surface-modified region 4648 can be the same as described above. Figures 27 to 29 The methods used are basically the same, so a detailed description is not required.

[0332] Figure 35 It is used to describe Figure 22 A schematic cross-sectional view of another example of the deposition mask shown.

[0333] Reference Figure 35 The deposition mask 4000 may include a mask substrate 4100, a film 4300 disposed on the mask substrate 4100, and a mask alignment key 4600 disposed on the mask substrate 4100. The mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. Additionally, the deposition mask 4000 may include an intermediate inorganic film 4200, a second intermediate inorganic film 4400, and a post-inorganic film 4500. In one or more embodiments, the mask substrate 4100, the intermediate inorganic film 4200, the film 4300, the second intermediate inorganic film 4400, the post-inorganic film 4500, and the mask alignment key 4600 may be as described above. Figures 17 to 32 The mask substrate 4100, intermediate inorganic film 4200, film 4300, second intermediate inorganic film 4400, rear inorganic film 4500 and mask alignment key 4600 are basically the same, so their detailed description is not required.

[0334] According to one or more embodiments, a patterned region 4620 may be formed on a surface portion of the film 4300. In this case, a portion of the film 4300 surrounding (e.g., around) the patterned region 4620 may serve as a peripheral region 4610 of the mask alignment key 4600. For example, the patterned region 4620 may have a recess 4639 formed in the surface portion of the film 4300, and a surface-modified region 4649 may be formed in the bottom surface portion of the recess 4639. The recess 4639 and the surface-modified region 4649 may be formed by an anisotropic etching process (e.g., RIE process). For example, the RIE process can be performed using passivation gases (such as CF4, C2F6, C3F6, C4F6 and / or C4F8) for forming the polymer layer 4604, sputtering gases (such as Ar, He, Ne, Xe and / or O2) for anisotropically etching the polymer layer 4604 and the film 4300, and reactive gases (such as SF6, CHF3, CH3F, CH2F2 and / or O2) for isotropically etching the film 4300. In one or more embodiments, the method for forming the recess 4639 and the surface-modified region 4649 can be the same as described above. Figures 27 to 29 The methods used are basically the same, so a detailed description is not required.

[0335] According to one or more embodiments, a passivation film 4350 may be disposed on the film 4300 and the mask alignment key 4600. The passivation film 4350 may be used to protect the patterned area 4620 of the mask alignment key 4600. For example, the passivation film 4350 may comprise silicon oxide (e.g., SiO₂). x ) and / or silicon nitride (e.g., SiN) xAnd it can be formed by a CVD process. If the passivation film 4350 includes silicon oxide (e.g., SiO2), it can be formed by a CVD process. x (For example, made of silicon oxide (e.g., SiO2) x (Formed as follows) (For example, when the passivation film 4350 includes silicon oxide (e.g., SiO2) x (For example, made of silicon oxide (e.g., SiO2) x When the cell opening 4110 can be formed, the passivation film 4350 can be formed on the film 4300 and the mask alignment bond 4600 (e.g., the passivation film 4350 can be formed on the film 4300 and the mask alignment bond 4600). As another example, if the passivation film 4350 comprises silicon nitride (e.g., SiN...). x (For example, silicon nitride (e.g., SiN) x (Formed as follows) (For example, when the passivation film 4350 includes silicon nitride (e.g., SiN) x (For example, silicon nitride (e.g., SiN) x When the process is completed, after the depression 4639 and the surface modification region 4649 can be formed, the passivation film 4350 can be formed on the film 4300 and the mask alignment key 4600 (for example, the passivation film 4350 can be formed on the film 4300 and the mask alignment key 4600).

[0336] Figure 36 It is used to describe Figure 24 A schematic cross-sectional view of another example of the camera and lighting components shown.

[0337] Reference Figure 36 The illumination section 2840 can provide light through the deposition mask 4000 to the backing substrate 3000, and the camera 2800 can be used to detect light reflected from the backing substrate 3000 and transmitted through the deposition mask 4000. For example, a via 2820 can be provided at the edge portion of the mask chuck 2400, through which light provided from the illumination section 2840 and light reflected from the backing substrate 3000 pass, and an optical unit 2850 (or prism unit) can be arranged below the mask chuck 2400 (e.g., under), which guides the light provided from the illumination section 2840 to the backing substrate 3000 and guides the light reflected from the backing substrate 3000 to the camera 2800.

[0338] Light provided from illumination section 2840 can be transmitted through deposition mask 4000 and provided onto backplane substrate 3000, and light reflected from backplane substrate 3000 can be transmitted through deposition mask 4000 and guided to camera 2800. For example, illumination section 2840 may include a light-emitting diode (LED) lamp for providing visible light. As an example, illumination section 2840 can provide visible light with a wavelength of about 413 nm or about 530 nm, and optical unit 2850 may include beam splitter 2852 and reflector 2854. Beam splitter 2852 can be used to transmit some light provided from illumination section 2840 and can reflect some light reflected from backplane substrate 3000 toward camera 2800. Reflector 2854 can reflect light transmitted through beam splitter 2852 toward backplane substrate 3000 and can reflect light reflected from backplane substrate 3000 toward beam splitter 2852.

[0339] Figure 37 It is used to describe Figure 22 A schematic cross-sectional view of another example of a mask alignment key shown.

[0340] Reference Figure 37 The mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. Additionally, the mask alignment key 4600 may include a surface layer 4150 of a mask substrate 4100, and the mask substrate 4100 may have a second key opening 4140 that exposes the mask alignment key 4600. For example, the second key opening 4140 may be used to expose the surface layer 4150 of the mask substrate 4100.

[0341] According to one or more embodiments, the surface layer 4150 of the mask substrate 4100 may have a sufficiently small thickness to allow visible light supplied from the illumination portion 2840 to pass through. For example, the surface layer 4150 of the mask substrate 4100 may have a thickness of about 5 μm to about 50 μm. The patterned region 4620 may be on the surface layer 4150 of the mask substrate 4100 (e.g., formed on the surface layer 4150 of the mask substrate 4100).

[0342] As an example, pattern area 4620 can have, for example, Figure 26 The recess 4630 shown may include a surface-modified region 4640 formed in the bottom surface portion of the recess 4630. As another example, the patterned region 4620 may have, for instance... Figure 30 The recess 4632 shown may include a surface-modified region 4642 formed in the bottom surface portion of the recess 4632. As another example, the patterned region 4620 may have, for instance... Figure 31The recess 4634 shown may include a surface-modified region 4644 formed in the bottom surface portion of the recess 4634. As another example, the patterned region 4620 may have, for instance... Figure 32 The depression shown is 4636.

[0343] According to one or more embodiments, the second bond opening 4140 can be formed by a wet etching process using an etchant such as a TMAH solution and / or a KOH solution. For example, the deposition mask 4000 may include an etch stop region 4160 for preventing or reducing etching of the mask alignment bond 4600 during periods in which a wet etching process can be performed. According to one or more embodiments, the etch stop region 4160 may be formed in a surface layer 4150 of the mask substrate 4100 and may include one or more group III impurities. For example, the etch stop region 4160 may be formed below the surface modification region 4640 and may have an area larger than the second bond opening 4140. For example, the etch stop region 4160 may include one or more group III impurities selected from boron (B) and / or gallium (Ga), and one or more group III impurities may be implanted into the surface layer 4150 of the mask substrate 4100 by an ion implantation process.

[0344] For example, after forming an intermediate inorganic film 4200 on the mask substrate 4100, a photoresist pattern can be formed on the intermediate inorganic film 4200 (e.g., a photoresist pattern can be formed on the intermediate inorganic film 4200), and an ion implantation process can be performed by using the photoresist pattern as an ion implantation mask. Additionally, a heat treatment process can be performed to recover lattice damage to the mask substrate 4100 caused by the ion implantation process. For example, the heat treatment process can be performed at a temperature of about 800°C to about 1000°C.

[0345] One or more impurities selected from Group III can increase etch resistance to etchants such as TMAH solution and / or KOH solution, thus preventing or reducing etching of mask-aligned bonds 4600 in wet etching processes used to form the second bond opening 4140. For example, the etch stop region 4160 can have approximately 2E19 atoms / cm². 3 Approximately 3E20 atoms / cm 3 The concentration of impurities.

[0346] For example, the second bond opening 4140 may include a third bond opening 4520 penetrating the rear inorganic film 4500, a fourth bond opening 4420 penetrating the second intermediate inorganic film 4400, and a fifth bond opening 4170 exposing the etch stop region 4160 through the mask substrate 4100. For example, the third bond opening 4520 and the fourth bond opening 4420 may be formed concurrently (e.g., simultaneously) with the rear opening 4510 and the second intermediate opening 4410, respectively, and the fifth bond opening 4170 may be formed concurrently (e.g., simultaneously) with the cell opening 4110. In this case, a wet etching process for forming the cell opening 4110 and the fifth bond opening 4170 may be performed until the intermediate inorganic film 4200 is exposed, and the mask alignment bond 4600 may be protected by the etch stop region 4160.

[0347] According to one or more embodiments, visible light provided from the illumination portion 2840 can illuminate the mask alignment key 4600 through the second key opening 4140, and the light incident on the surface-modified region 4640 can be scattered and / or refracted by the surface-modified region 4640. Light transmitted through the peripheral region 4610 of the mask alignment key 4600 can be reflected by the backplate substrate 3000. The light reflected by the backplate substrate 3000 can pass through the peripheral region 4610 of the mask alignment key 4600 and is then detected by the camera 2800.

[0348] According to one or more embodiments, although not in Figure 37 As shown, however, the deposition mask 4000 may also include, for example... Figure 33 The passivation film 4250 shown is shown.

[0349] Additionally, according to one or more embodiments, the patterned area 4620 may have, for example... Figure 34 The recess 4638 shown is formed in the surface portion of the intermediate inorganic film 4200 and may include a surface-modified region 4648 formed in the bottom surface portion of the recess 4638. In this case, an etch stop region 4160 may be formed in the surface layer 4150 of the mask substrate 4100 to overlap with the patterned region 4620 and the peripheral region 4610 formed in the surface portion of the intermediate inorganic film 4200, and a second bond opening 4140 may be formed to expose the etch stop region 4160. For example, the etch stop region 4160 may be formed in the surface portion of the mask substrate 4100, and a mask alignment bond 4600 formed in the intermediate inorganic film 4200 may be disposed on the etch stop region 4160.

[0350] Figure 38 It is used to describe Figure 22 A schematic cross-sectional view of another example of a mask alignment key shown.

[0351] Reference Figure 38 The mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. According to one or more embodiments, the patterned region 4620 may have a recess 4639 formed in a surface portion of the film 4300 (see...). Figure 35 ), and may include a surface modification region 4649 in the bottom surface portion of recess 4639 (see Figure 35 According to one or more embodiments, a passivation film 4350 may be disposed on film 4300 and mask alignment key 4600. In one or more embodiments, recess 4639, surface modification region 4649, and passivation film 4350 may be disposed as described above. Figure 35 The described depression 4639, surface modification region 4649 and passivation film 4350 are basically the same, so detailed descriptions are not required.

[0352] According to one or more embodiments, the mask substrate 4100 may have a second bond opening 4142 that exposes the mask alignment key 4600. For example, the second bond opening 4142 may include a third bond opening 4522 penetrating the rear inorganic film 4500, a fourth bond opening 4422 penetrating the second intermediate inorganic film 4400, a fifth bond opening 4172 penetrating the mask substrate 4100, and a sixth bond opening 4260 penetrating the intermediate inorganic film 4200. For example, the third bond opening 4522 and the fourth bond opening 4422 may be formed concurrently (e.g., simultaneously) with the rear opening 4510 and the second intermediate opening 4410, respectively; the fifth bond opening 4172 may be formed concurrently (e.g., simultaneously) with the cell opening 4110; and the sixth bond opening 4260 may be formed concurrently (e.g., simultaneously) with the intermediate opening 4210.

[0353] Figures 39 to 45 This is a schematic cross-sectional view used to describe a method of manufacturing a deposition mask according to one or more embodiments of the present disclosure.

[0354] Reference Figure 39 The intermediate inorganic film 4200 can be formed on the mask substrate 4100 (e.g., the intermediate inorganic film 4200 can be formed on the mask substrate 4100). The mask substrate 4100 can include monocrystalline silicon (e.g., made of monocrystalline silicon). For example, a monocrystalline silicon substrate having a thickness of about 700 μm to about 800 μm (e.g., about 775 μm) can be used as the mask substrate 4100.

[0355] The intermediate inorganic film 4200 may include, for example, silicon oxide (e.g., SiO2). x (For example, made of silicon oxide (e.g., SiO2) xThe intermediate inorganic film 4200 can be formed on the front surface of the mask substrate 4100 (e.g., the intermediate inorganic film 4200 can be formed on the front surface of the mask substrate 4100 by a thermal oxidation process) to have a thickness of about 0.3 μm to about 2 μm. Additionally, a second intermediate inorganic film 4400 can be formed on the rear surface of the mask substrate 4100 (e.g., the second intermediate inorganic film 4400 can be formed on the rear surface of the mask substrate 4100). For example, the second intermediate inorganic film 4400 can be formed concurrently (e.g., simultaneously) with the intermediate inorganic film 4200 by a thermal oxidation process. Therefore, the second intermediate inorganic film 4400 can comprise a material substantially the same as the material of the intermediate inorganic film 4200 (e.g., made of a material substantially the same as the material of the intermediate inorganic film 4200), and can have a thickness substantially the same as the thickness of the intermediate inorganic film 4200.

[0356] Reference Figure 40 Mask alignment key 4600 (see Figure 22 and Figure 23 Mask alignment keys 4600 can be formed on the mask substrate 4100 (for example, mask alignment keys 4600 can be formed on the mask substrate 4100). Figure 22 and Figure 23 According to one or more embodiments, the mask alignment key 4600 may include a patterned region 4620 and a peripheral region 4610 surrounding (e.g., around) the patterned region 4620. The patterned region 4620 may have a recess 4630 formed in a surface portion of the mask substrate 4100, and may include a surface-modified region 4640 formed in a bottom surface portion of the recess 4630. According to one or more embodiments, the surface-modified region 4640 of the patterned region 4620 may have a larger surface roughness than the peripheral region 4610.

[0357] According to one or more embodiments, the recess 4630 and the surface-modified region 4640 can be formed by a RIE process. For example, the recess 4630 can be formed in a surface portion of the mask substrate 4100 by a RIE process, and the surface-modified region 4640 can be formed in a bottom surface portion of the recess 4630 by a RIE process. For example, as referenced above. Figures 27 to 29The photoresist pattern 4602, which partially exposes the intermediate inorganic film 4200, can be formed on the intermediate inorganic film 4200 (e.g., a photoresist pattern 4602 partially exposing the intermediate inorganic film 4200 can be formed on the intermediate inorganic film 4200), and the photoresist pattern 4602 can be used as an etching mask to form a bond opening 4220 penetrating the intermediate inorganic film 4200 through an anisotropic etching process. Subsequently, the surface portion of the mask substrate 4100 exposed by the bond opening 4220 can be etched by a RIE process, thus forming a recess 4630 and a surface-modified region 4640. In one or more embodiments, the method of forming the bond opening 4220, the recess 4630, and the surface-modified region 4640 can be the same as described above. Figures 27 to 29 The methods used are basically the same, so a detailed description is not required.

[0358] As another example, such as Figure 30 As shown, the patterned area 4620 may have multiple recesses 4632, and the surface modification area 4642 may be formed in the bottom surface portion of the recesses 4632. This can be seen by referring to the above... Figures 27 to 29 The described RIE process is used to form the recess 4632 and the surface modification region 4642.

[0359] As another example, such as Figure 31 As shown, the recess 4634 and the surface-modified region 4644 can be formed using a MACE process. For example, the MACE process can be performed using an etchant comprising metal catalyst particles and a THAH solution and / or a KOH solution, thus the inner surface 4634s of the recess 4634 can be formed with an inclination angle of approximately 54.7° relative to the front surface of the mask substrate 4100. For example, the recess 4634 can be formed with a width that gradually decreases from the front surface of the mask substrate 4100 toward the surface-modified region 4644. The method of forming the recess 4634 and the surface-modified region 4644 using a MACE process is similar to that described above. Figure 31 The methods used are basically the same, so a detailed description is not required.

[0360] As another example, such as Figure 32 As shown, the patterned area 4620 may have a plurality of recesses 4636, and the recesses 4636 may be defined by inclined inner surfaces 4636s connected to each other.

[0361] Reference Figure 41Film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620 (e.g., film 4300 can be formed on the intermediate inorganic film 4200 and the patterned region 4620). In this case, a portion of film 4300 formed on the patterned region 4620 can be used as a passivation region 4330 for protecting the patterned region 4620. For example, film 4300 may include silicon nitride (e.g., SiN). x And it can be formed by a CVD process. For example, silicon source gases such as silane (e.g., SiH4), disilane (e.g., Si2H6) and / or dichlorosilane (DCS) (e.g., SiH2Cl2) and nitrogen source gases such as N2 and / or NH3 can be supplied to the intermediate inorganic film 4200, and the film 4300 can be formed to have a thickness of about 0.3 μm to about 3 μm by the reaction between the silicon source gas and the nitrogen source gas.

[0362] The post-inorganic film 4500 may be formed on the second intermediate inorganic film 4400 (e.g., the post-inorganic film 4500 may be formed on the second intermediate inorganic film 4400). The post-inorganic film 4500 may include silicon nitride (e.g., SiN). x (For example, silicon nitride (e.g., SiN) x (Made from) and can be formed by a CVD process. For example, membrane 4300 and post-inorganic membrane 4500 can be formed concurrently (e.g., simultaneously) by a CVD process. Therefore, post-inorganic membrane 4500 may comprise substantially the same material as membrane 4300 (e.g., made from substantially the same material as membrane 4300) and may have substantially the same thickness as membrane 4300.

[0363] Reference Figure 42 The pixel opening 4312 can be formed by patterning the film 4300. For example, a photoresist pattern that exposes the portion of the film to which the pixel opening 4312 will be formed can be formed on the film 4300 (e.g., a photoresist pattern that exposes the portion of the film to which the pixel opening 4312 will be formed can be formed on the film 4300), and the photoresist pattern can be used as an etch mask to form the pixel opening 4312 penetrating the film 4300 by performing an anisotropic etching process (e.g., a RIE process). The RIE process can be performed until the intermediate inorganic film 4200 is exposed by the pixel opening 4312, and the intermediate inorganic film 4200 can be used as an etch stop film. For example, if the film 4300 comprises silicon nitride (e.g., SiN... x (For example, silicon nitride (e.g., SiN) x (Formed as, for example, when film 4300 includes silicon nitride (e.g., SiN)) x (For example, silicon nitride (e.g., SiN) xWhen the intermediate inorganic membrane 4200 is prepared, the RIE process can be performed by using a first reactive gas including fluorine (such as CF4, C2F6, C3F6, C4F6, C4F8, CHF3, CH3F, CH2F2, NF3 and / or SF6), a second reactive gas including oxygen (such as O2, NO and / or NO2), and sputtering gases (such as He, Ne, Ar and / or Xe) until the intermediate inorganic membrane 4200 is exposed.

[0364] Reference Figure 43 and Figure 44 The cell opening 4110 can be formed by patterning the mask substrate 4100. According to one or more embodiments, a second intermediate opening 4410 and a rear opening 4510 can be formed, which can expose the rear surface portion of the mask substrate 4100 where the cell opening 4110 will be formed. For example, as... Figure 43 As shown, a photoresist pattern that exposes the portion where the rear opening 4510 will be formed can be formed on the rear inorganic film 4500 (e.g., a photoresist pattern that exposes the portion where the rear opening 4510 will be formed can be formed on the rear inorganic film 4500), and an anisotropic etching process (e.g., RIE process) utilizing the photoresist pattern as an etching mask can be performed. The anisotropic etching process described above can be performed until the rear surface portion of the mask substrate 4100 (e.g., the portion where the unit opening 4110 will be formed) can be exposed, thus forming a second intermediate opening 4410 and a rear opening 4510 that penetrate the second intermediate inorganic film 4400 and the rear inorganic film 4500, respectively.

[0365] The unit opening 4110 can be formed using a wet etching process. For example, as... Figure 44 As shown, the mask substrate 4100 can be partially removed by a wet etching process using the second intermediate inorganic film 4400 and the rear inorganic film 4500 as etching masks, thereby exposing the intermediate inorganic film 4200 and forming a cell opening 4110 penetrating the mask substrate 4100. For example, the wet etching process for forming the cell opening 4110 can be performed using an etchant such as a TMAH solution and / or a KOH solution. In this case, the cell opening 4110 can be formed with a width that gradually decreases from the rear surface of the mask substrate 4100 toward the front surface of the mask substrate 4100.

[0366] In the wet etching process used to form the cell opening 4110, the intermediate inorganic film 4200 can be used as an etching stop film. For example, if the intermediate inorganic film 4200 is not provided (e.g., when the intermediate inorganic film 4200 is not provided), the etchant may be provided to the front surface of the mask substrate 4100 through the pixel opening 4312, and hydrogen bubbles may be generated in the pixel opening 4312 by the reaction between the etchant and the mask substrate 4100. In this case, the mask cell region 4310 of the film 4300 may be damaged by hydrogen bubbles, and the intermediate inorganic film 4200 can be used to prevent or reduce the provision of etchant to the front surface of the mask substrate 4100 through the pixel opening 4312.

[0367] Reference Figure 45 The intermediate opening 4210 connecting the pixel opening 4312 and the unit opening 4110 can be formed by patterning the intermediate inorganic film 4200. The intermediate opening 4210 can be formed such that the mask unit region 4310 of the film 4300 can be exposed through the unit opening 4110. The intermediate opening 4210 can be formed by a wet etching process. For example, if the intermediate inorganic film 4200 comprises silicon oxide (e.g., SiO2). x (For example, made of silicon oxide (e.g., SiOx)) (For example, when the intermediate inorganic film 4200 includes silicon oxide (e.g., SiO) x (For example, when made of silicon oxide (e.g., SiOx), the intermediate opening 4210 can be formed by a wet etching process using BOE and / or diluted hydrofluoric acid.

[0368] According to one or more embodiments, passivation film 4250 (see Figure 33 A passivation film 4250 can be formed on the mask substrate 4100 and the mask alignment key 4600 (for example, a passivation film 4250 can be formed on the mask substrate 4100 and the mask alignment key 4600 (see...) Figure 33 For example, after forming pattern area 4620, such as Figure 33 As shown, passivation film 4250 can be formed on patterned region 4620 and intermediate inorganic film 4200 (e.g., passivation film 4250 can be formed on patterned region 4620 and intermediate inorganic film 4200). In this case, film 4300 can be formed on passivation film 4250 (e.g., film 4300 can be formed on passivation film 4250). For example, passivation film 4250 can include silicon oxide (e.g., SiO2). x It can be formed with a thickness of about 0.5 μm to about 1 μm by CVD process.

[0369] According to one or more embodiments, after forming the pixel opening 4312 of the film 4300, a second key opening 4140 exposing the mask alignment key 4600 can be formed by partially removing the mask substrate 4100 (see Figure 37 For example, such as Figure 37 As shown, the mask alignment key 4600 may include a surface layer 4150 of the mask substrate 4100, and the second key opening 4140 may be used to expose the surface layer 4150 of the mask substrate 4100. In this case, the mask alignment key 4600 may include an etch stop region 4160, and the second key opening 4140 may be used to expose the etch stop region 4160. The method of forming the etch stop region 4160 and the second key opening 4140 can be the same as described above. Figure 37 The methods used are basically the same, so a detailed description is not required.

[0370] According to one or more embodiments, after the intermediate inorganic film 4200 is formed, a patterned region 4620 may be formed on a surface portion of the intermediate inorganic film 4200. For example, as... Figure 34 As shown, by forming a photoresist pattern on the intermediate inorganic film 4200 that partially exposes the patterned area 4620, and then using the photoresist pattern as an etching mask to perform a RIE process, a recess 4638 and a surface-modified region 4648 can be formed in the surface portion of the intermediate inorganic film 4200. The method for forming the recess 4638 and the surface-modified region 4648 can be the same as described above. Figure 34 The methods used are basically the same, so a detailed description is not required.

[0371] According to one or more embodiments, although not shown, if the patterned region 4620 is formed on a surface portion of the intermediate inorganic film 4200 (e.g., when the patterned region 4620 is formed on a surface portion of the intermediate inorganic film 4200), then on the mask substrate 4100 (see...) Figure 37 An etch stop region 4160 is formed in the surface layer 4150, overlapping with the mask alignment bond 4600 (see...). Figure 37 And can form a second bond opening 4140 that exposes the etch stop region 4160 through the rear inorganic film 4500, the second intermediate inorganic film 4400 and the mask substrate 4100.

[0372] According to one or more embodiments, after the film 4300 is formed, a patterned region 4620 may be formed on a surface portion of the film 4300. For example, as... Figure 35As shown, by forming a photoresist pattern on film 4300 that partially exposes the patterned area 4620, and then using the photoresist pattern as an etching mask to perform a RIE process, recesses 4639 and surface-modified areas 4649 can be formed in the surface portion of film 4300. Additionally, according to one or more embodiments, such as... Figure 35 As shown, passivation film 4350 can be formed on film 4300 and patterned region 4620 (e.g., passivation film 4350 can be formed on film 4300 and patterned region 4620). The method for forming recess 4639, surface modified region 4649 and passivation film 4350 can be the same as described above. Figure 35 The methods used are basically the same, so a detailed description is not required.

[0373] Additionally, according to one or more embodiments, a second key opening 4142 may be formed to expose the mask alignment key 4600 formed on a surface portion of the membrane 4300 (see Figure 38 For example, the second bond opening 4142 can be formed in parallel (e.g., simultaneously) with the rear opening 4510, the second intermediate opening 4410, the unit opening 4110, and the intermediate opening 4210. The method for forming the second bond opening 4142 can be the same as described above. Figure 38 The methods used are basically the same, so a detailed description is not required.

[0374] The deposition mask, its fabrication apparatus / apparatus, method for fabricating the deposition mask, or any other related apparatus / apparatus or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of the apparatus can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of the apparatus can be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the apparatus can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the scope of the embodiments of this disclosure.

[0375] This disclosure should not be construed as being limited to the one or more embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosed concepts to those skilled in the art.

[0376] While this disclosure has been specifically shown and described with reference to one or more embodiments thereof, those skilled in the art will understand that one or more suitable changes in form and detail may be made therein without departing from the spirit or scope of the disclosure as defined by the claims and their equivalents.

Claims

1. A deposition mask, the deposition mask comprising: Mask substrate with unit openings; A membrane, on the mask substrate, having pixel openings communicating with the cell openings; as well as Mask alignment key, on the mask base, The mask alignment key includes a patterned area and a peripheral area surrounding the patterned area. The patterned area includes a surface-modified area, which has a larger surface roughness than the peripheral area.

2. The deposition mask as claimed in claim 1, wherein: The patterned area has a recess in the surface portion of the mask substrate, and The surface modification region is located in the recessed bottom surface portion.

3. The deposition mask as described in claim 2, wherein, The recess has a width that gradually decreases from the surface of the mask substrate toward the surface modification region.

4. The deposition mask of claim 1, further comprising an intermediate inorganic film between the mask substrate and the film. in, The intermediate inorganic membrane has bond openings that expose the patterned regions.

5. The deposition mask as described in claim 1, wherein, The surface roughness of the surface-modified region is in the range of 50 nm to 1 μm.

6. The deposition mask as claimed in claim 1, wherein, The membrane includes a passivation region on the patterned area.

7. The deposition mask of claim 1, further comprising a passivation film on the mask substrate and the mask alignment bond. in, The membrane is on the passivation membrane.

8. The deposition mask as claimed in claim 1, wherein, The mask substrate has key openings that expose the mask alignment keys.

9. The deposition mask as claimed in claim 8, wherein: The mask alignment key includes a surface layer of the mask substrate, the surface layer including the patterned area and the peripheral area, and The key opening exposes the surface layer.

10. The deposition mask as claimed in claim 9, wherein: The surface layer includes an etch stop region having an area larger than the bond opening, and The key opening exposes the etch stop region.

11. The deposition mask as claimed in claim 10, wherein, The etch stop region includes one or more impurities selected from Group III.

12. The deposition mask of claim 1, further comprising an intermediate inorganic film between the mask substrate and the film, wherein: The patterned area has a depression in the surface portion of the intermediate inorganic film, and The surface modification region is located in the recessed bottom surface portion.

13. The deposition mask of claim 12, further comprising an etch stop region in the surface layer of the mask substrate. in, The mask substrate has key openings that expose the etch stop region.

14. The deposition mask as claimed in claim 1, wherein: The patterned area has a recess in the surface portion of the film, and The surface modification region is located in the recessed bottom surface portion.

15. The deposition mask of claim 14, wherein the deposition mask further comprises a passivation film on the film and the mask alignment bond.

16. The deposition mask as claimed in claim 14, wherein, The mask substrate has key openings that expose the mask alignment keys.

17. A deposition mask, the deposition mask comprising: Mask substrate with unit openings; A membrane, on the mask substrate, having pixel openings communicating with the cell openings; as well as Mask alignment key, on the mask base, The mask alignment key includes a patterned area and a peripheral area surrounding the patterned area, the patterned area having at least one recess in a surface portion of the mask substrate, and The at least one recess is defined by an inclined inner surface that is connected to each other.

18. A method, the method comprising: Form mask alignment keys on the mask substrate; A film is formed on the mask substrate, the film having pixel openings; as well as A cell opening is formed through the mask substrate, and the cell opening communicates with the pixel opening. The mask alignment key includes a patterned area and a peripheral area surrounding the patterned area. The patterned area includes a surface-modified area, which has a larger surface roughness than the peripheral area. The method described herein is a method for manufacturing a deposition mask.

19. A display panel, the display panel comprising: Base; as well as Multiple light-emitting layers are formed on the substrate using a deposition mask as described in claim 1.

20. An electronic device comprising a display panel as claimed in claim 19.

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