A mobile experimental system and control method for electronic information engineering

Abstract

The present application relates to electronic experimental equipment technical field, specifically for a kind of electronic information engineering's movable experimental system and control method, system includes: propagation analysis module, apparent connection construction module, hidden connection determination module, topology construction module, regulation and control execution module.In the present application, by analyzing the port potential response, the intelligent detection and construction of circuit connection relationship are realized, the explicit and implicit connection are accurately identified and screened, and the precision and automation level of circuit regulation and control are improved.By comparing the complete circuit topology data constructed in real time with the preset standard connection state, abnormal connections in the circuit can be quickly found and corrected, and the reliability and efficiency of experimental operation are significantly improved.This way reduces the interference of manual operation in the process of circuit building, improves the accuracy of circuit debugging and verification, ensures the stability and repeatability of experimental data, and provides a more intelligent and accurate experimental environment for teaching and scientific research.

Description

Technical Field

[0001] This invention relates to the field of electronic experimental equipment technology, and in particular to a mobile experimental system and control method for electronic information engineering. Background Technology

[0002] The field of electronic experimental equipment technology involves experimental platforms, instruments, and their supporting operating systems for electronic information courses and engineering practices. It mainly includes electronic circuit construction devices, signal generation and measurement equipment, experimental bench structures, data acquisition interfaces, embedded control units, teaching experimental platforms, and experimental operating environments for circuit debugging and functional verification. The core focus is on using experimental devices to achieve electronic circuit construction, signal input / output testing, voltage and current measurement, logic function verification, and electronic system debugging. This allows learners to complete experiments on analog circuits, digital circuits, embedded systems, and communication circuits on the experimental platform. The experimental equipment integrates teaching demonstrations, experimental training, and engineering practice, thus forming an experimental equipment system oriented towards electronic information engineering teaching and research activities.

[0003] One traditional mobile experimental system and control method for electronic information engineering involves setting up an experimental platform with wheels. On the platform, a power module, experimental circuit connector, signal generator, voltage and current measuring instruments, a microcontroller control board, and wire interfaces for circuit connections are installed. The microcontroller control board controls the power on / off sequence, the experimental circuit's power supply voltage, and the signal output status according to a preset program. During the experiment, the experimenter connects components such as resistors, capacitors, and integrated circuits to the experimental circuit connector to form a circuit structure. A square wave or sine wave signal is then input into the circuit using the signal generator. Simultaneously, voltage and current measuring instruments measure the circuit nodes. Following the experimental manual, the experimenter completes circuit construction, signal input, data reading, and experimental recording, thus fulfilling the relevant experimental teaching activities for electronic information engineering.

[0004] Existing technologies have several limitations in practical operation. Traditional electronic experimental systems rely on manual insertion of various components onto circuit boards. This process is not only tedious and error-prone, but also lacks real-time feedback on incorrect connections during circuit setup, resulting in low experimental efficiency. Signal input, output, and measurement processes largely depend on manual adjustments by experimenters, failing to achieve automated and intelligent optimization management and easily introducing human error. Furthermore, the detection and adjustment of circuit topology during experiments rely on manual operation, making it difficult to accurately and efficiently judge and control circuit connection status. This limits the flexibility and precision of the experimental environment, affecting the stability and reliability of experimental results. Summary of the Invention

[0005] To address the technical problems existing in the prior art, embodiments of the present invention provide a mobile experimental system and control method for electronic information engineering. The technical solution is as follows: On the one hand, a mobile experimental system for electronic information engineering is provided, the system comprising: The propagation analysis module acquires port potential response sequence data and extracts the voltage jump start time and peak value. It sorts the voltage jump start times and calculates the amplitude difference sequence of the voltage peak values ​​to generate port propagation data and transmits it to the explicit connection construction module. The explicit connection construction module filters the direct correlation pairs between the amplitude difference sequence of the port propagation data and the preset direct connection determination threshold, and extracts the empty port set after sorting the voltage jump start time to construct explicit connection data and transmit it to the implicit connection determination module. The implicit connection determination module obtains the impulse response waveform data of the vacant port set based on the explicit connection data and calculates the port integral energy. It then filters the implicit connection data by combining it with a preset implicit determination threshold and transmits it to the topology construction module. The topology construction module performs a union operation on the explicit connection data and the implicit connection data to construct a full port connection mapping table and remove redundancies, construct experimental topology data, and transmit it to the control and execution module. The control execution module acquires a preset standard connection status table and performs a difference operation in conjunction with the experimental topology data. It then filters out the difference port pairs and sends relay control commands to the programmable switch circuit to construct experimental control data.

[0006] As a further embodiment of the present invention, the port propagation data includes voltage transition start timing, peak amplitude set, and amplitude difference distribution sequence; the explicit connection data includes directly associated port pairs, judgment threshold filtering results, and vacant port set; the implicit connection data includes impulse response feature set, integral energy distribution, and implicitly associated port pairs; the experimental topology data includes a full set of connection relationships, connection mapping index, and redundancy elimination results; and the experimental control data includes a relay control code set, instruction timing sequence, and control output state set.

[0007] As a further aspect of the present invention, the propagation analysis module specifically comprises: The data analysis submodule acquires port potential response sequence data, detects the output signal level of the acquisition interface and writes it into the buffer queue according to time, normalizes the voltage values ​​of multiple sampling points in the buffer queue, performs interval verification on the time marker according to the sampling period parameter and removes abnormal interval items, and generates potential time sequence quantity. The jump extraction submodule calculates the voltage difference between adjacent sampling points based on the potential time series and selects time points that meet the preset voltage change threshold as jump start positions. At the same time, it records the corresponding voltage peaks, arranges all start positions in ascending order of time and adjusts the peak order synchronously to generate a jump time series amplitude table. The propagation combination submodule calculates the difference between adjacent voltage peaks according to the jump timing amplitude table to form an amplitude difference sequence. It then combines the sorted time sequence and the amplitude difference sequence according to their positions to construct a time-amplitude difference mapping relationship and remove missing items, thereby generating port propagation data.

[0008] As a further aspect of the present invention, the voltage change threshold is determined by acquiring the reference potential sequence of the port idle state, calculating the absolute value of voltage fluctuation at adjacent sampling points within the reference potential sequence, extracting all absolute values ​​of voltage fluctuation and calculating the arithmetic mean, and multiplying the arithmetic mean by a set fluctuation tolerance coefficient.

[0009] As a further aspect of the present invention, the explicit connection construction module specifically comprises: The amplitude difference filtering submodule obtains the amplitude difference sequence of the port propagation data and a preset direct connection judgment threshold, performs threshold judgment on each difference item and records the port combination identifiers whose differences do not reach the direct connection judgment threshold, collects all port combination identifiers that meet the judgment conditions, and generates a direct association relationship pair sequence. The intersection construction submodule calls the sorted voltage time series based on the direct association relationship, extracts the corresponding port voltage time segment for each port combination in the sequence and performs time overlap judgment, records the intersection of port combinations with overlapping time segments, and obtains the sorted voltage time intersection set. The explicit connection generation submodule extracts port identifiers that do not participate in any intersection record based on the sorted voltage-time intersection set and performs set filtering on the multiple port identifiers to form empty port set records. At the same time, it generates explicit connection data for the sequence in combination with the direct association relationship.

[0010] As a further aspect of the present invention, the direct connection determination threshold is determined by obtaining a standard direct connection port reference amplitude difference sequence, extracting the absolute values ​​of multiple differences within the reference amplitude difference sequence and calculating the arithmetic mean, and multiplying the arithmetic mean by a set connection tolerance coefficient.

[0011] As a further aspect of the present invention, the hidden connection determination module specifically comprises: The pulse application submodule, based on the explicit connection data, acquires the ports included in the set of vacant ports and applies a pulse excitation signal, records the voltage amplitude changes of multiple ports in a continuous time series and constructs a set of sampling points, normalizes the amplitude of multiple sampling points and rearranges them according to time to obtain the port pulse response waveform. The waveform integration submodule extracts the time interval and corresponding amplitude data of adjacent sampling points based on the port impulse response waveform quantity, performs segmented summation of the amplitude sequence according to equidistant intervals and superimposes the interval area values, accumulates all interval areas, merges the sum of the corresponding energies of multiple ports, and obtains the port integrated energy. The threshold filtering submodule constructs an energy value set based on the port integral energy and reads the corresponding port identifier item by item. It filters the corresponding port set whose energy values ​​exceed the preset implicit judgment threshold and records the connection identifier. The filtering results are then organized to obtain implicit connection data.

[0012] As a further aspect of the present invention, the topology construction module specifically comprises: The data union submodule obtains the explicit connection data and the implicit connection data, performs a union operation, extracts the port identifiers and corresponding links within multiple connection data, compares the start and end ports of multiple connection links, summarizes multiple connection links and appends them to the blank mapping structure, and generates a full port connection mapping table. The redundancy removal submodule reads the start and end port identifiers of multiple connection links based on the full port connection mapping table, performs reverse combination comparison based on the start and end port identifiers, finds bidirectional duplicate link records with the same port node combination and deletes the marked duplicate link records to obtain the deduplicated connection mapping set. The topology generation submodule calls the deduplication connection mapping set, extracts port identifiers from the mapping set as topology point items, extracts unidirectional connection records as topology connection items, and arranges the topology node items according to the starting relationship of the topology connection items to establish experimental topology data.

[0013] As a further aspect of the present invention, the control execution module specifically comprises: The data receiving submodule obtains a preset standard connection status table through the communication interface and combines it with the experimental topology data. It rearranges the port numbers in the standard connection status table, extracts the connection relationship of the experimental topology data and expands it into a port connection sequence, aligns it with the format of the standard connection status table, and generates a port connection code set. The port calculation submodule performs a bit-by-bit comparison between the port connection code set and the port code set corresponding to the preset standard connection status table, performs difference operation on the code data to extract unmatched port code items, records the port number corresponding to the unmatched items and performs bidirectional pairing and combination to obtain the difference port combination table. The control generation submodule calls the differential port combination table to read multiple port pairing records, retrieves the corresponding relay hardware number of the switch circuit based on the pairing record, converts the status bit to obtain the basic control code sequence, arranges and reassembles it according to the trigger timing, and issues relay control commands to generate experimental control data.

[0014] On the other hand, a mobile experimental control method for electronic information engineering, which is based on the aforementioned mobile experimental system for electronic information engineering, includes the following steps: S1: Obtain port potential response sequence data and extract the voltage jump start time and peak value, sort the voltage jump start times and calculate the amplitude difference sequence of the voltage peak values ​​to generate port propagation data; S2: The amplitude difference sequence of the port propagation data is filtered with the preset direct connection determination threshold to select the direct correlation pair, and the empty port set is extracted by combining the sorted voltage jump start time to construct explicit connection data; S3: Based on the explicit connection data, obtain the impulse response waveform data of the vacant port set and calculate the port integral energy, and filter the implicit connection data in combination with the preset implicit judgment threshold. S4: Based on the union operation of the explicit connection data and the implicit connection data, construct a full port connection mapping table and remove redundancies to construct experimental topology data; S5: Obtain the preset standard connection status table and perform difference operation in combination with the experimental topology data, filter the difference port pairs and send relay control commands to the programmable switch circuit to construct experimental control data.

[0015] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: By analyzing port potential responses, intelligent detection and construction of circuit connections are achieved, accurately identifying and filtering explicit and implicit connections, thus improving the precision and automation level of circuit control. By constructing complete circuit topology data in real time and comparing it with preset standard connection states, abnormal connections in the circuit can be quickly detected and corrected, significantly improving the reliability and efficiency of experimental operations. This approach reduces interference from manual operation during circuit construction, improves the accuracy of circuit debugging and verification, ensures the stability and repeatability of experimental data, and provides a more intelligent and precise experimental environment for teaching and research. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a system schematic diagram of the present invention; Figure 2 This is a schematic diagram of the system framework of the present invention; Figure 3This is a flowchart of the propagation analysis module in this invention; Figure 4 This is a flowchart of the explicit connection construction module in this invention; Figure 5 This is a flowchart of the hidden connection determination module in this invention; Figure 6 This is a flowchart of the topology construction module in this invention; Figure 7 This is a flowchart of the control and execution module in this invention; Figure 8 This is a flowchart of the method of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0019] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0020] This invention provides a mobile experimental system for electronic information engineering, such as... Figure 1-2 The diagram shows a portable experimental system for electronic information engineering. The system includes: The propagation analysis module acquires port potential response sequence data and extracts the voltage jump start time and peak value. It sorts the voltage jump start times and calculates the amplitude difference sequence of the voltage peak values ​​to generate port propagation data and transmits it to the explicit connection construction module. The explicit connection construction module filters the direct correlation pairs between the amplitude difference sequence of port propagation data and the preset direct connection judgment threshold, and extracts the empty port set after sorting the voltage jump start time to construct explicit connection data and transmit it to the implicit connection judgment module. The implicit connection determination module obtains the impulse response waveform data of the set of vacant ports based on the explicit connection data and calculates the port integral energy. It then filters the implicit connection data by combining the preset implicit determination threshold and transmits it to the topology construction module. The topology construction module constructs a full port connection mapping table and removes redundancies based on the union operation of explicit and implicit connection data, and constructs experimental topology data and transmits it to the control and execution module. The control execution module acquires a preset standard connection status table and performs a difference operation in combination with the experimental topology data. It then filters out the difference port pairs and sends relay control commands to the programmable switch circuit to construct experimental control data.

[0021] Port propagation data includes voltage transition start timing, peak amplitude set, and amplitude difference distribution sequence; explicit connection data includes directly associated port pairs, judgment threshold filtering results, and vacant port set; implicit connection data includes impulse response feature set, integral energy distribution, and implicitly associated port pairs; experimental topology data includes full connection relationship set, connection mapping index, and redundancy elimination results; and experimental control data includes relay control code set, instruction timing sequence, and control output state set.

[0022] Specifically, such as Figure 2 , 3 As shown, the propagation analysis module specifically consists of: The data analysis submodule acquires port potential response sequence data, detects the output signal level of the acquisition interface and writes it into the buffer queue according to time, normalizes the voltage values ​​of multiple sampling points in the buffer queue, performs interval verification on the time marker according to the sampling period parameter and removes abnormal interval items, and generates potential time sequence quantity. The system receives port potential response sequence data from a voltage sensor via an analog-to-digital converter interface. The sensor sampling rate is set to 1000 Hz. The system detects the output signal level of the acquisition interface and writes the measured voltage values, along with microsecond-level timestamps, into a pre-allocated first-in-first-out (FIFO) buffer queue in chronological order. The system extracts the voltage values ​​from multiple sampling points in the buffer queue and performs amplitude normalization on them. It subtracts the reference zero-point voltage value from the current sampling point voltage value and then divides the difference by the full-scale voltage range to obtain the normalized voltage sequence. The reference zero-point voltage value is obtained by calculating the arithmetic mean of the voltages from 1000 continuously collected low-noise points while the sensor is in sleep mode. The full-scale voltage range is determined by subtracting the reference zero-point voltage value from the highest withstand voltage. The current sampling point voltage value is 3.2 volts. The pre-calibrated reference zero-point voltage value is retrieved as 0.2 volts, and the full-scale voltage range value is retrieved as 5.0 volts. 3.2 volts is subtracted from 0.2 volts to obtain 3.0 volts. Then, 3.0 volts is divided by 5.0 volts to obtain a normalized voltage value of 0.6. An interval check is performed on the time stamp based on the sampling period parameter. The timestamps of adjacent sampling points are extracted and subtracted to obtain the actual time interval. The actual time interval is compared with the standard sampling period parameter. If the absolute value of the difference exceeds the set tolerance deviation threshold, the interval corresponding to the subsequent sampling point is determined to be an abnormal interval and an erase command is executed to remove it. The tolerance threshold is set to three times the standard deviation of clock jitter under normal operating conditions. The standard sampling period is 1.0 millisecond. The pre-measured standard deviation of clock jitter is approximately 0.033 milliseconds, and the tolerance threshold is set to 0.1 milliseconds. When the timestamps of adjacent sampling points are 1.0 milliseconds and 2.2 milliseconds respectively, the actual time interval obtained by subtracting is 1.2 milliseconds. Comparing this with 1.0 milliseconds, the absolute value of the difference is 0.2 milliseconds, which is greater than the tolerance threshold of 0.1 milliseconds. Data records with a timestamp of 2.2 milliseconds are then discarded. The normalized voltage values ​​that pass verification and their corresponding timestamps are summarized to generate a potential time series.

[0023] The jump extraction submodule calculates the voltage difference between adjacent sampling points based on the potential time series and selects the time points that meet the preset voltage change threshold as the jump start position. At the same time, it records the corresponding voltage peak value, sorts all start positions in ascending order of time and adjusts the peak value order synchronously to generate a jump time series amplitude table. The system reads the potential time series data, iterates through all data nodes in the time series, extracts the normalized voltage value of the next sampling point and subtracts the normalized voltage value of the previous sampling point, thus completing the logic for calculating the voltage difference between adjacent sampling points. The voltage difference is compared with a preset voltage change threshold. If the voltage difference is greater than the preset voltage change threshold, it is determined that a state transition occurred between the previous and next sampling points, and the timestamp corresponding to the next sampling point is selected and marked as the start position of the transition. The preset voltage change threshold is determined by multiplying the maximum background noise peak value under interference-free conditions with a false alarm redundancy coefficient. The maximum background noise peak value is 0.1, and the false alarm redundancy coefficient is set to 2.0. Multiplying the two yields a preset voltage change threshold of 0.2. Substituting the previously output timestamp of 1.0 ms and the effective normalized voltage value of 0.6, the next adjacent effective sampling point is read. Its timestamp is 2.0 ms and the normalized voltage value is 0.9. Subtracting 0.6 from 0.9 yields a voltage difference of 0.3. This voltage difference of 0.3 is determined to be greater than the preset voltage change threshold of 0.2, and 2.0 ms is marked as a transition start position. After marking the transition start position, a time observation window with a length of 5 sampling periods is opened, starting from the timestamp corresponding to the start position. All normalized voltage values ​​within this window are scanned, and the maximum value comparison and extraction logic is executed. The found maximum value is recorded as the corresponding voltage peak value. Multiple transition start position records scattered in memory are read into a sorting stack, and a bubble comparison logic based on the timestamp value is executed. The data index is reconstructed according to the ascending time sorting rule, and the storage order of the corresponding voltage peak values ​​in the array is adjusted synchronously according to the reconstructed index mapping relationship. The ascending timestamps and the synchronously adjusted voltage peak values ​​are concatenated to generate a transition timing amplitude table.

[0024] The propagation combination submodule calculates the difference between adjacent voltage peaks based on the jump timing amplitude table to form an amplitude difference sequence. It then combines the sorted time sequence and the amplitude difference sequence according to their positions, constructs a time-amplitude difference mapping relationship, removes missing items, and generates port propagation data. The output transition timing amplitude table is loaded, and the voltage peak field in the amplitude table is parsed row by row. The voltage peak value after the current transition event is extracted and subtracted from the previous voltage peak value. The difference between adjacent voltage peak values ​​is calculated to form an amplitude difference sequence. The voltage peak value recorded at timestamp 2.0 milliseconds is 1.0. The next transition event is read, and its transition start timestamp is 15.0 milliseconds with a corresponding voltage peak value of 0.8. Subtracting the previous voltage peak value of 1.0 from the next voltage peak value of 0.8 yields an amplitude difference result of -0.2. This difference calculation result is stored sequentially in independent data blocks to form an amplitude difference sequence. The sorted time series in the transition timing amplitude table is used as the primary key identifier and is combined with the newly generated amplitude difference sequence using position-corresponding combinational logic. Based on the memory address offset, the timestamp and amplitude difference result under the same sequence number are bound together to construct a time-amplitude difference mapping relationship. All generated mapping items are scanned, and field integrity verification and comparison logic is executed. When a timestamp field or amplitude difference field in any mapping item is detected as a null pointer or a non-numeric identifier, the item is determined to be invalid dead zone data, and a memory release instruction is triggered to remove the missing item. The mapping items that pass the integrity verification are packaged into a standard communication payload to generate the port transmission data volume. Table 1, a portable experimental table, lists some of the generated associated data payloads. As shown in Table 1, the real-time load characteristics of data transmission are intuitively presented.

[0025] Table 1. Portable Experiment Table ; Specifically, such as Figure 2 , 4 As shown, the explicit connection building module is specifically as follows: The amplitude difference filtering submodule obtains the amplitude difference sequence of port propagation data and the preset direct connection judgment threshold, performs threshold judgment on each difference item and records the port combination identifiers whose difference does not reach the direct connection judgment threshold, collects all port combination identifiers that meet the judgment conditions, and generates a direct association pair sequence. The system acquires the amplitude difference sequence of port propagation data and a preset direct connection judgment threshold. It iterates through the amplitude difference sequence stored in memory, reading each current difference data item and performing an absolute value conversion operation. The extracted amplitude difference is then compared with the preset direct connection judgment threshold. The preset direct connection judgment threshold is obtained by multiplying the baseline noise dispersion parameter and the direct connection sensitivity coefficient. The baseline noise dispersion parameter is obtained by calculating the standard deviation of 1000 no-load voltage noise points collected during the device's power-on initialization phase, yielding a baseline noise dispersion parameter of 0.04 volts. The preset direct connection sensitivity coefficient is set to 3.5. Multiplying 0.04 volts by 3.5 yields a preset direct connection judgment threshold of 0.14 volts. The amplitude difference result from the previous operation is retrieved, which is -0.2 volts. Its absolute value is converted to 0.2 volts. This 0.2 volt is compared with the preset direct connection threshold of 0.14 volts. Since 0.2 volts is greater than 0.14 volts, this data is discarded. The next amplitude difference value, 0.1 volt, is read. After absolute value conversion, it is still 0.1 volts. This is compared with 0.14 volts. Since 0.1 volts does not reach the direct connection threshold, a recording instruction is triggered. The physical addressing codes of the transmitting and receiving ports corresponding to this amplitude difference value are extracted and merged into a port combination identifier. This comparison and concatenation logic is repeated until all elements in the amplitude difference value sequence have been traversed. Then, all port combination identifiers that meet the judgment conditions are collected in a pre-allocated contiguous memory space and generated into a sequence of directly related pairs according to the order in which they are written into memory. The advantage of this operational logic is that by performing a strict size comparison and screening operation on the absolute value of the amplitude difference and the preset direct connection judgment threshold, the accuracy of the direct correlation determination is effectively improved.

[0026] The intersection construction submodule calls the sorted voltage time series based on the direct association relationship, extracts the corresponding port voltage time segment for each port combination in the sequence and performs time overlap judgment, records the intersection of port combinations with overlapping time segments, and obtains the sorted voltage time intersection set. The system reads the sequence of directly related pairs and, based on this sequence, initiates a memory access request to the storage controller to simultaneously extract the sorted voltage time series globally. For each port combination in the sequence of directly related pairs, the system locates and extracts the corresponding port's voltage time segment in the sorted voltage time series based on the port's physical addressing code. The extracted voltage time segment includes the start and end timestamps of the port's signal transition. Time overlap judgment logic is executed on the two extracted port voltage time segments. The start timestamps of the first and second port time segments are extracted respectively, and a maximum value selection operation is performed on both to obtain the overlap start boundary. Simultaneously, the end timestamps of the first and second port time segments are extracted, and a minimum value selection operation is performed on both to obtain the overlap termination boundary. The overlap termination boundary is subtracted from the overlap start boundary, and the overlap status is verified by the positive or negative attribute of the difference. The voltage time interval of the first port is read to have a start timestamp of 12.0 milliseconds and an end timestamp of 18.0 milliseconds, while the second port has a start timestamp of 14.0 milliseconds and an end timestamp of 20.0 milliseconds. Comparing 12.0 milliseconds and 14.0 milliseconds, the maximum value of 14.0 milliseconds is selected as the overlap start boundary. Comparing 18.0 milliseconds and 20.0 milliseconds, the minimum value of 18.0 milliseconds is selected as the overlap end boundary. Then, 18.0 milliseconds is subtracted from 14.0 milliseconds to obtain a difference of positive 4.0 milliseconds. Since the difference is positive, it is determined that the current port combination has time interval overlap. The intersection of the port combination with overlapping time intervals and its corresponding 4.0 millisecond overlap interval data is recorded and written into the intersection data linked list. After traversing all port combinations, the sorted voltage-time intersection set is output. The advantage of this operation logic is that by extracting the extreme values ​​of the multi-port voltage time intervals and performing boundary subtraction operations, the time overlap interval can be accurately determined.

[0027] The explicit connection generation submodule extracts port identifiers that do not participate in any intersection records based on the sorted voltage-time intersection set and performs set filtering on the multiple port identifiers to form empty port set records. At the same time, it generates explicit connection data for the sequence by combining direct association relationships. The system loads the sorted voltage-time intersection set and the device's full port registry. It parses all intersection records in the sorted voltage-time intersection set, extracts the physical addressing codes contained within, and constructs a Boolean mapping table of occupied ports, setting the corresponding Boolean values ​​in the table to true. Based on the sorted voltage-time intersection set, it performs a state comparison operation, scanning the port identifiers in the device's full port registry item by item, extracting port identifiers that did not participate in any intersection record. When a port identifier is found to have a false value in the occupied port Boolean mapping table, it is determined that the port did not participate in any intersection record. The device's full port registry contains 10 port identifiers, numbered from port 1 to port 10. After parsing the sorted voltage-time intersection set, the Boolean states of ports 1 to 8 are set to true. During the item-by-item scan, the Boolean states of ports 9 and 10 are found to be false, and their identifiers are extracted. The extracted multi-port identifiers are then merged and filtered, and written into a separate free memory pool to form a set of empty ports. The sequence of direct association pairs generated in the aforementioned memory space is retrieved. This sequence is then combined with newly generated empty port set records, and topology graph data field concatenation logic is executed. The sequence of direct association pairs is treated as the connected edge dataset in the graph structure, and the empty port set records are treated as the isolated node dataset. Both are then summarized and written into a standard topology description text format, ultimately generating explicit connection data. The advantage of this operation logic is that it isolates empty port identifiers and synchronously merges the sequence of direct association pairs through Boolean state mapping and set subtraction operations.

[0028] Specifically, such as Figure 2 , 5 As shown, the hidden connection determination module is specifically as follows: The pulse application submodule, based on explicit connection data, acquires the ports included in the set of vacant ports and applies pulse excitation signals, records the voltage amplitude changes of multiple ports in a continuous time series and constructs a set of sampling points, normalizes the amplitude of multiple sampling points and rearranges them according to time to obtain the port pulse response waveform. Load the explicit connection data memory block and parse and extract the port identification information from the set of empty ports. Drive the digital-to-analog converter hardware to apply pulse excitation signals to the target ports one by one, with the pulse peak value set to 3.3 volts and the pulse duration width set to 2.0 milliseconds. Activate the analog-to-digital converter channel to record the transient voltage amplitude change data of the target ports in a continuous time series at a frequency of 10000 Hz, and store the absolute voltage values ​​with timestamps into memory to construct the initial sampling point set. Traverse the amplitude values ​​of multiple sampling points in the initial sampling point set and perform amplitude normalization operations. Retrieve the pre-calibrated zero-point bias voltage value and full-scale range voltage value. The zero-point bias voltage value is obtained by arithmetic averaging 500 background noise voltage points collected in sleep mode, which is 0.1 volts. The full-scale range voltage value is determined by subtracting the zero-point bias voltage value from the hardware's highest voltage threshold, which is 3.2 volts. The current sampling point's absolute voltage value is read as 1.7 volts. Subtracting 0.1 volts from 1.7 volts yields a net amplitude difference of 1.6 volts. Dividing 1.6 volts by 3.2 volts yields a normalized amplitude of 0.5. All normalized amplitude values ​​and their associated timestamps are extracted into a sorting buffer. Alignment logic based on timestamp ascending order is executed to rearrange the data frames according to time, obtaining the port impulse response waveform. The advantage of this operation logic is that it eliminates the zero-point drift error of physical devices through range normalization.

[0029] The waveform integration submodule extracts the time interval and corresponding amplitude data of adjacent sampling points based on the port impulse response waveform. It then segments the amplitude sequence into equal intervals, sums the interval area values, accumulates all interval areas, and merges the sum of the corresponding energies of multiple ports to obtain the port integrated energy. The port impulse response waveform is retrieved, and the ordered data nodes within the waveform are traversed. For each scan, the timestamps and normalized amplitude data corresponding to two adjacent sampling points are extracted. The time interval between adjacent sampling points is obtained by subtracting the previous timestamp from the subsequent timestamp. The average amplitude of the interval is obtained by adding the previous normalized amplitude to the subsequent normalized amplitude and dividing by two. The average amplitude is multiplied by the time interval between adjacent sampling points to obtain the area value of a single segment. Substituting the normalized amplitude of 0.5 at the aforementioned timestamp of 1.2 ms, the normalized amplitude of 0.7 at the subsequent timestamp of 1.3 ms is extracted. Subtracting 1.2 ms from 1.3 ms gives the time interval of 0.1 ms. Adding 0.5 and 0.7 and dividing by two gives the average amplitude of 0.6. Multiplying 0.6 by 0.1 ms gives the area value of a single segment of the equidistant interval as 0.06 millisecond volts. An accumulation register is allocated, and the area values ​​of each segment are superimposed segment by segment. The total area of ​​all segments is obtained by summing all the area values ​​of the single port for the entire time period. The total energy across multiple ports is matched and merged using logic, binding the physical identifier of each port with its corresponding area value over the entire time period to obtain the integrated energy of the port. Table 2, a port energy assessment integral table, lists the integral calculation data for some ports. As shown in Table 2, the energy distribution of the multiple ports is clearly displayed. The advantage of this calculation logic is that it smooths out transient interference spikes through piecewise area multiplication and accumulation.

[0030] Table 2. Port Energy Assessment Integral Table ; The threshold filtering submodule constructs an energy value set based on the port integral energy and reads the corresponding port identifier item by item. It filters the corresponding port set whose energy value exceeds the preset implicit judgment threshold and records the connection identifier. The filtering results are then sorted to obtain implicit connection data. The received port integrated energy data array is stored in a local database to construct a one-dimensional hash energy value set. The corresponding port identifier and its associated cumulative integrated energy are read sequentially from this value set. The configuration parameter memory area is retrieved, and the environmental energy dispersion parameter and implicit connection amplification factor are extracted. These two are multiplied to obtain a preset implicit judgment threshold. The environmental energy dispersion parameter is calculated as 0.4 millisecond volts by arithmetically averaging 300 small unloaded energy fluctuations collected from unconnected cables in a shielded room. The implicit connection amplification factor is hard-coded to 3.5 based on the lower limit attenuation of electromagnetic coupling theory. Multiplying 0.4 millisecond volts by 3.5 yields a preset implicit judgment threshold of 1.4 millisecond volts. The calculated cumulative energy of port 9, 3.55 millisecond volts, is read and compared with a preset implicit threshold of 1.4 millisecond volts. Since 3.55 millisecond volts is greater than 1.4 millisecond volts, this energy value exceeds the threshold. Port 9 is marked as having an implicit coupling loop, and the corresponding port set is extracted and its physical address is written into the connectivity database as a connection identifier. The process continues by reading the cumulative energy of port 11, 0.85 millisecond volts, which is less than 1.4 millisecond volts, and is discarded. All connection identifiers that meet the conditions are packaged and formatted into an array with their corresponding energy values ​​to generate implicit connection data. The advantage of this operation logic is that the adaptive threshold comparison operation, constructed by multiplying the amplification factor by the environmental dispersion, enhances robustness under different environmental noise levels.

[0031] Specifically, such as Figure 2 , 6 As shown, the topology building module is specifically as follows: The data union submodule obtains explicit connection data and implicit connection data, performs union operation, extracts port identifiers and corresponding links within multiple connection data, compares the start and end ports of multiple connection links, summarizes multiple connection links and appends them to the blank mapping structure, and generates a full port connection mapping table. The system retrieves explicit and implicit connection data from the storage array, parses and extracts all port identifiers and corresponding link mappings contained within these connection data sets. It reads the first explicit link from the explicit connection data, extracting its start and end port codes. Simultaneously, it reads the first implicit link from the implicit connection data, extracting its corresponding start and end port codes. For all extracted links, it performs hash index value allocation operations, pre-setting the hash mapping prime number to 31. The maximum capacity of the hash table is calculated by multiplying the maximum number of interfaces on the device's physical panel by a redundancy coefficient. The maximum number of interfaces on the device's physical panel is retrieved from the hardware configuration table as 50, and the preset redundancy coefficient is read from the configuration document as 2. Multiplying 50 by 2 yields a maximum hash table capacity of 100. The start port code value is multiplied by the preset hash mapping prime number to obtain an intermediate hash value. This intermediate hash value is then added to the end port code value to obtain the absolute mapping total. Finally, the absolute mapping total is moduloed by the preset maximum hash table capacity to derive the target hash index value. The explicit connection data contains a link pointing from the starting port code value 1 to the ending port code value 9. Multiplying 1 by 31 yields an intermediate hash value of 31. Adding 31 to 9 gives an absolute mapping total of 40. Taking the modulo operation of 40 divided by 100 yields the hash index value of 40 for the corresponding link. The implicit connection data from the previous section retrieves the implicit link pointing from the starting port code value 9 to the ending port code value 11. Multiplying 9 by 31 yields an intermediate hash value of 279. Adding 279 to 11 gives an absolute mapping total of 290. Taking the modulo operation of 290 divided by 100 yields the hash index value of 90 for the corresponding link. Based on the calculated hash index values, a blank mapping structure is created at the corresponding address in the memory stack. The starting and ending ports of multiple connection links are compared. If different links yield the same hash index value, chaining is used to append the data. Multiple connection link data nodes are aggregated according to their index positions and directly appended to the blank mapping structure, ultimately generating a full port connection mapping table.

[0032] The redundancy removal submodule reads the start and end port identifiers of multiple connection links based on the full port connection mapping table, performs reverse combination comparison based on the start and end port identifiers, finds bidirectional duplicate link records with the same port node combination and deletes the marked duplicate link records to obtain the deduplicated connection mapping set. The system receives and reads the node association data stored in the full port connection mapping table, extracting the start and end port identifiers of multiple connection links recorded in the table. Based on the extracted start and end port identifiers, it performs a reverse combination comparison operation. For each link in the full port connection mapping table, it extracts two endpoint values, configures them as independent array pairs, and adds the start and end port values ​​in each array pair to obtain the link feature summation value. Simultaneously, it multiplies the start and end port values ​​to obtain the link feature product value. A node encoding offset base is introduced to calibrate and verify the calculation results. To ensure that the feature product value does not overflow or overlap with the displacement data of the feature summation value, and given that the maximum total number of interfaces on the device's physical panel is 50, the maximum link feature product value is 2500. The node encoding offset base must be set to an independent constant of 10000, which is greater than the maximum link feature product value. The link feature summation value is multiplied by the node encoding offset base and then added to the link feature product value to generate the absolute feature identifier code for that link. If the absolute feature identifiers of any two different links are completely identical, then these two links are determined to be bidirectional duplicate links with the same port node combination. The first link's starting port value is read as 1 and the ending port value as 9. The operation is performed on the first link: adding 1 and 9 gives a link feature summation value of 10; multiplying 1 and 9 gives a link feature product value of 9; then multiplying the link feature summation value of 10 by the node code offset base of 10000 gives 100000; adding 100000 to the link feature product value of 9 gives the absolute feature identifier of the first link as 100009. The second link's starting port value is read as 9 and the ending port value as 1. The same operation is performed on the second link: adding 9 and 1 gives 10; multiplying 9 and 1 gives 9; substituting this into subsequent operations gives the absolute feature identifier of the second link as 100009. Comparing the calculation results of the first and second links, it was found that their absolute feature identifiers were identical, both being 100009. Based on this reverse combination comparison result, the records of these two bidirectional duplicate links with the same port node combination were located and locked. A boolean value of "true" was added to the memory for the second duplicate link, which was scanned later, and a memory reclamation instruction was executed to delete the marked duplicate link record. All links in the full port connection mapping table were traversed, and the above feature calculation and comparison logic was continuously executed. After complete cleanup, memory defragmentation was performed to obtain the final deduplicated connection mapping set.

[0033] The topology generation submodule calls the deduplication connection mapping set, extracts the port identifiers in the mapping set as topology point items, extracts the one-way connection records as topology connection items, and arranges the topology node items according to the starting relationship of the topology connection items to establish experimental topology data. The deduplication map set is invoked, and all unique port identifiers recorded in the deduplication map set are extracted as topology node items in the topology graph structure. The deduplication map set is traversed, and each unidirectional connection record is extracted as a topology connection item in the topology graph structure. Based on the starting relationship and layer depth indicated by each topology connection item, the topology node items are arranged in a two-dimensional planar position connection. A horizontal axis coordinate value and a vertical axis coordinate value are assigned to all topology node items. The horizontal axis coordinate value is calculated by multiplying the current node's network depth layer value by a preset horizontal spacing baseline value. The vertical axis coordinate value is calculated by multiplying the node's arrangement sequence number within the same layer by a preset vertical spacing baseline value. The preset horizontal spacing baseline value is calculated by dividing the maximum width of the display interface by the maximum estimated depth layer value. The maximum width of the display interface is set to 1000 regular pixels by reading the rendering hardware driver configuration file. The maximum estimated depth layer value is set to 5 based on the node tree traversal depth. Dividing 1000 by 5 yields a preset horizontal spacing baseline value of 200 regular pixels. The preset vertical spacing baseline value is calculated by dividing the maximum height of the display interface by the maximum number of parallel nodes in a single layer. The maximum height of the display interface is set to 800 regular pixels, and the maximum number of parallel nodes in a single layer is 4. Dividing 800 by 4 yields a preset vertical spacing baseline value of 200 regular pixels. The port 9 node from the previous output is read, and its network depth level is determined to be 2 using breadth-first search, with its arrangement index within the same level being 1. The network depth level value of 2 is multiplied by the preset horizontal spacing baseline value of 200 regular pixels, resulting in a horizontal axis coordinate value of 400 regular pixels for port 9. The arrangement index value of 1 is multiplied by the preset vertical spacing baseline value of 200 regular pixels, resulting in a vertical axis coordinate value of 200 regular pixels for port 9. Based on all the calculated two-dimensional coordinate parameters, all topology nodes are virtually deployed, a spatial matrix coordinate set is established, and the extracted unidirectional connection records are mapped to vector line segments with directional attributes to connect the positions of each node. Experimental topology data in standard format is established and output in the memory rendering buffer.

[0034] Specifically, such as Figure 2 , 7 As shown, the control execution module is specifically as follows: The data receiving submodule obtains a preset standard connection status table through the communication interface and combines it with the experimental topology data. It rearranges the port numbers in the standard connection status table, extracts the connection relationship of the experimental topology data and expands it into a port connection sequence, aligns it with the format of the standard connection status table, and generates a port connection code set. The underlying general asynchronous transceiver communication interface is activated, and the pre-set standard connection status table in the configuration server is retrieved. The previously constructed experimental topology data is then synchronously read from memory. Before reading the experimental topology data, a data cleaning and filtering command is executed to verify the completeness of each data node's information and remove empty nodes and invalid connection records to ensure continuous memory distribution of the unfolded sequence. The initial port numbers based on the physical panel location distribution in the standard connection status table are read, and a one-dimensional rearrangement operation is performed on the initial port numbers according to the network depth level values ​​contained in the experimental topology data. Each communication node in the experimental topology data is extracted, and its network depth level value and its arrangement sequence number within the same level are read to calculate the node's alignment index base value. A preset depth offset coefficient is set. This coefficient is obtained by arithmetic and rounding the ratio of the highest bus communication frequency to the node scanning frequency. The highest bus communication frequency read from the configuration is 500 Hz, and the node scanning frequency is 50 Hz. Dividing 500 by 50 yields a depth offset coefficient of 10. Extract the network depth level value 2 and the arrangement number value 1 of node 9 in the aforementioned experimental records. Multiply the network depth level value 2 by the depth offset coefficient 10 to obtain the intermediate depth offset value 20. Add the intermediate depth offset value 20 to the arrangement number value 1 to derive the alignment index base value of port 9 as 21. Based on the alignment index base values ​​of all nodes, perform logical mapping over the memory addresses of the port numbering order in the standard connection status table to complete the port numbering rearrangement. Analyze the directed edge attributes of the rearranged experimental topology data, extract the topological connection relationships between nodes, expand them into a flat structure, and combine them into a port connection sequence. Convert this port connection sequence into a two-dimensional adjacency matrix data format and establish matrix position index parameters to achieve format alignment. The matrix position index parameters are calculated by multiplying the link start port value by the maximum total number of interfaces on the physical panel and adding the end port value. The maximum total number of physical panel interfaces is read from the hardware factory configuration table as 50. The starting port value (9) and ending port value (11) of the first link in the aforementioned expansion sequence are read. The starting port value (9) is multiplied by the maximum total number of physical panel interfaces (50) to obtain an intermediate product of 450. Then, 450 is added to the ending port value (11) to calculate the matrix position index parameter as 461. Based on the matrix position index parameter, the topology connection states are written bit by bit into a contiguous memory stack, ultimately generating a port connection code set that is completely aligned with the standard connection state table format.

[0035] The port calculation submodule compares the port connection code set with the port code set corresponding to the preset standard connection status table bit by bit, performs difference operation on the encoded data to extract the unmatched port code items, records the port number corresponding to the unmatched items and performs bidirectional pairing and combination to obtain the difference port combination table. The generated port connection code set is retrieved, and the corresponding port code set in the preset standard connection status table is extracted simultaneously. The internally configured parallel comparison logic operation register is activated, and the two-dimensional adjacency matrix data in both sets are converted into a one-dimensional continuous Boolean value stream according to row-major principle. A bit-by-bit scanning and traversal comparison is performed from beginning to end. Difference values ​​are calculated for the dual-coded data under the same matrix position index parameter. The baseline connection value at the corresponding memory position in the standard connection status table is subtracted from the actual connection value at the corresponding memory position in the port connection code set to calculate the link difference evaluation value for each link. The link difference evaluation value is set as follows: a value of 1 represents a missing link state where the standard requires a connection but no connection has actually been established; a value of -1 represents a redundant link state where the standard does not require a connection but a physical connection actually exists; and a value of 0 represents that the actual connection state of the port node completely matches the standard configuration. The baseline connection value 1 and the actual connection value 0 at matrix position index parameter 461 are read. The difference between the baseline connection value 1 and the actual connection value 0 is subtracted from the actual connection value 0 to directly calculate the link difference evaluation value as 1. Based on this value, the link corresponding to this index position is determined to be an unmatched port code item. If the read link difference assessment value is negative 1, it is also judged as an abnormal redundant match and a recording instruction is issued. The matrix position index parameter 461 bound to this unmatched item is extracted and recorded. Then, a reverse division addressing derivation is performed, dividing the matrix position index parameter by the maximum total number of physical panel interfaces to obtain the corresponding start port number and end port number. The previously confirmed maximum total number of physical panel interfaces, 50, is called, and 461 is divided by 50 to perform a floor operation, yielding a quotient of 9. This quotient is used as the start port number. Simultaneously, a remainder operation is performed on 461 divided by 50 to obtain a remainder of 11, which is used as the end port number. The start port number 9 and end port number 11 are bidirectionally paired and combined, and packaged with the link difference assessment value to generate a complete difference connection combination record, which is appended to the allocated memory combination array table block. All Boolean stream index parameters are continuously traversed and checked, and all records of missing and redundant connection nodes filtered out by the derivation are summarized to obtain a complete difference port combination table. Table 3 lists the distribution data of various differential connection records extracted through comparison. As shown in Table 3, the specific port node allocation and differential evaluation values ​​of each unmatched item are clearly and correspondingly presented.

[0036] Table 3. Difference Port Combination Table ; The control generation submodule calls the differential port combination table to read multiple port pairing records, retrieves the corresponding relay hardware number of the switch circuit based on the pairing record, converts the status bit to obtain the basic control code sequence, arranges and reassembles it according to the trigger timing sequence, issues relay control commands, and generates experimental control data. The system retrieves the port combination table in memory, iterating through rows to read the port pairing data recorded in the table. The programmable switch circuit employs a cross-matrix physical matrix topology. All experimental ports are mapped to the row and column buses of the physical matrix, respectively. Relays located at the intersection of row and column lines act as connecting arms, controlling the physical on / off state of the corresponding ports. The underlying physical hardware of the programmable switch circuit is constructed as a cross-matrix network. All experimental ports are divided into start-addressed columns and end-addressed rows, connected to the matrix bus array. Each specific relay switch element is connected across the intersection of a column bus containing a start port and a row bus containing an end port, thus forming the underlying execution unit that enables physical connection or isolation between any two ports. For each pairing record containing the start and end port numbers, the corresponding relay hardware number at the bottom layer of the switch circuit panel is retrieved using a cross-addressing conversion mechanism. The relay hardware number in the cross-addressing table is determined by the sum of the base memory offset address, the start port number multiplied by the hardware channel interval parameter, and the end port number. The circuit communication mapping protocol configuration document is read, and the relay array reference memory offset base address is extracted as 1000, and the hardware channel interval parameter is extracted as 64. Substituting the starting port number 9 and the ending port number 11 extracted in the previous steps, the starting port number 9 is multiplied by the hardware channel interval parameter 64 to calculate 576. The relay array reference memory offset base address 1000 is added to 576 to calculate 1576. Then, the ending port number 11 is added to 1576, and the target relay hardware number for closed-loop control is finally accurately derived as 1587. The link difference evaluation value 1 attached to the difference connection record is read, and the physical state bit conversion operation is performed on the evaluation value according to the preset digital level conversion rule. The link difference evaluation value 1 representing the missing link is converted into a high-level closed state bit code, and the link difference evaluation value -1 representing the redundant link is converted into a low-level open state bit code. The state bit is combined with the hardware number to obtain the basic control code sequence of a single node. A hardware action timing allocation mechanism is further introduced, configuring an independent trigger timestamp for each basic control code. This trigger timestamp is calculated by adding the current base millisecond time to the trigger execution sequence number and multiplying by the mechanical action delay parameter. The current base millisecond time is read from the motherboard's built-in clock register as 5000 milliseconds. The mechanical action delay parameter is extracted from the relay's electrical physical specifications as 15 milliseconds. The trigger execution sequence number currently allocated according to the scan order is 1. Multiplying the trigger execution sequence number 1 by the mechanical action delay parameter 15 milliseconds yields 15 milliseconds. Adding 15 milliseconds to the base millisecond time of 5000 milliseconds gives a trigger timestamp of 5015 milliseconds for this correction instruction. All basic control code sequences carrying the target relay hardware number, level control status bits, and independent trigger timestamps are strictly rearranged and reorganized according to the ascending order comparison rule of the trigger timestamp, constructing an execution queue with strict anti-collision timing dependencies.The reorganized queue is sent to the underlying microcontroller unit to execute relay control commands, ultimately generating experimental control data for automated reconfiguration of the physical circuit.

[0037] Please see Figure 8 A mobile experimental control method for electronic information engineering is implemented based on the aforementioned mobile experimental system for electronic information engineering, and includes the following steps: S1: Obtain port potential response sequence data and extract the voltage jump start time and peak value, sort the voltage jump start times and calculate the amplitude difference sequence of the voltage peak values ​​to generate port propagation data; S2: Filter the direct correlation pairs between the amplitude difference sequence of port propagation data and the preset direct connection judgment threshold, and extract the empty port set after sorting the voltage jump start time to construct explicit connection data; S3: Obtain impulse response waveform data of the vacant port set based on explicit connection data and calculate port integral energy, and filter implicit connection data by combining with preset implicit judgment threshold; S4: Based on the union operation of explicit connection data and implicit connection data, construct a full port connection mapping table and remove redundancies to build experimental topology data; S5: Obtain the preset standard connection status table and perform difference operation in combination with the experimental topology data, filter the difference port pairs and send relay control commands to the programmable switch circuit to construct experimental control data.

[0038] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A mobile experimental system for electronic information engineering, characterized in that, The system includes: The propagation analysis module acquires port potential response sequence data and extracts the voltage jump start time and peak value. It sorts the voltage jump start times and calculates the amplitude difference sequence of the voltage peak values ​​to generate port propagation data and transmits it to the explicit connection construction module. The explicit connection construction module filters the direct correlation pairs between the amplitude difference sequence of the port propagation data and the preset direct connection determination threshold, and extracts the empty port set after sorting the voltage jump start time to construct explicit connection data and transmit it to the implicit connection determination module. The implicit connection determination module obtains the impulse response waveform data of the vacant port set based on the explicit connection data and calculates the port integral energy. It then filters the implicit connection data by combining it with a preset implicit determination threshold and transmits it to the topology construction module. The topology construction module performs a union operation on the explicit connection data and the implicit connection data to construct a full port connection mapping table and remove redundancies, construct experimental topology data, and transmit it to the control and execution module. The control execution module acquires a preset standard connection status table and performs a difference operation in conjunction with the experimental topology data. It then filters out the difference port pairs and sends relay control commands to the programmable switch circuit to construct experimental control data.

2. The mobile experimental system for electronic information engineering according to claim 1, characterized in that, The port propagation data includes voltage transition start timing, peak amplitude set, and amplitude difference distribution sequence; the explicit connection data includes directly associated port pairs, judgment threshold filtering results, and vacant port set; the implicit connection data includes impulse response feature set, integral energy distribution, and implicitly associated port pairs; the experimental topology data includes a full set of connection relationships, connection mapping index, and redundancy elimination results; and the experimental control data includes a relay control code set, instruction timing sequence, and control output state set.

3. The mobile experimental system for electronic information engineering according to claim 1, characterized in that, The propagation analysis module specifically includes: The data analysis submodule acquires port potential response sequence data, detects the output signal level of the acquisition interface and writes it into the buffer queue according to time, normalizes the voltage values ​​of multiple sampling points in the buffer queue, performs interval verification on the time marker according to the sampling period parameter and removes abnormal interval items, and generates potential time sequence quantity. The jump extraction submodule calculates the voltage difference between adjacent sampling points based on the potential time series and selects time points that meet the preset voltage change threshold as jump start positions. At the same time, it records the corresponding voltage peaks, arranges all start positions in ascending order of time and adjusts the peak order synchronously to generate a jump time series amplitude table. The propagation combination submodule calculates the difference between adjacent voltage peaks according to the jump timing amplitude table to form an amplitude difference sequence. It then combines the sorted time sequence and the amplitude difference sequence according to their positions to construct a time-amplitude difference mapping relationship and remove missing items, thereby generating port propagation data.

4. The mobile experimental system for electronic information engineering according to claim 3, characterized in that, The voltage change threshold is determined by acquiring the reference potential sequence of the port idle state, calculating the absolute value of voltage fluctuation at adjacent sampling points within the reference potential sequence, extracting all absolute values ​​of voltage fluctuation and calculating the arithmetic mean, and multiplying the arithmetic mean by a set fluctuation tolerance coefficient.

5. The mobile experimental system for electronic information engineering according to claim 1, characterized in that, The explicit connection construction module is specifically as follows: The amplitude difference filtering submodule obtains the amplitude difference sequence of the port propagation data and a preset direct connection judgment threshold, performs threshold judgment on each difference item and records the port combination identifiers whose differences do not reach the direct connection judgment threshold, collects all port combination identifiers that meet the judgment conditions, and generates a direct association relationship pair sequence. The intersection construction submodule calls the sorted voltage time series based on the direct association relationship, extracts the corresponding port voltage time segment for each port combination in the sequence and performs time overlap judgment, records the intersection of port combinations with overlapping time segments, and obtains the sorted voltage time intersection set. The explicit connection generation submodule extracts port identifiers that do not participate in any intersection record based on the sorted voltage-time intersection set and performs set filtering on the multiple port identifiers to form empty port set records. At the same time, it generates explicit connection data for the sequence in combination with the direct association relationship.

6. The mobile experimental system for electronic information engineering according to claim 5, characterized in that, The direct connection determination threshold is determined by obtaining the reference amplitude difference sequence of the standard direct connection port, extracting the absolute values ​​of multiple differences in the reference amplitude difference sequence and calculating the arithmetic mean, and multiplying the arithmetic mean by the set connection tolerance coefficient.

7. The mobile experimental system for electronic information engineering according to claim 1, characterized in that, The hidden connection determination module is specifically as follows: The pulse application submodule, based on the explicit connection data, acquires the ports included in the set of vacant ports and applies a pulse excitation signal, records the voltage amplitude changes of multiple ports in a continuous time series and constructs a set of sampling points, normalizes the amplitude of multiple sampling points and rearranges them according to time to obtain the port pulse response waveform. The waveform integration submodule extracts the time interval and corresponding amplitude data of adjacent sampling points based on the port impulse response waveform quantity, performs segmented summation of the amplitude sequence according to equidistant intervals and superimposes the interval area values, accumulates all interval areas, merges the sum of the corresponding energies of multiple ports, and obtains the port integrated energy. The threshold filtering submodule constructs an energy value set based on the port integral energy and reads the corresponding port identifier item by item. It filters the corresponding port set whose energy values ​​exceed the preset implicit judgment threshold and records the connection identifier. The filtering results are then organized to obtain implicit connection data.

8. The mobile experimental system for electronic information engineering according to claim 1, characterized in that, The topology construction module is specifically as follows: The data union submodule obtains the explicit connection data and the implicit connection data, performs a union operation, extracts the port identifiers and corresponding links within multiple connection data, compares the start and end ports of multiple connection links, summarizes multiple connection links and appends them to the blank mapping structure, and generates a full port connection mapping table. The redundancy removal submodule reads the start and end port identifiers of multiple connection links based on the full port connection mapping table, performs reverse combination comparison based on the start and end port identifiers, finds bidirectional duplicate link records with the same port node combination and deletes the marked duplicate link records to obtain the deduplicated connection mapping set. The topology generation submodule calls the deduplication connection mapping set, extracts port identifiers from the mapping set as topology point items, extracts unidirectional connection records as topology connection items, and arranges the topology node items according to the starting relationship of the topology connection items to establish experimental topology data.

9. A mobile experimental system for electronic information engineering according to claim 1, characterized in that, The control execution module is specifically: The data receiving submodule obtains a preset standard connection status table through the communication interface and combines it with the experimental topology data. It rearranges the port numbers in the standard connection status table, extracts the connection relationship of the experimental topology data and expands it into a port connection sequence, aligns it with the format of the standard connection status table, and generates a port connection code set. The port calculation submodule performs a bit-by-bit comparison between the port connection code set and the port code set corresponding to the preset standard connection status table, performs difference operation on the code data to extract unmatched port code items, records the port number corresponding to the unmatched items and performs bidirectional pairing and combination to obtain the difference port combination table. The control generation submodule calls the differential port combination table to read multiple port pairing records, retrieves the corresponding relay hardware number of the switch circuit based on the pairing record, converts the status bit to obtain the basic control code sequence, arranges and reassembles it according to the trigger timing, and issues relay control commands to generate experimental control data.

10. A mobile experimental control method for electronic information engineering, characterized in that, The mobile experimental system for electronic information engineering according to any one of claims 1-9 comprises the following steps: S1: Obtain port potential response sequence data and extract the voltage jump start time and peak value, sort the voltage jump start times and calculate the amplitude difference sequence of the voltage peak values ​​to generate port propagation data; S2: The amplitude difference sequence of the port propagation data is filtered with the preset direct connection determination threshold to select the direct correlation pair, and the empty port set is extracted by combining the sorted voltage jump start time to construct explicit connection data; S3: Based on the explicit connection data, obtain the impulse response waveform data of the vacant port set and calculate the port integral energy, and filter the implicit connection data in combination with the preset implicit judgment threshold. S4: Based on the union operation of the explicit connection data and the implicit connection data, construct a full port connection mapping table and remove redundancies to construct experimental topology data; S5: Obtain the preset standard connection status table and perform difference operation in combination with the experimental topology data, filter the difference port pairs and send relay control commands to the programmable switch circuit to construct experimental control data.

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