A dual-mode multiplexer design method based on topology optimization
By adopting a dual-mode multiplexer design method based on topology optimization algorithm, low loss and low crosstalk performance are achieved in an ultra-compact scale, which solves the problems of large device size and high manufacturing difficulty in the prior art and is suitable for optical interconnect systems on high-density silicon substrates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHWEST JIAOTONG UNIV
- Filing Date
- 2026-04-17
- Publication Date
- 2026-06-23
Smart Images
Figure CN122260640A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of silicon-based photonic integration and on-chip optical interconnect technology, and particularly relates to a dual-mode multiplexer design method based on topology optimization. Background Technology
[0002] As the requirements for communication capacity and transmission rate in on-chip optical interconnect systems continue to increase, traditional single-dimensional multiplexing methods can no longer meet the development needs of high-density integrated optical communication systems. Mode multiplexing technology can carry multiple mutually orthogonal eigenmodes in the same waveguide, thereby significantly improving channel capacity, and has therefore attracted widespread attention.
[0003] Existing mode multiplexers mostly employ traditional forward design methods such as asymmetric directional couplers, multimode interferometers, or asymmetric Y-junctions. These methods typically rely heavily on the designer's experience and physical intuition, and are constrained by conditions such as phase matching, self-imaging, or adiabatic evolution. They often require long coupling lengths and gradual structural transitions, which can easily lead to problems such as large device size, sensitivity to manufacturing tolerances, and high integration difficulty, hindering the miniaturization and high-density integration of on-chip photonic devices.
[0004] In recent years, reverse engineering methods for photonic devices have gradually developed, providing a new technical path for the miniaturization and high-performance design of mode multiplexers. Unlike traditional forward design, which relies on experience and pre-defined structures, reverse engineering discretizes the device design area into a large number of pixel units and automatically searches for the optimal dielectric constant distribution by combining objective functions and numerical optimization algorithms, thus offering greater design freedom. Among these methods, topology optimization can achieve coordinated control of the optical field propagation path, phase distribution, and mode evolution process within a larger parameter space, potentially overcoming the limitations of traditional mode multiplexers in terms of size, loss, and crosstalk. Therefore, there is an urgent need to propose a dual-mode multiplexer design method based on topology optimization algorithms to achieve low-loss, low-crosstalk, and highly manufacturable device structures at ultra-compact scales. Summary of the Invention
[0005] To address the above shortcomings, this invention provides a dual-mode multiplexer design method based on topology optimization.
[0006] The present invention provides a dual-mode multiplexer design method based on topology optimization, comprising the following steps:
[0007] Step 1: Construct the initial physical model of the dual-mode multiplexer.
[0008] An initial structure of a dual-input single-output dual-mode multiplexer is established on a silicon-on-insulator platform. The structure includes a first input waveguide, a second input waveguide, a central optimized design region, and a multimode output waveguide. Both input waveguides are used to input the fundamental mode TE0 optical signal, and the multimode output waveguide is used to carry the TE0 mode and the TE1 mode.
[0009] Step 2: Establish the objective function and solve it using topology optimization.
[0010] (1) Discretize the central optimization design area into multiple nanoscale pixel units, and construct the design variable matrix by using the dielectric constant of each pixel unit as the variable to be optimized.
[0011] (2) Assign initial dielectric constant distribution values to the design region and introduce random disturbances to break the initial symmetry of the structure.
[0012] (3) Let the material distribution variable of each pixel unit in the central optimization design area be denoted as ρ(r), and the equivalent dielectric constant at each pixel position be expressed as:
[0013] ;
[0014] in, The dielectric constant of silicon is is the dielectric constant of silicon dioxide.
[0015] (4) Based on the functional requirements of the dual-mode multiplexer, the quality factor (FOM) is established as the objective function, and its expression is:
[0016] ;
[0017] Among them, T 11 and T 22 These represent the normalized transmittance of the corresponding target mode measured in the multimode output waveguide when the TE0 optical signal is independently injected from the first and second input waveguides, respectively.
[0018] (5) By combining forward simulation and adjoint simulation, the sensitivity information of the objective function to the dielectric constant of each pixel unit is calculated, and the global gradient distribution in the design area is obtained.
[0019] Step 3: Iteratively update the device structure and output the final topology layout.
[0020] Based on the obtained global gradient information, the gradient optimization algorithm is used to iteratively update the dielectric constant of each pixel unit in the design area. During the update process, filtering constraints and binarization projection constraints are introduced to limit excessively small structural features and gray-scale transition areas. When the change in the objective function is lower than the preset threshold or the preset maximum number of iterations is reached, the optimization process is terminated, and the final topology layout of the dual-mode multiplexer is output.
[0021] Furthermore, in step 1, the waveguide layer of the silicon-on-insulator platform is a silicon layer, and the upper and lower cladding layers are silicon dioxide layers with a silicon layer thickness of 220 nm; the dual-mode multiplexer includes two input waveguides and one output waveguide, with an input waveguide width of 0.5 μm, an output waveguide width of 0.9 μm, and a central optimized design area size of 3.6 μm × 3.6 μm.
[0022] Furthermore, in step 2, the central optimization design area is discretized into pixels, with the initial design area divided into 32,761 pixels. During the optimization evolution, the dielectric constant of each pixel unit continuously changes between the dielectric constants of silicon and silicon dioxide. To avoid getting trapped in local optima in the early stages of optimization and to prevent gradient deadlock caused by geometric symmetry, random perturbations are introduced into the initial dielectric constant distribution.
[0023] Furthermore, in step 2, the topology optimization uses the adjoint method to solve the gradient. By calculating the partial derivative of the objective function with respect to the dielectric constant of each pixel unit through the overlap relationship between the positive electromagnetic field and the adjoint electromagnetic field, the global sensitivity information of all pixels in the design area is obtained. After the topology optimization model is completed, the optimization algorithm parameters are set. The optimizer adopts the L-BFGS-B algorithm, with a maximum number of iterations of 400, an initial gradient scaling factor of 0.25, a projection filter radius of 120nm, an asymptotic binarization period of 40, an optimization working wavelength range of 1525nm to 1575nm, and 11 broadband wavelength sampling points.
[0024] Furthermore, in step 3, projection filtering and binarization constraints are introduced during the structure update process, so that the gray-scale transition region in the design area gradually converges into a binary material distribution of pure silicon and pure silicon dioxide, thereby improving the actual manufacturability of the device structure; finally, a dual-mode multiplexer layout that meets the process feature size requirements is obtained.
[0025] The beneficial technical effects of this invention compared to the prior art are as follows:
[0026] The dual-mode multiplexer design method based on topology optimization algorithm provided by this invention can achieve global optimization of the dielectric constant distribution within the design region without relying on traditional empirical structural presets, significantly improving the design freedom of the device. Compared with the traditional forward design method, this method can achieve TE0 mode pass-through transmission and TE1 mode efficient conversion in an ultra-compact size, while taking into account low insertion loss, low mode crosstalk, and high manufacturability. Simulation results show that the dual-mode multiplexer designed by this method has a target mode insertion loss of less than 0.6dB and a mode crosstalk of less than -30dB in the operating wavelength range of 1525nm to 1575nm, exhibiting good broadband stable operating performance and engineering application value. Attached Figure Description
[0027] Figure 1 This is a system block diagram of a dual-mode multiplexer design method based on topology optimization according to the present invention.
[0028] Figure 2 This is a graph showing the relationship between the number of algorithm iterations and the objective function.
[0029] Figure 3 This is the final device layout for the dual-mode multiplexer.
[0030] Figure 4 The electric field component transmission field diagram of the two-mode multiplexer.
[0031] Figure 5 This is a diagram showing the transmission performance analysis of the mode multiplexer. Detailed Implementation
[0032] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0033] The present invention provides a dual-mode multiplexer design method based on topology optimization. The overall design flow is as follows: Figure 1 As shown, specifically:
[0034] First, an initial structure of a dual-input, single-output dual-mode multiplexer is constructed, and an optimization design region is set at the center of the device. In this embodiment, the material distribution variable of each pixel unit within the central optimization design region is denoted as... To facilitate continuous medium topology optimization, the equivalent dielectric constant at each pixel location is expressed as:
[0035] ;
[0036] in, The dielectric constant of silicon is Let be the dielectric constant of silicon dioxide material; then, based on the mode multiplexing functional requirements, an objective function is established, and gradient information within the design region is obtained by combining forward simulation and adjoint simulation to iteratively optimize the device structure; to achieve the functional objective of the dual-mode multiplexer, this embodiment constructs the quality factor FOM as the optimization objective function, the expression of which is:
[0037] ;
[0038] Among them, T 11 and T 22 These represent the normalized transmittance of the corresponding target mode measured in the multimode output waveguide when the TE0 optical signal is independently injected from the first and second input waveguides, respectively.
[0039] The overall optimization objective of this invention is to reduce the two transmittance error terms in the objective function through gradient updates.
[0040] After determining the objective function, a virtual companion light source is set at the target output end, allowing it to propagate backward within the design region. Based on the Lorentz reciprocity theorem, the forward field and companion field are overlaid at each discrete grid point to obtain the gradient of the objective function with respect to the dielectric constant of each pixel. Subsequently, the optimizer iteratively updates the dielectric constant distribution within the design region according to the gradient descent direction and adaptive step size, causing the structure to evolve along the optimal direction. Optimization terminates when the change in the objective function falls below a set threshold or the number of iterations reaches its upper limit. In the later stages of optimization, a continuity penalty and binarization projection are combined to push the grayscale region towards either silicon or silicon dioxide, ultimately obtaining a binary device layout that meets the requirements of photolithography manufacturing.
[0041] Figure 2 The relationship between the number of algorithm iterations and the objective function in this embodiment is presented. From... Figure 2 It can be seen that in the early stage of optimization, the objective function value decreases rapidly with the increase of the number of iterations, indicating that the algorithm can quickly establish a dominant optical path that is conducive to mode conversion and transmission based on the accompanying gradient information. Subsequently, in the middle stage, the objective function enters an adjustment stage with a slow decrease and small fluctuations. At this time, the optimization mainly focuses on the refinement of the structural boundary and the binarization compression of the gray area. Finally, when the iteration is carried out to about 216 times, the objective function converges to a stable value, indicating that the device structure has reached a better state and finally forms a device topology that meets the requirements of photolithography.
[0042] Figure 3The image shows the binarized device layout of the dual-mode multiplexer obtained after topology optimization iterations. It can be seen that the optimized structure forms a complex but continuous high-refractive-index transmission channel and localized scattering interface within the central design region. This effectively controls the propagation path and phase distribution of the excitation light field at different input ports, thereby achieving mode-selective coupling and conversion. Simultaneously, the final layout has converged from a continuous grayscale dielectric constant distribution to a clear binary material distribution, indicating that the designed structure not only meets the expected mode multiplexing function but also possesses good manufacturability.
[0043] Figure 4 The propagation distribution of electric field components in a dual-mode multiplexer under different input excitation conditions is presented to characterize the optical field evolution process and mode conversion mechanism within the device. When the fundamental mode TE0 optical signal is injected into the first input waveguide, the optical field propagates stably along a predetermined path within the optimized region, achieving efficient direct transmission of the TE0 mode. When the fundamental mode TE0 optical signal is injected into the second input waveguide, the optical field undergoes significant redistribution and interference coupling within the optimized region, ultimately forming a corresponding higher-order mode distribution at the output, achieving effective conversion from the input fundamental mode to the target higher-order mode.
[0044] Figure 5 The diagram shows the transmission performance analysis of the mode multiplexer, reflecting the insertion loss and crosstalk performance of the device within the operating wavelength range of 1525nm to 1575nm. Throughout the entire 50nm operating bandwidth, the insertion loss of each target mode is controlled below 0.6dB, indicating that the device has high energy transmission efficiency. Simultaneously, the crosstalk between non-target modes is below -30dB, indicating that the device has good mode isolation performance. Therefore, the dual-mode multiplexer designed in this embodiment is not only compact in size but also maintains stable low-loss, low-crosstalk transmission characteristics over a wide wavelength range.
[0045] In summary, the dual-mode multiplexer design method based on topology optimization algorithm provided in this embodiment successfully achieves dual-mode multiplexing functionality—simultaneous TE0 mode pass-through transmission and efficient TE1 mode conversion—by performing pixel-level global optimization of the dielectric constant distribution within an ultra-compact design region of 3.6μm × 3.6μm. Simultaneously, by introducing filtering constraints and binarized projection constraints during the optimization process, the resulting device structure balances excellent optical performance with practical manufacturability, making it suitable for mode multiplexer design in high-density silicon substrate optical interconnect systems.
Claims
1. A design method for a dual-mode multiplexer based on topology optimization, characterized in that, Includes the following steps: Step 1: Construct the initial physical model of the dual-mode multiplexer; An initial structure of a dual-input single-output dual-mode multiplexer is established on a silicon-on-insulator platform. The structure includes a first input waveguide, a second input waveguide, a central optimized design area, and a multimode output waveguide. Both input waveguides are used to input the fundamental mode TE0 optical signal, and the multimode output waveguide is used to carry the TE0 mode and the TE1 mode. Step 2: Establish the objective function and solve it using topology optimization; (1) Discretize the central optimization design area into multiple nanoscale pixel units, and construct a design variable matrix using the dielectric constant of each pixel unit as the variable to be optimized; (2) Assign initial dielectric constant values to the design region and introduce random disturbances to break the initial symmetry of the structure; (3) Let the material distribution variable of each pixel unit in the central optimization design area be denoted as ρ(r), and the equivalent dielectric constant at each pixel position be expressed as: ； in, The dielectric constant of silicon is The dielectric constant of silicon dioxide material; (4) Based on the functional requirements of the dual-mode multiplexer, the quality factor (FOM) is established as the objective function, and its expression is: ； Among them, T 11 and T 22 These represent the normalized transmittance of the corresponding target mode measured in the multimode output waveguide when the TE0 optical signal is independently injected from the first and second input waveguides, respectively. (5) Using a combination of forward simulation and adjoint simulation, the sensitivity information of the objective function to the dielectric constant of each pixel unit is calculated to obtain the global gradient distribution within the design area; Step 3: Iteratively update the device structure and output the final topology layout; Based on the obtained global gradient information, the gradient optimization algorithm is used to iteratively update the dielectric constant of each pixel unit in the design area. During the update process, filtering constraints and binarization projection constraints are introduced to limit excessively small structural features and gray-scale transition areas. When the change in the objective function is lower than the preset threshold or the preset maximum number of iterations is reached, the optimization process is terminated, and the final topology layout of the dual-mode multiplexer is output.
2. The dual-mode multiplexer design method based on topology optimization according to claim 1, characterized in that, In step 1, the waveguide layer of the silicon-on-insulator platform is a silicon layer, and the upper and lower cladding layers are silicon dioxide layers with a silicon layer thickness of 220nm. The dual-mode multiplexer includes two input waveguides and one output waveguide. The input waveguide width is 0.5μm, the output waveguide width is 0.9μm, and the size of the central optimized design area is 3.6μm×3.6μm.
3. The dual-mode multiplexer design method based on topology optimization according to claim 1, characterized in that, In step 2, the topology optimization uses the adjoint method to solve the gradient. The partial derivative of the objective function with respect to the dielectric constant of each pixel unit is calculated by the overlap relationship between the positive electromagnetic field and the adjoint electromagnetic field to obtain the global sensitivity information of all pixels in the design area. After the topology optimization model is completed, the optimization algorithm parameters are set. The optimizer adopts the L-BFGS-B algorithm, with a maximum number of iterations of 400, an initial gradient scaling factor of 0.25, a projection filter radius of 120nm, an asymptotic binarization period of 40, an optimization working wavelength range of 1525nm to 1575nm, and 11 broadband wavelength sampling points.
4. The dual-mode multiplexer design method based on topology optimization according to claim 1, characterized in that, In step 3, projection filtering and binarization constraints are introduced during the structure update process, so that the gray-scale transition area in the design area gradually converges into a distribution of two binary materials, pure silicon and pure silicon dioxide, thereby improving the actual manufacturability of the device structure; finally, a dual-mode multiplexer layout that meets the process feature size requirements is obtained.