A phase-locked loop design method based on a lookup table

Abstract

The application discloses a design method of a phase-locked loop based on a lookup table mode, and first constructs a standard sine table containing 1024 points, wherein the interval between each point corresponds to the time difference of the lookup table; if the sine lookup table time is T, and the input power grid voltage period is T, then: T=T+T / N; when the value of N is larger, the lookup table step length step is smaller, and the phase locking is more accurate. The error of the dynamic adjustment of the phase locking step length is adjusted by a PI controller, so that the error is minimized. After the error between the power grid voltage period and the phase locking period is transmitted into the PI controller, the dynamic compensation error required for the adjustment at the current time is obtained, and then the error is superposed on the step length, so that the final accurate phase locking step length is obtained. The phase-locked loop parameters can be quickly determined, and the calculation burden in the design process is reduced.

Description

Technical Field

[0001] This invention relates to phase-locked loop (PLL) technology, and more particularly to a PLL design method based on a lookup table. Background Technology

[0002] A phase-locked loop (PLL) is a feedback control system used to synchronize the frequency and phase of an input signal, and it has wide applications in communication, clock recovery, and frequency synthesis. Traditional PLL designs typically require precise frequency and phase adjustments, and the design process necessitates extensive mathematical calculations of loop parameters (such as filters and gains). This not only increases design complexity but also impacts design efficiency, especially in the case of multi-frequency conversion, where the wide frequency range further complicates the design.

[0003] Existing technology and its limitations:

[0004] Existing phase-locked loop (PLL) design methods, such as those based on frequency response analysis or digital control, require repeated adjustments to circuit parameters to achieve optimal performance, resulting in relatively long design cycles and high computational complexity. Therefore, providing a method that can quickly determine PLL parameters and reduce the computational burden of the design process is of great significance.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a phase-locked loop design method based on a lookup table to solve the aforementioned technical problems in the prior art.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] The design method of phase-locked loop based on table lookup includes the following steps:

[0009] First, construct a standard sine table containing 1024 points, where the interval between each point corresponds to the time difference for table lookup;

[0010] If the sine lookup table time is The input grid voltage period is ,but:

[0011]

[0012] Where n represents the number of power grid voltage cycles between lookups when looking up the table. For switching frequency, The frequency of the input grid voltage;

[0013] The step size for each table lookup is calculated as follows:

[0014]

[0015] The larger the value of N, the smaller the step size for each table lookup, and the more accurate the phase-locked loop (PLL).

[0016] Compared with existing technologies, the phase-locked loop design method based on table lookup provided by this invention can quickly determine phase-locked loop parameters and reduce the computational burden of the design process. Attached Figure Description

[0017] Figure 1 A structural block diagram of a phase-locked loop design method based on a lookup table is provided for embodiments of the present invention;

[0018] Figure 2 This is a schematic diagram showing the results of verification in a simulation platform for an embodiment of the present invention;

[0019] Figure 3 As an embodiment of the present invention, a schematic diagram of the phase-locked loop angular frequency response curve after the phase-locked loop stabilizes. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0021] First, the following explanations are provided for the terms that may be used in this article:

[0022] The terms “including,” “contains,” “comprising,” “having,” or other similar semantic descriptions shall be interpreted as non-exclusive inclusion.

[0023] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0024] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0025] like Figure 1 As shown, a phase-locked loop (PLL) design method based on a lookup table includes the following steps:

[0026] First, construct a standard sine table containing 1024 points, where the interval between each point corresponds to the time difference for table lookup;

[0027] If the sine lookup table time is The input grid voltage period is ,but:

[0028]

[0029] Where n represents the number of power grid voltage cycles between lookups when looking up the table. For switching frequency, The frequency of the input grid voltage;

[0030] The step size for each table lookup is calculated as follows:

[0031]

[0032] The larger the value of N, the smaller the lookup step size, and the more accurate the phase-locked loop (PLL).

[0033] The error of the phase-locked loop step size is dynamically adjusted by a PI controller to minimize it.

[0034] After the error between the grid voltage cycle and the phase-locked loop cycle is fed into the PI controller, the dynamic compensation error that needs to be adjusted at the current moment is obtained. Then, the error is added to the step size to obtain the final accurate phase-locked loop step size.

[0035] In summary, the phase-locked loop (PLL) design method based on table lookup in this invention can quickly determine PLL parameters and reduce the computational burden of the design process.

[0036] To more clearly demonstrate the technical solution and its effects provided by the present invention, the embodiments of the present invention will be described in detail below with reference to specific examples.

[0037] Example 1

[0038] like Figure 1 As shown, the present invention adopts the following technical solution:

[0039] First, construct a standard sine table containing 1024 points, where the interval between each point corresponds to the time difference for table lookup. If the sine lookup time is... The input grid voltage period is ,but:

[0040]

[0041] Where n represents the number of times the power grid voltage cycle is intermittent when looking up the table. For switching frequency, The frequency of the input grid voltage;

[0042] The step size for each table lookup is calculated as follows:

[0043]

[0044] The larger the value of N, the smaller the lookup step size (step), and the more accurate the phase-locked loop (PLL). To further improve the PLL accuracy, a PI controller is introduced to dynamically adjust the error of the PLL step size to minimize it.

[0045] Its structural block diagram is as follows Figure 1 As shown.

[0046] After the error between the grid voltage cycle and the phase-locked loop cycle is fed into the PI controller, the dynamic compensation error that needs to be adjusted at the current moment is obtained. Then, the error is added to the step size to obtain the final accurate phase-locked loop step size.

[0047] Detection and experimental verification

[0048] The method of this invention was verified on a simulation platform, and the results are as follows: Figure 2 As shown, the upper curve is a sine curve of the simulated 220V effective voltage input of the power grid, and the lower curve is the output unit sine curve that follows the input signal and is phase-locked, with a peak-to-peak value of 1.

[0049] Simulation results show that once the phase-locked loop stabilizes, the phase difference between the output and input is negligible. The phase-locked loop angular frequency response curve is shown below. Figure 3 As shown, the stabilization time is relatively fast.

[0050] This invention is mainly used in the power electronics industry to track the frequency and phase of input signals.

[0051] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A design method of a phase-locked loop based on a table lookup method, characterized by, Including the following steps: First, construct a standard sine table containing 1024 points, where the interval between each point corresponds to the time difference for table lookup; If the sine lookup time is The input grid voltage period is ,but: ； Where n represents the number of power grid voltage cycles between lookups when looking up the table. For switching frequency, The frequency of the input grid voltage; The step size for each table lookup is calculated as follows: ； The larger the value of N, the smaller the lookup step size, and the more accurate the phase-locked loop (PLL).

2. The phase-locked loop design method based on table lookup as described in claim 1, characterized in that, The error of the phase-locked loop step size is dynamically adjusted by a PI controller to minimize it.

3. The phase-locked loop design method based on table lookup according to claim 2, characterized in that, After the error between the grid voltage cycle and the phase-locked loop cycle is fed into the PI controller, the dynamic compensation error that needs to be adjusted at the current moment is obtained. Then, the error is added to the step size to obtain the final accurate phase-locked loop step size.

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