SC-LDPC code decoding method and related device based on a look-ahead pipeline and aggregated storage

Abstract

The application discloses an SC-LDPC code decoding method and related equipment based on a forward-looking pipeline and aggregated storage, which can be applied to the fields of digital communication and storage technology. When a plurality of serial processors are scheduled by a control module of a decoder to perform iterative calculation on a to-be-decoded SC-LDPC code, all variable nodes and all check nodes corresponding to the to-be-decoded SC-LDPC code are updated based on a forward-looking message update strategy in each processor, so that the problem of pipeline message update lag can be effectively solved. Meanwhile, the same calculation module in the decoder is shared by the plurality of processors in time based on an aggregated storage architecture and an address mapping mechanism, so that the problem of storage resource fragmentation is solved, and then the convergence speed and the throughput of the decoding process are effectively improved. Finally, the final soft information obtained through the iterative calculation is subjected to hard decision to obtain the decoding result corresponding to the to-be-decoded SC-LDPC code, so that the accuracy of the decoding result is improved.

Description

Technical Field

[0001] This application relates to the field of digital communication and storage technology, and in particular to an SC-LDPC code decoding method and related equipment based on look-ahead pipeline and aggregated storage. Background Technology

[0002] In related technologies, the decoding of Spatially-Coupled LDPC (SC-LDPC) codes typically employs iterative decoding based on belief propagation (BP) or its simplified algorithms (such as the minimum sum algorithm). To meet the stringent requirements of modern communication systems for high throughput (e.g., exceeding 100 Gbps or even Tbps), hardware decoders must adopt a highly parallel pipeline architecture. In pipeline design, a complete iterative computation is broken down into multiple sequentially executed stages (pipeline stages), with data flowing continuously between different stages, thereby significantly improving the system's clock frequency and data processing throughput.

[0003] However, when mapping iterative algorithms to deeply pipelined hardware, the message update of the nth iteration heavily depends on the complete result of the (n-1)th iteration. But when the data from the nth iteration enters subsequent pipeline stages, the latest message it depends on, which should have been generated by this iteration, may not yet have been computed from the preceding pipeline stages. Therefore, the hardware has to use outdated messages for computation, resulting in pipeline conflicts. These conflicts weaken the information update efficiency of each iteration, leading to a decrease in decoding convergence speed. To achieve the same error correction performance as non-pipelined decoding, the pipelined architecture needs to increase the number of iterations, thus increasing power consumption. Furthermore, when implementing SC-LDPC decoders on hardware platforms such as FPGAs, the sliding window decoding process of SC-LDPC codes requires storing and accessing a large number of intermediate variable nodes and check node information for each window. Existing solutions use distributed storage (such as multiple independent Block RAMs) to allocate dedicated memory to different computational units. This approach leads to storage resource fragmentation as parallelism increases.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose an SC-LDPC code decoding method and related equipment based on look-ahead pipeline and aggregated storage, which can effectively solve the problems of pipeline message update lag and storage resource fragmentation, thereby improving convergence speed and throughput.

[0006] To achieve the above objectives, one aspect of this application proposes an SC-LDPC code decoding method based on look-ahead pipeline and aggregated storage, the method comprising the following steps: Obtain the SC-LDPC code to be translated; When the control module of the decoder schedules multiple serial processors to perform iterative calculations on the SC-LDPC code to be translated, it controls each processor to update all variable nodes and all check nodes corresponding to the SC-LDPC code to be translated based on a look-ahead message update strategy. At the same time, based on the aggregated storage architecture and address mapping mechanism, it controls multiple processors to share the same calculation module in the decoder in a time-sharing manner. Hard decision is made on the final soft information obtained by iterative calculation to obtain the decoding result corresponding to the SC-LDPC code to be decoded.

[0007] In some embodiments, updating all variable nodes and all check nodes corresponding to the SC-LDPC code to be translated based on a look-ahead message update strategy includes: Update all variable nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm or the variable node look-ahead pipelined BP decoding algorithm. The look-ahead pipelined backpropagation (BP) decoding algorithm is used to update all check nodes corresponding to the SC-LDPC code to be decoded.

[0008] In some embodiments, updating all check nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm includes: Obtain the first received information of the associated variable node corresponding to the current verification node and the first target information updated by the previous processor within the current iteration cycle; The current verification node is updated based on the first received information and the first target information.

[0009] In some embodiments, updating all variable nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm or the variable node look-ahead pipelined BP decoding algorithm includes: Obtain the second received information of the verification node associated with the current variable node and the second target information updated by the previous processor in the current iteration cycle; The current variable node is updated based on the second received information and the second target information.

[0010] In some embodiments, the decoder includes an input buffer module, a control module, a matrix storage module, a data storage module, a calculation module, a hard decision module, and an output buffer module; The input caching module is used to temporarily cache the input SC-LDPC codes to be translated; The control module is used to generate control signals during the decoding process, and coordinate the working states of the input buffer module, the matrix storage module, the data storage module, the calculation module, the hard decision module, and the output buffer module according to the control signals. The matrix storage module is used to store the verification matrix of the SC-LDPC code to be translated; The data storage module is used to store all received information transmitted through the channel and intermediate variables generated during the decoding process. The calculation module is used to execute the update, storage, and transmission processes of all variable nodes and verification nodes; The hard decision module is used to make hard decisions on the final soft information; The output buffer module is used to buffer the decoding results of the SC-LDPC code to be decoded.

[0011] In some embodiments, the matrix storage module is used to store the position information of the non-zero elements of the check matrix corresponding to the SC-LDPC code to be translated.

[0012] To achieve the above objectives, another aspect of this application proposes an SC-LDPC code decoding apparatus based on look-ahead pipeline and aggregated storage, the apparatus comprising: The first module is used to obtain the SC-LDPC code to be translated; The second module is used to control each processor to update all variable nodes and all check nodes corresponding to the SC-LDPC code to be translated based on a look-ahead message update strategy when the control module of the decoder schedules multiple serial processors to perform iterative calculations on the SC-LDPC code to be translated. At the same time, based on the aggregated storage architecture and address mapping mechanism, the multiple processors are controlled to share the same calculation module in the decoder in a time-sharing manner. The third module is used to make a hard decision on the final soft information obtained by iterative calculation, so as to obtain the decoding result corresponding to the SC-LDPC code to be decoded.

[0013] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0014] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described above.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer program product, including a computer program that, when executed by a processor, implements the aforementioned method.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides an SC-LDPC code decoding method and related equipment based on look-ahead pipeline and aggregated storage. This scheme, by scheduling multiple serial processors to perform iterative calculations on the SC-LDPC code to be decoded in the decoder's control module, controls each processor to update all variable nodes and all check nodes corresponding to the SC-LDPC code to be decoded based on a look-ahead message update strategy, which can effectively solve the problem of pipeline message update lag. At the same time, based on the aggregated storage architecture and address mapping mechanism, it controls multiple processors to share the same calculation module in the decoder in a time-sharing manner to solve the problem of storage resource fragmentation, thereby effectively improving the convergence speed and throughput of the decoding process. Then, after hard decision on the final soft information obtained from the iterative calculation, the decoding result corresponding to the SC-LDPC code to be decoded is obtained, thereby improving the accuracy of the decoding result. Attached Figure Description

[0017] Figure 1 This is a flowchart of the SC-LDPC code decoding method based on look-ahead pipeline and aggregated storage provided in the embodiments of this application; Figure 2 This is a schematic diagram of a partial parity check matrix of the (5,3(2),5) SC-LDPC code provided in the embodiments of this application; Figure 3 This is provided in the embodiments of this application. Figure 2 A schematic diagram of the check node update corresponding to the SC-LDPC code; Figure 4 This is provided in the embodiments of this application. Figure 2 A schematic diagram of variable node updates corresponding to SC-LDPC codes; Figure 5 This is a schematic diagram illustrating the application of the look-ahead message update strategy provided in this application embodiment in the verification node update process; Figure 6 This is a schematic diagram showing the representation of the look-ahead message update strategy in the verification matrix during the verification node update process provided in this application embodiment; Figure 7 This is a schematic diagram illustrating the application of the look-ahead message update strategy provided in this application embodiment in the variable node update process; Figure 8 This is a schematic diagram showing the representation of the look-ahead message update strategy in the verification matrix during the variable node update process provided in this application embodiment; Figure 9 This is a comparative diagram illustrating the performance improvements introduced by the look-ahead message update strategy provided in the embodiments of this application; Figure 10 This is a schematic diagram of the decoder module provided in the embodiments of this application; Figure 11 This is a schematic diagram showing the location of the information required for updating the verification node according to an embodiment of this application; Figure 12 This is a schematic diagram of processor serial pipelined computing provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0020] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] In related technologies, error correction coding techniques are indispensable in modern digital communication and storage systems to ensure the reliability of information transmission in unreliable channels. Low-Density Parity-Check (LDPC) codes, due to their excellent error correction performance and potential for parallel decoding, have become one of the core channel coding schemes in fields such as 5G, Wi-Fi, and satellite communication. However, traditional LDPC codes face challenges when processing continuous data streams or pursuing extremely low decoding latency. Spatially-Coupled LDPC (SC-LDPC) codes, as an important branch of LDPC codes, introduce a convolutional coupling structure. When using sliding window decoding, they can achieve near-infinite code performance with finite decoding latency, exhibiting particularly excellent performance in threshold saturation characteristics and bit error rate plateau regions. Therefore, they are considered a powerful candidate coding scheme for next-generation ultra-high-speed communication systems.

[0023] Decoding SC-LDPC codes typically employs iterative decoding based on belief propagation (BP) or its simplified algorithms (such as the min-sum algorithm). To meet the stringent requirements of modern communication systems for high throughput (e.g., exceeding 100 Gbps or even Tbps), hardware decoders must utilize a highly parallel pipeline architecture. In pipelined design, a complete iterative computation is broken down into multiple sequentially executed stages (pipeline stages), with data flowing continuously between different stages, thereby significantly improving the system's clock frequency and data processing throughput.

[0024] However, mapping iterative algorithms to deeply pipelined hardware encounters the "message update lag" problem. In standard iterative decoding, the message update for the nth iteration heavily depends on the complete result of the (n-1)th iteration. But in a pipeline, when data from the nth iteration enters a subsequent pipeline stage, the latest message it depends on, which should have been generated by this iteration, may not yet have been computed from the preceding pipeline stage. Therefore, the hardware must use outdated messages for computation, a phenomenon known as "pipeline conflict." This conflict reduces the efficiency of information updates in each iteration, leading to a significant decrease in decoding convergence speed. To achieve the same error correction performance as non-pipeline decoding, the pipelined architecture requires additional iterations, thus offsetting its throughput advantage and increasing power consumption.

[0025] Furthermore, when implementing SC-LDPC decoders on hardware platforms such as FPGAs, the sliding window decoding process of SC-LDPC codes requires storing and accessing a large amount of intermediate variable nodes and check node information for each window. Traditional implementations use distributed storage (such as multiple independent Block RAMs), allocating dedicated memory to different computing units. This approach leads to severe storage resource fragmentation problems when parallelism increases, resulting in low utilization of many BRAM cells due to a mismatch between capacity and port requirements. Simultaneously, complex storage network interconnections also bring huge wiring overhead and timing pressures, further reducing decoder performance and resource efficiency.

[0026] In view of this, this application provides an SC-LDPC code decoding method and related equipment based on look-ahead pipeline and aggregated storage, which can effectively solve the problems of pipeline message update lag and storage resource fragmentation, thereby improving convergence speed and throughput.

[0027] The embodiments of this application will be described in detail below with reference to the accompanying drawings: Reference Figure 1 This application provides an SC-LDPC code decoding method based on look-ahead pipeline and aggregated storage, which includes, but is not limited to, the following steps: Step S110: Obtain the SC-LDPC code to be translated; Step S120: When the control module of the decoder schedules multiple serial processors to perform iterative calculations on the SC-LDPC code to be decoded, it controls each processor to update all variable nodes and all verification nodes corresponding to the SC-LDPC code to be decoded based on a look-ahead message update strategy. At the same time, it controls multiple processors to share the same calculation module in the decoder in a time-sharing manner based on an aggregated storage architecture and address mapping mechanism. Step S130: Perform a hard decision on the final soft information obtained from the iterative calculation to obtain the decoding result corresponding to the SC-LDPC code to be decoded.

[0028] It is understood that this application's embodiments, through a look-ahead message update strategy and its coordinated aggregated storage architecture and address mapping mechanism, can solve two major problems in traditional pipelined decoding: message update lag and hardware storage resource fragmentation. Specifically, in existing traditional pipelined Belief Propagation (BP) decoding algorithms, each processing unit (corresponding to one iteration) can only strictly rely on messages received after the previous iteration cycle has completely ended when updating the variable node (VN) or check node (CN). This results in the latest messages calculated within the current iteration cycle not being utilized in a timely manner, causing message transmission lag and reducing the decoding convergence speed. This application's embodiments solve the above problems through a look-ahead message update strategy. Specifically, at the update moment of a node in the current iteration, this embodiment dynamically identifies and integrates more reliable new messages that have been updated by its neighboring nodes within the current iteration cycle, replacing or partially replacing old messages for calculation, thereby accelerating the accuracy of this update and the convergence of the entire decoding process. The look-ahead message update strategy can be applied in both variable node and check node update processes. Based on this, this application specifically constructs two decoding algorithms: the PP-BP algorithm (look-ahead pipelined BP decoding algorithm) and the VNPP-BP algorithm (variable node look-ahead pipelined BP decoding algorithm). This application's embodiments update all variable nodes corresponding to the SC-LDPC code to be decoded based on either the look-ahead pipelined BP decoding algorithm or the variable node look-ahead pipelined BP decoding algorithm; and update all check nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm. Specifically, when updating all variable nodes corresponding to the SC-LDPC code to be decoded based on the variable node look-ahead pipelined BP decoding algorithm, the corresponding check nodes are still updated in the existing manner.

[0029] Meanwhile, to address the problem of wasted storage resources, this embodiment proposes an aggregated storage architecture and address mapping mechanism that works in conjunction with a look-ahead message update strategy. Specifically, in existing FPGA implementations, multiple storage units of each processor (corresponding to a pipeline stage) are independently instantiated in multiple independent block RAMs (BRAMs). Since the capacity of each BRAM is fixed, and the size required for each FIFO often cannot completely fill a BRAM, a large amount of storage space is left idle, resulting in low utilization—a phenomenon known as "resource fragmentation." This embodiment utilizes the serial computation scheduling characteristic of the decoder (multiple processors sharing the same computation module in a time-sharing manner) to propose an aggregated storage architecture. Specifically, this embodiment physically aggregates storage units with the same logical function (i.e., the same number) in all processors into the same large BRAM. Through address planning, data originally scattered across dozens of small BRAMs is integrated into a few large BRAMs, thereby greatly eliminating storage fragmentation and significantly reducing the required storage resource consumption.

[0030] This embodiment, employing a converged storage architecture, also includes a corresponding address mapping method. This method accurately converts the "data logical address" and "processor number" in the algorithm model into a "data physical address." This mapping relationship is implemented by the storage control module, transparent to the upper-layer algorithm, ensuring efficient utilization of storage resources while accurately supporting pipelined decoding data flow access.

[0031] For example, the transpose of a time-varying periodic SC-LDPC code parity-check matrix with a code rate R=b / c is expressed as follows: ; In the formula, yes submatrix, This refers to the memory length of SC-LDPC. For a specific time point.

[0032] For all , All are of full rank, and have , It is the period of the SC_LDPC code. If This becomes a time-invariant periodic SC-LDPC code. Similar to LDPC codes, the transpose of the parity-check matrix of an SC-LDPC code has [missing information - likely related to parity-check matrix]. The first 1, from the first Listed Therefore, the degrees of the variable node and the check node of this SC-LDPC code are respectively 1. and The SC-LPDC code with the above structure can be represented as: SC-LDPC code. The parity-check matrix of SC-LDPC can be obtained by constructing an appropriate base matrix and then performing cut-shift copying. The method of obtaining the parity-check matrix from the base matrix is ​​not related to the content of this invention and will not be described in detail here. Taking the (5,3(2),5) SC-LDPC code with a code rate of 1 / 2 as an example, one of its base matrices... and the parity check matrix obtained from the basis matrix. It is expressed as follows: ; ; The parity-check matrix obtained by cutting, shifting, copying, and concatenating the base matrix exhibits a combination of sparsity and periodicity in its code structure. Specifically, its parity-check matrix can be formed by periodically arranging several sub-matrices with the same structure along the time or spatial dimension, thus forming a convolutional parity-check relationship. Based on the above structural characteristics, SC-LDPC codes have significant advantages in both encoding and decoding. In terms of encoding, due to the regular periodic structure and finite memory of the parity-check matrix, an SC-LDPC encoder can be constructed using registers and XOR gates, resulting in a simple structure and low encoding complexity. In terms of decoding, the semi-infinite structure of SC-LDPC codes allows the decoding process to begin without waiting for the complete codeword to be received. The decoder can start iterative calculation after receiving a partial codeword, achieving low latency and continuous decoding. At the same time, due to the convolutional nature of the code structure, its code length is not fixed and can be flexibly configured according to actual system requirements, which is beneficial for supporting communication scenarios with different frame lengths or variable rates. In summary, SC-LDPC has significant technical advantages in reducing encoding and decoding complexity, reducing system latency, and improving hardware implementation flexibility, making it particularly suitable for communication systems with high requirements for real-time performance and resource utilization.

[0033] In some embodiments, taking the (5,3(2),5) SC-LDPC code as an example, the traditional pipelined decoding (BP) algorithm for SC-LDPC codes is described in detail. Specifically, the parity-check matrix of the SC-LDPC code is shown in the attached figure. Figure 2 As shown, the decoder constructed by this decoding method consists of I parallel processing units, each containing J+1 levels of data buffer, where I represents the number of iterations. In the J+1 level buffer, the first level stores the initial log-likelihood ratio l(n) of the channel, while the remaining J levels store intermediate iteration results. The decoding process can be visualized as follows: The code flows sequentially through the Level I processing unit, completing one iteration at each level. The specific decoding process is as follows: (1) Initialization: Initialize all units in the J+1 level cache to ∞; (2) Shifting stage: For each c adjacent variable bits and parity bits of the channel received value, the corresponding log-likelihood metric is calculated and stored in the first c bits of the first-level buffer, and all other values ​​in the buffer are shifted c bits to the right in sequence. (3) Verification node update: as shown in the appendix Figure 3 As shown, processor P i (i=1,…,I) Based on the current verification relationship, obtain the log-likelihood ratio metric values ​​that need to be updated from each level of cache, update them using the following formula, and then store them back in the original location. Figure 3 The processor P is shown in the image. i and P i-1 The update diagram shows the current checksum being processed by the processor, indicated by the red box on the right. There are four levels of cache on the left: the first level stores the log-likelihood metric l(n) received from the channel; the second, third, and fourth levels store intermediate decoding iterations; and the data involved in the processor's update is represented by Z. j (i) (n) represents the following formula: ; In the formula, C(ni) is the set of K pairs (j,n); C(ni) / (j,n) represents the part remaining after removing (j,n) from C(ni). Ni = n0 - 2(i-1)(M+1) represents the verification node being processed by processor i, and n0 represents the variable node that was just moved to the first processor. (j,n) indicates that the nth variable node is included in the verification relationship being processed by the i-th processor, and this verification relationship is the j-th verification relationship in which the nth variable node participates.

[0034] (4) Variable node update: as shown in the appendix Figure 4 As shown, processor P i (i=1,…,I) Update the c variable nodes that are about to leave the current processor using the following formula, and store the calculation results back in the cache: ; in, Figure 4 The processor P is shown in the image. i and P i-1 The update diagram shows the variable node currently being processed by the processor, indicated by the red box on the right.

[0035] (5) If the information has been moved to the end of the last processor, then processor I makes a hard decision, outputs the decision result and returns to step (2); otherwise, it returns directly to step (2).

[0036] Based on the above, in the traditional pipelined BP decoding algorithm, it is evident that each processing unit can only rely on the messages generated in the previous iteration for updates to the variable and check nodes, and cannot promptly utilize the intermediate results updated in the current iteration, resulting in limited message transmission efficiency. To improve this problem, this embodiment proposes a look-ahead message update strategy. The core idea of ​​the look-ahead message update strategy is to first determine whether the information upon which the current update depends can be more reliably estimated using messages updated in previous iterations during the update process of the check and variable nodes; if feasible, then calculate and adopt the estimated value in advance, thereby improving message accuracy and transmission efficiency.

[0037] Specifically, in this embodiment of the application, when updating all check nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm, the current check node can be updated according to the first received information and the first target information updated by the previous processor within the current iteration cycle after obtaining the first received information and the first target information of the associated variable node corresponding to the current check node. When updating all variable nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm or the variable node look-ahead pipelined BP decoding algorithm, the current variable node can be updated according to the second received information and the second target information updated by the previous processor within the current iteration cycle after obtaining the second received information and the second target information of the associated check node corresponding to the current variable node.

[0038] The application process of the look-ahead message update strategy in this embodiment is explained below, focusing on the two steps of updating the verification node and the variable node: like Figure 5 As shown, Figure 5 Taking processor 2 (corresponding to the second processing unit in the pipeline) as an example, this embodiment specifically demonstrates the application scenario of the look-ahead message update strategy proposed in the verification node update step. Figure 5 The diagram shows a local Tanner graph structure, with the top and bottom rows representing variable nodes V1 to V2. 18 The middle row represents check nodes C1 to C9. The lines connecting the nodes represent the corresponding non-zero elements in the check matrix, i.e., the connection relationship between variable nodes and check nodes, and also correspond to a piece of data in the data cache. The color of the lines represents the direction of data flow; for example, green indicates information flowing from variable nodes to check nodes, and red indicates information flowing from check nodes to variable nodes. Updating check nodes and variable nodes involves the nodes using the received information to perform calculations and then passing the resulting information outwards along the lines. Currently, processor 2 needs to update check node C6. Traditional methods can only use all connected variable nodes (V2, V3, V9, V...). 11 V 12The "look-ahead" message passing strategy allows processor 2 to determine if certain variable nodes (e.g., V2, V3, V9) have already been updated by processor 1 within the current iteration. In this case, processor 2 can directly use the latest, more reliable messages from these variable nodes to calculate and pass them to C6. The connection between V2 and C1 in the diagram indicates that V2 has obtained more reliable information from C1. Calculating this information before C6 updates it improves the decoding convergence speed. Figure 6 This indicates the application of the look-ahead message update strategy in the verification matrix. The dashed box represents a message that needs to be updated before the verification node is updated. In summary, in step (3) of the above decoding process, the reliability of the information involved in the update is first improved using the following formula, and then the verification node update is completed based on the original formula: ; Secondly, the look-ahead message update strategy is also applicable to the update process of variable nodes. (See attached image) Figure 7 As shown, processor 1 updates variable node V 13 V 14 With V 13 For example, traditional methods can only use old messages passed by all connected check nodes (such as C7, C8, and C9) after the previous iteration. However, the look-ahead message update strategy allows for judgment: if messages passed by some check nodes (such as C7) have already been updated in an earlier step of this update, processor 1 can directly use the latest, more reliable messages generated by these check nodes to recalculate the check node's message to V. 13 This improves the accuracy of V13 updates and speeds up decoding convergence by transmitting information. Figure 8 The application of the look-ahead message update strategy is marked in the verification matrix. The dashed box indicates that the information at this point needs to be updated before the variable node is updated. In summary, in step (4) of the above decoding process, the reliability of the message involved in the update is first improved using the following formula, and then the variable node is updated based on the original formula.

[0039] ; Therefore, by integrating the look-ahead message update strategy, the update process of the verification node and variable node can fully utilize the latest messages generated in the previous iteration, thereby effectively improving the reliability of the information used in this update, accelerating the propagation efficiency of information in the Tanner graph, and improving the convergence performance of the decoder. Simulation results are attached. Figure 9As shown, it is clear that introducing a look-ahead message update strategy (i.e., the VNPP-BP algorithm) into the variable node update of (M,3(2),5)SC-LDPC (M=129 / 513 / 1025) can reduce the number of decoding iterations I by about 25% while maintaining the same bit error rate performance. When this message passing strategy is applied to both types of node updates, the number of decoding iterations I can be reduced by about 50% while maintaining the same bit error rate performance, resulting in a significant improvement in algorithm performance.

[0040] Based on the principle of look-ahead message update strategy, analysis of the SC-LDPC decoding algorithm shows that existing pipelined decoding architectures, when the number of iterations is set to I, consist of I parallel processors, each responsible for one complete iterative decoding process. FPGA, with its reconfigurable characteristics and powerful parallel computing capabilities, has become an ideal hardware platform for implementing SC-LDPC decoders. This invention, based on Xilinx series FPGAs, implements the traditional pipelined BP decoding algorithm, the PP-BP decoding algorithm with look-ahead message update strategy, and the VNPP-BP decoding algorithm for SC-LDPC codes with memory length M = 129, 513, 1025 and 16-bit fixed-point quantization (M, 3(2), 5) structure. The hardware simulation results are compared and analyzed with the theoretical simulation results.

[0041] like Figure 10 As shown, the decoder in this embodiment adopts a modular design, specifically including an input buffer module, a controller module, a matrix memory module, a data memory module, a calculator module, a hard-decision module, and an output buffer module. Each module in the decoder works collaboratively under the scheduling of the controller module. This embodiment employs a collaborative optimization strategy of "serial computation, aggregated storage," where multiple decoding processors (corresponding to pipeline levels / iteration counts) time-sharingly reuse the same set of computational units, sacrificing some latency to greatly save logic resources. Simultaneously, an aggregated storage architecture is designed to fundamentally solve the problem of storage resource fragmentation.

[0042] It is understandable that the working principle of each module in the decoder of this embodiment is as follows: The input buffer module is used to temporarily buffer the input SC-LDPC codes to be translated; The control module is used to generate control signals during the decoding process, and coordinates the working status of the input buffer module, matrix storage module, data storage module, calculation module, hard decision module and output buffer module according to the control signals; The matrix storage module is used to store the check matrix of the SC-LDPC code to be decoded; The data storage module is used to store all received information transmitted through the channel and intermediate variables generated during the decoding process; The calculation module is used to perform the update, storage, and transmission processes for all variable nodes and verification nodes; The hard decision module is used to make hard decisions on the final soft information; The output buffer module is used to buffer the decoding results of the SC-LDPC codes to be decoded.

[0043] Understandably, since the parity-check matrix of an SC-LDPC code can be generated from the basis matrix through operations such as copying, shifting, and concatenation, this semi-infinite structure with periodic characteristics makes the basis matrix a complete carrier of structural information during encoding and decoding. However, the storage requirements of the basis matrix expand with the increase of the memory length: for an SC-LDPC code with a memory length of M, the dimension of its basis matrix is ​​2M. 1)×(2M 1) This structural characteristic brings two problems: First, the storage requirement of the basis matrix increases significantly with M, leading to a sharp increase in storage resource demand; second, during the decoding process, each processing unit needs to frequently access the matrix to obtain the current parity check, thus introducing significant clock cycle overhead. In-depth analysis of the decoding process reveals that its core computation can be reduced to accessing and processing the non-zero elements (i.e., row and column indices) in the parity check matrix. (See attached...) Figure 11 As shown, processor P i With P i-1 The iteration calculation can be completed simply by obtaining the row and column coordinates corresponding to the "1" element marked in red in the figure. Based on the sparsity of the parity-check matrix, i.e., the proportion of non-zero elements in each column is extremely low, this embodiment proposes a storage optimization strategy. This storage optimization strategy only stores the position information of non-zero elements in the corresponding base matrix of the parity-check matrix in the matrix storage module, thereby significantly improving storage efficiency while ensuring decoding correctness, and improving the timing performance of index access due to the reduction in data volume. Taking the (5,3(2),5)SC-LDPC code as an example, the local structure of its parity-check matrix is ​​as follows Figure 2As shown, it can be observed that starting from column 6, the matrix exhibits a clear periodicity: the effective regions corresponding to columns 6–9 (i.e., the submatrix containing non-zero elements) are completely repeated in columns 10–13. Therefore, storing only the non-zero element positions of the first nine columns is sufficient to support arbitrary code length SC-LDPC decoding based on this structure. Specifically, each column corresponds to an independent parity check. In this architecture, the processor can be modeled as a ten-state machine: state 0 indicates that the processor is idle (the data to be processed has not yet arrived), and states 1 to 9 correspond to the processor processing nine different parity checks, respectively.

[0044] During decoding, all processors perform the same computational operations in each computation cycle. From a parallel computing perspective, the optimal implementation is to configure a dedicated computing unit for each processor, forming a fully parallel pipeline of "data fetch-computation-write-back," thereby achieving the lowest decoding latency. However, the hardware resource consumption of this parallel scheme increases linearly with the number of processors, making it difficult to promote in resource-constrained practical applications. For resource-constrained scenarios, a time-division multiplexing strategy for computing modules can be adopted. For example... Figure 12 As shown, this embodiment reduces the number of computing groups, allowing multiple processors to share the same computing module and reducing resource overhead through serial scheduling. This solution requires a centralized controller to coordinate the sequential access of each processor to the shared computing module, thereby optimizing resource efficiency.

[0045] Understandably, in conventional distributed storage structures, storage units of different processors need to be instantiated independently and cannot share underlying storage resources, leading to significant resource waste. To address this issue, this embodiment proposes an aggregated storage architecture. By leveraging the time-sharing nature of processors under serial computing scheduling, which eliminates the need for simultaneous storage access, storage resources are integrated at the physical layer, thereby improving storage resource utilization. After aggregated storage, an address mapping mechanism maps "logical access" to "physical address." Specifically, the address mapping formula can be expressed as follows: ; In the formula, ADDR offset This represents the memory value stored by the logical address, as indicated by the CPU. offset This indicates the offset caused by the memory order.

[0046] In some embodiments, the bit error rate (BER) performance of the decoder designed in this application and the MATLAB simulation results are compared and analyzed under different parameter configurations. The simulation analysis results show that the overall trends of the two are highly consistent, indicating that the decoder designed in this example can correctly implement the algorithm function in hardware. Meanwhile, the BER performance of the FPGA implementation is slightly lower than that of the MATLAB floating-point simulation. This is mainly because the hardware implementation uses fixed-point computation and a parallel pipeline structure, which reduces numerical fluctuations and rounding errors during iteration to a certain extent, thus improving decoding convergence. Therefore, the simulation results verify the correctness and superiority of the FPGA-based SC-LDPC decoding architecture proposed in this embodiment.

[0047] This application also proposes an SC-LDPC code decoding device based on look-ahead pipeline and aggregated memory, the device comprising: The first module is used to obtain the SC-LDPC code to be translated; The second module is used to control each processor to update all variable nodes and all verification nodes corresponding to the SC-LDPC code to be translated based on a look-ahead message update strategy when the control module of the decoder schedules multiple serial processors to perform iterative calculations on the SC-LDPC code to be translated. At the same time, based on the aggregated storage architecture and address mapping mechanism, the module controls multiple processors to share the same calculation module in the decoder in a time-sharing manner. The third module is used to make a hard decision on the final soft information obtained by iterative calculation, and obtain the decoding result corresponding to the SC-LDPC code to be decoded.

[0048] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0049] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0050] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0051] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0052] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0053] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0054] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0055] This application provides an SC-LDPC code decoding method and related equipment based on look-ahead pipeline and aggregated storage. Through the collaborative innovation of look-ahead updates at the algorithm level and aggregated storage at the hardware level, it achieves a simultaneous improvement in decoding convergence speed and hardware resource utilization efficiency without significantly increasing hardware complexity or even reducing resource consumption.

[0056] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0057] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0058] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0059] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0060] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0062] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0063] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0064] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0065] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for decoding SC-LDPC codes based on look-ahead pipelined and aggregated storage, characterized in that, The method includes the following steps: Obtain the SC-LDPC code to be translated; When the control module of the decoder schedules multiple serial processors to perform iterative calculations on the SC-LDPC code to be translated, it controls each processor to update all variable nodes and all check nodes corresponding to the SC-LDPC code to be translated based on a look-ahead message update strategy. At the same time, based on the aggregated storage architecture and address mapping mechanism, it controls multiple processors to share the same calculation module in the decoder in a time-sharing manner. Hard decision is made on the final soft information obtained by iterative calculation to obtain the decoding result corresponding to the SC-LDPC code to be decoded.

2. The method according to claim 1, characterized in that, The update of all variable nodes and all check nodes corresponding to the SC-LDPC code to be translated based on the look-ahead message update strategy includes: Update all variable nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm or the variable node look-ahead pipelined BP decoding algorithm. The look-ahead pipelined backpropagation (BP) decoding algorithm is used to update all check nodes corresponding to the SC-LDPC code to be decoded.

3. The method according to claim 2, characterized in that, The update of all check nodes corresponding to the SC-LDPC code to be decoded based on the look-ahead pipelined BP decoding algorithm includes: Obtain the first received information of the associated variable node corresponding to the current verification node and the first target information updated by the previous processor within the current iteration cycle; The current verification node is updated based on the first received information and the first target information.

4. The method according to claim 2, characterized in that, The update of all variable nodes corresponding to the SC-LDPC code to be decoded, based on the look-ahead pipelined BP decoding algorithm or the variable node look-ahead pipelined BP decoding algorithm, includes: Obtain the second received information of the verification node associated with the current variable node and the second target information updated by the previous processor in the current iteration cycle; The current variable node is updated based on the second received information and the second target information.

5. The method according to claim 1, characterized in that, The decoder includes an input buffer module, a control module, a matrix storage module, a data storage module, a calculation module, a hard decision module, and an output buffer module; The input caching module is used to temporarily cache the input SC-LDPC codes to be translated; The control module is used to generate control signals during the decoding process, and coordinate the working states of the input buffer module, the matrix storage module, the data storage module, the calculation module, the hard decision module, and the output buffer module according to the control signals. The matrix storage module is used to store the verification matrix of the SC-LDPC code to be translated; The data storage module is used to store all received information transmitted through the channel and intermediate variables generated during the decoding process. The calculation module is used to execute the update, storage, and transmission processes of all variable nodes and verification nodes; The hard decision module is used to make hard decisions on the final soft information; The output buffer module is used to buffer the decoding results of the SC-LDPC code to be decoded.

6. The method according to claim 5, characterized in that, The matrix storage module is used to store the position information of the non-zero elements of the check matrix corresponding to the SC-LDPC code to be translated.

7. An SC-LDPC code decoding device based on look-ahead pipeline and aggregated storage, characterized in that, The device includes: The first module is used to obtain the SC-LDPC code to be translated; The second module is used to control each processor to update all variable nodes and all check nodes corresponding to the SC-LDPC code to be translated based on a look-ahead message update strategy when the control module of the decoder schedules multiple serial processors to perform iterative calculations on the SC-LDPC code to be translated. At the same time, based on the aggregated storage architecture and address mapping mechanism, the multiple processors are controlled to share the same calculation module in the decoder in a time-sharing manner. The third module is used to make a hard decision on the final soft information obtained by iterative calculation, so as to obtain the decoding result corresponding to the SC-LDPC code to be decoded.

8. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

Images