Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. According to an embodiment, the semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; an epitaxial layer positioned on the first surface of the substrate and including a gate trench, the epitaxial layer having a first conductivity type; a gate electrode positioned within the gate trench; a gate insulating layer positioned between the epitaxial layer and the gate electrode; a source electrode positioned on the epitaxial layer; a well region positioned on one side of the gate electrode between the epitaxial layer and the source electrode and having a second conductivity type different from the first conductivity type; a first deep well region positioned on the other side of the gate electrode between the epitaxial layer and the source electrode and having the second conductivity type; a shield pattern positioned between the epitaxial layer and the first deep well region and overlapping the gate electrode; and a drain electrode positioned on the second surface of the substrate; wherein a lower surface of the shield pattern includes a convexly curved surface toward the drain electrode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] In modern society, semiconductor devices are closely related to our daily lives. In particular, the importance of power semiconductor devices, used in various fields such as transportation (e.g., electric vehicles, railways, and trams), renewable energy systems (e.g., solar and wind power), and mobile devices, is gradually increasing. Power semiconductor devices are semiconductor devices used to handle high voltages or large currents and perform functions such as power conversion and control in high-power systems or high-power electronic devices. Power semiconductor devices have the ability to handle high power and durability, allowing them to handle large currents and withstand high voltages. For example, power semiconductor devices can handle voltages of hundreds to thousands of volts and currents of tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power losses. Furthermore, power semiconductor devices can operate stably even in environments such as high temperatures.

[0003] These power semiconductor devices can be classified by material; for example, there are SiC power semiconductor devices and GaN power semiconductor devices. Using SiC or GaN instead of existing silicon wafers (Si wafers) to fabricate power semiconductor devices overcomes the shortcomings of silicon, which is unstable at high temperatures. SiC power semiconductor devices are heat-resistant and have low power loss, making them suitable for electric vehicles and renewable energy systems. GaN power semiconductor devices are expensive but highly efficient in terms of speed, making them suitable for fast charging of mobile devices. Summary of the Invention

[0004] The disclosed embodiments provide a semiconductor device with stable electrical characteristics and improved reliability.

[0005] In an embodiment, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; an epitaxial layer positioned on the first surface of the substrate and including a gate trench, the epitaxial layer having a first conductivity type; a gate electrode positioned within the gate trench; a gate insulating layer positioned between the epitaxial layer and the gate electrode; a source electrode positioned on the epitaxial layer; a well region positioned on a first side of the gate electrode, between the epitaxial layer and the source electrode, and having a second conductivity type different from the first conductivity type; a first deep well region positioned on a second side of the gate electrode opposite to the first side, between the epitaxial layer and the source electrode, and having the second conductivity type and extending a greater distance below the source electrode than the well region; a shielding pattern positioned between the epitaxial layer and the first deep well region, and the shielding pattern overlapping the gate electrode; and a drain electrode positioned on the second surface of the substrate; wherein the lower surface of the shielding pattern includes a convex curved surface convex toward the drain electrode.

[0006] According to an embodiment, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; an epitaxial layer positioned on the first surface of the substrate, including a gate trench and having a first conductivity type; a gate electrode positioned within the gate trench; a gate insulating layer positioned between the epitaxial layer and the gate electrode; a source electrode positioned on the epitaxial layer; a well region positioned on a first side of the gate electrode, located between the epitaxial layer and the source electrode, and having a second conductivity type different from the first conductivity type; a first deep well region positioned on a second side of the gate electrode opposite to the first side and located between the epitaxial layer and the source electrode, the first deep well region having the second conductivity type; and a second deep well region positioned on the epitaxial layer. The second deep well region has the second conductivity type and is located on a first side of the well region between the source electrode and the source electrode; a first doped layer, the first doped layer being positioned between the well region and the source electrode, the first doped layer having the first conductivity type; a second doped layer, the second doped layer being positioned between the first deep well region and the source electrode, the second doped layer having the second conductivity type; a third doped layer, the third doped layer being positioned between the second deep well region and the source electrode; a shielding pattern, the shielding pattern being positioned between the epitaxial layer and the first deep well region, the shielding pattern having the second conductivity type; and a drain electrode, the drain electrode being positioned on a second surface of the substrate; wherein the width of the shielding pattern is greater than or equal to the width of the first deep well region, and the doping concentration of the shielding pattern is greater than or equal to the doping concentration of the first deep well region.

[0007] According to an embodiment, a semiconductor device includes: a substrate including an active region in which a plurality of cells are positioned and a peripheral region surrounding at least a portion of the active region; and a gate frame positioned in the peripheral region, including a first portion and a second portion extending in a first direction and arranged to be spaced apart in a second direction intersecting the first direction; the plurality of cells being positioned between the first portion and the second portion of the gate frame; wherein each of the plurality of cells includes: an epitaxial layer including a gate trench positioned on a first surface of the substrate and extending in the second direction, the epitaxial layer having a first conductivity type; a gate electrode positioned within the gate trench and electrically connected to the gate frame; and a gate insulating layer positioned within the gate trench. Between the epitaxial layer and the gate electrode; a source electrode positioned on the epitaxial layer; a well region positioned on a first side of the gate electrode along the first direction and between the epitaxial layer and the source electrode, the well region having a second conductivity type different from the first conductivity type; a first deep well region positioned on a second side of the gate electrode along the first direction opposite to the first side and between the epitaxial layer and the source electrode, the first deep well region having the second conductivity type; a shielding pattern positioned between the epitaxial layer and the first deep well region, extending in the second direction and overlapping the gate electrode; and a drain electrode positioned on a second surface of the substrate opposite to the first surface, wherein the lower surface of the shielding pattern includes a convex curved surface convex toward the drain electrode.

[0008] According to an embodiment, a method for manufacturing a semiconductor device includes the following steps: forming an epitaxial layer having a first conductivity type on a first surface of a substrate; forming a second preliminary shielding layer having a second conductivity type different from the first conductivity type within the epitaxial layer using a tunneling ion implantation process; forming a first preliminary shielding layer overlapping the second preliminary shielding layer and having the second conductivity type within the epitaxial layer; forming a first deep well region overlapping the first preliminary shielding layer and having the second conductivity type within the epitaxial layer; forming a preliminary well region having the second conductivity type on at least one side of the first deep well region; forming a gate trench by patterning the preliminary well region and the first deep well region to form a well region; forming a first shielding layer and a second shielding layer by patterning the first preliminary shielding layer and the second preliminary shielding layer; forming a gate insulating layer within the gate trench; forming a gate electrode filling the gate trench; forming a source electrode above the well region; and including the step of forming a drain electrode on a second surface opposite to the first surface.

[0009] The lower surface of the second shielding layer may include a convex curved surface facing the first surface of the substrate.

[0010] The doping concentration of the first deep well region can be greater than the doping concentration of the well region.

[0011] The thickness of the first deep well region along the vertical direction can be greater than the thickness of the well region along the vertical direction.

[0012] The doping concentration of the second shielding layer can be greater than or equal to the doping concentration of the first deep well region.

[0013] After forming the preliminary well region described above, the method may further include: forming a first doped layer having the first conductivity type in the preliminary well region described above, and forming a second doped layer having the second conductivity type in the first deep well region described above.

[0014] After forming the first deep well region, the method further includes: forming a second deep well region having the second conductivity type within the epitaxial layer, wherein the thickness of the second deep well region may be greater than the thickness of the well region.

[0015] The second deep well region can be positioned to be spaced apart from the first deep well region.

[0016] The doping concentration in the second deep well region can be greater than the doping concentration in the well region.

[0017] The shielding pattern may include: a first shielding layer positioned below the gate insulating layer and having the second conductivity type; and a second shielding layer positioned below the first deep well region and having the second conductivity type, wherein the lower surface of the second shielding layer may include a convex curved surface toward the drain electrode.

[0018] The first shielding layer may protrude from the lower surface of the gate insulating layer toward the first surface of the substrate.

[0019] The width of the first shielding layer is smaller than the width of the gate trench.

[0020] A portion of the first shielding layer may overlap with the epitaxial layer, and the remainder of the first shielding layer may overlap with the second shielding layer.

[0021] The first shielding layer may overlap with the gate electrode or may not overlap with the first deep well region.

[0022] The semiconductor device further includes a dummy pattern positioned between the epitaxial layer and the gate insulating layer, wherein the dummy pattern may be positioned spaced apart from the first shielding layer.

[0023] The dummy pattern may include the same material as the gate insulating layer.

[0024] According to the embodiments, the reliability of semiconductor devices can be improved. Attached Figure Description

[0025] Figure 1 This is a top view showing a semiconductor device according to an embodiment.

[0026] Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0027] Figure 3 yes Figure 2 Enlarged cross-sectional view of region S1.

[0028] Figures 4 to 16 This illustrates a semiconductor device according to some embodiments. Figure 2 The cross-sectional view corresponding to region S1.

[0029] Figure 17 This is a top view showing a semiconductor device according to some embodiments.

[0030] Figures 18 to 30 This illustrates a method for manufacturing a semiconductor device according to an embodiment. Figure 1 The cross-sectional view corresponding to A-A'.

[0031] Figures 31 to 35 It shows the method of manufacturing according to Figures 14 to 16 The method of the semiconductor device in the embodiment of the Figure 1 The cross-sectional view corresponding to A-A'. Detailed Implementation

[0032] In the following description, various embodiments will be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement the invention. The invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0033] To illustrate the invention clearly and concisely, certain parts may be omitted, and throughout the specification, the same reference numerals are used for identical or similar components.

[0034] Furthermore, for ease of explanation, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrary, so the invention is not necessarily limited to what is shown. To clearly illustrate the various layers and regions in the drawings, the thicknesses are enlarged as shown. And in the drawings, for ease of explanation, the thicknesses of some layers and regions are exaggerated.

[0035] It will be understood that when an element is referred to as being "connected" or "bonded" to another element or "on" another element, it is able to be directly connected or bonded to or on another element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly connected" or "directly bonded" to another element or referred to as being "in contact" with another element or "in contact with" another element (or any form of the word "in contact"), there are no intermediate elements at the point of contact.

[0036] For example, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” “top,” “bottom,” “front,” and “back” are used in this document to describe positional relationships, such as those shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms also encompass different orientations of the device.

[0037] In addition, spatial relative terms such as “above” and “below” as used in this article have their general broad meanings—for example, element A can be above element B even if there is no overlap between the two elements when looking down (just as something in the sky is usually above something on the ground, even if it is not directly above).

[0038] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that, unless the context otherwise indicates, the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term “composed of” indicates that the component is formed solely by the listed (one or more) elements.

[0039] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. Unless the context otherwise indicates, these terms are used only to distinguish one element, component, region, layer, or portion from another, for example, as a naming convention. Therefore, without departing from the teachings of the invention, a first element, component, region, layer, or portion discussed in one part of the specification below may be referred to as a second element, component, region, layer, or portion in another part of the specification or in the claims. Furthermore, in some cases, even if the terminology is not described using "first," "second," etc., in the specification, it may still be referred to as "first" or "second" in the claims in order to distinguish different claimed elements from each other.

[0040] An item, layer, or portion of an item or layer is described as extending "longitudinally" in a particular direction, having a length in that direction and a width perpendicular to that direction, wherein the length is greater than the width.

[0041] Items described in the singular herein may be set to multiples, as can be seen, for example, in the accompanying figures. Therefore, unless the context otherwise indicates, a description of a single item set to multiples should be understood to apply to the remaining multiple items.

[0042] Terms such as “about” or “approximately” can reflect quantities, dimensions, orientations, or layouts that vary only in a small relative manner and / or in a way that does not significantly alter the operation, function, or structure of certain components. For example, a range of “about 0.1 to about 1” can encompass a range such as from 0% to 1% deviation of about 0.1 to 0% to 1% deviation, or a specific value that can deviate by as much as plus or minus 1%, especially if such deviation maintains the same effect as the listed range.

[0043] When referring to orientation, layout, location, shape, size, composition, quantity, or other measures, terms such as “identical,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean exactly identical orientations, layouts, locations, shapes, sizes, compositions, quantities, or other measures, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, compositions, quantities, or other measures within the range of typical variations that may arise from conventional manufacturing processes. Unless otherwise indicated by context or other statements, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially planar” may be exactly identical, equal, or planar, or may be identical, equal, or planar within the range of acceptable variations that may occur, for example, due to manufacturing processes.

[0044] Additionally, throughout the specification, "top view" refers to the target portion viewed from above, and "section view" or "section" refers to the target portion viewed from the side in a vertically cut section.

[0045] In the following text, reference will be made to Figures 1 to 3 A semiconductor device according to an embodiment is described.

[0046] Figure 1 This is a top view showing a semiconductor device according to an embodiment.

[0047] refer to Figures 1 to 3 The substrate 110 of the semiconductor device according to the embodiment may include an active region AR and a peripheral region PERI surrounding at least a portion of the active region AR.

[0048] An active region (AR) can be a region in which a semiconductor device, according to an embodiment, is driven. In an active region (AR), multiple units comprising semiconductor devices such as transistors and diodes can be located, and electrodes for supplying signals or power to the units can also be located therein.

[0049] In this embodiment, the multiple units located in the active region AR may include transistor and diode elements. For example, the multiple units of the semiconductor device according to the embodiment may include n-type field-effect transistors (n-FETs) and diode devices. However, the example embodiment is not limited thereto, and the multiple units may include p-type field-effect transistors.

[0050] The active region AR of the semiconductor device according to the embodiment may include a transistor region TA in which transistors are implemented and a diode region DA in which diode elements are implemented. For example, the active region AR may include one or more transistor regions TA and one or more diode regions DA arranged, for example, along a particular direction (e.g., the X direction).

[0051] The transistor region TA can be the region where the transistor is located. For example, the source electrode (see...). Figure 2 173), gate electrode 150, well region (see ...). Figure 2 133 in the middle) and drain electrode (see 13 ... Figure 2 175 in the diagram can be located in the transistor region TA. The well region (see...) Figure 2 133 in the diagram can be used as the source electrode (see [reference]) based on the signal from the gate electrode 150. Figure 2 173 in the middle) and drain electrode (see 173 ... Figure 2 A channel providing an electrical connection path between 175 (in the diagram). Source electrode (see...) Figure 2 173), gate electrode 150, well region (see ...). Figure 2 133 in the middle) and drain electrode (see 13 ... Figure 2 (175) can be used to form transistors.

[0052] The diode region DA can be the area where the diode element is located. For example, a shielding pattern (see...). Figure 2 (300 in the middle) and epitaxial layer (see 300) and epitaxial layer (see Figure 2 131 in the diagram can be positioned in the diode region DA, and the shielding pattern (see [reference]) can be used. Figure 2 (300 in the middle) and epitaxial layer (see ... Figure 2 The interface between 131 in (see 131) Figure 3 The IF in the diode can form a PN junction, thereby configuring the diode element.

[0053] In an embodiment, the transistor region TA and the diode region DA may be defined by gate trenches GT. For example, the semiconductor device according to an embodiment may include a plurality of gate trenches GT extending in a second direction (Y direction) and spaced apart from each other along a first direction (X direction), and the transistor region TA and the diode region DA may be defined by the plurality of gate trenches GT and arranged alternately along the first direction (X direction). Here, the second direction (Y direction) may be a direction intersecting the first direction (X direction). For example, the second direction (Y direction) may be a direction orthogonal to the first direction (X direction).

[0054] The transistor region TA and the diode region DA can be positioned between the first portion 211 and the second portion 212 of the gate frame 210, as will be described later. Additionally, the transistor region TA and the diode region DA can be positioned between the second portion 212 and the third portion 213 of the gate frame 210, as will be described later.

[0055] The transistor region TA and the diode region DA may extend in a second direction (Y direction), e.g., longitudinally. Each transistor region TA and diode region DA may extend in the second direction (Y direction) between a first portion 211 and a second portion 212 of the gate frame 210, as will be described later. In this case, the length of the transistor region TA along the second direction (Y direction) may be greater than the length of the transistor region TA along the first direction (X direction), but the example embodiment is not limited thereto. Similarly, the length of the diode region DA along the second direction (Y direction) may be greater than the length of the diode region DA along the first direction (X direction), but the example embodiment is not limited thereto. The transistor region TA and the diode region DA may contact the gate frame 210, as will be described later.

[0056] The peripheral region PERI can surround at least a portion of the active region AR. For example... Figure 1 As shown, when two active regions AR are included on substrate 110, the peripheral region PERI may surround at least a portion of each active region AR. In the embodiment, the peripheral region PERI is shown as having a generally "E" shape, thus surrounding the three corners of each active region AR, but the example embodiment is not limited thereto. For example, the peripheral region PERI may surround the entire perimeter of the active region AR, or it may only surround a portion of the entire perimeter.

[0057] The peripheral region (PERI) can accommodate various configurations for supplying power or electrical signals to components in the active region (AR). For example, the gate frame 210 that interconnects components in the active region (AR) can be located in the peripheral region (PERI).

[0058] According to an embodiment, the gate frame 210 of the semiconductor device may surround at least a portion of the active region AR. For example, the gate frame 210 may include a first portion 211, a second portion 212, and a third portion 213 arranged spaced apart from each other along a first direction (X direction) and a second direction (Y direction), and may include a fourth portion 214 extending along the second direction (Y direction) and electrically connected to the first portions 211 to the third portions 213. In an embodiment, the active region AR may be positioned between the first portion 211 and the second portion 212. The fourth portion 214 may be positioned on one side of the active region AR located between the first portion 211 and the second portion 212. For example, at least a portion of the active region AR may be surrounded by the first portion 211, the second portion 212, and the fourth portion 214. The active region AR may be positioned between the second portion 212 and the third portion 213. The fourth portion 214 may be positioned on one side of the active region AR located between the second portion 212 and the third portion 213. That is, at least a portion of the active region AR can be surrounded by the second portion 212, the third portion 213, and the fourth portion 214. In an embodiment, the gate frame 210 can define the active region AR. For example, the first portion 211 and the second portion 212 of the gate frame 210 can define the transistor region TA and the diode region DA.

[0059] In this embodiment, the gate frame 210 may be electrically connected to the active region AR. For example, the gate frame 210 may be electrically connected to the gate electrode 150 of the active region AR. The gate frame 210 may be positioned on or in the same layer as the gate electrode 150, but the example embodiment is not limited thereto. The gate frame 210 may comprise the same material as the gate electrode 150 and the gate frame 210 may be integrally formed with the gate electrode 150 (e.g., by forming it during the same process with the same material, so that no grain boundary is formed between the gate electrode 150 and the gate frame 210), but the example embodiment is not limited thereto.

[0060] exist Figure 1 In the diagram, three transistor regions TA and two diode regions DA are shown arranged alternately along a first direction (X direction) in each active region AR, but the number and location of transistor regions TA and diode regions DA in the active regions AR included on each substrate 110 are not limited thereto. For example, only one or two transistor regions TA and only one diode region DA may be located in one active region AR on the substrate 110, or four or more transistor regions TA and diode regions DA may be arranged in various ways.

[0061] exist Figure 1For ease of illustration, this is depicted as if there were a boundary between each active region AR and the peripheral region PERI, but there may not be a physical boundary that clearly separates the active region AR and the peripheral region PERI. For example, for each active region AR, the peripheral region PERI and the active region AR may include some overlapping areas near the boundary.

[0062] Further references will be made below. Figure 2 and Figure 3 Describes a plurality of units of a semiconductor device according to an embodiment.

[0063] Figure 2 It is along Figure 1 The cross-sectional view taken from line AA. Figure 3 yes Figure 2 Enlarged cross-sectional view of region S1.

[0064] refer to Figure 2 and Figure 3 According to an embodiment, a plurality of units of a semiconductor device include a substrate 110, an epitaxial layer 131 positioned on a first surface of the substrate 110 and including a gate trench GT, a gate electrode 150 positioned within the gate trench GT, a gate insulating layer 140 positioned between the epitaxial layer 131 and the gate electrode 150, a source electrode 173 positioned on the epitaxial layer 131, a well region 133 positioned between the epitaxial layer 131 and the source electrode 173, a first deep well region 161 positioned between the epitaxial layer 131 and the source electrode 173, a shielding pattern 300 positioned between the epitaxial layer 131 and the first deep well region and overlapping with the gate electrode 150, and a drain electrode 175 positioned on a second surface 110b of the substrate 110.

[0065] Substrate 110 may be a semiconductor substrate including SiC. For example, substrate 110 may be made of 4H SiC substrate. In some cases, substrate 110 may be made of 3C SiC substrate, 6H SiC substrate, etc. Substrate 110 may have a first conductivity type. Substrate 110 may be heavily doped with the first conductivity type. The first conductivity type may be n-type, but is not limited thereto. The resistivity of substrate 110 may be greater than or equal to about 0.005 Ωcm and less than or equal to about 0.035 Ωcm (e.g., in the range from 0.005 Ωcm to 0.035 Ωcm). The thickness of substrate 110 may be greater than or equal to about 10 μm and less than or equal to about 700 μm (e.g., in the range from 10 μm to 700 μm). The material, doping type, doping concentration, resistivity, thickness, etc. of substrate 110 are not limited thereto and may be varied in various ways.

[0066] Substrate 110 may include a first surface 110a and a second surface 110b opposite to each other. The first surface 110a of substrate 110 may refer to the upper surface of substrate 110, and the second surface 110b of substrate 110 may refer to the lower surface of substrate 110. Epitaxial layer 131 may be positioned on the first surface 110a of substrate 110. The lower surface of epitaxial layer 131 may be in contact with the first surface 110a of substrate 110 (e.g., may be directly connected to the first surface 110a of substrate 110). However, the exemplary embodiment is not limited thereto, and another layer may be additionally positioned between substrate 110 and epitaxial layer 131. Epitaxial layer 131 may be an epitaxial layer formed on substrate 110 using an epitaxial growth method. Epitaxial layer 131 may include SiC. For example, epitaxial layer 131 may include 4HSiC. As described herein, certain layers or regions are described as being in contact with each other, even though they may have a smooth transition from one layer to the next at the microscopic level. This could occur with a second layer formed on top of the first layer using epitaxial growth, or with a second layer that differs from the first layer due to different doping levels within each layer (e.g., where the doping concentration at the interface between layers is gradual rather than abrupt). It should be understood that such layers, described as being in “contact” with each other, are directly connected or adjacent to each other, with no other layer in between at the interface between the two layers. Other uses of “contact” could refer to different layers formed from different substrate materials and having grain boundaries therebetween.

[0067] In an embodiment, the crystal planes of the material comprising the epitaxial layer 131 may be formed at a predetermined angle relative to the first surface 110a of the substrate 110, for example, not parallel to the first surface 110a. For example, the crystal planes of the material comprising the epitaxial layer 131 may be tilted from the first surface 110a of the substrate 110 by approximately 4°. For example, when the epitaxial layer 131 comprises SiC, the (0001) crystal plane of SiC may be tilted from the first surface 110a of the substrate 110 by approximately 4°. This may be due to process characteristics used to prevent lattice distortions caused by dislocations, etc., within the epitaxial layer 131 during the process of forming the epitaxial layer 131 using an epitaxial growth method.

[0068] Epitaxial layer 131 may have a first conductivity type. Epitaxial layer 131 may be lightly doped with the first conductivity type. The first conductivity type may be n-type, but the example embodiment is not limited thereto. The doping concentration of epitaxial layer 131 may be lower than the doping concentration of substrate 110. The doping concentration (e.g., average doping concentration) of epitaxial layer 131 may be approximately 1 × 10⁻⁶. 15 cm -3 Above and approximately 1×10 17 cm -3 The following (for example, from 1×10) 15 cm -3 Up to 1×1017 cm -3 Within the range of ( ). The doping concentration of a layer or region refers to the concentration of dopant within a specific volume of that layer or region, and may refer to, for example, the average doping concentration of that volume, where the dopant may have a doping gradient within that volume. Unless otherwise clearly indicated, a layer, region, or other item described as having a doping concentration (or "having a doped concentration") has that doping concentration relative to the entire layer, region, or item. The boundary between a region or layer having a particular doping concentration and another region or layer not having doping concentration may be a location where the doping concentration of a small-volume slice of a doped region or layer drops below a specific value. Additionally, in semiconductor technology, if a semiconductor comprises both p-type and n-type impurities, the conductivity type of the semiconductor will be determined by which type of impurity has a greater concentration. Therefore, if a semiconductor has both p-type and n-type impurities, the net conductivity type will be determined by the concentration of the dominant impurity. As used herein, a semiconductor region of "first conductivity type" means that the dominant impurity in the semiconductor region is a first conductivity type impurity. The thickness of the epitaxial layer 131 (e.g., the maximum thickness in the vertical Z direction) may be greater than approximately 1 μm and less than approximately 13 μm. The material, doping type, doping concentration, thickness, etc. of the epitaxial layer 131 are not limited to these, and can be changed in various ways.

[0069] The epitaxial layer 131 may include a gate trench GT. The gate trench GT may be formed to have a predetermined depth on the upper surface (e.g., below) of the epitaxial layer 131. Figure 2 and Figure 3 As shown, the gate trench GT can be formed in a generally U-shape in cross-section. The gate trench GT may include a bottom surface and inner sidewalls extending from the bottom surface. The edge of the gate trench GT where the bottom surface and the inner sidewall meet may include, but is not limited to, a curved surface. Figure 2 and Figure 3 In this example, the angle of the inner sidewall of the gate trench GT relative to the bottom surface is depicted as vertical (e.g., 90 degrees), but the example embodiment is not limited to this.

[0070] The gate trench GT may extend in a second direction (Y direction) (e.g., longitudinally). In an embodiment, the gate trench GT may extend in the second direction (Y direction) between a first portion 211 and a second portion 212 of the gate frame 210, and the gate trench GT may extend between a second portion 212 and a third portion 213 of the gate frame 210 (e.g., longitudinally). The gate trench GT may contact the first portion 211 and the second portion 212 of the gate frame 210 and may extend upward to directly connect to the first portion 211 and the second portion 212 of the gate frame 210. The gate trench GT may contact the second portion 212 and the third portion 213 of the gate frame 210 and may extend upward to directly connect to the second portion 212 and the third portion 213 of the gate frame 210. The semiconductor device according to the embodiment may include a plurality of gate trenches GT extending in the second direction (Y direction) and spaced apart from each other in a first direction (X direction). Each of the plurality of gate trenches GT may extend in a direction parallel to each other. The length of each of the plurality of gate trenches GT along the second direction (Y direction) may be greater than the distance between the plurality of adjacent gate trenches GT along the first direction (X direction) along the first direction (X direction), but the example embodiment is not limited thereto.

[0071] In an embodiment, each of the plurality of gate trenches GT may include a bottom surface and an inner sidewall extending from the bottom surface. The bottom surface of each of the plurality of gate trenches GT may be defined by an epitaxial layer 131 and a shielding pattern 300 (described later). The inner sidewalls of each of the plurality of gate trenches GT along a first direction (X direction) or multiple inner sidewalls may be defined by an epitaxial layer 131, a well region 133 (described later), a first deep well region 161, a first doped layer 181, a second doped layer 182, and a shielding pattern 300. The inner sidewalls of each of the plurality of gate trenches GT along a second direction (Y direction) may be defined by a gate frame 210.

[0072] The gate electrode 150 may be located within the gate trench GT. The gate electrode 150 may be spaced apart from the epitaxial layer 131. The gate electrode 150 may be spaced apart from the epitaxial layer 131 at a substantially constant interval. However, the exemplary embodiment is not limited thereto, and the distance between the gate electrode 150 and the epitaxial layer 131 may vary depending on the position on the gate electrode 150.

[0073] The gate electrode 150 may include a side 150_S1 (e.g., a first side) along a first direction (X direction) and another side 150_S2 (e.g., a second side) opposite to side 150_S1. Side 150_S1 of the gate electrode 150 may be the side of the gate electrode 150 located in the transistor region TA along the first direction (X direction). Side 150_S1 of the gate electrode 150 may be the side of the gate electrode 150 facing the well region 133 along the first direction (X direction). The other side 150_S2 of the gate electrode 150 may be the side of the gate electrode 150 located in the diode region DA of the semiconductor device according to the embodiment along the first direction (X direction). For example, the other side 150_S2 of the gate electrode 150 may be the side of the gate electrode 150 facing the first deep well region 161 along the first direction (X direction).

[0074] In the following text, for ease of explanation of this embodiment, the side of the gate electrode 150 located in the transistor region TA along the first direction (X direction) is referred to as the transistor region side of the gate electrode 150 (i.e., one side 150_S1 of the gate electrode 150), and the side of the gate electrode 150 located in the diode region DA along the first direction (X direction) is referred to as the diode region side of the gate electrode 150 (i.e., the other side 150_S2 of the gate electrode 150).

[0075] The gate electrode 150 may have a cross-sectional shape similar to that of the gate trench GT. The lower surface and side surfaces of the gate electrode 150 (e.g., side surfaces corresponding to one side 150_S1 and the other side 150_S2) may have a generally U-shaped cross-section along the shape of the gate trench GT. The lower surface of the gate electrode 150 may face the bottom surface of the gate trench GT. The side surfaces of the gate electrode 150 may face the inner sidewall of the gate trench GT.

[0076] The gate electrode 150 may extend in a second direction (Y direction), e.g., longitudinally. In an embodiment, the gate electrode 150 extends in the second direction (Y direction) between a first portion 211 and a second portion 212 of the gate frame 210 and between a second portion 212 and a third portion 213 of the gate frame 210. The length of the gate electrode 150 in the second direction (Y direction) may be substantially equal to the distance between the first portion 211 and the second portion 212. The gate electrode 150 may contact the first portion 211 and the second portion 212 of the gate frame 210 or may be integrally formed with the first portion 211 and the second portion 212 of the gate frame 210 to be directly connected to the first portion 211 and the second portion 212. Alternatively or additionally, the gate electrode 150 may contact the second portion 212 and the third portion 213 of the gate frame 210 or may be integrally formed with the second portion 212 and the third portion 213 of the gate frame 210. In one embodiment, the gate electrode 150 may include the same material as the gate frame 210 and may be integrally formed therewith, but the example embodiment is not limited thereto.

[0077] The semiconductor device according to an embodiment may include a plurality of gate electrodes 150 positioned within a plurality of gate trenches GT. Each of the plurality of gate electrodes 150 may extend in a direction parallel to the plurality of gate trenches GT. The plurality of gate electrodes 150 may be arranged spaced apart from each other along a first direction (X direction). The length of each of the plurality of gate electrodes 150 along a second direction (Y direction) may be greater than the distance between a plurality of adjacent gate electrodes 150 along the first direction (X direction), but the exemplary embodiment is not limited thereto.

[0078] The gate electrode 150 may include a conductive material. For example, the gate electrode 150 may include or may be polycrystalline silicon doped with impurities. As another example, the gate electrode 150 may include or may be a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a combination thereof. The gate electrode 150 may be formed of a single layer or multiple layers.

[0079] A gate insulating layer 140 may be positioned between the epitaxial layer 131 and the gate electrode 150. The gate insulating layer 140 may be positioned below the gate electrode 150 and may cover the lower surface of the gate electrode 150. The gate insulating layer 140 may be positioned on the bottom surface and inner sidewalls of the gate trench GT. The gate insulating layer 140 may surround at least a portion of the gate electrode 150. For example, the gate insulating layer 140 may be positioned on the lower surface of the gate electrode 150, on one side 150_S1, and on the other side 150_S2. Therefore, the gate electrode 150 can be insulated from the epitaxial layer 131 through the gate insulating layer 140.

[0080] In one embodiment, the gate insulating layer 140 may be positioned between the shielding pattern 300 and the gate electrode 150, as will be described in further detail later. Additionally, the gate insulating layer 140 may be positioned between the well region 133 (described later) and the gate electrode 150, between the first deep well region 161 (described later) and the gate electrode 150, between the first doped layer 181 (described later) and the gate electrode 150, and between the second doped layer 182 (described later) and the gate electrode 150.

[0081] In an embodiment, the gate insulating layer 140 may include a side 140_S1 along a first direction (X direction) and an opposite side 140_S2. The side 140_S1 of the gate insulating layer 140 may refer to the side of the gate insulating layer 140 located in the transistor region TA of the semiconductor device according to the embodiment, along the first direction (X direction). The side 140_S1 of the gate insulating layer 140 may be the side of the gate insulating layer 140 facing the well region 133 (described later) along the first direction (X direction). The opposite side 140_S2 of the gate insulating layer 140 may refer to the side of the gate insulating layer 140 located in the diode region DA of the semiconductor device according to the embodiment, along the first direction (X direction). The opposite side 140_S2 of the gate insulating layer 140 may be the side of the gate insulating layer 140 facing the first deep well region 161 along the first direction (X direction).

[0082] The gate insulating layer 140 of the semiconductor device according to the embodiment may include a horizontal portion 140_H positioned between the epitaxial layer 131 and the gate electrode 150, and a vertical portion 140_V positioned on one side 150_S1 and the other side 150_S2 of the gate electrode 150.

[0083] The horizontal portion 140_H can be positioned between the epitaxial layer 131 and the gate electrode 150. Additionally, the horizontal portion 140_H can be positioned between the shielding pattern 300 and the gate electrode 150, as will be described later. In an embodiment, when viewed from a direction parallel to the longitudinal extension direction (e.g., the Y direction) of the gate electrode 150, the horizontal portion 140_H can extend by a greater amount in the horizontal direction (e.g., the X direction) than in the vertical direction (e.g., the Z direction). In an embodiment, the horizontal portion 140_H can have a first thickness TH1 along a third direction (Z direction), where the first thickness TH1 corresponds to the thickness from the bottom surface of the contact epitaxial layer 131 and the shielding pattern 300 to the top surface of the contact gate electrode 150. The first thickness TH1 of the horizontal portion 140_H along the third direction (Z direction) can be constant, but the example embodiment is not limited thereto. For example, the first thickness TH1 of the horizontal portion 140_H along the third direction (Z direction) can gradually decrease or increase from the center of the horizontal portion 140_H (e.g., the center along the X direction) to the opposite edge. See later. Figure 12 and Figure 13 An explanation is provided for this.

[0084] The vertical portion 140_V can be positioned on one side 150_S1 and the other side 150_S2 of the gate electrode 150. The vertical portion 140_V can be positioned between the well region 133 (described later) and the gate electrode 150, and between the first deep well region 161 (described later) and the gate electrode 150. The gate electrode 150 can be electrically insulated from the well region 133 and the first deep well region 161 by the vertical portion 140_V. When viewed from a direction parallel to the longitudinal extension direction (e.g., the Y direction) of the gate electrode 150, the vertical portion 140_V can extend by a greater amount in the vertical direction (e.g., the Z direction) than in the horizontal direction (e.g., the X direction).

[0085] The vertical portion 140_V may have a second thickness TH2 along a first direction (X direction). The second thickness TH2 of the vertical portion 140_V along the first direction (X direction) may be less than the first thickness TH1 of the horizontal portion 140_H along a third direction (Z direction). Therefore, the distance between the gate electrode 150 and the epitaxial layer 131 along the third direction (Z direction) may be greater than the distance between the gate electrode 150 and the well region 133 (described later) along the first direction (X direction). Therefore, at least in part due to the thicker bottom portion compared to the sidewall portion, the electric field formed from the drain electrode 175 and / or the epitaxial layer 131 can be prevented from concentrating on the gate electrode 150, and the breakdown voltage of the semiconductor device according to the embodiment can be improved.

[0086] In this embodiment, the second thickness TH2 of the vertical portion 140_V along the first direction (X direction) can be constant, but the example embodiment is not limited thereto. For example, the second thickness TH2 of the vertical portion 140_V along the first direction (X direction) can gradually decrease or increase from the center of the vertical portion 140_V to the opposite edge.

[0087] The gate insulating layer 140 may include or may be an insulating material. For example, the gate insulating layer 140 may include or may be SiO2. However, the example embodiment is not limited thereto, and the material of the gate insulating layer 140 may be varied in various ways. As another example, the gate insulating layer 140 may include or may be one or more of SiN, SiON, SiC, and SiCN. The gate insulating layer 140 may be formed of a single layer or multiple layers.

[0088] The semiconductor device according to an embodiment may further include a capping layer 142 positioned on a gate electrode 150. The capping layer 142 may cover the upper surface of the gate electrode 150. Additionally, the capping layer 142 may cover at least a portion of the gate insulating layer 140, the first doped layer 181 (described later), and at least a portion of the second doped layer 182 (described later) adjacent to the gate electrode 150. The capping layer 142 may be positioned between the gate electrode 150 and the source electrode 173 (described later). The gate electrode 150 may be insulated from the source electrode 173 by the capping layer 142.

[0089] The thickness of the capping layer 142 in the third direction (Z direction) can gradually decrease from the center of the capping layer 142 to the opposite edge. However, the example embodiment is not limited to this, and the thickness of the capping layer 142 along the third direction (Z direction) can be constant or nearly constant. The thickness of the capping layer 142 (e.g., along the Z direction) can be different from the thickness of the gate insulating layer 140 (e.g., along the Z direction). For example, the thickness of the capping layer 142 can be thicker than the thickness of the gate insulating layer 140. In some cases, the thickness of the capping layer 142 can be similar to the thickness of the gate insulating layer 140.

[0090] The capping layer 142 may include or be formed of an insulating material. For example, the capping layer 142 may include or be formed of one or more of SiO2, SiOP, SiN, and SiON. However, the example embodiment is not limited thereto, and the material of the capping layer 142 may be varied in various ways. The capping layer 142 may be formed of a single layer or multiple layers. The capping layer 142 may include the same material as the gate insulating layer 140 or may include a different material. When the capping layer 142 is made of the same material as the gate insulating layer 140, the boundary between the capping layer 142 and the gate insulating layer 140 may not be clearly distinguishable at the contact points.

[0091] The source electrode 173 can be located on the epitaxial layer 131. The source electrode 173 can be located on the first doped layer 181, the second doped layer 182, and the third doped layer 183, which will be described later.

[0092] The source electrode 173 can be positioned separately from the gate trench GT. For example, the source electrode 173 can be positioned spaced apart from the gate trench GT along a first direction (X direction). The source electrode 173 can also be positioned spaced apart from the gate trench GT along a third direction (Z direction).

[0093] The source electrode 173 may include a conductive material. For example, the source electrode 173 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a combination thereof. For example, the source electrode 173 may be formed of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), or molybdenum (Mo). It can be, but is not limited to, molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The source electrode 173 can be formed of a single layer or multiple layers.

[0094] Well region 133 may be located on epitaxial layer 131. Well region 133 may be located on epitaxial layer 131 located in transistor region TA. Well region 133 may be located between epitaxial layer 131 and source electrode 173. Well region 133 may be located on one side 150_S1 of gate electrode 150. Well region 133 may face gate electrode 150, and gate insulating layer 140 is located between well region 133 and gate electrode 150. Well region 133 may contact one side 140_S1 of gate insulating layer 140. The lower surface of well region 133 may contact epitaxial layer 131. Well region 133 may not be located on the other side 150_S2 of gate electrode 150. Well region 133 may not overlap with first deep well region 161 or shielding pattern 300 in the third direction (Z direction), as will be described later.

[0095] Well region 133 may comprise SiC. For example, well region 133 may comprise 4H SiC. Well region 133 may have a second conductivity type different from the first conductivity type. Well region 133 may be lightly doped with the second conductivity type. The second conductivity type may be p-type, but is not limited thereto. The doping concentration of well region 133 may be approximately 1 × 10⁻⁶. 17 cm -3 Above and approximately 1×10 19 cm -3 The following (for example, from 1×10) 17 cm -3 Up to 1×10 19 cm -3 The thickness of the well region 133 can be greater than approximately 0.3 μm and less than approximately 1.1 μm (e.g., in the range of 0.3 μm to 1.1 μm), but the example embodiment is not limited thereto. The material, doping type, doping concentration, thickness, etc. of the well region 133 are not limited thereto and can be varied in various ways.

[0096] The well region 133 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, the well region 133 may be formed using a random ion implantation process. Alternatively, the well region 133 may be an epitaxial layer formed from the epitaxial layer 131 using an epitaxial growth method.

[0097] The first deep well region 161 may be located on the epitaxial layer 131. The first deep well region 161 may be located on the epitaxial layer 131 located within the diode region DA. The first deep well region 161 may be located between the epitaxial layer 131 and the source electrode 173. The first deep well region 161 may be located on the other side 150_S2 of the gate electrode 150. The first deep well region 161 may face the gate electrode 150, and the gate insulating layer 140 is located between the first deep well region 161 and the gate electrode 150. The lower surface of the first deep well region 161 may contact the shielding pattern 300, which will be described later. The lower surface of the first deep well region 161 may not contact the epitaxial layer 131, but the example embodiment is not limited thereto. The first deep well region 161 may not be located on one side 150_S1 of the gate electrode 150. The first deep well region 161 may not overlap with the well region 133 in the third direction (Z direction).

[0098] The first deep well region 161 may have a predetermined depth. For example, the lower surface of the first deep well region 161 may be at a lower height than the lower surface of the well region 133. The lower surface of the first deep well region 161 may be closer to the first surface 110a of the substrate 110 than the lower surface of the well region 133 is to the first surface 110a of the substrate 110. The distance (e.g., minimum distance) between the lower surface of the first deep well region 161 and the first surface 110a of the substrate 110 may be smaller than the distance (e.g., minimum distance) between the lower surface of the well region 133 and the first surface 110a of the substrate 110. The upper surface of the first deep well region 161 may be at substantially the same height as the upper surface of the well region 133, but the exemplary embodiment is not limited thereto. The thickness (e.g., maximum thickness) of the first deep well region 161 along the third direction (Z direction) may be greater than the thickness of the well region 133 along the third direction (Z direction). Therefore, the breakdown voltage of the transistor can be prevented from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. The first deep well region 161 may overlap with the well region 133 in the first direction (X direction).

[0099] The first deep well region 161 may include SiC. For example, the first deep well region 161 may include 4H SiC. The first deep well region 161 may have a second conductivity type. The first deep well region 161 may be doped with a second conductivity type. The second conductivity type may be p-type, but is not limited thereto. The doping concentration of the first deep well region 161 may be greater than the doping concentration of the well region 133. Therefore, the breakdown voltage of the transistor can be prevented from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. The material, doping type, doping concentration, thickness, etc. of the first deep well region 161 are not limited thereto, and can be changed in various ways.

[0100] The first deep well region 161 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, the first deep well region 161 may be formed using a random ion implantation process. Alternatively, the first deep well region 161 may be an epitaxial layer formed from the epitaxial layer 131 using an epitaxial growth method.

[0101] The semiconductor device according to the embodiment may further include a second deep well region 162 located between the epitaxial layer 131 and the source electrode 173.

[0102] The second deep well region 162 may be located on the epitaxial layer 131. The second deep well region 162 may be located on the epitaxial layer 131 located in the transistor region TA. The second deep well region 162 may be located between the epitaxial layer 131 and the source electrode 173. The second deep well region 162 may be located on one side of the well region 133. The second deep well region 162 may be located on one side 150_S1 of the gate electrode 150. The second deep well region 162 may face the gate insulating layer 140, and the well region 133 is located between the second deep well region 162 and the gate insulating layer 140. The well region 133 may be located between the second deep well region 162 and the gate insulating layer 140. The lower surface of the second deep well region 162 may contact the epitaxial layer 131. The lower surface of the second deep well region 162 may not contact the shielding pattern 300, which will be described later, but the example embodiment is not limited thereto. The second deep well region 162 may not be located on the other side 150_S2 of the gate electrode 150.

[0103] The second deep well region 162 may have a predetermined depth. For example, the lower surface (e.g., the lowest surface) of the second deep well region 162 may be located at a lower height compared to the lower surface (e.g., the lowest surface) of the well region 133. The lower surface of the second deep well region 162 may be closer to the first surface 110a of the substrate 110 compared to the distance of the lower surface of the well region 133 from the first surface 110a of the substrate 110. The upper surface of the second deep well region 162 may be located at substantially the same height as the upper surface of the well region 133, but the exemplary embodiment is not limited thereto. In the embodiment, the thickness (e.g., the maximum thickness) of the second deep well region 162 along the third direction (Z direction) may be greater than the thickness (e.g., the maximum thickness) of the well region 133 along the third direction (Z direction). Therefore, the breakdown voltage of the transistor can be prevented from decreasing due to the electric field generated by the voltage applied to the gate electrode 150.

[0104] In an embodiment, the thickness (e.g., maximum thickness) of the second deep well region 162 along the third direction (Z direction) may be substantially the same as the thickness (e.g., maximum thickness) of the first deep well region 161 along the third direction (Z direction). The lower surface of the second deep well region 162 may be positioned at a distance substantially the same from the first surface 110a of the substrate 110 as the lower surface of the first deep well region 161 is positioned from the first surface 110a of the substrate, but the exemplary embodiment is not limited thereto.

[0105] The second deep well region 162 may comprise the same material as the first deep well region 161. The second deep well region 162 may be formed simultaneously with the first deep well region 161 in the same process. For example, the second deep well region 162 may comprise SiC. As another example, the second deep well region 162 may comprise 4H SiC. The second deep well region 162 may have a second conductivity type. The second deep well region 162 may be doped with a second conductivity type. The second conductivity type may be p-type, but is not limited thereto.

[0106] The doping concentration of the second deep well region 162 can be greater than that of the well region 133. Therefore, the second deep well region 162 can prevent the transistor's breakdown voltage from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. The doping concentration of the second deep well region 162 can be substantially the same as that of the first deep well region 161. However, the exemplary embodiment is not limited thereto, and for example, the doping concentration of the second deep well region 162 can be greater than that of the first deep well region 161. As another example, the doping concentration of the second deep well region 162 can be less than that of the first deep well region 161. The material, doping type, doping concentration, thickness, etc., of the second deep well region 162 are not limited thereto and can be varied in various ways.

[0107] The second deep well region 162 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, the second deep well region 162 may be formed using a random ion implantation process. Alternatively, the second deep well region 162 may be an epitaxial layer formed from the epitaxial layer 131 using an epitaxial growth method.

[0108] The semiconductor device according to the embodiment may further include a first doped layer 181 positioned on a well region 133, a second doped layer 182 positioned on a first deep well region 161, and a third doped layer 183 positioned on a second deep well region 162.

[0109] The first doped layer 181 can be positioned on the epitaxial layer 131. The first doped layer 181 can be positioned on the epitaxial layer 131 located in the transistor region TA. The first doped layer 181 can be positioned on the well region 133. For example, the first doped layer 181 can be directly positioned on the upper surface of the well region 133. The first doped layer 181 can be positioned between the well region 133 and the source electrode 173. One surface of the first doped layer 181 can contact the well region 133, and the other surface of the first doped layer 181 can contact the first silicide layer 191 or the source electrode 173.

[0110] A first doped layer 181 may be positioned on one side 150_S1 of the gate electrode 150. The first doped layer 181 may face the gate electrode 150, and a gate insulating layer 140 is interposed between the first doped layer 181 and the gate electrode 150. The surface of the first doped layer 181 facing the gate electrode 150 may be positioned on the same boundary line as the sidewall of the gate trench GT. The upper surface of the first doped layer 181 may contact the first silicide layer 191, which will be described later, and the lower surface of the first doped layer 181 may contact the well region 133. However, the exemplary embodiment is not limited thereto, and another layer of a predetermined type may be positioned between the first doped layer 181 and the source electrode 173. At least a portion of the upper surface of the first doped layer 181 may be covered by a capping layer 142, but the exemplary embodiment is not limited thereto. The source electrode 173 and the first silicide layer 191 may be in ohmic contact with the first doped layer 181.

[0111] An ion implantation process can be used to form a first doped layer 181 within the well region 133. The first doped layer 181 may include SiC. For example, the first doped layer 181 may include 4H SiC. The first doped layer 181 may have a first conductivity type. The first conductivity type may be n-type, but is not limited thereto. Compared to other regions, the region within the first doped layer 181 that contacts the first silicide layer 191 can be doped at a relatively high concentration. The doping concentration of the first doped layer 181 may be greater than the doping concentration of the epitaxial layer 131. The doping concentration of the first doped layer 181 may be approximately 1 × 10⁻⁶. 18 cm -3 Above and approximately 5×10 20 cm -3 The following (for example, from 1×10) 18 cm -3 Up to 5×10 20 cm -3The thickness of the first doped layer 181 can be greater than approximately 0.1 μm and less than approximately 0.5 μm (e.g., in the range of 0.1 μm to 0.5 μm). The material, doping type, doping concentration, etc. of the first doped layer 181 are not limited thereto and can be changed in various ways.

[0112] The second doped layer 182 can be positioned on the first deep well region 161. The second doped layer 182 can be positioned on the first deep well region 161 located in the diode region DA. The second doped layer 182 can be positioned between the first deep well region 161 and the source electrode 173. One surface of the second doped layer 182 can contact the first deep well region 161, and the other surface of the second doped layer 182 can contact the second silicide layer 192 or the source electrode 173.

[0113] The second doped layer 182 can be positioned on the other side 150_S2 of the gate electrode 150. The second doped layer 182 can face the gate electrode 150, and the gate insulating layer 140 is located between the second doped layer 182 and the gate electrode 150. The surface of the second doped layer 182 facing the gate electrode 150 can be positioned on the same boundary line as the sidewall of the gate trench GT. The upper surface of the second doped layer 182 can contact the second silicide layer 192, which will be described later, and the lower surface of the second doped layer 182 can contact the second deep well region 162. However, the exemplary embodiment is not limited thereto, and another layer of a predetermined type can be positioned between the second doped layer 182 and the source electrode 173. At least a portion of the upper surface of the second doped layer 182 can be covered by the capping layer 142, but the exemplary embodiment is not limited thereto. The source electrode 173 and the second silicide layer 192 can be in ohmic contact with the second doped layer 182.

[0114] The second doped layer 182 can be formed within the epitaxial layer 131 using an ion implantation process. The second doped layer 182 may include SiC. For example, the second doped layer 182 may include 4H SiC. The second doped layer 182 may have a second conductivity type. The second doped layer 182 may be heavily doped with a second conductivity type. The second conductivity type may be p-type, but is not limited thereto. The doping concentration of the second doped layer 182 may be greater than the doping concentration of the first deep well region 161 and the doping concentration of the second deep well region 162. The doping concentration of the second doped layer 182 may be approximately 1 × 10⁻⁶. 18 cm -3 Above and approximately 5×10 20 cm -3 The following (for example, from 1×10) 18 cm -3 Up to approximately 5×10 20 cm -3(within the range). The material, doping type, doping concentration, etc. of the second doped layer 182 are not limited to this, and can be changed in various ways.

[0115] The third doped layer 183 can be positioned on the second deep well region 162. The third doped layer 183 can be positioned on the second deep well region 162 located in the transistor region TA. The third doped layer 183 can be positioned between the second deep well region 162 and the source electrode 173.

[0116] In an embodiment, the third doped layer 183 may be positioned on one side of the first doped layer 181. For example, the third doped layer 183 may be positioned on one side of the first doped layer 181 along a first direction (X direction). For example, the first doped layer 181 may be positioned between the third doped layer 183 and the gate electrode 150. The third doped layer 183 may be positioned to be spaced apart from the gate trench GT in the first direction (X direction). The third doped layer 183 may be positioned to be spaced apart from the gate insulating layer 140 in the first direction (X direction).

[0117] The third doped layer 183 may be located in the same layer as the first doped layer 181. The upper surface of the third doped layer 183 may be positioned at substantially the same height as the upper surface of the first doped layer 181. For example, the upper surface of the third doped layer 183 may be positioned at substantially the same distance from the first surface 110a of the substrate 110 as the upper surface of the first doped layer 181 is positioned from the first surface 110a of the substrate 110. The lower surface of the third doped layer 183 may be located at the same height as the lower surface of the first doped layer 181, but the exemplary embodiments are not limited thereto. For example, in some embodiments, the lower surface of the third doped layer 183 may be located at a lower height than the lower surface of the first doped layer 181, such that the lower surface of the third doped layer 183 is closer to the first surface 110a of the substrate 110 than the lower surface of the first doped layer 181 is positioned from the first surface 110a of the substrate 110, but the exemplary embodiments are not limited thereto.

[0118] The third doped layer 183 can be formed within the epitaxial layer 131 using an ion implantation process. The third doped layer 183 can include SiC. For example, the third doped layer 183 can include 4H SiC. The third doped layer 183 can have a second conductivity type. The third doped layer 183 can be heavily doped with a second conductivity type. The second conductivity type can be p-type, but is not limited thereto. The doping concentration of the third doped layer 183 can be greater than the doping concentration of the first deep well region 161 and the second deep well region 162. The doping concentration of the third doped layer 183 can be substantially the same as the doping concentration of the second doped layer 182, but the example embodiment is not limited thereto. The doping concentration of the third doped layer 183 can be approximately 1 × 10⁻⁶. 18 cm -3Above and approximately 5×10 20 cm -3 The following (for example, from 1×10) 18 cm -3 Up to 5×10 20 cm -3 (Within the range). The material, doping type, doping concentration, etc. of the third doped layer 183 are not limited to this, and can be changed in various ways.

[0119] The semiconductor device according to the embodiment may further include silicide layers 191 and 192 positioned between the source electrode 173 and the well region 133. Silicide layers 191 and 192 may include a first silicide layer 191 positioned between the first doped layer 181 and the source electrode 173 and between the third doped layer 183 and the source electrode 173, and a second silicide layer 192 positioned between the second doped layer 182 and the source electrode 173.

[0120] The first doped layer 181 and the source electrode 173, as well as the third doped layer 183 and the source electrode 173, can be electrically smoothly connected through the first silicide layer 191. Additionally, the second doped layer 182 and the source electrode 173 can be electrically smoothly connected through the second silicide layer 192.

[0121] The shielding pattern 300 can be positioned on the epitaxial layer 131. The shielding pattern 300 can be positioned on the epitaxial layer 131 located in the diode region DA. The shielding pattern 300 can be positioned between the epitaxial layer 131 and the first deep well region 161. The shielding pattern 300 may not be located in the transistor region TA. The shielding pattern 300 can overlap with the first deep well region 161 in the third direction (Z direction). The shielding pattern 300 can be electrically connected to the source electrode 173 through the second doped layer 182 and the first deep well region 161.

[0122] In this embodiment, the shielding pattern 300 may overlap with the gate trench GT in the third direction (Z direction). The shielding pattern 300 may overlap with the gate electrode 150 in the third direction (Z direction). The shielding pattern 300 may overlap with the gate insulating layer 140 in the third direction (Z direction). The shielding pattern 300 does not overlap with the well region 133 in the third direction (Z direction). The upper surface of the shielding pattern 300 may contact the lower surface of the first deep well region 161 and the lower surface of the gate insulating layer 140. The lower surface 300_B of the shielding pattern 300 may contact the epitaxial layer 131.

[0123] The shielding pattern 300 may extend in a second direction (Y direction). In an embodiment, the shielding pattern 300 may extend in the second direction (Y direction) between the first portion 211 and the second portion 212 of the gate frame 210 and between the second portion 212 and the third portion 213. The length of each shielding pattern 300 in the second direction (Y direction) may be substantially equal to the distance between the first portion 211 and the second portion 212.

[0124] The shielding pattern 300 can be formed to have a predetermined depth from the lower surface of the first deep well region 161. The thickness DD of the shielding pattern 300 along the third direction (Z direction) (e.g., the distance in the Z direction between the uppermost and lowermost surfaces of the shielding pattern 300) can be greater than the depth of the gate trench GT along the third direction (Z direction). For example, the thickness DD of the shielding pattern 300 in the third direction (Z direction) can be approximately two to three times the depth of the gate trench GT in the third direction (Z direction), but the example embodiment is not limited thereto. The thickness DD of the shielding pattern 300 along the third direction (Z direction) can be greater than the thickness of the well region 133 along the third direction (Z direction). The thickness DD of the shielding pattern 300 along the third direction (Z direction) can be greater than the thickness of the first deep well region 161 along the third direction (Z direction). Therefore, the shielding pattern 300 can prevent the breakdown voltage of the transistor from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. Here, the thickness DD of the shielding pattern 300 along the third direction (Z direction) can be the maximum length along the third direction (Z direction) between the upper surface of the shielding pattern 300 that contacts the first deep well region 161 (e.g., the highest part of the upper surface in the Z direction) and the lower surface of the shielding pattern 300 (e.g., the lowest part of the lower surface in the Z direction). The third direction (Z direction) can be the direction that intersects the first direction (X direction) and the second direction (Y direction), and the third direction (Z direction) can be a vertical direction that is perpendicular to the first surface 110a of the substrate 110.

[0125] Additionally, in this embodiment, the thickness DD of the shielding pattern 300 along the third direction (Z direction) can be less than the distance along the third direction (Z direction) between the first deep well region 161 and the drain electrode 175. Therefore, the shielding pattern 300 and the drain electrode 175 can be spaced apart in the third direction (Z direction), and the interface IF between the shielding pattern 300 and the epitaxial layer 131 located between the shielding pattern 300 and the drain electrode 175 can form a PN junction interface.

[0126] The lower surface 300_B of the shielding pattern 300 may include a convex curved surface toward the drain electrode 175. For example, the lower surface 300_B of the shielding pattern 300 may have a convex shape toward the first surface 110a of the substrate 110. This may be due to the process characteristics of forming the shielding pattern 300 using tunneling ion implantation and / or high-energy implantation processes within the epitaxial layer 131.

[0127] The width of the shielding pattern 300 along the first direction (X direction) can be greater than or equal to the width of the first deep well region 161 along the first direction (X direction). For example, the width of the shielding pattern 300 in the first direction (X direction) (e.g., the maximum width) can be greater than or equal to the distance between adjacent gate trenches GT in the first direction (X direction). Therefore, at least a portion of the shielding pattern 300 can overlap with the gate insulating layer 140 located within the gate trench GT in the third direction (Z direction).

[0128] The shielding pattern 300 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, at least a portion of the shielding pattern 300 may be a doped region formed using a tunneling ion implantation process and / or a high-energy implantation process, and the remainder may be a doped region formed using a random ion implantation process. The shielding pattern 300 may include SiC. For example, the shielding pattern 300 may include 4H SiC. The shielding pattern 300 may have the same conductivity type as the well region 133 and the third doped layer 183. The shielding pattern 300 may have a second conductivity type. The shielding pattern 300 may be doped with a second conductivity type. The second conductivity type may be p-type, but is not limited thereto. In this case, the doping concentration of the shielding pattern 300 may be greater than the doping concentration of the well region 133. The doping concentration of the shielding pattern 300 may be greater than or equal to the doping concentration of the first deep well region 161 and the second deep well region 162. The doping concentration of the shielding pattern 300 may be less than the doping concentration of the second doped layer 182. Therefore, the shielding pattern 300 can effectively mitigate the electric field generated around the gate electrode 150. In some embodiments, the shielding pattern 300 may consist of a single layer or multiple layers.

[0129] The shielding pattern 300 of the semiconductor device according to the embodiment may include a first shielding layer 310 positioned on the lower surface of the first deep well region 161 and the lower surface of the gate insulating layer 140, and a second shielding layer 320 positioned between the first shielding layer 310 and the epitaxial layer 131.

[0130] The first shielding layer 310 may be located below the first deep well region 161 and the gate insulating layer 140. The first shielding layer 310 may be located below the gate trench GT. The first shielding layer 310 may be positioned on the lower surface of the gate trench GT.

[0131] The upper surface of the first shielding layer 310 may contact the gate insulating layer 140 and the first deep well region 161. The first shielding layer 310 may overlap with the gate trench GT in the third direction (Z direction). The first shielding layer 310 may overlap with the gate electrode 150 in the third direction (Z direction). The first shielding layer 310 does not overlap with the well region 133 in the third direction (Z direction). In addition, the first shielding layer 310 does not overlap with the first doped layer 181 and the third doped layer 183 in the third direction (Z direction).

[0132] The width (e.g., maximum width) of the first shielding layer 310 along the first direction (X direction) can be greater than or equal to the width (e.g., maximum width) of the first deep well region 161 along the first direction (X direction). For example, the width of the first shielding layer 310 in the first direction (X direction) can be greater than or equal to the distance between adjacent gate trenches GT in the first direction (X direction). Here, the width of the first shielding layer 310 along the first direction (X direction) can be the maximum width of the first shielding layer 310 along the first direction (X direction). Therefore, at least a portion of the first shielding layer 310 can overlap with the gate insulating layer 140 located within the gate trench GT in the third direction (Z direction). Therefore, the first shielding layer 310 can effectively mitigate the electric field generated around the gate electrode 150.

[0133] The upper surface of the first shielding layer 310 may be located at a higher height than the lower surface of the gate insulating layer 140. The upper surface of the first shielding layer 310 may be further away from the first surface 110a of the substrate 110 than the lower surface of the gate insulating layer 140. The distance between the upper surface of the first shielding layer 310 and the first surface 110a of the substrate 110 may be greater than the distance between the lower surface of the gate insulating layer 140 and the first surface 110a of the substrate 110. Therefore, the first shielding layer 310 may overlap with at least a portion of the gate insulating layer 140 in the horizontal direction (a first direction (X direction) and / or a second direction (Y direction)). The first shielding layer 310 may contact at least a portion of the other side 140_S2 of the gate insulating layer 140. In one embodiment, the upper surface of the first shielding layer 310 may be located at a lower height than the lower surface of the gate electrode 150, but the embodiment is not limited to this. Compared to the distance between the lower surface of the gate electrode 150 and the first surface 110a of the substrate 110, the upper surface of the first shielding layer 310 can be closer to the first surface 110a of the substrate 110. The first shielding layer 310 does not overlap with the gate electrode 150 in the horizontal direction (first direction (X direction) and / or second direction (Y direction)). However, the example embodiment is not limited to this, and for example, the first shielding layer 310 may overlap with the gate electrode 150 in the horizontal direction (first direction (X direction) and / or second direction (Y direction)). Further illustration of this example is shown in... Figure 7 middle.

[0134] The lower surface 310_B of the first shielding layer 310 may include a convex curved surface toward the drain electrode 175. For example, the lower surface 310_B of the first shielding layer 310 may have a convex shape toward the first surface 110a of the substrate 110. This may be due to the process characteristics of forming the first shielding layer 310 using an ion implantation process within the epitaxial layer 131. The ion implantation process may be, for example, a random ion implantation process.

[0135] The first shielding layer 310 may have a second conductivity type. The first shielding layer 310 may be doped with a second conductivity type. Here, the second conductivity type may be p-type, but the example embodiment is not limited to this.

[0136] The second shielding layer 320 can be positioned between the epitaxial layer 131 and the first shielding layer 310. The second shielding layer 320 can protrude from the lower surface 310_B of the first shielding layer 310 toward the first surface 110a of the substrate 110. The upper surface of the second shielding layer 320 can contact the first shielding layer 310, and the lower surface 320_B of the second shielding layer 320 can contact the epitaxial layer 131. The second shielding layer 320 can overlap with the gate trench GT in the third direction (Z direction). The second shielding layer 320 can overlap with the gate electrode 150 in the third direction (Z direction). The second shielding layer 320 does not overlap with the well region 133 in the third direction (Z direction). In addition, the second shielding layer 320 does not overlap with the first doped layer 181 and the third doped layer 183 in the third direction (Z direction). The second shielding layer 320 can be electrically connected to the drain electrode 175 through the epitaxial layer 131.

[0137] The width (e.g., maximum width) of the second shielding layer 320 along the first direction (X direction) can be greater than or equal to the width (e.g., maximum width) of the first deep well region 161 along the first direction (X direction). For example, the width of the second shielding layer 320 in the first direction (X direction) can be greater than or equal to the distance between adjacent gate trenches GT in the first direction (X direction). Here, the width of the second shielding layer 320 along the first direction (X direction) can be the maximum width of the second shielding layer 320 along the first direction (X direction). Therefore, the second shielding layer 320 can effectively mitigate the electric field generated around the gate electrode 150.

[0138] In an embodiment, the width (e.g., maximum width) of the second shielding layer 320 along the first direction (X direction) may be substantially the same as the width (e.g., maximum width) of the first shielding layer 310 along the first direction (X direction), but the example embodiment is not limited thereto. Further illustration shows... Figures 4 to 6 middle.

[0139] The thickness of the second shielding layer 320 along the third direction (Z direction) can be greater than the depth of the gate trench GT along the third direction (Z direction). The thickness of the second shielding layer 320 along the third direction (Z direction) can be greater than the thickness of the well region 133 along the third direction (Z direction). The thickness of the second shielding layer 320 along the third direction (Z direction) can be greater than the thickness of the first deep well region 161 along the third direction (Z direction). Therefore, the second shielding layer 320 can prevent the breakdown voltage of the transistor from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. Here, the thickness of the second shielding layer 320 along the third direction (Z direction) can be the maximum length of the second shielding layer 320 along the third direction (Z direction) or the length in the Z direction between the uppermost and lowermost surfaces of the second shielding layer 320.

[0140] The lower surface 320_B of the second shielding layer 320 may include a convex curved surface toward the drain electrode 175. For example, the lower surface 320_B of the second shielding layer 320 may have a convex shape toward the first surface 110a of the substrate 110. In this case, the curvature of the lower surface 320_B of the second shielding layer 320 may be greater than or equal to the curvature of the lower surface 310_B of the first shielding layer 310. This may be due to the process characteristics of forming the second shielding layer 320 using tunneling ion implantation and / or high-energy implantation processes within the epitaxial layer 131 while simultaneously forming the first shielding layer 310 using random ion implantation processes within the epitaxial layer 131.

[0141] The second shielding layer 320 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, the second shielding layer 320 may be formed using a tunneling ion implantation process and / or a high-energy implantation process. Therefore, ions can be implanted from the upper surface of the epitaxial layer 131 into a deep region to form the second shielding layer 320 of the semiconductor device according to the embodiment. The second shielding layer 320 may have a second conductivity type. The second shielding layer 320 may be doped with a second conductivity type. Here, the second conductivity type may be p-type, but the example embodiment is not limited thereto. In the embodiment, the doping concentration of the second shielding layer 320 may differ from the doping concentration of the first shielding layer 310, but the example embodiment is not limited thereto.

[0142] According to an embodiment, the second shielding layer 320 of the semiconductor device may have a second conductivity type, and the epitaxial layer 131 may have a first conductivity type. Therefore, the semiconductor device according to the embodiment can form a PN junction interface at the interface IF between the lower surface 320_B of the second shielding layer 320 and the epitaxial layer 131, and can perform the function of a diode device.

[0143] Drain electrode 175 may be positioned on a second surface (i.e., lower surface) of substrate 110. The upper surface of drain electrode 175 may contact the lower surface of substrate 110. Drain electrode 175 may have an ohmic contact with substrate 110. The region within substrate 110 in contact with drain electrode 175 may be doped at a relatively high concentration compared to other regions. However, the exemplary embodiment is not limited thereto, and another layer may be additionally positioned between drain electrode 175 and substrate 110. For example, a silicide layer may be further positioned between drain electrode 175 and substrate 110. Drain electrode 175 and substrate 110 may be electrically smoothly connected via the silicide layer.

[0144] The drain electrode 175 may include a conductive material. For example, the drain electrode 175 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a combination thereof. The drain electrode 175 may be made of the same material as the source electrode 173 or may be made of a different material. The drain electrode 175 may be formed of a single layer or multiple layers.

[0145] In an embodiment, the source electrode 173, drain electrode 175, and gate electrode 150 can form a transistor having a well region 133 as a channel region. According to an embodiment, when a conduction signal is applied to the gate electrode 150, the semiconductor device allows charge carriers to flow from the source electrode 173 toward the drain electrode 175 in a third direction (Z direction). In this case, charge carriers can flow from the source electrode 173 to the drain electrode 175 through the first doped layer 181, the well region 133, the epitaxial layer 131, and the substrate 110.

[0146] The shielding pattern 300 of the semiconductor device according to the embodiment can be positioned between the first deep well region 161 and the epitaxial layer 131. Additionally, a second deep well region 162 can be positioned on one side of the well region 133. The second deep well region 162 and / or the shielding pattern 300 can prevent the transistor's breakdown voltage from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. Therefore, the reliability of the semiconductor device according to the embodiment can be improved.

[0147] The semiconductor device according to the embodiment may be an n-type field-effect transistor (n-FET). However, the example embodiment is not limited thereto, and the semiconductor device according to the embodiment may be a p-type field-effect transistor (p-FET). In this case, the substrate 110, the epitaxial layer 131 and the first doped layer 181 may have a second conductivity type, and the well region 133, the first deep well region 161, the second deep well region 162 and the shielding pattern 300 may have a first conductivity type.

[0148] According to embodiments, semiconductor devices have been described having a structure in which a gate electrode 150 is positioned within a gate trench GT and a source electrode 173 is positioned at a higher layer than the gate electrode 150; however, exemplary embodiments are not limited thereto. For example, a semiconductor device according to some embodiments may have a gate electrode 150 positioned within a gate trench GT and a source electrode 173 positioned within a source trench located on one side of the gate trench GT. As another example, a semiconductor device according to some embodiments may have a gate electrode 150 positioned on the upper surface of an epitaxial layer 131 and a source electrode 173 positioned on the side surface of the gate electrode 150 above the epitaxial layer 131. As another example, a semiconductor device according to some embodiments may include a Si insulated gate bipolar transistor (IGBT) structure. As another example, a semiconductor device according to some embodiments may include a superjunction structure in which the p-type and n-type regions are completely depleted, thereby forming a two-dimensional uniform electric field distribution.

[0149] In the following text, reference will be made to Figures 4 to 17 Describes a semiconductor device according to some embodiments.

[0150] Figures 4 to 16 This illustrates a semiconductor device according to some embodiments. Figure 2 The cross-sectional view corresponding to region S1. Figure 17 This is a top view showing a semiconductor device according to some embodiments.

[0151] Figures 4 to 17 Showing according to Figures 1 to 3 Various modifications of the semiconductor device in the illustrated embodiments. Figures 4 to 17 The illustrated embodiments and Figures 1 to 3 The embodiments shown are essentially identical; therefore, the differences will only be described below. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0152] refer to Figure 4 According to some embodiments, the first shielding layer 310 of the semiconductor device can completely cover the lower surface (e.g., the lowest surface) of the gate trench GT.

[0153] In some embodiments, the first shielding layer 310 may be positioned on the lower surface of the gate trench GT. The edge 310E of the first shielding layer 310 may be aligned with the inner sidewall of the gate trench GT. For example, the edge 310E of the first shielding layer 310 may be aligned with one side 140_S1 of the gate insulating layer 140. The first shielding layer 310 may completely cover the lower surface of the gate insulating layer 140 (e.g., two adjacent gate insulating layers 140). The lower surface of the gate insulating layer 140 (e.g., the lowermost surface) may be positioned separate from the epitaxial layer 131. The lower surface 310_B of the first shielding layer 310 may contact the epitaxial layer 131 and the second shielding layer 320. Therefore, the shielding pattern 300 of the semiconductor device according to the embodiment can effectively mitigate the electric field generated around the gate electrode 150.

[0154] In some embodiments, the width W1 of the second shielding layer 320 along the first direction (X direction) may be different from the width W2 of the first shielding layer 310 along the first direction (X direction). For example, the width W2 of the first shielding layer 310 along the first direction (X direction) may be greater than the width W1 of the second shielding layer 320 along the first direction (X direction).

[0155] refer to Figure 5 According to some embodiments, the shielding pattern 300 of the semiconductor device can completely cover the lower surface of the gate insulating layer 140.

[0156] In some embodiments, the first shielding layer 310 may completely cover the lower surface of the gate insulating layer 140 (e.g., two adjacent gate insulating layers 140), and the second shielding layer 320 may completely cover the lower surface of the first shielding layer 310. Therefore, the lower surface (e.g., the lowest surface) of the gate insulating layer 140 may be spaced apart from the epitaxial layer 131.

[0157] In some embodiments, the edges of the first shielding layer 310 and the second shielding layer 320 may be aligned with the inner sidewalls of the gate trench GT. For example, the edges of the first shielding layer 310 and the second shielding layer 320 may be aligned with one side 140_S1 of the gate insulating layer 140. In some embodiments, the width W2 of the first shielding layer 310 along the first direction (X direction) may be substantially equal to the width W1 of the second shielding layer 320 along the first direction (X direction). Therefore, the shielding pattern 300 of the semiconductor device according to the embodiment can effectively mitigate the electric field generated around the gate electrode 150.

[0158] refer to Figure 6According to some embodiments, the width W1 (e.g., maximum width) of the second shielding layer 320 of the semiconductor device along the first direction (X direction) may be smaller than the width W3 (e.g., maximum width) of the first deep well region 161 along the first direction (X direction). In some embodiments, the second shielding layer 320 may overlap with the first deep well region 161 in the third direction (Z direction) and may not overlap with the gate trench GT in the third direction (Z direction). For example, the second shielding layer 320 may not overlap with the gate electrode 150 and the gate insulating layer 140 in the third direction (Z direction). Even in this case, since the first shielding layer 310 is located between the first deep well region 161 and the second shielding layer 320, and also between the gate insulating layer 140 and the second shielding layer 320, and the first shielding layer 310 is formed with a width sufficient to cover at least a portion of the lower surface of the gate insulating layer 140, the shielding pattern 300 of the semiconductor device according to the embodiments can effectively mitigate the electric field generated around the gate electrode 150.

[0159] refer to Figure 7 According to some embodiments, the first shielding layer 310 of the semiconductor device may overlap with the gate electrode 150 in a horizontal direction (a first direction (X direction) and / or a second direction (Y direction)). In some embodiments, the upper surface of the first shielding layer 310 may be located at a higher height than the lower surface of the gate electrode 150. The upper surface of the first shielding layer 310 may be further away from the first surface 110a of the substrate 110 than the distance between the lower surface of the gate electrode 150 and the first surface 110a of the substrate 110.

[0160] refer to Figure 8 According to some embodiments, the first shielding layer 310 of the semiconductor device does not overlap with the gate trench GT in the horizontal direction (first direction (X direction) and / or second direction (Y direction)). In some embodiments, the upper surface 310_U of the first shielding layer 310 may be located at a lower height compared to the lower surface of the gate electrode 150. The upper surface 310_U of the first shielding layer 310 may be positioned closer to the first surface 110a of the substrate 110 compared to the distance of the lower surface of the gate electrode 150 from the first surface 110a of the substrate 110. In some embodiments, the upper surface 310_U of the first shielding layer 310 does not overlap with the gate insulating layer 140 and the gate electrode 150 in the horizontal direction (first direction (X direction) and / or second direction (Y direction)). The upper surface 310_U of the first shielding layer 310 may be flat, but the example embodiments are not limited thereto.

[0161] refer to Figure 9According to some embodiments, the semiconductor device may not include the first deep well region 161. In some embodiments, the first shielding layer 310 may be positioned between adjacent gate trenches GT in a first direction (X direction). A second doped layer 182 may be positioned on the first shielding layer 310. The second doped layer 182 may be in contact with the first shielding layer 310.

[0162] refer to Figure 10 According to some embodiments, the shielding pattern 300 of the semiconductor device may be formed from a single layer. In some embodiments, the shielding pattern 300 may be formed from only the second shielding layer 320, but the example embodiments are not limited thereto.

[0163] refer to Figure 11 According to some embodiments, the shielding pattern 300 of the semiconductor device may also include a third shielding layer 330 positioned between the first shielding layer 310 and the second shielding layer 320.

[0164] The third shielding layer 330 can be positioned between the first shielding layer 310 and the second shielding layer 320. The third shielding layer 330 can overlap with the first deep well region 161, the gate electrode 150 and the gate insulating layer 140 in the third direction (Z direction). The third shielding layer 330 does not overlap with the well region 133 in the third direction (Z direction).

[0165] In some embodiments, the width of the third shielding layer 330 along the first direction (X direction) may be substantially the same as the width of the first shielding layer 310 along the first direction (X direction) and / or the width of the second shielding layer 320 along the first direction (X direction), but the embodiments are not limited thereto.

[0166] In some embodiments, the lower surface of the third shielding layer 330 may include a convex curved surface toward the drain electrode 175. For example, the lower surface of the third shielding layer 330 may have a convex shape toward the first surface 110a of the substrate 110. In this case, the curvature of the lower surface of the third shielding layer 330 may be greater than or equal to the curvature of the lower surface 310_B of the first shielding layer 310. The curvature of the lower surface of the third shielding layer 330 may be less than or equal to the curvature of the lower surface 320_B of the second shielding layer 320.

[0167] The third shielding layer 330 may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, the third shielding layer 330 may be formed using a tunneling ion implantation process and / or a high-energy implantation process. As another example, the third shielding layer 330 may be formed using a random ion implantation process. The third shielding layer 330 may have a second conductivity type. The third shielding layer 330 may be doped with a second conductivity type. Here, the second conductivity type may be p-type, but the example embodiment is not limited thereto. In the embodiment, the doping concentration of the third shielding layer 330 may be different from the doping concentration of the first shielding layer 310 and / or the doping concentration of the second shielding layer 320, but the example embodiment is not limited thereto.

[0168] refer to Figure 12 and Figure 13 According to some embodiments, the gate insulating layer 140 of the semiconductor device may have various shapes.

[0169] In some embodiments, the gate insulating layer 140 may include an edge 140E. The edge 140E of the gate insulating layer 140 may refer to a portion at the point where the lower surface of the gate insulating layer 140 meets the side surface of the gate insulating layer 140.

[0170] In some embodiments, the gate electrode 150 may have a different shape than the gate trench GT. Therefore, the third thickness TH3 between the edge 140E of the gate insulating layer 140 and the gate electrode 150 may be different from the first thickness TH1 of the gate insulating layer 140 along the third direction (Z direction). For example, as... Figure 12 As shown, the third thickness TH3 between the edge 140E of the gate insulating layer 140 and the gate electrode 150 can be greater than the first thickness TH1 of the gate insulating layer 140 along the third direction (Z direction). In this case, the third thickness TH3 between the edge 140E of the gate insulating layer 140 and the gate electrode 150 can be greater than the second thickness TH2 of the gate insulating layer 140 along the first direction (X direction). As another example, such as Figure 13 As shown, the third thickness TH3 between the edge 140E of the gate insulating layer 140 and the gate electrode 150 can be less than the first thickness TH1 of the gate insulating layer 140 along the third direction (Z direction). In this case, the third thickness TH3 between the edge 140E of the gate insulating layer 140 and the gate electrode 150 can be greater than the second thickness TH2 of the gate insulating layer 140 along the first direction (X direction).

[0171] refer to Figures 14 to 16 The first shielding layer 310_1 of the semiconductor device according to some embodiments may have various shapes.

[0172] refer to Figure 14The first shielding layer 310_1 can be positioned below the gate trench GT. The first shielding layer 310_1 can be positioned between the gate trench GT and the epitaxial layer 131, and between the gate trench GT and the second shielding layer 320. The first shielding layer 310_1 can protrude from the bottom surface of the gate trench GT toward the first surface 110a of the substrate 110. The first shielding layer 310_1 can be positioned between the gate insulating layer 140 and the epitaxial layer 131, and between the gate insulating layer 140 and the second shielding layer 320. The first shielding layer 310_1 can protrude from the lower surface of the gate insulating layer 140 toward the first surface 110a of the substrate 110.

[0173] The first shielding layer 310_1 may overlap with the gate trench GT in the third direction (Z direction). For example, the entire first shielding layer 310_1 may overlap with the gate trench GT in the third direction (Z direction), but the example embodiment is not limited thereto. The first shielding layer 310_1 may overlap with the gate electrode 150 and the gate insulating layer 140 in the third direction (Z direction). In one embodiment, the first shielding layer 310_1 does not overlap with the first deep well region 161 and the well region 133 in the third direction (Z direction). At least a portion of the first shielding layer 310_1 may overlap with the second shielding layer 320 in the third direction (Z direction). For example, a portion of the first shielding layer 310_1 may overlap with the second shielding layer 320 in the third direction (Z direction), and the remaining portion may overlap with the epitaxial layer 131 in the third direction (Z direction) without overlapping with the second shielding layer 320 in the third direction (Z direction). The upper surface of the first shielding layer 310_1 may contact the gate insulating layer 140, but the example embodiment is not limited thereto. The lower surface of the first shielding layer 310_1 may contact the second shielding layer 320 and the epitaxial layer 131, but the example embodiment is not limited thereto.

[0174] The width W4 of the first shielding layer 310_1 along the first direction (X direction) can be smaller than the width W5 of the gate trench GT along the first direction (X direction). The width W4 of the first shielding layer 310_1 along the first direction (X direction) can be smaller than the maximum width of the gate insulating layer 140 along the first direction (X direction). Here, the maximum width of the gate insulating layer 140 along the first direction (X direction) can be the distance between one side 140_S1 and the other side 140_S2 of the gate insulating layer 140 along the first direction (X direction). This can be due to the formation of the gate trench GT and the formation of spacers within the gate trench GT (see...). Figure 33 After 350), through the spacer in the epitaxial layer 131 (see 350) Figure 33This is due to the process characteristics of forming the first shielding layer 310_1 using tunneling ion implantation and / or high-energy implantation processes on a portion of the exposed area (350). Therefore, even when the gate trench GT is formed so that it does not overlap with the shielding pattern 300_1 in the third direction (Z direction) due to misalignment, the first shielding layer 310_1 can still be formed below the gate trench GT. Therefore, the shielding pattern 300 can prevent the transistor's breakdown voltage from decreasing due to the electric field generated by the voltage applied to the gate electrode 150, and improve the reliability of the semiconductor device according to the embodiment. Reference will be made later. Figures 31 to 35 Detailed explanation is provided. However, the example embodiment is not limited thereto, and the width W4 of the first shielding layer 310_1 along the first direction (X direction) may be greater than or equal to the width W5 of the gate trench GT along the first direction (X direction).

[0175] The second shielding layer 320 may be located below the first deep well region 161. The upper surface of the second shielding layer 320 may contact the first deep well region 161, but the example embodiment is not limited thereto.

[0176] refer to Figure 15 The first shielding layer 310_1 does not overlap with the second shielding layer 320 in the third direction (Z direction). For example, a semiconductor device according to some embodiments may include a plurality of gate trenches GT spaced apart from each other in a first direction (X direction) and a plurality of first shielding layers 310_1 positioned below each of the plurality of gate trenches GT. At least one of the plurality of first shielding layers 310_1 may not overlap with the second shielding layer 320 in the third direction (Z direction). Figure 15 In the illustration, the side of the first shielding layer 310_1 is depicted as contacting the side of the second shielding layer 320, but the example embodiment is not limited thereto. As another example, the first shielding layer 310_1 may be positioned to be spaced apart from the second shielding layer 320 in a first direction (X direction).

[0177] refer to Figure 16 The semiconductor device according to some embodiments may also include a dummy pattern 355 positioned within a gate trench GT.

[0178] The dummy pattern 355 can be positioned on the bottom surface and / or inner sidewall of the gate trench GT. For example, the dummy pattern 355 can be located at the edge of the gate trench GT where the bottom surface and inner sidewall of the gate trench GT meet. The dummy pattern 355 can be positioned between the gate insulating layer 140 and the epitaxial layer 131. The dummy pattern 355 can be spaced apart from the first shielding layer 310_1. For example, the dummy pattern 355 can be spaced apart from the first shielding layer 310_1 in the first direction (X direction). Alternatively, the dummy pattern 355 can be spaced apart from the first shielding layer 310_1 in the third direction (Z direction). The dummy pattern 355 can not overlap with the first shielding layer 310_1 in the third direction (Z direction). Additionally, the dummy pattern 355 can not overlap with the first shielding layer 310_1 in the first direction (X direction). The dummy pattern 355 can not overlap with the well region 133 in the first direction (X direction), but the example embodiment is not limited thereto. The upper surface of the dummy pattern 355 can be located at a lower height than the lower surface of the well region 133. The upper surface of the dummy pattern 355 can be positioned closer to the first surface 110a of the substrate 110 than the lower surface of the well region 133 is at a distance from the first surface 110a of the substrate 110.

[0179] The dummy pattern 355 can be a spacer (see...) Figure 33 At least a portion of (350) is used to remove spacers located within the gate trench GT (see Figure 33 The dummy pattern 355 is retained during the process of the gate insulating layer 140 and is not removed. The dummy pattern 355 can include various insulating materials. The dummy pattern 355 can include the same material as the gate insulating layer 140, but the example embodiments are not limited thereto. For example, the dummy pattern 355 can include SiO2. When the dummy pattern 355 is made of the same material as the gate insulating layer 140, the boundary between the dummy pattern 355 and the gate insulating layer 140 may not be clearly distinguishable at the region where they contact.

[0180] refer to Figure 17The transistor region TA and diode region DA located in the active region AR of a semiconductor device according to some embodiments can be arranged in various ways. For example, the active region AR of a semiconductor device according to some embodiments may include a first active region AR positioned between a first portion 211 and a second portion 212 of a gate frame 210 and a second active region AR positioned between a second portion 212 and a third portion 213 of the gate frame 210. The first active region AR may have transistor regions TA and diode regions DA alternately positioned along a first direction (X direction), and the second active region AR may have diode regions DA and transistor regions TA alternately positioned along the first direction (X direction). The transistor regions TA of the first active region AR and the diode regions DA of the second active region AR may overlap along a second direction (Y direction), and the diode regions DA of the first active region AR and the transistor regions TA of the second active region AR may overlap along the second direction (Y direction), but the example embodiments are not limited thereto.

[0181] In the following text, reference will be made to Figures 18 to 30 A method for manufacturing a semiconductor device according to an embodiment is described.

[0182] Figures 18 to 30 This illustrates a method for manufacturing a semiconductor device according to an embodiment. Figure 1 The cross-sectional view corresponding to A-A'.

[0183] refer to Figure 18 An epitaxial layer 131 is formed on the substrate 110.

[0184] Substrate 110 may be a semiconductor substrate including SiC. For example, substrate 110 may be made of 4H SiC substrate. In some cases, substrate 110 may be made of 3C SiC substrate, 6H SiC substrate, etc. Substrate 110 may have a first conductivity type. Substrate 110 may be heavily doped with the first conductivity type. The first conductivity type may be n-type, but is not limited thereto. The resistivity of substrate 110 may be about 0.005 Ωcm or more and about 0.035 Ωcm or less. The thickness of substrate 110 may be about 10 μm or more and about 700 μm or less. The material, doping type, doping concentration, resistivity, thickness, etc. of substrate 110 are not limited thereto and may be varied in various ways.

[0185] The substrate 110 may include a transistor region TA and a diode region DA. The transistor region TA and the diode region DA may be positioned alternately along a first direction (X direction). The transistor region TA may be a region in which an n-type field-effect transistor (n-FET) is formed, and the diode region DA may be a region in which a diode element is formed. However, the example embodiment is not limited thereto, and a p-type field-effect transistor may be formed in the transistor region TA.

[0186] The substrate 110 may include a first surface 110a and a second surface 110b that are opposite to each other. The first surface 110a of the substrate 110 may be the upper surface of the substrate 110, and the second surface 110b of the substrate 110 may be the lower surface of the substrate 110.

[0187] Epitaxial layer 131 may be formed on a first surface 110a of substrate 110. The lower surface of epitaxial layer 131 may contact the first surface 110a of substrate 110. However, the exemplary embodiment is not limited thereto, and another layer may be additionally positioned between substrate 110 and epitaxial layer 131. Epitaxial layer 131 may be an epitaxial layer formed from substrate 110 using an epitaxial growth method.

[0188] In this embodiment, the crystal plane of the material comprising the epitaxial layer 131 can be formed at a predetermined angle relative to the first surface 110a of the substrate 110. For example, the crystal plane of the material comprising the epitaxial layer 131 can be tilted from the first surface 110a of the substrate 110 by approximately 4°. For example, when the epitaxial layer 131 comprises SiC, the (0001) crystal plane of SiC can be tilted from the first surface 110a of the substrate 110 by approximately 4°. Therefore, in the process of forming the epitaxial layer 131 using an epitaxial growth method, lattice distortions caused by dislocations, etc., within the epitaxial layer 131 can be prevented.

[0189] Epitaxial layer 131 may include SiC. For example, epitaxial layer 131 may include 4H SiC. Epitaxial layer 131 may have a first conductivity type. Epitaxial layer 131 may be lightly doped with the first conductivity type. The first conductivity type may be n-type, but is not limited thereto.

[0190] refer to Figure 19 A second preliminary shielding layer 320P is formed within the epitaxial layer 131 in the diode region DA. The second preliminary shielding layer 320P may be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, the second preliminary shielding layer 320P may be formed within the epitaxial layer 131 using a tunneling ion implantation process and / or a high-energy implantation process.

[0191] Specifically, the semiconductor element can be positioned on the support 111. The support 111 can be a carrier substrate, or it can be a support for performing tunneling ion implantation and / or high-energy implantation processes. The upper surface of the support 111 can be tilted at a predetermined angle θ. The tilt angle θ of the upper surface of the support 111 can be substantially the same as the angle at which the crystal plane of the material including the epitaxial layer 131 described above tilts from the first surface 110a of the substrate 110. The tilt angle θ of the upper surface of the support 111 can be approximately 4°, but the example embodiment is not limited to this. Therefore, the semiconductor element can be rotated by a predetermined angle θ.

[0192] To perform tunneling ion implantation and / or high-energy implantation processes, the lattice orientation of the elements including epitaxial layer 131 needs to be aligned with a predetermined direction. As the support 111 tilts at a predetermined angle θ, the crystal planes of the material including epitaxial layer 131 can be aligned, and tunneling ion implantation and / or high-energy implantation processes can be performed within epitaxial layer 131 to deeply form a second preliminary shielding layer 320P. The second preliminary shielding layer 320P may have a second conductivity type. The second preliminary shielding layer 320P may be doped with a second conductivity type. The second conductivity type may be p-type, but is not limited to this.

[0193] The lower surface of the second preliminary shielding layer 320P may include a convex curved surface facing the first surface 110a of the substrate 110. For example, the lower surface of the second preliminary shielding layer 320P may have a convex shape facing the first surface 110a of the substrate 110. This may be due to the process characteristics of forming the shielding pattern 300 in the epitaxial layer 131 using tunneling ion implantation and / or high-energy implantation processes.

[0194] In this configuration, a first dummy region DIA1 can be formed on the upper side of the epitaxial layer 131 by using a tunneling ion implantation process and / or a high-energy implantation process to form a second preliminary shielding layer 320P. The first dummy region DIA1 may be formed due to a small number of ions entering the upper portion of the epitaxial layer 131 during the formation of the second preliminary shielding layer 320P. The first dummy region DIA1 may be substantially undoped or lightly doped. The doping concentration of the first dummy region DIA1 may be lower than the doping concentration of the second preliminary shielding layer 320P. The first dummy region DIA1 may correspond to a region where the first preliminary shielding layer 310P is subsequently formed, but the example embodiment is not limited thereto.

[0195] refer to Figure 20 After the semiconductor element tilted at a predetermined angle θ is rotated back to its original position, a first preliminary shielding layer 310P can be formed in the epitaxial layer 131, which overlaps with the second preliminary shielding layer 320P in the third direction (Z direction).

[0196] In an embodiment, within the diode region DA, an ion implantation process can be used within the epitaxial layer 131 to form a first preliminary shielding layer 310P that overlaps with the second preliminary shielding layer 320P in the third direction (Z direction). A random ion implantation process can be used to perform the formation of the first preliminary shielding layer 310P. The first preliminary shielding layer 310P can be a doped region formed within the epitaxial layer 131 using an ion implantation process. For example, an ion implantation process can be used to form the first preliminary shielding layer 310P within the first dummy region DIA1. The first preliminary shielding layer 310P can have a second conductivity type. The first preliminary shielding layer 310P can be doped with a second conductivity type. The second conductivity type can be p-type, but is not limited thereto. The doping concentration of the first preliminary shielding layer 310P can differ from the doping concentration of the second preliminary shielding layer 320P, but the example embodiment is not limited thereto.

[0197] The lower surface of the first preliminary shielding layer 310P may include a convex curved surface facing the first surface 110a of the substrate 110. For example, the lower surface of the first preliminary shielding layer 310P may have a convex shape facing the first surface 110a of the substrate 110. In this case, the curvature of the lower surface of the second preliminary shielding layer 320P may be greater than or equal to the curvature of the lower surface of the first preliminary shielding layer 310P. This may be due to the process characteristics of forming the second preliminary shielding layer 320P using tunneling ion implantation and / or high-energy implantation processes within the epitaxial layer 131 while simultaneously forming the first preliminary shielding layer 310P using random ion implantation processes within the epitaxial layer 131.

[0198] In this configuration, a second dummy region DIA2 can be formed on the upper portion of the epitaxial layer 131 by using an ion implantation process to form the first preliminary shielding layer 310P. The second dummy region DIA2 can be a region formed by implanting a small number of ions into the upper portion of the epitaxial layer 131 during the formation of the first preliminary shielding layer 310P. The second dummy region DIA2 can be substantially undoped or lightly doped. The doping concentration of the second dummy region DIA2 can be lower than the doping concentration of the first preliminary shielding layer 310P. The second dummy region DIA2 can correspond to the region where the first deep well region 161 is later formed, but the example embodiment is not limited thereto.

[0199] refer to Figure 21 A first deep well region 161 is formed in the epitaxial layer 131 that overlaps with the first preliminary shielding layer 310P along the third direction (Z direction).

[0200] In the diode region DA, an ion implantation process can be performed to form a first deep well region 161 within the second dummy region DIA2 of the first preliminary shielding layer 310P. In this case, the first deep well region 161 can be formed together in a portion of the first dummy region DIA1 of the second preliminary shielding layer 320P and a portion of the epitaxial layer 131. The first deep well region 161 can have a predetermined depth. The first deep well region 161 can overlap with the first preliminary shielding layer 310P and the second preliminary shielding layer 320P in the third direction (Z direction).

[0201] The first deep well region 161 may have a second conductivity type. The first deep well region 161 may be doped with a second conductivity type. The second conductivity type may be p-type, but is not limited to this. The doping concentration of the first deep well region 161 may be less than or equal to the doping concentration of the first preliminary shielding layer 310P and the second preliminary shielding layer 320P. Therefore, the breakdown voltage of the transistor can be prevented from decreasing due to the electric field generated by the voltage applied to the gate electrode 150. The material, doping type, doping concentration, thickness, etc., of the first deep well region 161 are not limited to this and can be changed in various ways.

[0202] Additionally, a second deep well region 162 can be further formed within the epitaxial layer 131.

[0203] In the transistor region TA, an ion implantation process can be performed to form a second deep well region 162 within the epitaxial layer 131. The second deep well region 162 may have a predetermined depth. The thickness of the second deep well region 162 along the third direction (Z direction) may be substantially the same as the thickness of the first deep well region 161 along the third direction (Z direction), but the exemplary embodiment is not limited thereto. The second deep well region 162 does not overlap with the first preliminary shielding layer 310P and the second preliminary shielding layer 320P in the third direction (Z direction).

[0204] The second deep well region 162 may have a second conductivity type. The second deep well region 162 may be doped with a second conductivity type. The second conductivity type may be p-type, but is not limited thereto. The doping concentration of the second deep well region 162 may be substantially the same as the doping concentration of the first deep well region 161, but the example embodiment is not limited thereto. The doping concentration of the second deep well region 162 may be less than or equal to the doping concentration of the first preliminary shielding layer 310P and the second preliminary shielding layer 320P. The material, doping type, doping concentration, thickness, etc., of the second deep well region 162 are not limited thereto and can be changed in various ways.

[0205] exist Figure 21In the diagram, the first deep well region 161 and the second deep well region 162 are depicted as being positioned spaced apart from each other along a first direction (X direction), but this is not limited to this. For example, the first deep well region 161 and the second deep well region 162 may be positioned adjacent to each other. Alternatively, a side of the first deep well region 161 may be in contact with the second deep well region 162.

[0206] refer to Figure 22 A preliminary well region 133P can be formed on at least one side of the first deep well region 161. For example, in the transistor region TA, the preliminary well region 133P can be formed within the epitaxial layer 131 using an ion implantation process. The preliminary well region 133P can be located on the opposite side of the second deep well region 162.

[0207] The lower surface of the preliminary well region 133P can be positioned at a higher height than the lower surface of the second deep well region 162. The lower surface of the preliminary well region 133P can be positioned further away from the first surface 110a of the substrate 110 than the distance of the lower surface of the second deep well region 162 from the first surface 110a of the substrate 110. The upper surface of the preliminary well region 133P can be positioned at substantially the same height as the upper surface of the second deep well region 162, but the exemplary embodiment is not limited thereto. In the embodiment, the thickness of the preliminary well region 133P in the third direction (Z direction) can be less than the thickness of the second deep well region 162 in the third direction (Z direction). Therefore, it is possible to prevent the breakdown voltage of the transistor from decreasing due to the electric field generated by the voltage applied to the gate electrode 150.

[0208] The initial well region 133P may have a second conductivity type different from the first conductivity type. The initial well region 133P may be lightly doped with the second conductivity type. The second conductivity type may be p-type, but is not limited to this. The doping concentration of the initial well region 133P may be lower than the doping concentration of the first initial shielding layer 310P and the second initial shielding layer 320P. The doping concentration of the initial well region 133P may be lower than the doping concentration of the first deep well region 161 and the second deep well region 162. The doping concentration of the initial well region 133P may be approximately 1 × 10⁻⁶. 17 cm -3 Above and approximately 1×10 19 cm -3 The thickness of the initial well region 133P can be approximately 0.3 μm or more and approximately 1.1 μm or less, but the example embodiment is not limited thereto. The material, doping type, doping concentration, thickness, etc. of the initial well region 133P are not limited thereto and can vary.

[0209] exist Figure 21 and Figure 22In this process, a preliminary well region 133P is formed after the formation of the first deep well region 161 and the second deep well region 162, but this is not a limitation. As another example, the first deep well region 161 and the second deep well region 162 may be formed after the formation of the preliminary well region 133P.

[0210] refer to Figure 23 For example, an ion implantation process is used to form a first doped layer 181 in the initial well region 133P, an ion implantation process is used to form a second doped layer 182 in the first deep well region 161, and an ion implantation process is used to form a third doped layer 183 in the second deep well region 162. The first doped layer 181 and the third doped layer 183 can be formed in the transistor region TA, and the second doped layer 182 can be formed in the diode region DA.

[0211] The first doped layer 181 to the third doped layer 183 may have substantially the same thickness. For example, the thickness of the first doped layer 181 along the third direction (Z direction), the thickness of the second doped layer 182 along the third direction (Z direction), and the thickness of the third doped layer 183 along the third direction (Z direction) may be substantially the same, but are not limited thereto.

[0212] The first doped layer 181 may have a first conductivity type. The first doped layer 181 may be doped with a first conductivity type. The first conductivity type may be n-type, but is not limited to this. The doping concentration of the first doped layer 181 may be greater than the doping concentration of the epitaxial layer 131. The doping concentration of the first doped layer 181 may be approximately 1 × 10⁻⁶. 18 cm -3 Above and approximately 5×10 20 cm -3 The thickness of the first doped layer 181 can be approximately 0.1 μm or more and approximately 0.5 μm or less. The material, doping type, doping concentration, etc. of the first doped layer 181 are not limited to these and can be changed in various ways.

[0213] The second doped layer 182 may have a second conductivity type. The second doped layer 182 may be heavily doped with a second conductivity type. The second conductivity type may be p-type, but is not limited thereto. In embodiments, the doping concentration of the second doped layer 182 may be greater than the doping concentration of the first deep well region 161 and the doping concentration of the second deep well region 162. Furthermore, the doping concentration of the second doped layer 182 may be greater than the doping concentration of the first preliminary shielding layer 310P. Additionally, the doping concentration of the second doped layer 182 may be approximately 1 × 10⁻⁶. 18 cm -3 Above and approximately 5×10 20 cm -3The material, doping type, doping concentration, etc. of the second doped layer 182 are not limited to these, and can be changed in various ways.

[0214] The third doped layer 183 may have a second conductivity type. The third doped layer 183 may be heavily doped with a second conductivity type. The second conductivity type may be p-type, but is not limited to this.

[0215] refer to Figure 24 A mask pattern MK with an opening OP is formed on the first doped layer 181 to the third doped layer 183, and the mask pattern MK is used as a mask to pattern the first doped layer 181, the second doped layer 182, the well region 133 and the first deep well region 161 to form the gate trench GT.

[0216] The mask pattern MK may have an opening OP. The opening OP may expose a first doped layer 181 and a second doped layer 182. The gate trench GT may be formed by patterning the first doped layer 181, the second doped layer 182, the well region 133, and the first deep well region 161 exposed by the opening OP.

[0217] The gate trench GT can be formed to a predetermined depth. The depth of the gate trench GT in the third direction (Z direction) can be greater than the thickness of the well region 133 in the third direction (Z direction). The depth of the gate trench GT in the third direction (Z direction) can be greater than the thickness of the first deep well region 161 in the third direction (Z direction) and the thickness of the second deep well region 162 in the third direction (Z direction).

[0218] In this configuration, at least a portion of the initial epitaxial layer 131, at least a portion of the first initial shielding layer 310P, and at least a portion of the second initial shielding layer 320P can be removed together. At least a portion of the initial well region 133P can be removed to form the well region 133. At least a portion of the first initial shielding layer 310P can be removed to form the first shielding layer 310. At least a portion of the second initial shielding layer 320P can be removed to form the second shielding layer 320. Therefore, the shielding pattern 300 can be formed. The depth of the gate trench GT in the third direction (Z direction) can be less than the thickness of the shielding pattern 300 in the third direction (Z direction).

[0219] As the gate trench GT is formed, the first deep well region 161 and the epitaxial layer 131 can be spaced apart in the first direction (X direction). In addition, as the gate trench GT is formed, the first doped layer 181 and the second doped layer 182 can be spaced apart in the first direction (X direction).

[0220] refer to Figure 25 After removing the mask pattern MK, a preliminary gate insulating layer 140P is formed in the gate trench GT.

[0221] A preliminary gate insulating layer 140P can be formed on the bottom surface and inner sidewalls of the gate trench GT. In this case, the preliminary gate insulating layer 140P can be formed together with the first doped layers 181 to the third doped layers 183. In an embodiment, the preliminary gate insulating layer 140P can be positioned on the shielding pattern 300 and the epitaxial layer 131. The lower surface of the preliminary gate insulating layer 140P can contact the shielding pattern 300 and the epitaxial layer 131. The preliminary gate insulating layer 140P can contact the well region 133 and the first deep well region 161. The preliminary gate insulating layer 140P can contact the first doped layer 181 and the second doped layer 182.

[0222] The process of forming the preliminary gate insulating layer 140P can be performed by repeating a deposition process for depositing the preliminary gate insulating layer material layer and an etching process for etching at least a portion of the preliminary gate insulating layer material layer several times. The deposition process for depositing the preliminary gate insulating layer material layer can be performed using atomic layer deposition methods, but the example embodiment is not limited thereto. Additionally, the etching process for etching at least a portion of the preliminary gate insulating layer material layer can be performed using wet etching methods, but the example embodiment is not limited thereto. For example, the preliminary gate insulating layer 140P can be formed by repeatedly forming a preliminary gate insulating layer material layer of uniform thickness and using an etching process to remove at least a portion of the preliminary gate insulating layer material layer located on the side surface of the first doped layer 181, the side surface of the well region 133, the side surface of the first deep well region 161, and the side surface of the second doped layer 182 several times, but the example embodiment is not limited thereto. Therefore, the thickness of the preliminary gate insulating layer 140P perpendicular to the surface on which the preliminary gate insulating layer 140P is formed in the first direction (X direction) can be less than its thickness in the third direction (Z direction).

[0223] refer to Figure 26 A gate electrode material layer 150P is formed within the gate trench GT. The gate electrode material layer 150P may fill the gate trench GT. The gate electrode material layer 150P may include a conductive material. For example, the gate electrode material layer 150P may include polysilicon doped with impurities. As another example, the gate electrode material layer 150P may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a combination thereof. The gate electrode material layer 150P may be formed from a single layer or multiple layers.

[0224] refer to Figure 27The gate electrode 150 is formed by removing at least a portion of the gate electrode material layer 150P positioned on the initial gate insulating layer 140P. The process of removing at least a portion of the gate electrode material layer 150P can be performed using a dry etching method, but the exemplary embodiments are not limited thereto. The gate electrode 150 may be located within a gate trench GT.

[0225] refer to Figure 28 A preliminary capping layer 142P is formed on the upper surface of the preliminary gate insulating layer 140P and the upper surface of the gate electrode 150. The preliminary capping layer 142P may cover the upper surface of the gate electrode 150. The preliminary capping layer 142P may cover the preliminary gate insulating layer 140P. The preliminary capping layer 142P may include an insulating material. For example, the preliminary capping layer 142P may include SiO2, SiOP, SiN, SiON, or combinations thereof. However, the example embodiment is not limited thereto, and the material of the preliminary capping layer 142P may be varied in various ways. The preliminary capping layer 142P may be formed of a single layer or multiple layers. The preliminary capping layer 142P may include the same material as the gate insulating layer 140 or may include a different material. When the preliminary capping layer 142P is made of the same material as the gate insulating layer 140, the boundary between the preliminary capping layer 142P and the gate insulating layer 140 may not be clearly distinguishable at the portion where the preliminary capping layer 142P and the gate insulating layer 140 contact.

[0226] refer to Figure 29 The capping layer 142 and the gate insulating layer 140 can be formed by patterning the preliminary capping layer 142P and the preliminary gate insulating layer 140P. The gate insulating layer 140 can cover at least a portion of the first doped layer 181 and at least a portion of the second doped layer 182. One side of the capping layer 142 can be aligned with one side of the gate insulating layer 140.

[0227] refer to Figure 30 A source electrode 173 is formed on the first doped layer 181 to the third doped layer 183 and the capping layer 142, and a drain electrode 175 is formed on the second surface 110b of the substrate 110, thereby forming a semiconductor device according to the embodiment.

[0228] The source electrode 173 may have an ohmic contact with the first doped layer 181 and the third doped layer 183. The source electrode 173 may include a conductive material. For example, the source electrode 173 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a combination thereof. For example, the source electrode 173 can be formed of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), and molybdenum (Mo). It can be, but is not limited to, molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. The source electrode 173 can be formed of a single layer or multiple layers.

[0229] The drain electrode 175 can have a 110-ohm contact with the substrate 173. The drain electrode 175 can include a conductive material. For example, the drain electrode 175 can include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a combination thereof. The drain electrode 175 can be made of the same material as the source electrode 173, or it can be made of a different material. The drain electrode 175 can be formed of a single layer or multiple layers.

[0230] In the following text, reference will be made to Figures 31 to 35 Methods for manufacturing semiconductor devices according to some embodiments are described.

[0231] Figures 31 to 35 It shows the method of manufacturing according to Figures 14 to 16 The method of the semiconductor device in the embodiment of the Figure 1 The cross-sectional view corresponding to A-A'.

[0232] Figures 31 to 35 The illustrated embodiments and Figures 18 to 30 The illustrated embodiments are essentially identical, so their description will be omitted and the differences will be primarily described. Additionally, the same reference numerals are used for the same components as in the previous embodiments. Figures 31 to 35 In the embodiments, with Figures 18 to 30In different embodiments, the formation of the first preliminary shielding layer after forming the second preliminary shielding layer within the epitaxial layer 131 can be omitted (see [reference]). Figure 20 The process of 310P).

[0233] refer to Figure 31 An epitaxial layer 131 is formed on the first surface 110a of the substrate 110. A second preliminary shielding layer is formed within the epitaxial layer 131 using tunneling ion implantation and / or high-energy implantation processes. A first deep well region 161, a second deep well region 162, and a well region 133 can be formed within the epitaxial layer 131. Next, a first doped layer 181 can be formed within the well region 133, and a second doped layer 182 can be formed within the first deep well region 161. Next, a mask pattern MK with openings is formed on the first doped layer 181 to the third doped layer 183, and the mask pattern MK is used as a mask to pattern the first doped layer 181, the second doped layer 182, the well region 133, and the first deep well region 161 to form a gate trench GT.

[0234] A gate trench GT can be formed to a predetermined depth. The depth of the gate trench GT in the third direction (Z direction) can be greater than the thickness of the well region 133 in the third direction (Z direction). The depth of the gate trench GT in the third direction (Z direction) can be greater than the thickness of the first deep well region 161 in the third direction (Z direction) and the thickness of the second deep well region 162 in the third direction (Z direction). At least a portion of the second preliminary shielding layer can be removed to form a second shielding layer 320. The second shielding layer 320 and the epitaxial layer 131 can be exposed by the gate trench GT. The bottom surface of the gate trench GT can be defined by the second shielding layer 320 and the epitaxial layer 131. The inner sidewall of the gate trench GT can be defined by the first doped layer 181, the well region 133, the epitaxial layer 131, the second doped layer 182, and the first deep well region 161.

[0235] refer to Figure 32 A preliminary spacer 350P can be formed within the gate trench GT. For example, the preliminary spacer 350P can be formed on the upper surface of the mask pattern MK, the inner sidewall of the gate trench GT, and the bottom surface. The preliminary spacer 350P can be conformally formed on the upper surface of the mask pattern MK, the inner sidewall of the gate trench GT, and the bottom surface. The preliminary spacer 350P can be formed on the second shielding layer 320 and the epitaxial layer 131 defining the bottom surface of the gate trench GT. The preliminary spacer 350P can be formed on the first doped layer 181, the well region 133, the epitaxial layer 131, the second doped layer 182, and the first deep well region 161 defining the inner sidewall of the gate trench GT.

[0236] The initial spacer 350P can comprise various insulating materials. The initial spacer 350P may comprise the same material as the gate insulating layer 140, but the example embodiment is not limited thereto. For example, the initial spacer 350P may comprise SiO2.

[0237] refer to Figure 33 At least a portion of the initial spacer 350P can be etched to form spacer 350. The process of etching at least a portion of the initial spacer 350P can be performed using a dry etching method, but the example embodiment is not limited thereto. A portion of the initial spacer 350P positioned on the bottom surface of the gate trench GT and a portion of the initial spacer 350P positioned on the upper surface of the mask pattern MK can be removed to form spacer 350. Therefore, a portion of the second shielding layer 320 and a portion of the epitaxial layer 131 forming the bottom surface of the gate trench GT can be exposed. In this case, spacer 350 can be positioned on the inner surface of the gate trench GT. The inner surface of the gate trench GT may not be exposed by spacer 350.

[0238] refer to Figure 34 The first shielding layer 310_1 can be formed within the exposed second shielding layer 320 and epitaxial layer 131 using tunneling ion implantation and / or high-energy implantation processes.

[0239] The first shielding layer 310_1 may be formed below the gate trench GT. The first shielding layer 310_1 may be formed between the gate trench GT and the epitaxial layer 131 and between the gate trench GT and the second shielding layer 320. The first shielding layer 310_1 may protrude from the bottom surface of the gate trench GT toward the first surface 110a of the substrate 110.

[0240] The first shielding layer 310_1 may overlap with the gate trench GT in the third direction (Z direction). For example, the entire first shielding layer 310_1 may overlap with the gate trench GT in the third direction (Z direction), but the example embodiment is not limited thereto. The first shielding layer 310_1 does not overlap with the first deep well region 161 and the well region 133 in the third direction (Z direction). At least a portion of the first shielding layer 310_1 may overlap with the second shielding layer 320 in the third direction (Z direction). For example, a portion of the first shielding layer 310_1 may overlap with the second shielding layer 320 in the third direction (Z direction), and the remaining portion may not overlap with the second shielding layer 320 in the third direction (Z direction). The lower surface of the first shielding layer 310_1 may contact the second shielding layer 320 and the epitaxial layer 131, but the example embodiment is not limited thereto.

[0241] The width of the first shielding layer 310_1 along the first direction (X direction) can be less than the width of the gate trench GT along the first direction (X direction). This is because the first shielding layer 310_1 is formed within the portion of the epitaxial layer 131 exposed by the spacer 350 and the portion of the second shielding layer 320. However, the exemplary embodiment is not limited to this, and the width of the first shielding layer 310_1 along the first direction (X direction) can be greater than or equal to the width of the gate trench GT along the first direction (X direction).

[0242] Therefore, even when the gate trench GT is formed such that it does not overlap with the shielding pattern 300_1 in the third direction (Z direction) due to misalignment, the first shielding layer 310_1 can still be formed below the gate trench GT. Thus, the shielding pattern 300 can prevent the transistor's breakdown voltage from decreasing due to the electric field generated by the voltage applied to the gate electrode 150, and can improve the reliability of the semiconductor device according to the embodiment.

[0243] Because the inner sidewalls of the gate trench GT are not exposed by the spacer 350, the components including the inner sidewalls of the gate trench GT can be left undoped. For example, in the process of forming the second shielding layer 320, ions can be prevented from being implanted into the well region 133 due to the spacer 350.

[0244] refer to Figure 35 The spacer 350 and the mask pattern MK can be removed. In this case, at least a portion of the spacer 350 located within the gate trench GT can be retained without being removed to form Figure 16 The dummy pattern of the embodiment (see Figure 16 355). Dummy pattern (see 355). Figure 16 (355) can be a pattern in which at least a portion of the spacer 350 is not removed during the process of removing the spacer 350 located in the gate trench GT.

[0245] Next, a gate insulating layer 140 can be formed on the bottom surface and inner sidewalls of the gate trench GT, and a gate electrode 150 can be formed within the gate trench GT. Next, a capping layer 142 can be formed on the gate electrode 150, a source electrode 173 can be formed on the first doped layers 181 to the third doped layers 183 and the capping layer 142, and a drain electrode 175 can be formed on the second surface 110b of the substrate 110, thereby forming a structure according to... Figures 14 to 16 The semiconductor device of the embodiment.

[0246] Although the embodiments have been described in detail above, the scope of the invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the invention as defined in the appended claims also fall within the scope of the invention.

Claims

1. A semiconductor device, the semiconductor device comprising: The substrate includes a first surface and a second surface that are opposite to each other; An epitaxial layer, the epitaxial layer being positioned on the first surface of the substrate and including a gate trench, the epitaxial layer having a first conductivity type; A gate electrode, wherein the gate electrode is positioned within the gate trench; A gate insulating layer, wherein the gate insulating layer is positioned between the epitaxial layer and the gate electrode; A source electrode, wherein the source electrode is positioned on the epitaxial layer; A well region is located on the first side of the gate electrode, between the epitaxial layer and the source electrode, and has a second conductivity type different from the first conductivity type; A first deep well region is located on a second side of the gate electrode opposite to the first side, between the epitaxial layer and the source electrode, has the second conductivity type, and extends a greater distance below the source electrode compared to the well region. A shielding pattern is positioned between the epitaxial layer and the first deep well region, and the shielding pattern overlaps with the gate electrode; as well as A drain electrode, wherein the drain electrode is positioned on the second surface of the substrate; The lower surface of the shielding pattern includes a convex curved surface that protrudes toward the drain electrode.

2. The semiconductor device according to claim 1, in, The doping concentration in the first deep well region is greater than the doping concentration in the well region.

3. The semiconductor device according to claim 2, in, The maximum thickness of the first deep well region in the vertical direction is greater than the maximum thickness of the well region in the vertical direction.

4. The semiconductor device according to claim 2, in, The shielding pattern has the second conductivity type, and The doping concentration of the shielding pattern is greater than or equal to the doping concentration of the first deep well region.

5. The semiconductor device according to claim 1, in, The thickness of the shielding pattern in the vertical direction is greater than the thickness of the well region in the vertical direction, and The thickness of the shielding pattern in the vertical direction is less than the distance between the first deep well region and the drain electrode.

6. The semiconductor device according to claim 1, in, The shielding pattern is in contact with the lower surface of the gate insulating layer and the lower surface of the first deep well region.

7. The semiconductor device according to claim 1, in, The shielding pattern includes: A first shielding layer, positioned on the lower surface of the gate insulating layer and the lower surface of the first deep well region, the first shielding layer having the second conductivity type; and A second shielding layer is positioned between the first shielding layer and the epitaxial layer, and the second shielding layer has the second conductivity type; The lower surface of the second shielding layer includes a convex curved surface that protrudes toward the drain electrode.

8. The semiconductor device according to claim 7, in, The lower surface of the first shielding layer includes a convex curved surface protruding toward the drain electrode, and The curvature of the lower surface of the second shielding layer is greater than the curvature of the lower surface of the first shielding layer.

9. The semiconductor device according to claim 7, in, The first shielding layer is in contact with at least a portion of the side surface of the gate insulating layer.

10. The semiconductor device according to claim 7, in, At least a portion of the first shielding layer overlaps with the gate electrode in the horizontal direction.

11. The semiconductor device according to claim 7, in, The edge of the first shielding layer is aligned with the side surface of the gate insulating layer.

12. The semiconductor device according to claim 7, in, The width of the first shielding layer is greater than the width of the first deep well region.

13. The semiconductor device according to claim 1, in, The gate insulating layer includes: A vertical portion, positioned between the well region and the gate electrode and between the first deep well region and the gate electrode, and having a first thickness in a first direction parallel to the first surface of the substrate; and A horizontal portion, positioned between the shielding pattern and the gate electrode, and having a second thickness in a second direction perpendicular to the first surface of the substrate. Wherein, the first thickness is less than the second thickness.

14. The semiconductor device according to claim 1, further comprising: A first doped layer is located between the well region and the source electrode, and the first doped layer has the first conductivity type; as well as A second doped layer is positioned between the first deep well region and the source electrode, and the second doped layer has the second conductivity type.

15. The semiconductor device of claim 14, further comprising: A second deep well region is located between the epitaxial layer and the source electrode, and the second deep well region has the second conductivity type. as well as A third doped layer is positioned between the second deep well region and the source electrode. The well region is located between the gate insulating layer and the second deep well region.

16. A semiconductor device, the semiconductor device comprising: The substrate includes a first surface and a second surface that are opposite to each other; An epitaxial layer, positioned on the first surface of the substrate, including a gate trench and having a first conductivity type; A gate electrode, wherein the gate electrode is positioned within the gate trench; A gate insulating layer, wherein the gate insulating layer is positioned between the epitaxial layer and the gate electrode; A source electrode, wherein the source electrode is positioned on the epitaxial layer; A well region is located on the first side of the gate electrode, between the epitaxial layer and the source electrode, and has a second conductivity type different from the first conductivity type; A first deep well region is located on a second side of the gate electrode opposite to the first side and between the epitaxial layer and the source electrode, and the first deep well region has the second conductivity type. A second deep well region is located between the epitaxial layer and the source electrode and on a first side of the well region, and the second deep well region has the second conductivity type. A first doped layer is positioned between the well region and the source electrode, and the first doped layer has the first conductivity type; A second doped layer is positioned between the first deep well region and the source electrode, and the second doped layer has the second conductivity type. A third doped layer is positioned between the second deep well region and the source electrode; A shielding pattern, wherein the shielding pattern is positioned between the epitaxial layer and the first deep well region, and the shielding pattern has the second conductivity type; as well as A drain electrode, wherein the drain electrode is positioned on the second surface of the substrate; Wherein, the width of the shielding pattern is greater than or equal to the width of the first deep well region, and The doping concentration of the shielding pattern is greater than or equal to the doping concentration of the first deep well region.

17. The semiconductor device according to claim 16, in, The doping concentration in the first deep well region and the doping concentration in the second deep well region are greater than the doping concentration in the well region.

18. The semiconductor device according to claim 16, in, The distance between the lower surface of the first deep well region and the first surface of the substrate is less than the distance between the lower surface of the well region and the first surface of the substrate.

19. The semiconductor device according to claim 16, in, The shielding pattern overlaps with the gate electrode but not with the well region.

20. A semiconductor device, said semiconductor device comprising: A substrate, the substrate comprising an active region in which a plurality of cells are located and a peripheral region surrounding at least a portion of the active region; as well as A gate frame, positioned in the peripheral region, includes a first portion and a second portion, the first portion and the second portion extending in a first direction and arranged to be spaced apart in a second direction intersecting the first direction. The plurality of units are positioned between the first portion and the second portion of the gate frame. Each of the plurality of units includes: An epitaxial layer, the epitaxial layer including a gate trench positioned on a first surface of the substrate and extending in a second direction, the epitaxial layer having a first conductivity type; A gate electrode, wherein the gate electrode is positioned within the gate trench and electrically connected to the gate frame; A gate insulating layer, wherein the gate insulating layer is positioned between the epitaxial layer and the gate electrode; A source electrode, wherein the source electrode is positioned on the epitaxial layer; A well region is located on a first side of the gate electrode along the first direction and between the epitaxial layer and the source electrode, the well region having a second conductivity type different from the first conductivity type; A first deep well region is located on a second side of the gate electrode opposite to the first side along the first direction and between the epitaxial layer and the source electrode, and the first deep well region has the second conductivity type. A shielding pattern, positioned between the epitaxial layer and the first deep well region, extending in the second direction and overlapping the gate electrode; and A drain electrode, wherein the drain electrode is positioned on a second surface of the substrate opposite to the first surface. The lower surface of the shielding pattern includes a convex curved surface that protrudes toward the drain electrode.

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