Semiconductor structure and method of manufacturing the same

Abstract

This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; a dielectric layer disposed on the substrate; an optical waveguide structure disposed within the dielectric layer; a cavity surrounding the optical waveguide structure; and a dielectric layer, including a first dielectric layer disposed on the cavity wall. This semiconductor structure can reduce the risk of corrosion by moisture.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the increasing demand for optical communication, network data transmission and processing, silicon photonics technology has become one of the important technical solutions in the field of communication. Silicon photonic devices are compatible with existing CMOS (Complementary Metal Oxide Semiconductor) standard processes and can be integrated with microelectronic circuits in integrated circuits. They have attracted widespread attention due to their small size, low cost, and excellent performance.

[0003] One of the key indicators of silicon photonic chips is optical loss. Currently, edge coupling is a common method for coupling optical signals from optical fibers into the chip waveguide in silicon photonic chips. However, semiconductor structures are currently susceptible to corrosion by moisture. Summary of the Invention

[0004] The semiconductor structure and its fabrication method provided in this application aim to solve the problem that semiconductor structures are easily corroded by moisture.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a semiconductor structure, the semiconductor structure comprising: a substrate; a dielectric layer disposed on the substrate; an optical waveguide structure disposed within the dielectric layer; a cavity disposed around the optical waveguide structure; and a dielectric layer, including a first dielectric layer disposed on the cavity wall of the cavity.

[0006] In one embodiment of this application, the semiconductor structure includes an optical coupling region; the optical waveguide structure is disposed in the optical coupling region; the dielectric layer further includes a second dielectric layer, which is located in the optical coupling region and disposed on the side surface of the dielectric layer opposite to the substrate.

[0007] In one embodiment of this application, the thickness of the first dielectric layer and / or the second dielectric layer is greater than or equal to 20 nm and less than 100 nm.

[0008] In one embodiment of this application, the semiconductor structure further includes a non-optically coupled region;

[0009] The dielectric layer further includes a third dielectric layer, which is located in the non-optically coupled region and is disposed on the side surface of the dielectric layer opposite to the substrate.

[0010] In one embodiment of this application, the thickness of the third dielectric layer is greater than the thickness of the first dielectric layer; and / or the thickness of the third dielectric layer is greater than the thickness of the second dielectric layer.

[0011] In one embodiment of this application, the dielectric layer further includes a fourth dielectric layer, which is at least disposed on the side surface of the second dielectric layer opposite to the dielectric layer, and the sum of the thickness of the second dielectric layer and the thickness of the fourth dielectric layer is less than the thickness of the third dielectric layer.

[0012] In one embodiment of this application, the thickness of the third dielectric layer is greater than or equal to 100 nm and less than or equal to 400 nm.

[0013] In one embodiment of this application, the material of the third dielectric layer includes silicon nitride and / or aluminum oxide; and / or the material of the first dielectric layer and / or the second dielectric layer includes silicon nitride and / or aluminum oxide.

[0014] In one embodiment of this application, the cavities are continuously distributed along the circumferential direction of the optical waveguide structure.

[0015] In one embodiment of this application, the cavity surrounds 50%-90% of the optical waveguide structure along the circumferential direction of the optical waveguide structure.

[0016] In one embodiment of this application, the cavity extends at least from the side surface of the dielectric layer away from the substrate to the side surface of the dielectric layer facing the substrate.

[0017] In one embodiment of this application, the cavity extends from the side surface of the dielectric layer opposite to the substrate into the substrate.

[0018] In one embodiment of this application, the substrate includes an SOI substrate, the SOI substrate including a bottom semiconductor layer, a buried oxide layer and a top semiconductor layer stacked sequentially; the top semiconductor layer faces the dielectric layer; the cavity penetrates at least the dielectric layer or the top semiconductor layer or the buried oxide layer.

[0019] In one embodiment of this application, the cavity has a bottom wall and a side wall; the first medium layer is disposed on the bottom wall and the side wall of the cavity.

[0020] In one embodiment of this application, the width of the cavity is 8μm-15μm.

[0021] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a method for fabricating a semiconductor structure, the method comprising: providing a semiconductor substrate; the semiconductor substrate comprising a substrate and a dielectric layer disposed on the substrate, wherein an optical waveguide structure is disposed within the dielectric layer; forming a cavity in the semiconductor substrate, the cavity surrounding the optical waveguide structure; and disposing a first dielectric layer on the cavity wall.

[0022] In one embodiment of this application, the semiconductor substrate includes an optical coupling region; prior to the step of forming a cavity in the semiconductor substrate, the method further includes:

[0023] A third dielectric layer is disposed on the surface of the dielectric layer facing away from the substrate;

[0024] The third dielectric layer located in the optical coupling region is etched, and the etched third dielectric layer serves as the second dielectric layer disposed on the dielectric layer.

[0025] In one embodiment of this application, the step of forming a first dielectric layer on the cavity wall includes:

[0026] Dielectric materials are respectively deposited on the surface of the third dielectric layer and the second dielectric layer opposite to the semiconductor substrate and on the cavity wall using the same process;

[0027] Along the thickness direction of the semiconductor substrate, at least a portion of the dielectric material on the side surface of the third dielectric layer and the second dielectric layer facing away from the semiconductor substrate is removed to form the first dielectric layer at least on the cavity wall of the cavity.

[0028] In one embodiment of this application, a maskless etching process is used to etch at least a portion of the dielectric material on the side surface of the third dielectric layer and the second dielectric layer opposite to the semiconductor substrate.

[0029] In one embodiment of this application, the thickness of the third dielectric layer is greater than or equal to 100 nm and less than or equal to 400 nm; the thickness of the first dielectric layer is greater than or equal to 20 nm and less than 100 nm.

[0030] The beneficial effects of this application embodiment, which differ from the prior art, are as follows: The semiconductor structure provided in this application embodiment includes a substrate, a dielectric layer, an optical waveguide structure, and a cavity, wherein the cavity is disposed around the optical waveguide structure. Since the refractive index of the coupling medium within the cavity is much lower than that of the dielectric layer, light entering the high-refractive-index dielectric layer is difficult to diffuse into the low-refractive-index cavity. The cavity helps to limit light dispersion, allowing the optical signal to be coupled into the optical waveguide structure as much as possible, reducing the probability of the optical signal coupling into the substrate. Therefore, the cavity helps to reduce the loss caused by refraction during light propagation, and correspondingly reduces the probability of light loss from the substrate during propagation, thereby improving optical coupling efficiency and thus improving the performance of the semiconductor structure. Furthermore, by providing a first dielectric layer on the cavity wall, this semiconductor structure effectively reduces the risk of external moisture eroding the dielectric layer through the cavity wall; thereby reducing the risk of light field distortion and increased coupling loss due to moisture erosion altering the refractive index of the dielectric layer and the cavity. Meanwhile, the absorption loss of water when moisture enters the semiconductor structure can also lead to failure of the semiconductor structure during the reliability process; therefore, this application effectively improves the reliability of the semiconductor structure while improving the waterproof performance. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of a semiconductor structure provided in another embodiment of this application;

[0033] Figure 3 A top view of the optical coupling region of a semiconductor structure provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of a semiconductor structure provided in yet another embodiment of this application;

[0035] Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0036] Figure 6 A schematic diagram of the structure of a semiconductor substrate is provided for one embodiment of this application;

[0037] Figures 7 to 10 This is a structural diagram corresponding to the specific implementation process of step S2.

[0038] Explanation of reference numerals in the attached figures

[0039] 1 Substrate; 2 Dielectric layer; 3 Optical waveguide structure; 4 Cavity; 5 Dielectric layer; 50 Dielectric material; 51 First dielectric layer; 52 Second dielectric layer; 53 Third dielectric layer; 54 Fourth dielectric layer; 6 Interconnect structure; A Optical coupling region; B Non-optical coupling region. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0041] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0042] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0043] Edge couplers for silicon photonic chips are crucial components for achieving optical coupling between optical fibers and the chip. Currently, edge couplers typically employ deep trench etching processes for air isolation. Since the refractive index of air is much lower than that of the silicon oxide dielectric layer, coupling loss can be significantly reduced.

[0044] However, using air as a protective layer increases the risk of moisture erosion of the silicon oxide dielectric layer. Moisture erosion not only changes the refractive index of silicon oxide but also the refractive index of the air medium, thus distorting the light field and increasing light coupling loss. At the same time, moisture entering the semiconductor structure also introduces water absorption loss, all of which can lead to the failure of silicon photonics chips in terms of reliability.

[0045] In some embodiments, a silicon nitride dielectric layer of several hundred nanometers is disposed on the surface of the semiconductor structure. The silicon nitride dielectric layer has a strong ability to prevent the diffusion of impurity ions or other contaminants and water vapor penetration, and has good chemical stability and good anti-oxidation and anti-corrosion properties.

[0046] In some embodiments, a novel semiconductor structure and its fabrication method are provided, which can reduce the risk of semiconductor structure being corroded by moisture and further improve the problem of increased light coupling loss due to the large thickness of the dielectric layer, so that the semiconductor structure can have low coupling loss performance while ensuring a certain moisture protection effect.

[0047] The following is a detailed description with reference to the accompanying drawings and embodiments.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application. In this embodiment, a semiconductor structure is provided, including an optically coupled region A and a non-optically coupled region B; the non-optically coupled region B may be disposed around the optically coupled region A. The semiconductor structure includes a substrate 1, a dielectric layer 2, an optical waveguide structure 3, a cavity 4, and a dielectric layer 5.

[0049] In this embodiment, substrate 1 serves as a process platform for the formation of semiconductor structures. In this embodiment, the material of substrate 1 is silicon. In other embodiments, the material of substrate 1 may also be germanium, silicon germanide, silicon carbide, silicon arsenide, or indium gallium phosphate, etc. Substrate 1 may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0050] In some embodiments, substrate 1 includes an SOI (Silicon-On-Insulator) substrate, which includes a bottom semiconductor layer, a buried oxide layer, and a top semiconductor layer stacked sequentially. The top and bottom semiconductor layers can be silicon, and the buried oxide layer can be silicon oxide or silicon oxynitride.

[0051] The dielectric layer 2 is disposed on the substrate 1 to achieve electrical isolation between various devices or components, and also to protect the components located inside it. As an example, the material of the dielectric layer 2 includes silicon oxide. In some embodiments, the dielectric layer 2 is disposed on the side of the top semiconductor layer opposite to the buried oxide layer.

[0052] An optical waveguide structure 3 is disposed within the dielectric layer 2 and located in the optical coupling region A, for coupling and transmission of optical signals. The optical waveguide structure 3 and the substrate 1 are spaced apart along the stacking direction Y of the semiconductor structure.

[0053] As an example, the optical waveguide structure 3 and the substrate 1 are isolated by a dielectric layer 2 of a certain thickness to increase the distance between the optical waveguide structure 3 and the substrate 1 along the stacking direction Y of the semiconductor structure, thereby reducing the probability of optical signals being coupled into the substrate 1.

[0054] In some embodiments, the material of the optical waveguide structure 3 includes silicon nitride. Compared with silicon waveguides, silicon nitride waveguides have higher optical power tolerance and lower transmission loss, and are temperature insensitive, resulting in less optical loss. Therefore, using silicon nitride material is beneficial to improving the performance of silicon optical devices.

[0055] In other embodiments, the material of the optical waveguide structure 3 may also include at least one of silicon, silicon oxide, or silicon oxynitride.

[0056] Cavity 4 is located in optical coupling region A and is disposed around optical waveguide structure 3. In some embodiments, cavity 4 is disposed around the circumferential direction of optical waveguide structure 3, and cavity 4 extends from the side surface of dielectric layer 2 away from substrate 1 to the side of optical waveguide structure 3 facing substrate 1.

[0057] In some embodiments, the cavity 4 extends at least from the side surface of the dielectric layer 2 away from the substrate 1 to the side surface of the dielectric layer 2 facing the substrate 1.

[0058] In other embodiments, see Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure provided in another embodiment of this application; and Figure 1 The difference in the structure shown is that the cavity 4 extends further into the substrate 1. Since the refractive index of the coupling medium in the cavity 4 is lower than that of the substrate 1 and the dielectric layer 2, extending the cavity 4 into the substrate 1 helps to reduce the probability of light scattering outward through the substrate 1 during propagation, thereby improving the optical coupling efficiency. This allows the optical waveguide structure 3 to transmit optical signals more efficiently, thus improving the performance of the semiconductor structure.

[0059] In some embodiments, the cavity 4 extends into the substrate 1 and penetrates at least the top semiconductor layer or buried oxide layer of the dielectric layer 2 or SOI substrate. The depth of the portion of the cavity 4 extending into the substrate 1 can be 100-200 μm.

[0060] Cavity 4 can be an air cavity; the coupling medium in the air cavity is air; of course, in other embodiments, the coupling medium in cavity 4 can also be other gases.

[0061] Since the refractive index of the coupling medium in cavity 4 is much lower than that of dielectric layer 2, light entering the high-refractive-index dielectric layer 2 is difficult to diffuse into the low-refractive-index cavity 4. Cavity 4 helps to limit the outward diffusion of light, so that the optical signal is coupled into the optical waveguide structure 3 as much as possible, reducing the probability of the optical signal being coupled into the substrate 1. Therefore, cavity 4 helps to reduce the loss caused by refraction during light propagation, and correspondingly helps to reduce the probability of light loss from the substrate 1 during propagation, thereby improving the optical coupling efficiency and thus improving the performance of the semiconductor structure.

[0062] In some embodiments, see Figure 3 , Figure 3 This is a top view of the optical coupling region A of a semiconductor structure provided in an embodiment of this application; the cavity 4 extends along the circumferential direction of the optical waveguide structure 3, and the cavity 4 is continuously distributed along the circumferential direction of the optical waveguide structure 3. The cavity 4 surrounds 50%-90% of the optical waveguide structure 3 along the circumferential direction; therefore, the surrounding in this application can be a 360-degree all-around surrounding or a partial surrounding. In other words, the orthographic projection of the cavity 4 onto the optical waveguide structure 3 along a direction perpendicular to the stacking direction Y of the semiconductor structure is the first orthographic projection. The ratio of the length of the first orthographic projection along the circumferential direction of the optical waveguide structure 3 to the circumference of the optical waveguide structure 3 along the circumferential direction is 0.5-0.9; for example, 0.5, 0.6, 0.7, 0.8, or 0.9, etc.

[0063] The size of cavity 4 should not be too small or too large. If the size of cavity 4 is too small, its contribution to reducing coupling loss will be small. If the size of cavity 4 is too large, it may adversely affect the mechanical strength of the remaining dielectric layer 2. Therefore, in this embodiment, the width W0 of cavity 4 is 8 micrometers to 15 micrometers; for example, W0 is 8 micrometers, 10 micrometers, 12 micrometers, or 15 micrometers, etc. Here, the size of cavity 4 refers to the width of cavity 4.

[0064] The orthographic projection of cavity 4 onto substrate 1 can be arc-shaped or zigzag-shaped.

[0065] The above scheme can reduce the risk of the optical waveguide structure 3 falling off the dielectric layer 2 and allow light to enter the non-optical coupling region B through the dielectric layer 2; and compared with the scheme of the cavity 4 including multiple spaced air sub-cavities, it can maximize the area of ​​the cavity 4 to better limit the outward spread of light and reduce the coupling loss of light.

[0066] Of course, in other embodiments, the cavity 4 may also include multiple air sub-cavities, which are spaced apart along the circumferential direction of the optical waveguide structure 3. This is beneficial for ensuring that the dielectric layer 2 above the optical waveguide structure 3 has sufficient mechanical strength, reducing the probability of collapse of the optical waveguide structure 3 and the dielectric layer 2 above it. In addition, it is beneficial for improving the etching uniformity during the formation of the cavity 4, which not only improves the formation quality of the cavity 4 but also reduces the impact on the surrounding area of ​​the dielectric layer 2.

[0067] The orthographic projection of each air sub-cavity onto the optical waveguide structure 3 along a direction perpendicular to the stacking direction Y of the semiconductor structure is called the second orthographic projection. The ratio of the sum of the lengths of the multiple second orthographic projections corresponding to the multiple air sub-cavities along the circumferential direction of the optical waveguide structure 3 to the circumference of the optical waveguide structure 3 along the circumferential direction is 0.5-0.9; for example, 0.5, 0.6, 0.7, 0.8 or 0.9, etc.; of course, in some embodiments it can also be greater than 0.9 and less than 1.

[0068] In some embodiments, the width of the air sub-cavity is 8 to 15 micrometers; for example, 8 micrometers, 10 micrometers, 12 micrometers, or 15 micrometers, etc.

[0069] The orthographic projection of the air sub-cavity onto substrate 1 can be rectangular, circular, arc-shaped, or elongated, etc. If the orthographic projection of the air sub-cavity onto substrate 1 is rectangular, the size of the air sub-cavity refers to the size of its shorter side. If the orthographic projection of the air sub-cavity onto substrate 1 is circular, the size of the air sub-cavity refers to its radial dimension.

[0070] The dielectric layer 5 protects the surface of the dielectric layer 2 to reduce the risk of moisture penetration into the dielectric layer 2. The dielectric layer 5 includes a first dielectric layer 51 and a second dielectric layer 52, with the first dielectric layer 51 disposed on the cavity wall of the cavity 4. In some embodiments, the cavity 4 has a bottom wall and a side wall, with the first dielectric layer 51 disposed on both the bottom wall and side wall of the cavity to improve the waterproofing effect of the cavity 4. Since the cavity 4 is relatively deep, external moisture generally has difficulty penetrating the dielectric layer 2 through the bottom wall of the cavity 4. Therefore, in some other embodiments, the first dielectric layer 51 may not be disposed on the bottom wall of the cavity 4. This allows for the use of maskless etching (Blanket etch) to form the first dielectric layer 51 on the side wall of the cavity 4 during the fabrication of the semiconductor structure, resulting in higher fabrication efficiency and lower cost.

[0071] The second dielectric layer 52 is located in the optical coupling region A and is disposed on the side surface (i.e., the top surface) of the dielectric layer 2 away from the substrate 1.

[0072] In this way, the cavity wall of the cavity 4 can be protected by the first dielectric layer 51, and the top surface of the dielectric layer 2 located in the optical coupling region A can be protected by the second dielectric layer 52. This effectively reduces the risk of external water vapor eroding the dielectric layer 2 through the cavity wall of the cavity 4 and the top surface of the dielectric layer 2. Furthermore, it reduces the risk of water vapor erosion altering the refractive index of the dielectric layer 2 and the cavity 4, leading to optical field distortion and increased coupling loss. Simultaneously, since water vapor entering the semiconductor structure also introduces water absorption losses, these factors can cause the semiconductor structure to fail during reliability testing. Therefore, this application effectively improves the reliability of the semiconductor structure while enhancing waterproof performance.

[0073] The dielectric layer 5 further includes a third dielectric layer 53, which is located in the non-optical coupling region B and is disposed on the side surface of the dielectric layer 2 away from the substrate 1. The thickness of the first dielectric layer 51 is less than the thickness of the third dielectric layer 53; and / or the thickness of the second dielectric layer 52 is less than the thickness of the third dielectric layer 53.

[0074] In this way, the thicker third dielectric layer 53 can reduce the risk of impurity ions, water vapor, or other contaminants penetrating into the dielectric layer 2 of the non-optical coupling region B, thereby improving the oxidation and corrosion resistance of the non-optical coupling region B of the semiconductor structure. The thinner first dielectric layer 51 and second dielectric layer 52 can also protect the surface of the dielectric layer 2 of the optical coupling region A, reducing the risk of water vapor erosion of the dielectric layer 2 of the optical coupling region A. Furthermore, because the first dielectric layer 51 and second dielectric layer 52 are thinner, the amount of light entering the first dielectric layer 51 and second dielectric layer 52 is reduced, resulting in a smaller impact on the light field and effectively reducing light coupling loss. This allows the semiconductor structure to possess both good water vapor erosion resistance and low coupling loss performance.

[0075] In some embodiments, the second dielectric layer 52 and the third dielectric layer 53 may be integral; during the preparation of the second dielectric layer 52 and the third dielectric layer 53, the second dielectric layer 52 and the third dielectric layer 53 may be formed in a common deposition step, but they may undergo different treatments in subsequent etching steps.

[0076] In some embodiments, the thickness H3 of the third dielectric layer 53 is greater than or equal to 100 nm and less than or equal to 400 nm; for example, H3 is 100 nm, 200 nm, 300 nm, or 400 nm. The thickness H1 of the first dielectric layer 51 and the thickness H2 of the second dielectric layer 52 may be equal or unequal. The thickness H1 of the first dielectric layer 51 and / or the thickness H2 of the second dielectric layer 52 is greater than or equal to 20 nm and less than 100 nm; for example, H1 and / or H2 is 20 nm, 40 nm, 60 nm, or 80 nm.

[0077] As an example, the thickness H3 of the third dielectric layer 53 is 400 nm; the thickness H1 of the first dielectric layer 51 and / or the thickness H2 of the second dielectric layer 52 is 50 nm.

[0078] In this way, the third dielectric layer 53 can protect the surface of the dielectric layer 2 in the non-optical coupling region B, thereby reducing the risk of moisture erosion of the dielectric layer 2 in the non-optical coupling region B. At the same time, the first dielectric layer 51 and / or the second dielectric layer 52 protect the dielectric layer 2 in the optical coupling region A, thereby reducing the risk of moisture erosion of the dielectric layer 2 in the optical coupling region A; moreover, the thickness of the first dielectric layer 51 and / or the second dielectric layer 52 can reduce the entry of light, have a smaller impact on the optical field, and effectively reduce the coupling loss caused by the first dielectric layer 51 and / or the second dielectric layer 52.

[0079] In some embodiments, see Figure 4 , Figure 4 This is a schematic diagram of a semiconductor structure provided in another embodiment of this application; the dielectric layer 5 further includes a fourth dielectric layer 54, which is disposed at least on the surface of the second dielectric layer 52 opposite to the dielectric layer 2, and the sum of the thickness H2 of the second dielectric layer 52 and the thickness H4 of the fourth dielectric layer 54 is less than the thickness H3 of the third dielectric layer 53; in order to minimize the amount of light entering the second dielectric layer 52 and the fourth dielectric layer 54, thereby reducing optical coupling loss. The material of the fourth dielectric layer 54 can be the same as the material of the second dielectric layer 52 and the third dielectric layer 53.

[0080] The sum of the thickness H2 of the second dielectric layer 52 and the thickness H4 of the fourth dielectric layer 54 can be greater than or equal to 20 nm and less than 100 nm; for example, the sum of the thickness H2 of the second dielectric layer 52 and the thickness H4 of the fourth dielectric layer 54 can be 20 nm, 40 nm, 60 nm or 80 nm.

[0081] In this embodiment, the sum of the thickness H2 of the second dielectric layer 52 and the thickness H4 of the fourth dielectric layer 54 may be equal to or unequal to the thickness H1 of the first dielectric layer 51.

[0082] In one specific embodiment, the fourth dielectric layer 54 is also disposed on the side surface of the third dielectric layer 53 facing away from the dielectric layer 2; in order to improve the waterproof performance of the dielectric layer 5 to the dielectric layer 2 in the non-optical coupling region B and reduce the risk of the dielectric layer 2 in the non-optical coupling region B being eroded by water vapor.

[0083] Silicon nitride possesses strong resistance to the diffusion of impurity ions or other contaminants and to water vapor penetration, as well as good chemical stability, oxidation resistance, and corrosion resistance. Therefore, in some embodiments, the first dielectric layer 51, the second dielectric layer 52, and / or the third dielectric layer 53 are made of silicon nitride. As an example, the third dielectric layer 53, the second dielectric layer 52, and the first dielectric layer 51 are all silicon nitride layers.

[0084] Of course, in other embodiments, the materials of the first dielectric layer 51, the second dielectric layer 52, and / or the third dielectric layer 53 may also include aluminum oxide. Alternatively, the materials of the first dielectric layer 51, the second dielectric layer 52, and / or the third dielectric layer 53 may include silicon nitride and aluminum oxide. Alternatively, some of the dielectric layers in the first dielectric layer 51, the second dielectric layer 52, and the third dielectric layer 53 may be made of silicon oxide, and some of the dielectric layers may be made of aluminum oxide.

[0085] In some embodiments, see Figure 1 or Figure 2 The semiconductor structure also includes an interconnect structure 6, which is disposed within the dielectric layer 2 and located in the non-optically coupled region B. The interconnect structure 6 is used for electrical connections between devices and / or wiring, etc. In some embodiments, the interconnect structure 6 is used for electrical connections between devices, thereby powering a specific device through the interconnect structure 6.

[0086] As an example, the material of interconnect structure 6 is copper. In other embodiments, the material of the interconnect structure may also be other conductive materials, such as aluminum, tungsten, etc.

[0087] The semiconductor structure provided in this embodiment includes a cavity 4 surrounding an optical waveguide structure 3. Since the refractive index of the coupling medium within the cavity 4 is much lower than that of the dielectric layer 2, light entering the high-refractive-index dielectric layer 2 is difficult to diffuse into the low-refractive-index cavity 4. The cavity 4 effectively restricts light outward dispersion, allowing the optical signal to couple into the optical waveguide structure 3 as much as possible, reducing the probability of the optical signal coupling into the substrate 1. Therefore, the cavity 4 helps reduce losses caused by refraction during light propagation, correspondingly reducing the probability of light loss from the substrate 1 during propagation, thereby improving optical coupling efficiency and ultimately improving the performance of the semiconductor structure. Furthermore, the semiconductor structure also includes a dielectric layer 5, which includes a first dielectric layer 51. The first dielectric layer 51 is disposed on the cavity wall of the cavity 4 to protect the cavity wall, effectively reducing the risk of external moisture eroding the dielectric layer 2 through the cavity wall; thus reducing the risk of moisture erosion altering the refractive indices of the dielectric layer 2 and the cavity 4, leading to optical field distortion and increased coupling loss. Meanwhile, moisture entering the semiconductor structure also introduces water absorption losses, which can lead to failure of the semiconductor structure during reliability testing. Therefore, this application effectively improves the reliability of the semiconductor structure while enhancing waterproof performance. No prior art has a solution where the first dielectric layer 51 is located on the sidewall of the cavity 4. This is because forming a dielectric layer on the sidewall typically increases the overall thickness of the dielectric layer, thus affecting device performance. This application effectively overcomes this limitation, especially in the field of silicon photonics, where sensitivity to moisture is even greater. The proposed solution further effectively prevents moisture erosion while ensuring device performance, discovering problems previously undiscovered in the field, and overcoming existing biases.

[0088] See Figure 5 , Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. In this embodiment, a method for fabricating a semiconductor structure is provided, which can be used to fabricate the semiconductor structure provided in any of the above embodiments. The method includes:

[0089] Step S1: Provide a semiconductor substrate; the semiconductor substrate includes a substrate 1 and a dielectric layer 2 disposed on the substrate 1, and an optical waveguide structure 3 is disposed in the dielectric layer 2.

[0090] See Figure 6 , Figure 6 A schematic diagram of a semiconductor substrate is provided for one embodiment of this application. The semiconductor substrate includes an optical coupling region A and a non-optical coupling region B. The substrate 1 provides a process platform for subsequent processes. The optical waveguide structure 3 is disposed within the dielectric layer 2 and located in the optical coupling region A, for coupling and transmission of optical signals. The relevant descriptions of the substrate 1, dielectric layer 2, and optical waveguide structure 3 can be found above.

[0091] In some embodiments, the semiconductor substrate further includes an interconnect structure 6 disposed within the dielectric layer 2 and located in the non-optically coupled region B. See the relevant description above for details.

[0092] Step S2: Create a cavity in the semiconductor substrate, with the cavity surrounding the optical waveguide structure.

[0093] In the specific implementation process, photolithography and etching can be used to process the dielectric layer 2 to form the cavity 4. The cavity 4 extends to the side of the optical waveguide structure 3 facing the substrate 1.

[0094] In one embodiment, the cavity 4 extends at least to the surface of the dielectric layer 2 facing the substrate 1. In another embodiment, the cavity 4 extends further into the substrate 1. This helps to reduce the probability of light scattering outwards from the substrate 1 during propagation, thereby improving optical coupling efficiency and enabling the optical waveguide structure 3 to transmit optical signals more efficiently, thus improving the performance of the semiconductor structure.

[0095] In one embodiment, the cavity 4 extends along the circumferential direction of the optical waveguide structure 3, and the cavity 4 is continuously distributed along the circumferential direction of the optical waveguide structure 3; wherein, the cavity 4 surrounds 50%-90% of the optical waveguide structure 3 along the circumferential direction of the optical waveguide structure 3. Other specific structures of the cavity 4 can be found above.

[0096] The width W0 of the cavity 4 is 8 micrometers to 15 micrometers; for example, W0 is 8 micrometers, 10 micrometers, 12 micrometers or 15 micrometers, etc.

[0097] See Figures 7 to 10 , Figures 7 to 10 This is a structural diagram corresponding to the specific implementation process of step S2; in one embodiment, before step S2, it further includes:

[0098] See Figure 7 Step 21: A third dielectric layer 53 is disposed on the side of the dielectric layer 2 facing away from the substrate 1.

[0099] Specifically, a third dielectric layer 53 can be formed on the entire surface of the dielectric layer 2 on the side facing away from the substrate 1 using a deposition process. The thickness H3 of the third dielectric layer 53 is greater than or equal to 100 nm and less than or equal to 400 nm; for example, H3 is 100 nm, 200 nm, 300 nm or 400 nm.

[0100] The material of the third dielectric layer 53 includes silicon nitride and / or aluminum oxide. As an example, the material of the third dielectric layer 53 includes silicon nitride.

[0101] See Figure 8Step 22: Etch the third dielectric layer 53 located in the optical coupling region A. The etched third dielectric layer 53 serves as the second dielectric layer 52 disposed on the dielectric layer 2.

[0102] It is understood that the second dielectric layer 52 and the third dielectric layer 53 are made of the same material and are formed using the same deposition step. However, in step S22, the material deposited in the optical coupling region A is etched to form the second dielectric layer 52. The thickness of the second dielectric layer 52 is less than the thickness of the third dielectric layer 53 located in the non-optical coupling region B. In this way, the larger thickness of the third dielectric layer 53 can reduce the risk of impurity ions, water vapor or other contaminants penetrating into the dielectric layer 2 of the non-optical coupling region B, thereby improving the oxidation and corrosion resistance of the non-optical coupling region B of the semiconductor structure. The smaller thickness of the second dielectric layer 52 can also protect the surface of the dielectric layer 2 of the optical coupling region A, thereby reducing the risk of water vapor eroding the dielectric layer 2 of the optical coupling region A. Moreover, since the thickness of the second dielectric layer 52 is smaller, the amount of light entering the second dielectric layer 52 is reduced, resulting in a smaller impact on the light field, and thus effectively reducing the light coupling loss.

[0103] The thickness H2 of the second dielectric layer 52 is greater than or equal to 20 nm and less than 100 nm; for example, H2 is 20 nm, 40 nm, 50 nm, 60 nm or 80 nm. As an example, H2 is 50 nm.

[0104] Combination Figure 8 In some embodiments, the second dielectric layer 52 and the third dielectric layer 53 define a groove, the groove width W1 being greater than or equal to 60 micrometers and less than or equal to 70 micrometers. For example, the groove width W1 is 60 micrometers, 63 micrometers, 65 micrometers, 68 micrometers, or 70 micrometers.

[0105] In this embodiment, see Figure 9 In step S2, a cavity 4 is opened in the groove, and the cavity 4 extends from the side surface of the second dielectric layer 52 away from the substrate 1 toward the substrate 1.

[0106] The above-mentioned method of forming a cavity 4 in the optical coupling region A after forming the second dielectric layer 52 and the third dielectric layer 53 can prevent the material of the third dielectric layer 53 from further filling the cavity 4 during the formation of the second dielectric layer 52 and the third dielectric layer 53, which would result in the formation of a dielectric layer with a large thickness in the cavity 4, affecting the optical field and increasing the optical coupling loss.

[0107] Step S3: Set a first dielectric layer on the cavity wall.

[0108] In some implementations, combined Figure 2 and Figure 10 Step S3 specifically includes:

[0109] See Figure 10 Step S31: Using the same process, dielectric material 50 is respectively deposited on the surface of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate and on the cavity wall of the cavity 4.

[0110] The dielectric material 50 can be deposited on the side of the dielectric layer 2 away from the substrate 1 using a deposition process, so that the dielectric material 50 is respectively disposed on the surface of the third dielectric layer 53 and the second dielectric layer 52 away from the semiconductor substrate and on the cavity wall of the cavity 4. The dielectric material 50 includes silicon nitride and / or aluminum oxide. As an example, the dielectric material 50 includes silicon nitride.

[0111] The thickness of the dielectric material 50 is greater than or equal to 20 nm and less than 100 nm; for example, the thickness of the dielectric material 50 can be 20 nm, 40 nm, 50 nm, 60 nm or 80 nm.

[0112] Combination Figure 2 or Figure 4 Step S32: Along the thickness direction Y of the semiconductor substrate, remove at least a portion of the dielectric material 50 from the side surface of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate, so as to form a first dielectric layer 51 at least on the cavity wall of the cavity 4.

[0113] In some implementations, a maskless etching process can be used to etch at least a portion of the dielectric material 50 on the side surface of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate. This removes at least a portion of the dielectric material 50 on the side surface of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate along the thickness direction Y of the semiconductor substrate, and also removes at least a portion of the dielectric material 50 on the bottom wall of the cavity 4, forming a first dielectric layer 51 on the side wall of the cavity 4. Using a maskless etching process allows for adjustment of the overall thickness of the dielectric layer 5 formed on the side surface of the dielectric layer 2 facing away from the substrate 1, improving process flexibility, simplifying the process, eliminating the need for a mask, and reducing costs.

[0114] In one specific implementation, such as Figure 2 As shown, a maskless etching process can be used to remove all dielectric material 50 from the surfaces of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate along the thickness direction Y of the semiconductor substrate, as well as all dielectric material 50 from the bottom wall of the cavity 4, to form the first dielectric layer 51 on the cavity wall of the cavity 4. All embodiments in this application are described using this example. Of course, in other embodiments, all dielectric material 50 from the surfaces of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate can be removed, but the dielectric material 50 on the bottom wall of the cavity 4 can remain unremoved to improve the waterproofing effect of the cavity 4.

[0115] In this embodiment, a thicker third dielectric layer 53 can be formed on the surface of the dielectric layer 2 in the non-optical coupling region B on the side facing away from the substrate 1. This third dielectric layer 53 reduces the risk of impurity ion diffusion, moisture, or other contaminants penetrating into the dielectric layer 2 in the non-optical coupling region B, thereby improving the resistance of the non-optical coupling region B of the semiconductor structure to oxidation, corrosion, and other contaminants. Simultaneously, a thinner second dielectric layer 52 can be formed on the surface of the dielectric layer 2 in the optical coupling region A on the side facing away from the substrate 1, and a thinner first dielectric layer 51 can be formed on the sidewall of the cavity 4. This protects the surface of the dielectric layer 2 in the optical coupling region A through the second dielectric layer 52 and the first dielectric layer 51, reducing the risk of moisture erosion of the dielectric layer 2 in the optical coupling region A. Furthermore, the thinner thickness of the second dielectric layer 52 and the first dielectric layer 51 reduces the amount of light entering the first dielectric layer 51 and the second dielectric layer 52, minimizing the impact on the light field and effectively reducing light coupling loss.

[0116] In the specific implementation process, maskless etching is used. After etching away all the dielectric material 50 on the side surface of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate along the thickness direction Y of the semiconductor substrate, a further portion of the third dielectric layer 53 and the second dielectric layer 52 may be etched away. In this embodiment, it can be understood that the thickness of the third dielectric layer 53 in the above-described semiconductor structure embodiment is less than the thickness of the third dielectric layer 53 formed in step S21; the thickness of the second dielectric layer 52 in the above-described semiconductor structure embodiment is less than the thickness of the second dielectric layer 52 formed in step S22.

[0117] In another specific implementation, such as Figure 4 As shown, a maskless etching process can be used to remove a portion of the dielectric material 50 on the side of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate along the thickness direction Y of the semiconductor substrate, as well as a portion of the dielectric material 50 on the bottom wall of the cavity 4. The remaining dielectric material 50 forms the fourth dielectric layer 54. This fourth dielectric layer 54 covers the side of the third dielectric layer 53 and the second dielectric layer 52 facing away from the semiconductor substrate, and also covers the bottom wall of the cavity 4.

[0118] The sum of the thickness H2 of the second dielectric layer 52 and the thickness H4 of the fourth dielectric layer 54 can be greater than or equal to 20 nm and less than 100 nm; for example, the sum of the thickness H2 of the second dielectric layer 52 and the thickness H4 of the fourth dielectric layer 54 can be 20 nm, 40 nm, 60 nm or 80 nm.

[0119] In step S32, after processing according to any of the above embodiments, the thickness of the dielectric layer formed on the side of the optical coupling region A of the dielectric layer 2 facing away from the substrate 1 is less than the thickness of the dielectric layer formed on the side of the non-optical coupling region B of the dielectric layer 2 facing away from the substrate 1. And / or the thickness of the dielectric layer formed in the cavity 4 is less than the thickness of the dielectric layer formed on the side of the non-optical coupling region B of the dielectric layer 2 facing away from the substrate 1.

[0120] In the above embodiments, the thickness of the dielectric layer covering the optical coupling region A of the dielectric layer 2, the thickness of the dielectric layer inside the cavity 4, and the thickness of the dielectric layer covering the non-optical coupling region B of the dielectric layer 2 are adjustable. This allows for the selection of a thicker dielectric layer on the non-optical coupling region B of the dielectric layer 2 to provide water and vapor protection, depending on actual needs. Conversely, a thinner dielectric layer is provided on the top surface of the dielectric layer 2 located in the optical coupling region A, and a thinner first dielectric layer 51 is provided on the cavity wall of the cavity 4. This allows the first dielectric layer 51 and the dielectric layer on the top surface of the dielectric layer 2 in the optical coupling region A to provide water and vapor protection while simultaneously reducing the influence of these dielectric layers on the optical field. This reduces optical coupling loss, improves coupling efficiency, and lowers the risk of failure of the fabricated semiconductor structure during reliability testing.

[0121] It is understood that, in the semiconductor structure obtained by any of the above embodiments, the thickness H3 of the third dielectric layer 53 covering the dielectric layer 2 in the non-optical coupling region B is still greater than or equal to 100 nm and less than or equal to 400 nm. The thickness H2 of the second dielectric layer 52 covering the dielectric layer 2 in the optical coupling region A is still greater than or equal to 20 nm and less than 100 nm. The thickness H1 of the first dielectric layer 51 formed on the sidewall of the cavity 4 is greater than or equal to 20 nm and less than 100 nm.

[0122] As an example, the thickness H3 of the third dielectric layer 53 formed above is 400 nm; the thickness H2 of the second dielectric layer 52 and the thickness H1 of the first dielectric layer 51 are both 50 nm.

[0123] The semiconductor structure fabrication method provided in this embodiment involves providing a semiconductor substrate, including a substrate 1 and a dielectric layer 2 disposed on the substrate 1, with an optical waveguide structure 3 disposed within the dielectric layer 2. A cavity 4 is then formed on the semiconductor substrate, surrounding the optical waveguide structure 3. A first dielectric layer 51 is then disposed on the cavity wall of the cavity 4. This restricts the outward dispersion of light within the dielectric layer 2 through the cavity 4, allowing the optical signal to be coupled into the optical waveguide structure 3 as much as possible, reducing the probability of the optical signal coupling into the substrate 1, thereby improving optical coupling efficiency and the performance of the semiconductor structure. Simultaneously, the cavity wall of the cavity 4 is protected by the first dielectric layer 51, and the top surface of the dielectric layer 2 located in the optical coupling region A is protected by the second dielectric layer 52. This effectively reduces the risk of external moisture eroding the dielectric layer 2 through the cavity wall of the cavity 4 and the top surface of the dielectric layer 2; further reducing the risk of moisture erosion altering the refractive index of the dielectric layer 2 and the cavity 4, leading to optical field distortion and increased coupling loss. Meanwhile, the absorption loss of water when moisture enters the semiconductor structure can also lead to failure of the semiconductor structure during the reliability process; therefore, this application effectively improves the reliability of the semiconductor structure while improving the waterproof performance.

[0124] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A semiconductor structure, characterized by, include: Substrate; A dielectric layer is disposed on the substrate; An optical waveguide structure is disposed within the dielectric layer; A cavity is provided around the optical waveguide structure; The dielectric layer includes a first dielectric layer disposed on the cavity wall of the cavity.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes an optical coupling region; the optical waveguide structure is disposed in the optical coupling region; The dielectric layer further includes a second dielectric layer, which is located in the optical coupling region and disposed on the side surface of the dielectric layer opposite to the substrate.

3. The semiconductor structure according to claim 2, characterized in that, The thickness of the first dielectric layer and / or the second dielectric layer is greater than or equal to 20 nm and less than 100 nm.

4. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes a non-optically coupled region; The dielectric layer further includes a third dielectric layer, which is located in the non-optically coupled region and is disposed on the side surface of the dielectric layer opposite to the substrate.

5. The semiconductor structure according to claim 4, characterized in that, The thickness of the third dielectric layer is greater than the thickness of the first dielectric layer; and / or the thickness of the third dielectric layer is greater than the thickness of the second dielectric layer.

6. The semiconductor structure according to claim 4 or 5, characterized in that, The dielectric layer further includes a fourth dielectric layer, which is at least disposed on the side surface of the second dielectric layer opposite to the dielectric layer, and the sum of the thickness of the second dielectric layer and the thickness of the fourth dielectric layer is less than the thickness of the third dielectric layer.

7. The semiconductor structure according to claim 4 or 5, characterized in that, The thickness of the third dielectric layer is greater than or equal to 100 nm and less than or equal to 400 nm.

8. The semiconductor structure according to claim 4 or 5, characterized in that, The material of the third dielectric layer includes silicon nitride and / or aluminum oxide; and / or The material of the first dielectric layer and / or the second dielectric layer includes silicon nitride and / or aluminum oxide.

9. The semiconductor structure according to claim 1, characterized in that, The cavities are continuously distributed along the circumferential direction of the optical waveguide structure.

10. The semiconductor structure according to claim 9, characterized in that, The cavity surrounds 50%-90% of the optical waveguide structure along its circumferential direction.

11. The semiconductor structure according to claim 1, characterized in that, The cavity extends at least from the side of the dielectric layer facing away from the substrate to the side of the dielectric layer facing the substrate.

12. The semiconductor structure according to claim 11, characterized in that, The cavity extends from the side of the dielectric layer facing away from the substrate into the substrate.

13. The semiconductor structure according to claim 12, characterized in that, The substrate includes an SOI substrate, which includes a bottom semiconductor layer, a buried oxide layer, and a top semiconductor layer stacked sequentially; the top semiconductor layer faces the dielectric layer; the cavity penetrates at least the dielectric layer, the top semiconductor layer, or the buried oxide layer.

14. The semiconductor structure according to claim 1, characterized in that, The cavity has a bottom wall and side walls; the first medium layer is disposed on the bottom wall and side walls of the cavity.

15. The semiconductor structure of claim 1, wherein, The width of the cavity is 8μm-15μm.

16. A method of fabricating a semiconductor structure, comprising: include: A semiconductor substrate is provided; the semiconductor substrate includes a substrate and a dielectric layer disposed on the substrate, wherein an optical waveguide structure is provided in the dielectric layer; A cavity is formed in the semiconductor substrate, and the cavity is arranged around the optical waveguide structure; A first dielectric layer is disposed on the cavity wall of the cavity.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The semiconductor substrate includes an optical coupling region; prior to the step of creating a cavity in the semiconductor substrate, the method further includes: A third dielectric layer is disposed on the surface of the dielectric layer facing away from the substrate; The third dielectric layer located in the optical coupling region is etched, and the etched third dielectric layer serves as the second dielectric layer disposed on the dielectric layer.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, The step of setting a first dielectric layer on the cavity wall includes: Dielectric materials are respectively deposited on the surface of the third dielectric layer and the second dielectric layer opposite to the semiconductor substrate and on the cavity wall using the same process; Along the thickness direction of the semiconductor substrate, at least a portion of the dielectric material on the side surface of the third dielectric layer and the second dielectric layer facing away from the semiconductor substrate is removed to form the first dielectric layer at least on the cavity wall of the cavity.

19. The method for preparing a semiconductor structure according to claim 18, characterized in that, At least a portion of the dielectric material on the side of the third dielectric layer and the second dielectric layer facing away from the semiconductor substrate is etched using a maskless etching process.

20. The method for preparing a semiconductor structure according to claim 17, characterized in that, The thickness of the third dielectric layer is greater than or equal to 100 nm and less than or equal to 400 nm; the thickness of the first dielectric layer is greater than or equal to 20 nm and less than 100 nm.

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