A multi-chip optical interconnect architecture and method of manufacture

Abstract

This invention belongs to the field of advanced packaging technology, specifically relating to a multi-chip optical interconnect architecture and manufacturing method. The manufacturing method includes the following steps: S1, depositing a hard mask on the substrate surface; S2, spin-coating photoresist on the hard mask, pre-baking, alignment exposure, development, and post-baking to transfer the lower layer pattern onto the hard mask, followed by photoresist removal and cleaning; S3, manufacturing a surface ion-exchange optical waveguide; S4, printing matrix electrodes and their circuitry on the substrate surface to achieve a controllable electric field and form the lower layer optical waveguide; S5, depositing, photolithography, and etching on the substrate surface to form the upper layer optical waveguide; S6, mounting a photonic integrated chip and an arrayed waveguide grating router on the substrate surface and aligning and coupling them with the upper and lower layer optical waveguides; S7, depositing a cladding layer on the substrate surface and polishing to expose the upper surface of the photonic integrated chip. This invention effectively reduces optical path crossings and increases interconnect density, thereby achieving high-bandwidth, low-loss optical interconnects between multiple chips on a single chip.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging technology, specifically relating to a multi-chip optical interconnect architecture and manufacturing method. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and high-performance computing (HPC), the information throughput within data centers continues to expand, placing higher demands on interconnect bandwidth, power consumption, and transmission efficiency. Traditionally, data transmission between chips primarily uses electrical interconnects. However, as transmission rates continue to increase, electrical interconnects are increasingly revealing problems such as bandwidth limitations, severe crosstalk, decreased signal integrity, and increased power consumption and heat dissipation. Traditional electrical interconnects can no longer meet the high-speed data exchange requirements of next-generation high-performance computing systems. Therefore, developing new high-bandwidth, low-power interconnect technologies is a crucial way to overcome the bottlenecks in electrical interconnect development.

[0003] Against this backdrop, co-packaged optics (CPO) technology has gradually become a research hotspot. Optoelectronic co-packaging shortens the transmission distance of high-speed electrical signals and reduces electrical channel losses and impedance discontinuities by bringing optical transceiver units closer to application-specific integrated circuit (ASIC) chips, thereby improving system transmission rates and reducing power consumption. The future development goal is to integrate optical transceiver units and ASIC chips onto the same packaging substrate, achieving high-density optoelectronic interconnection on the board. ASIC chips typically include switching chips or computing chips, such as central processing units (CPUs), graphics processing units (GPUs), and artificial intelligence accelerators.

[0004] However, as system scale continues to expand, existing optoelectronic co-packaging structures are no longer sufficient to meet the increasing demands of multi-chip interconnects. Currently, there are no mature and feasible technical solutions for on-chip optical interconnects of multiple chips and all-optical input / output between chip substrates.

[0005] Chinese patent document CN202511988912.9 discloses an on-chip optical interconnect and switching chip and its application system. It configures each ASIC chip with an optical transceiver unit, and then interconnects all optical transceiver units in pairs via optical waveguides to achieve optical interconnection between two rows of ASIC chips. However, since the interconnecting optical waveguides are all in the same layer, cross-over between the waveguides is unavoidable, causing signal crosstalk and loss. Furthermore, each ASIC chip uses the same optical waveguide for optical transceiver, and two beams of opposing light in the same waveguide will interfere with each other, causing transmission loss. In addition, since at least one optical waveguide must be set between each pair of ASIC chips to achieve optical interconnection, the number of optical waveguides on the board becomes enormous, and the number of cross-over between waveguides increases dramatically. Moreover, the number of optical waveguides increases exponentially with the number of ASIC chips, which is very unfavorable for multi-chip integration.

[0006] Chinese patent document CN202311072051.0 discloses an optical interconnect architecture for data center switches. It connects hybrid switches, tunable wavelength converter modules, and external arrayed waveguide grating routers to server racks, forming an optical interconnect architecture. The hybrid switches are connected to each other via tunable wavelength converter modules and external arrayed waveguide grating routers. By abandoning optical buffering in the network architecture and adopting circuit switching, it alleviates queuing latency caused by network congestion. However, it mainly focuses on optimizing optical interconnects between switches and does not address the optical interconnection problem between multiple chips. Furthermore, it does not achieve all-optical interconnection, and when facing rapidly increasing information throughput demands, it still suffers from problems such as high heat generation and losses that surge with increasing circuit distance due to electrical interconnects.

[0007] Therefore, a new multi-chip optical interconnect architecture and manufacturing method are needed. Summary of the Invention

[0008] The purpose of this invention is to provide a multi-chip optical interconnect architecture and manufacturing method to solve the problem that the existing optoelectronic co-packaging structure mentioned in the background art can hardly meet the expansion requirements of multi-chip interconnect.

[0009] To achieve the above objectives, the present invention provides a method for manufacturing a multi-chip inter-optical interconnect architecture, comprising the following steps:

[0010] S1. Deposit a hard mask on the surface of the glass substrate;

[0011] S2. Spin-coat photoresist onto the hard mask, pre-bake, align and expose, develop, post-bake, then transfer the lower layer pattern onto the hard mask by etching, and remove the photoresist and clean.

[0012] S3. Manufacturing surface ion-exchange optical waveguides;

[0013] S4. Print matrix electrodes and their circuits on the surface of a glass substrate. By applying different voltages to each electrode, a controllable electric field is achieved. At the same time, the temperature of the glass substrate is applied to increase the ion activity, so that the exchange ions in the glass substrate can undergo controllable electromigration under the action of the electric field, forming a three-dimensional lower optical waveguide.

[0014] S5. Then, by coating, photolithography and etching on the surface of the glass substrate, the upper two-dimensional optical waveguide pattern is transferred to the surface of the glass substrate, and the upper optical waveguide is formed on the surface of the glass substrate by depositing a material that matches the refractive index of the optical fiber.

[0015] S6. The photonic integrated chip is laid on the substrate surface and aligned and coupled with the upper and lower optical waveguides; the arrayed waveguide grating router is laid on the substrate surface. The arrayed waveguide grating routers are arranged in pairs, and the optical signal transmission directions of the paired arrayed waveguide grating routers are different. The paired arrayed waveguide grating routers are aligned and coupled with the upper and lower optical waveguides respectively.

[0016] S7. Deposit cladding material on the upper surface of the glass substrate, and then polish and thin it to expose the upper surface of the photonic integrated chip, thus obtaining the optical interconnect architecture between multiple chips.

[0017] In one specific embodiment, the fabrication of the surface ion-exchange optical waveguide involves immersing a glass substrate in a molten ion-exchange salt. After the exchange process, an ion-exchange optical waveguide is formed on the surface of the glass substrate. The molten ion-exchange salt is a mixed salt of silver nitrate, calcium nitrate, and sodium nitrate.

[0018] In one specific embodiment, the cladding material is silicon dioxide.

[0019] The present invention also provides a multi-chip optical interconnect architecture, which is prepared by the manufacturing method of the multi-chip optical interconnect architecture described above.

[0020] The present invention also provides a method for manufacturing a multi-chip inter-optical interconnect package, including the steps in the method for manufacturing a multi-chip inter-optical interconnect architecture as described above, and further including the following steps:

[0021] S8. Repeatedly depositing, photolithography, and etching to deposit metal bumps and wiring on the waveguide cladding, connecting the contacts of the photonic integrated chip to the metal bumps, and completing the metal wiring for electrical interconnection between the electronic integrated chip and the main chip.

[0022] S9. Deposit cladding material and grind it thin to expose the metal bumps and wiring;

[0023] S10. Align and couple the electronic integrated chip and main chip with the metal bumps and wiring to complete the optoelectronic interconnection packaging between multiple chips on the entire glass substrate.

[0024] The present invention also provides a multi-chip optoelectronic interconnect package, which is prepared by the manufacturing method of the multi-chip optoelectronic interconnect package as described above.

[0025] The present invention also provides a switch cabinet, which includes a cabinet body, optical fiber and optical splitter / combiner structure, and multiple switches. The switches are provided with multi-chip optoelectronic interconnection packages as described above. External laser light source and external optical signal are transmitted to each switch through optical fiber and optical splitter structure. The output optical signal of each switch is then combined into a main optical fiber through optical fiber and optical combiner structure and output to the outside of the cabinet.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] This invention is based on the glass substrate integrated array waveguide grating router (AWGR) and constructs a double-layer optical waveguide structure, which can effectively reduce optical path crossings and increase interconnection density, thereby realizing high-bandwidth, low-loss optical interconnection between multiple chips on the chip, providing a very promising solution for high-performance computing and high-speed data exchange.

[0028] 1. By using a multi-layer optical waveguide interconnect architecture between multiple chips, the crossover problem existing in traditional two-dimensional optical waveguides is avoided, thereby solving the signal interference and loss caused by crossover.

[0029] 2. By setting up a bidirectional AWGR routing structure, not only is full interconnection between multiple chips achieved, but the number of optical waveguide wirings is also greatly reduced, while avoiding losses caused by bidirectional signal transmission in the optical waveguide.

[0030] 3. By layering and packaging optoelectronic chips, the degree of freedom of optical waveguides is extended from two-dimensional plane to three-dimensional space. Since electronic integrated chips generate more heat than photonic integrated chips, packaging photonic integrated chips in the lower layer and electronic integrated chips in the top layer is beneficial for heat dissipation and maintenance of the overall substrate.

[0031] In addition to the objectives, features, and advantages described above, the present invention has other objectives, features, and advantages. The present invention will now be described in further detail. Attached Figure Description

[0032] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0033] Figure 1 This is a schematic diagram of a switch cabinet according to an embodiment of the present invention; wherein, 1, cabinet; 2, optical fiber and optical splitter / combiner structure; 3, switch; 4, output optical signal after processing by the cabinet; 5, external laser source and external input optical signal;

[0034] Figure 2 This is a schematic diagram of the main view of a switch according to an embodiment of the present invention; wherein, 31, inter-chip electrical interconnection architecture; 32, inter-chip optical interconnection architecture;

[0035] Figure 3 This is a side view schematic diagram of a switch according to an embodiment of the present invention; wherein, 31, multi-chip electrical interconnection architecture; 321, lower optical waveguide; 322, photonic integrated chip; 323, upper optical waveguide; 324, arrayed waveguide grating router;

[0036] Figure 4 This is a schematic diagram of a multi-chip optical interconnect architecture according to an embodiment of the present invention; wherein, 321, lower optical waveguide; 322, photonic integrated chip; 323, upper optical waveguide; 324, arrayed waveguide grating router;

[0037] Figure 5 This is a schematic diagram illustrating the mutual conversion and input / output of photoelectric signals in a multi-chip inter-optoelectronic interconnect package according to an embodiment of the present invention; wherein, 31, multi-chip inter-electrical interconnect architecture; 321, lower optical waveguide; 322, photonic integrated chip; 323, upper optical waveguide;

[0038] Figure 6 This is a schematic flowchart of a manufacturing method for a multi-chip inter-optoelectronic interconnect package according to an embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of a multilayer optical waveguide in a multi-chip optoelectronic interconnect package according to an embodiment of the present invention. Detailed Implementation

[0040] The embodiments of the present invention will be described in detail below. The specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0041] Example 1

[0042] The present invention discloses a method for manufacturing a multi-chip inter-optical interconnect architecture, comprising the following steps:

[0043] S1. A hard mask is deposited on the surface of a glass substrate; the material of the hard mask is a high-temperature resistant material such as chromium or aluminum that does not react with glass or exchange salts and can adhere well to the glass surface, and the high-temperature standard is the ion exchange temperature.

[0044] S2. Spin-coat photoresist onto the hard mask, pre-bake, align and expose, develop, post-bake, then transfer the lower layer pattern onto the hard mask by etching, and remove the photoresist and clean.

[0045] S3. Manufacturing a surface ion-exchange optical waveguide; specifically, immersing a glass substrate in a molten ion-exchange salt, and after exchange, forming an ion-exchange optical waveguide on the surface of the glass substrate. The molten ion-exchange salt is a mixed salt of silver nitrate, calcium nitrate, and sodium nitrate.

[0046] S4. Print matrix electrodes and their circuits on the surface of a glass substrate. By applying different voltages to each electrode, a controllable electric field is achieved. At the same time, the temperature of the glass substrate is applied to increase the ion activity, so that the exchange ions in the glass substrate can undergo controllable electromigration under the action of the electric field, forming a three-dimensional lower optical waveguide 321.

[0047] S5. Then, the upper two-dimensional optical waveguide pattern is transferred to the surface of the glass substrate by coating, photolithography and etching, and the upper optical waveguide is formed on the surface of the glass substrate by depositing a material that matches the refractive index of the optical fiber; preferably, the material that matches the refractive index of the optical fiber is germanium-doped silicon dioxide, phosphorus-doped silicon dioxide, boron-doped silicon dioxide or titanium-doped silicon dioxide.

[0048] S6. The photonic integrated chip 322 is mounted on the substrate surface and aligned and coupled with the upper optical waveguide 323 and the lower optical waveguide 321. An arrayed waveguide grating router 324 is mounted on the substrate surface, with the arrayed waveguide grating routers 324 arranged in pairs. The optical signal transmission directions of the paired arrayed waveguide grating routers 324 are different. The paired arrayed waveguide grating routers 324 are aligned and coupled with the upper optical waveguide 323 and the lower optical waveguide 321 respectively. The arrayed waveguide grating router 324 is also known as the AWGR. The AWGR is placed at a predetermined position on the glass substrate and coupled to the optical waveguides in the glass substrate via an evanescent field coupling method. Specifically, the upper optical waveguide 323 is coupled to the input / output optical path in the AWGR via evanescent field coupling; the lower optical waveguide 321 is first bent to the upper layer and then coupled to the AWGR via evanescent field coupling as well.

[0049] S7. A cladding material is deposited on the upper surface of the glass substrate, followed by polishing and thinning to expose the upper surface of the photonic integrated chip 322, i.e., the PIC chip, thus obtaining the multi-chip optical interconnect architecture 32. The cladding material is silicon dioxide.

[0050] The present invention provides a multi-chip optical interconnect architecture 32, which is prepared by the manufacturing method of the multi-chip optical interconnect architecture described above.

[0051] The present invention provides a method for manufacturing a multi-chip inter-optical interconnect package, comprising the steps of the method for manufacturing a multi-chip inter-optical interconnect architecture as described above, and further comprising the following steps:

[0052] S8. Repeated coating, photolithography, and etching are performed to deposit metal bumps and wiring on the waveguide cladding. The contacts of the PIC chip are connected to the metal bumps, and the metal wiring for electrical interconnection between the electronic integrated chip and the main chip is completed. The electronic integrated chip is the EIC chip. Preferably, the main chip is an ASIC chip or an XPU, where the XPU is a CPU or GPU. The memory chip is also set up synchronously with the main chip. The memory chip is the HBM chip, and it is also connected to the main chip through electrical interconnection.

[0053] S9. Deposit cladding material and grind it thin to expose the metal bumps and wiring;

[0054] S10. Align and couple the EIC chip and ASIC chip with the metal bumps and wiring to complete the multi-chip optoelectronic interconnection packaging on the entire glass substrate.

[0055] The present invention provides a multi-chip optoelectronic interconnect package, which is prepared by the manufacturing method of the multi-chip optoelectronic interconnect package as described above.

[0056] A data center typically consists of multiple switch cabinets.

[0057] The present invention provides a switch cabinet, comprising a cabinet body 1, an optical fiber and optical splitter / combiner structure 2, and multiple switches 3. Each switch 3 is provided with an inter-chip optoelectronic interconnect package as described above. External laser light sources and external optical signals are transmitted to each switch 3 through the optical fiber and optical splitter structure. The output optical signals of each switch 3 are then aggregated into a main optical fiber through the optical fiber and optical combiner structure and output to the outside of the cabinet.

[0058] The multi-chip optical interconnect of the present invention adopts a multi-layer optical waveguide architecture and a crossover-like design, so that the waveguides that intersect on the two-dimensional projection plane are staggered in three-dimensional space.

[0059] This invention sets up a bidirectional AWGR routing structure in the transmission path of optical signals to avoid bidirectional optical signals in the waveguide, and enables multiple wavelength optical signals to be transmitted simultaneously on the same waveguide, and enables specific wavelength signals to be focused at specific output ports.

[0060] Each input port can simultaneously input optical signals of multiple wavelengths. After being transmitted to the array coupling area, the light will diffuse and be evenly distributed to each entrance of the array waveguide. Subsequently, when passing through the array waveguide, due to the different path lengths of each waveguide, a wavelength-related phase difference will be introduced, thereby focusing optical signals of different wavelengths at different output ports in the output coupling area, so that each wavelength is routed to a specific port, realizing full interconnection between multiple chips.

[0061] To avoid cross-overlapping between optical waveguides connecting multiple chips, which would cause signal interference and loss, the optical waveguide transmitting right-direction signals is fabricated inside the glass substrate, while the optical waveguide transmitting left-direction signals is fabricated on the surface of the glass substrate. There is no cross-over between the two waveguide layers, and the bidirectional optical signals are transmitted in separate waveguides, thus the optical signals are not affected by reverse signals or interference from other lines. When the external laser source fiber approaches the substrate, it is split into two paths by a splitter structure: one path connects to the light source input port of the upper optical waveguide, and the other path connects to the light source input port of the lower optical waveguide. After the laser source inputs to the two optical waveguide ports, the light is evenly distributed to the corresponding PIC chip of each ASIC chip after passing through the on-board optical splitter structure.

[0062] The mutual conversion and input / output of photoelectric signals are jointly accomplished by the inter-chip electrical interconnect architecture 31 and the inter-chip optical interconnect architecture 32. A specific architecture of the inter-chip optoelectronic interconnect package is as follows: Figure 5 As shown. In terms of electro-optical conversion and output, the electrical signal output by the ASIC chip is first passed to a serializer / deserializer for data conversion, signal shaping, and output of a high-speed differential signal. Subsequently, the serializer / deserializer passes the processed electrical signal to the modulator driver, amplifying the small-amplitude electrical signal to a voltage capable of driving the optical modulator. Finally, the modulator driver passes the amplified voltage signal to the micro-ring modulator, which changes the refractive index of a specific region on the micro-ring according to the voltage signal, thereby shifting the resonant wavelength of the micro-ring and controlling the output light intensity of the straight waveguide, realizing the conversion of the electrical signal to an optical signal and its output. In terms of photoelectric conversion and input, the optical signal from other chips is filtered by the micro-ring to select a specific wavelength and coupled into the optical path of the photodetector. The coupled optical signal generates a photocurrent in the photodetector, which is then passed to a transimpedance amplifier. The transimpedance amplifier converts the photocurrent into a voltage and amplifies it, then passes it to a limiting amplifier. The limiting amplifier further amplifies and shapes the voltage signal into a standard digital level and passes it to a clock data recovery circuit. The clock data recovery circuit recovers the clock from the standard digital level data stream and resamples the data. Finally, it is passed to the ASIC chip for direct use.

[0063] This invention realizes a full-process packaging technology for multi-chip, multi-layer optical interconnect architectures. Through reasonable optoelectronic circuit layout design and cyclic steps S5-S9, multi-layer optical waveguides can be fabricated on the substrate surface.Figure 7 As shown.

[0064] When the number of ASIC chips to be placed is large, and stacking one layer is insufficient, after completing step S10, steps S5~S9 are repeated above the ASIC chips to create a double-layer ASIC chip stack. If further additions are needed, two more layers of ASIC chips are added above the upper glass substrate and below the lower glass substrate through glass vias and their metal filling. The optical interconnects between each ASIC layer only require adding one more AWGR and the corresponding number of optical paths.

[0065] The use and fabrication of multilayer optical waveguides in existing technologies present significant challenges because the receiving end of a photonic integrated chip is on a single plane, and the multilayer waveguides must ultimately converge onto a single layer. The traditional method involves fabricating micromirrors in the substrate to reflect light from other layers to the transceiver layer. However, this traditional approach has many drawbacks: high loss, large size, introduction of phase differences, and impact on structural strength. In traditional architectures, the optical waveguides and chip circuitry of the transceiver layer reside on the same layer, which also presents numerous problems: thermal deformation of the electronic integrated chip affects the optical signal, and space constraints exist. This invention employs a layered architecture for the EIC and PIC, solving problems related to insufficient space, heat dissipation, and thermal deformation. Existing conventional AWGRs (Optical Waveguides with Intersecting Arrays) are bidirectional, but bidirectional optical signal transmission inevitably involves crossover in traditional planar optical paths, leading to loss and interference. The AWGRs in this invention are arranged in pairs, with two AWGRs per pair, each responsible for transmission in one direction. This multilayer optical path method avoids the optical path crossover problem caused by bidirectional independent transmission.

[0066] This invention avoids the crossover problem present in traditional two-dimensional optical waveguides by using a multi-layer optical waveguide interconnect architecture between multiple chips, thereby solving the signal interference and loss caused by crossover.

[0067] This invention, by setting a bidirectional AWGR routing structure, not only achieves full interconnection between multiple chips, but also significantly reduces the number of optical waveguide wirings, while avoiding losses caused by bidirectional signal transmission in the optical waveguide.

[0068] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions and substitutions can be made without departing from the inventive concept, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a multi-chip inter-optical interconnect architecture, characterized in that, Includes the following steps: S1. Deposit a hard mask on the surface of the glass substrate; S2. Spin-coat photoresist onto the hard mask, pre-bake, align and expose, develop, post-bake, then transfer the lower layer pattern onto the hard mask by etching, and remove the photoresist and clean. S3. Manufacturing surface ion-exchange optical waveguides; S4. Print matrix electrodes and their circuits on the surface of a glass substrate. By applying different voltages to each electrode, a controllable electric field is achieved. At the same time, the temperature of the glass substrate is applied to increase the ion activity, so that the exchange ions in the glass substrate can undergo controllable electromigration under the action of the electric field, forming a three-dimensional lower optical waveguide. S5. Then, by coating, photolithography and etching on the surface of the glass substrate, the upper two-dimensional optical waveguide pattern is transferred to the surface of the glass substrate, and the upper optical waveguide is formed on the surface of the glass substrate by depositing a material that matches the refractive index of the optical fiber. S6. The photonic integrated chip is laid on the substrate surface and aligned and coupled with the upper and lower optical waveguides; the arrayed waveguide grating router is laid on the substrate surface. The arrayed waveguide grating routers are arranged in pairs, and the optical signal transmission directions of the paired arrayed waveguide grating routers are different. The paired arrayed waveguide grating routers are aligned and coupled with the upper and lower optical waveguides respectively. S7. Deposit cladding material on the upper surface of the glass substrate, and then polish and thin it to expose the upper surface of the photonic integrated chip, thus obtaining the optical interconnect architecture between multiple chips.

2. The manufacturing method of the multi-chip inter-optical interconnect architecture according to claim 1, characterized in that, The manufacturing of the surface ion-exchange optical waveguide specifically involves immersing a glass substrate in a molten ion-exchange salt. After the exchange process, an ion-exchange optical waveguide is formed on the surface of the glass substrate. The molten ion-exchange salt is a mixed salt of silver nitrate, calcium nitrate, and sodium nitrate.

3. The manufacturing method of the multi-chip inter-optical interconnect architecture according to claim 1, characterized in that, The cladding material is silicon dioxide.

4. A multi-chip optical interconnect architecture, characterized in that, The multi-chip optical interconnect architecture is prepared by the manufacturing method of the multi-chip optical interconnect architecture as described in any one of claims 1 to 3.

5. A method for manufacturing a multi-chip inter-optoelectronic interconnect package, characterized in that, The method for manufacturing a multi-chip optical interconnect architecture as described in any one of claims 1 to 3 further includes the following steps: S8. Repeatedly depositing, photolithography, and etching to deposit metal bumps and wiring on the waveguide cladding, connecting the contacts of the photonic integrated chip to the metal bumps, and completing the metal wiring for electrical interconnection between the electronic integrated chip and the main chip. S9. Deposit cladding material and grind it thin to expose the metal bumps and wiring; S10. Align and couple the electronic integrated chip and main chip with the metal bumps and wiring to complete the optoelectronic interconnection packaging between multiple chips on the entire glass substrate.

6. A multi-chip optoelectronic interconnect package, characterized in that, The multi-chip optoelectronic interconnect package is prepared by the manufacturing method of the multi-chip optoelectronic interconnect package as described in claim 5.

7. A switch cabinet, characterized in that, The switch cabinet includes a cabinet, optical fiber and optical splitter / combiner structure, and multiple switches. Each switch is equipped with the multi-chip optoelectronic interconnect package as described in claim 6. External laser light source and external optical signal are transmitted to each switch through optical fiber and optical splitter structure. The output optical signal of each switch is then combined into a main optical fiber through optical fiber and optical combiner structure and output to the outside of the cabinet.

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