A modulator and a method of manufacturing the same

Abstract

This invention discloses a modulator and its manufacturing method, belonging to the field of silicon-based optoelectronics technology. The manufacturing method of the modulator includes the following steps: providing a substrate, forming an input waveguide, an output waveguide, a bulk, and a surrounding dielectric layer on the substrate; etching to thin the bulk and the surrounding dielectric layer in the area where the gate is located to form a groove; forming an insulating dielectric layer on top of the bulk; depositing a polysilicon layer, the thickness of which is not less than the depth of the groove; using a CMP process to thin the polysilicon layer at least to expose the top surface of the input waveguide, the output waveguide, and the surrounding dielectric layer, forming a polysilicon pattern in the groove; and continuing to etch to remove the polysilicon pattern outside the gate area to form the gate. By redesigning the interface structure of the input waveguide-SISCAP and SISCAP-output waveguide, the thickness of the gate is controlled by utilizing the thickness of the bulk and the thickness difference between the input and output waveguides, so that both the input and output waveguides are flush with the top of the gate, thereby making the device cross-section continuous and without abrupt changes in the vertical direction to limit interface reflection. Furthermore, the roughness of the gate top is reduced using the CMP process to reduce interface scattering.

Description

Technical Field

[0001] This invention relates to the field of silicon-based optoelectronics technology, and in particular to a modulator and its manufacturing method. Background Technology

[0002] Mach-Zehnder modulators (MZMs) are important active devices in silicon-based optoelectronic systems, responsible for loading electrical signals onto optical signals. They have wide applications in optical communication and quantum computing / deep learning. Key performance indicators include modulation efficiency (VL), modulation depth (extinction ratio), modulation speed (-3dB bandwidth), and optical loss. In general optical communication applications, modulation speed and modulation depth are prioritized, sacrificing some modulation efficiency. Therefore, the devices are relatively large, with the modulation arm typically several millimeters long, leading to significant optical propagation loss.

[0003] Figure 1 The diagram shows a partial structure of a common single SISCAP modulation arm MZM. This MZM consists of an input waveguide 10, an output waveguide (not shown), and two modulation arms. One modulation arm 20 is a SISCAP, and the other is a simple waveguide (not shown). The portion below the SISCAP is generally called the body, and the portion above is generally called the gate. Both the body and the gate are made of crystalline silicon and partially overlap in the horizontal direction, separated by an ultrathin dielectric material, typically SiO2. The overlapping area is the region through which light propagates. Contact electrodes are constructed on the body and the gate to apply a bias voltage (not shown). By changing the bias voltage, the phase of the light is modulated. The other modulation arm is a simple waveguide and has no electro-optic modulation capability. For ease of process integration, most existing SISCAPMZMs use patterned monocrystalline silicon for the bulk of the input waveguide 10 and modulation arm 20, while the gate of the modulation arm 20 is formed by depositing polycrystalline silicon on top of this silicon layer and then patterning it. However, when light propagates from the input waveguide into the modulation arm and then into the output waveguide, there is abrupt change in the cross-section, especially in the vertical direction, which leads to significant changes in mode size and severe interface reflection. Since the abrupt change is mainly in the vertical direction, constructing a vertically gradient structure for the transition is an effective solution; however, this is very difficult to implement in terms of process technology. Some studies have also used conventional horizontally gradient structures for the transition, which are easy to implement, but the actual results are not ideal.

[0004] Furthermore, the propagation loss of small-sized optical propagation structures (waveguides) is highly sensitive to interface roughness. Reducing the roughness of silicon waveguide sidewalls to decrease propagation loss has been extensively studied and implemented. For SISCAP MZMs, the top of the deposited polycrystalline silicon film is relatively rough due to the polycrystalline structure of polycrystalline silicon itself, whose roughness is typically significantly greater than that of the waveguide sidewalls. This results in significant interface scattering in SISCAPs, leading to propagation losses far exceeding ideal conditions. Some studies have proposed solutions to this problem, such as CMP planarization of polycrystalline silicon, using seed catalysis to form near-monocrystalline silicon, and first depositing a flat amorphous silicon film followed by silicon ion implantation and then annealing to form silicon grains. The first solution has poor thickness controllability, the second requires the introduction of a metal catalyst which carries the risk of metal contamination, and the third solution still results in a film carrier mobility that differs from directly deposited polycrystalline silicon.

[0005] Therefore, there is currently no relatively simple, easy-to-implement, and effective solution to the interface reflection and interface scattering problems of SISCAP MZM.

[0006] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a modulator and its manufacturing method to solve the problems of interface reflection and interface scattering in SISCAP-type Mach-Zehnder modulators.

[0008] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a modulator, comprising the following steps:

[0009] A substrate is provided on which an input waveguide, an output waveguide, a volume, and a surrounding dielectric layer are formed, wherein the top surface of the surrounding dielectric layer is not lower than the top surface of the input waveguide, the output waveguide, and the volume;

[0010] The body and the surrounding dielectric layer in the area where the gate is located are etched and thinned to form a groove;

[0011] An insulating dielectric layer is formed on the top of the body;

[0012] A polycrystalline silicon layer is deposited, wherein the thickness of the polycrystalline silicon layer is not less than the depth of the groove;

[0013] The polysilicon layer is thinned at least to expose the top surface of the input waveguide, output waveguide and surrounding dielectric layer using a CMP process, and a polysilicon pattern is formed in the groove.

[0014] Continue etching to remove the polysilicon pattern outside the gate region to form the gate.

[0015] Preferably, the substrate has a top silicon layer, wherein forming an input waveguide, an output waveguide, a bulk layer, and a surrounding dielectric layer on the substrate includes:

[0016] A pad oxide layer and a stop layer are sequentially formed on the top silicon layer;

[0017] Photolithography and etching are performed on the top silicon layer to the substrate to remove areas other than the bulk, input waveguide, and output waveguide;

[0018] A dielectric layer is formed on the substrate, and the thickness of the dielectric layer is not less than the thickness of the top silicon layer;

[0019] The dielectric layer is thinned until the input waveguide, output waveguide, and volume are exposed, and a surrounding dielectric layer is formed.

[0020] Preferably, the thickness of the dielectric layer is greater than the sum of the thicknesses of the top silicon layer, the pad oxide layer, and the stop layer. When thinning the dielectric layer, the dielectric layer is polished using a CMP process until the top surface of the stop layer is exposed, and then the stop layer and the pad oxide layer are removed by wet etching, thereby exposing the input waveguide, the output waveguide, and the bulk.

[0021] Preferably, after forming the input waveguide, output waveguide and bulk, and before depositing the polycrystalline silicon layer, ions of a first conductivity type are implanted into the bulk.

[0022] Preferably, after forming the polysilicon pattern, ions of a second conductivity type are implanted into the gate region on the polysilicon pattern, and then a rapid thermal annealing process is performed to continue etching away the polysilicon pattern outside the gate region to form the gate.

[0023] Preferably, after the gate is formed, a top capping layer is deposited, and then the top capping layer is thinned to the required thickness by a CMP process. Contact electrodes that are respectively connected to the body and the gate are then fabricated on the top capping layer.

[0024] Preferably, the stop layer is made of silicon nitride, the pad oxide layer is made of silicon oxide, the top silicon layer is made of monocrystalline silicon, and the insulating dielectric layer is made of one or more of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, and bismuth oxide in a stacked combination. The substrate includes a stacked silicon substrate and a buried oxide layer, and the substrate and the top silicon layer together constitute an SOI wafer.

[0025] A modulator, manufactured using the modulator manufacturing method described above, includes:

[0026] The first modulation arm is configured as a SISCAP, which includes a stacked body and a gate, the body and the gate having a partially overlapping area in the horizontal direction, and the body and the gate being separated by an insulating dielectric layer.

[0027] An input waveguide, wherein the end of the input waveguide is connected to a partially overlapping region of the body;

[0028] An output waveguide is provided, the end of which is connected to a partially overlapping area of ​​the body. The upper surfaces of both the input and output waveguides are flush with the top surface of the gate, and the lower surfaces of both the input and output waveguides are flush with the bottom surface of the body.

[0029] Preferably, it further includes a second modulation arm, the two ends of which are respectively connected to the input waveguide and the output waveguide, and the second modulation arm is configured as a SISCAP or a waveguide.

[0030] Preferably, the input waveguide, output waveguide, and body are all made of monocrystalline silicon; the gate is made of polycrystalline silicon; and the insulating dielectric layer is made of one or more of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, and bismuth oxide.

[0031] In the modulator fabrication method provided by this invention, the interface structure of the input waveguide-SISCAP and SISCAP-output waveguide is redesigned so that both the input and output waveguides are flush with the top surface of the gate. This ensures that the device cross-section is continuous and without abrupt changes in the vertical direction, thereby limiting interface reflection. Since the thickness of the bulk is less than the thickness of the input and output waveguides, the height difference between the input waveguide, output waveguide, and bulk can be used for CMP (Continuous Metallurgical Processing) to control the gate thickness. While controlling the gate thickness, the roughness of the top of the polysilicon gate is reduced, thereby reducing interface scattering.

[0032] The modulator provided by this invention and the manufacturing method of the modulator provided by this invention belong to the same inventive concept. Therefore, the modulator provided by this invention has at least all the advantages of the manufacturing method of the modulator provided by this invention, which will not be repeated here. Attached Figure Description

[0033] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0034] Figure 1 This is a schematic diagram of a partial structure of the existing SISCAP MZM.

[0035] Figure 2 This is a schematic diagram of the SISCAP MZM structure according to an embodiment of the present invention;

[0036] Figure 3 This is a partial structural diagram of the SISCAP MZM according to an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the YZ cross section of a SISCAP MZM according to an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the XZ cross section of a SISCAP MZM according to an embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram of the membrane structure according to another embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of the structure after etching the top silicon layer according to another embodiment of the present invention;

[0041] Figure 8 This is a schematic diagram of the structure after the dielectric layer is formed according to another embodiment of the present invention;

[0042] Figure 9 This is a schematic diagram of the structure after the surrounding dielectric layer is formed according to another embodiment of the present invention;

[0043] Figure 10 This is a schematic diagram of the structure after removing the stop layer and the pad oxide layer according to another embodiment of the present invention;

[0044] Figure 11 This is a schematic diagram of the structure behind the surrounding dielectric layer in the region where the thinned body and gate are located, according to another embodiment of the present invention;

[0045] Figure 12 This is a schematic diagram of the structure after covering the insulating dielectric layer according to another embodiment of the present invention;

[0046] Figure 13 This is a schematic diagram of the structure after depositing a polycrystalline silicon layer according to another embodiment of the present invention;

[0047] Figure 14 This is a schematic diagram of the structure after thinning the polysilicon layer to expose the top surface of the input waveguide, output waveguide and surrounding dielectric layer in another embodiment of the present invention;

[0048] Figure 15 This is a schematic diagram of the structure outside the gate region according to another embodiment of the present invention;

[0049] Figure 16 This is a schematic diagram of the structure after the top covering layer is formed and planarized according to another embodiment of the present invention;

[0050] Figure 17 This is a schematic diagram of the structure after the contact electrode is formed according to another embodiment of the present invention.

[0051] Figure 18This is an execution flowchart of another embodiment of the present invention.

[0052] Appendix Figure 1 middle:

[0053] 10. Input waveguide; 20. Modulation arm.

[0054] Appendix Figure 3 -Appendix Figure 18 middle:

[0055] 100, Substrate; 101, Silicon Substrate; 102, Buried Oxide Layer; 200, Top Silicon Layer; 201, Input Waveguide; 202, Second Modulation Arm; 203, Body; 204, Output Waveguide; 300, Dielectric Layer; 301, Surrounding Dielectric Layer; 302, Groove; 400, Insulating Dielectric Layer; 500, Polysilicon Layer; 501, Polysilicon Pattern; 502, Gate; 600, Top Cap Layer; 700, Contact Electrode; 800, Pad Oxide Layer; 900, Stop Layer. Detailed Implementation

[0056] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0057] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0058] The inventors discovered that in a conventional SISCAP-type Mach-Zehnder modulator, the bulk, input waveguide, and output waveguide are located on the same layer, while the grating is located above them. Therefore, when light propagates from the input waveguide into the modulation arm and then into the output waveguide, there are abrupt changes in cross-section at the junction of the input waveguide, output waveguide, and modulation arm. In particular, the abrupt changes in the vertical direction lead to significant changes in mode size and severe interface reflection. Furthermore, the top surface roughness of the directly deposited polycrystalline silicon grating is relatively large, which will cause severe interface scattering.

[0059] Based on this, the core idea of ​​this invention lies in designing the interface structure and fabrication method of the input waveguide-SISCAP and SISCAP-output waveguide, ensuring that both the input and output waveguides are flush with the top of the gate. This results in a continuous and abrupt change in the vertical cross-section of the device, limiting interface reflection. Simultaneously, since the thickness of the bulk in this interface structure is less than the thickness of the input and output waveguides, the height difference between the input waveguide, output waveguide, and bulk can be directly utilized for CMP processing to control the gate thickness. This control of the gate thickness reduces the roughness of the polysilicon gate top, thereby reducing interface scattering. Solving the severe interface reflection and scattering problems of SISCAP MZM can reduce the overall optical loss of the device, which helps to reduce the link optical power budget and the sensitivity requirements of the photodetector.

[0060] For details, please refer to Figures 2-18 This is a schematic diagram of an embodiment of the present invention. Figure 18 As shown, a method for manufacturing a modulator includes:

[0061] S1, as Figure 10 As shown, a substrate 100 is provided, on which an input waveguide 201, an output waveguide 204, a body 203, and a surrounding dielectric layer 301 are formed. The top surface of the surrounding dielectric layer 301 is not lower than the top surfaces of the input waveguide 201, the output waveguide 204, and the body 203. The substrate 100 includes a stacked silicon substrate 101 and a buried oxide layer 102. A top silicon layer 200 is present on the substrate 100. The substrate 100 and the top silicon layer 200 together constitute an SOI wafer. The top silicon layer 200 is made of monocrystalline silicon.

[0062] The formation of the input waveguide 201, the output waveguide 204, the body 203, and the surrounding dielectric layer 301 on the substrate 100 includes:

[0063] First, such as Figure 6 As shown, a pad oxide layer 800 and a stop layer 900 are sequentially formed on the top silicon layer 200. The pad oxide layer 800 is made of silicon oxide, and the stop layer 900 is made of silicon nitride.

[0064] Secondly, such as Figure 7 As shown, the multi-layer structure is patterned, and the top silicon layer 200 is photolithographically etched to the substrate 100 to remove the area other than the body 203, the input waveguide 201 and the output waveguide 204.

[0065] Furthermore, such as Figure 8As shown, a dielectric layer 300 is formed on the substrate 100, and the thickness of the dielectric layer 300 is not less than the thickness of the top silicon layer 200. The dielectric layer 300 is made of silicon oxide. It should be noted that the thickness of the dielectric layer 300 needs to be higher than or flush with the top silicon layer 200 so that the dielectric layer 300 can be thinned later to form an input waveguide 201, an output waveguide 204, a body 203 and a surrounding dielectric layer 301 of the same height.

[0066] Finally, as Figure 10 As shown, the dielectric layer 300 is thinned until the input waveguide 201, output waveguide 204 and body 203 are exposed, and a surrounding dielectric layer 301 is formed.

[0067] In one embodiment, considering subsequent CMP processes, the thickness of the dielectric layer 300 is greater than the sum of the thicknesses of the top silicon layer 200, the pad oxide layer 800, and the stop layer 900. For example... Figure 9 As shown, when thinning the dielectric layer 300, the dielectric layer 300 is polished using CMP process until the top surface of the stop layer 900 is exposed. Then, the stop layer 900 is removed by wet etching, and the pad oxide layer 800 is removed, thereby exposing the input waveguide 201, the output waveguide 204 and the body 203.

[0068] Understandably, after the stop layer 900 is removed by wet etching, there is a height difference between the top surface of the pad oxide layer 800 and the top surface of the surrounding dielectric layer 301, which is equal to the thickness of the stop layer 900. Similarly, the pad oxide layer 800 is removed by wet etching, which also thins the thickness of the surrounding dielectric layer 301. Since the pad oxide layer 800 is generally formed by high-temperature thermal growth, while the surrounding dielectric layer 301 is generally formed by chemical vapor deposition (CVD), the speed of wet etching of the surrounding dielectric layer 301 is much faster than that of etching the pad oxide layer 800. Therefore, after this step, the height difference can be basically smoothed out, that is, the top surface of the surrounding dielectric layer 301 is flush with the top surfaces of the input waveguide 201, the output waveguide 204, the second modulation arm 202, and the body 203.

[0069] Here, the second modulation arm 202 can be configured as a simple waveguide structure to form a single SISCAP modulation arm structure in subsequent processes, or it can be configured as a SISCAP and the gate 502 and body 203 can be formed using the method of this case to form a dual SISCAP modulation arm structure.

[0070] For example, after forming the input waveguide 201, the output waveguide 204 and the body 203, and before depositing the polysilicon layer 500, ions of a first conductivity type are implanted into the body 203.

[0071] S2, as Figure 11 As shown, photolithography and dry etching thin the body 203 and the surrounding dielectric layer 301 of the area where the gate 502 is located. The two are thinned to the same thickness, forming a groove 302 in the area where the body 203 and the gate 502 are located. The remaining thickness of the body 203 at this time is the thickness of the final structure.

[0072] S3, as Figure 12 As shown, an insulating dielectric layer 400 is formed on the top of the body 203. The insulating dielectric layer 400 is made of one or more of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, and bismuth oxide in a stacked combination. For example, the insulating dielectric layer 400 is made of silicon oxide. An ultrathin silicon oxide layer is grown on the body 203 as the insulating dielectric layer 400 by thermal oxidation. The insulating dielectric layer 400 is thin and its top surface is much lower than the height of the groove 302, for example, 3-12 nm. There is an insulating dielectric layer 400 of a certain thickness in the groove 302. During the deposition of the insulating dielectric layer 400, part of the insulating dielectric layer 400 may adhere to the sidewalls of the groove 302 that are in contact with the input waveguide 201, the output waveguide 204, and the surrounding dielectric layer 301. However, the insulating dielectric layer 400 on the sidewalls of the groove 302 has no device function. Therefore, the insulating dielectric layer 400 on the sidewalls of the groove 302 can be retained or removed according to the current device process flow.

[0073] S4, such as Figure 13 As shown, a polysilicon layer 500 is deposited, and the thickness of the polysilicon layer 500 is not less than the depth of the groove 302. Specifically, a polysilicon layer 500 is subsequently grown on the groove 302 and the surrounding dielectric layer 301, input waveguide 201, and output waveguide 204.

[0074] S5, such as Figure 14 As shown, the polysilicon layer 500 is thinned using a CMP process to expose the top surface of the input waveguide 201, output waveguide 204, and surrounding dielectric layer 301, forming a polysilicon pattern 501 within the groove 302. As described above, since the top surface of the surrounding dielectric layer 301 is flush with the top surfaces of the input waveguide 201, output waveguide 204, second modulation arm 202, and body 203, the CMP process thins the polysilicon layer 500 to the top surface of the surrounding dielectric layer 301.

[0075] After forming the polysilicon pattern 501, ions of a second conductivity type are implanted into the region of the gate 502 on the polysilicon pattern 501, followed by a rapid thermal annealing process to repair ion implantation damage and activate impurities. The conductivity types of the implanted ions in the body 203 and the gate 502 are opposite; for example, the first conductivity type is P-type, such as boron, and the second conductivity type is N-type, such as phosphorus. However, in other embodiments of the present invention, the first conductivity type is N-type, and correspondingly, the second conductivity type is P-type.

[0076] S6, such as Figure 15 As shown, the polysilicon pattern 501 outside the gate 502 region is further etched away to form the gate 502. The final gate 502 is flush with the top surface of the input waveguide 201, the output waveguide 204, and the surrounding dielectric layer 301.

[0077] S7, such as Figure 16 As shown, after forming the gate 502, a top capping layer 600 is deposited, and then the top capping layer 600 is thinned to the required thickness using a CMP process. The material of the top capping layer 600 is, for example, silicon oxide. Figure 17 As shown, contact electrodes 700 are respectively connected to the body 203 and the gate 502 on the top cover layer 600. The two contact electrodes 700 pass through the top cover layer 600 and directly contact and conduct with the gate 502 and the body 203 below.

[0078] For example, a 220nm top silicon layer 200 is used as a substrate 100, a 5-20nm silicon oxide pad oxide layer 800 is thermally grown, and then a 30-80nm silicon nitride stop layer 900 is deposited by CVD. Figure 6 As shown. The 220nm top silicon layer 200, excluding the input waveguide 201, the second modulation arm 202, the output waveguide 204, and the body 203 of the SISCAP, is removed sequentially by photolithography and dry etching. Figure 7 As shown, then CVD deposition of at least 300 nm SiO2 is performed as the dielectric layer 300, as... Figure 8 As shown, the CMP process polishing dielectric layer 300 stops on the silicon nitride stop layer 900, forming a surrounding dielectric layer 301, as... Figure 9 As shown, the silicon nitride stop layer 900 is removed by hot phosphoric acid wet process, and then the pad oxide layer 800 is removed by DHF wet process. After this step, the height difference between the surrounding dielectric layer 301 and the input waveguide 201 and other structures can be basically smoothed out. That is, the top surface of the surrounding dielectric layer 301 is flush with the top surfaces of the input waveguide 201, the output waveguide 204, the second modulation arm 202 and the body 203. Figure 10 As shown, photolithography was performed on body 203 followed by P-type ion implantation at a dose of 10. 13 cm -2 The order of magnitude. Subsequently, photolithography and dry etching are used to thin the surrounding dielectric layer 301 of the regions where the body 203 and gate 502 are located by 70-150 nm each, as shown in the example. Figure 11 As shown, a 3-12 nm SiO2 layer is then grown on bulk 203 via thermal oxidation as an insulating dielectric layer 400, as shown. Figure 12 As shown. Next, a polycrystalline silicon layer of at least 250 nm is deposited by CVD, as shown. Figure 13As shown, the CMP process then grinds the polysilicon layer 500 onto the top surface of the surrounding dielectric layer 301, as... Figure 14 As shown. Photolithography was performed on the gate 502 region, followed by N-type ion implantation at a dose of 10. 13 cm -2 At this scale, it's clear that N-type ion implantation can also be performed after removing the polysilicon pattern 502 outside the gate 502 to form the gate 502. No specific restrictions are placed here. Then, rapid thermal annealing at 1000℃ is used to repair damage and activate impurities. Next, photolithography and dry etching are used sequentially to remove the polysilicon pattern 501 outside the gate 502 region, as shown below. Figure 15 As shown, at least 500 nm of SiO2 is deposited by CVD as a top capping layer 600, and the top capping layer 600 is polished using a CMP process to reduce the remaining thickness to at least 300 nm. Figure 16 As shown, the final contact electrode 700 is fabricated, as follows: Figure 17 As shown.

[0079] The interface structures of the input waveguide-SISCAP and SISCAP-output waveguide were redesigned using the above process. The thickness of the gate 502 was directly controlled by utilizing the difference between the thickness of the body 203 and the thicknesses of the input waveguide 201 and the output waveguide 204. This ensured that both the input waveguide 201 and the output waveguide 204 were flush with the top of the gate 502, resulting in a continuous and abrupt cross-section of the device in the vertical direction, thus limiting interface reflection. The CMP process was used to control the thickness of the gate 502 while simultaneously reducing the roughness of the polysilicon gate top, thereby reducing interface scattering.

[0080] Based on the same technical concept, this disclosure also provides a modulator, which is prepared using the modulator manufacturing method described above, such as... Figures 2-5 As shown, it includes:

[0081] The first modulation arm is configured as a SISCAP, which includes a stacked body 203 and a gate 502, the body 203 and the gate 502 partially overlapping in the horizontal direction, and the body 203 and the gate 502 are separated by an insulating dielectric layer 400.

[0082] An input waveguide 201 is provided, the end of which is connected to a partially overlapping area of ​​the body 203.

[0083] Output waveguide 204, the end of output waveguide 204 is connected to a partially overlapping area of ​​body 203, wherein the upper surfaces of input waveguide 201 and output waveguide 204 are flush with the top surface of gate 502, and the lower surfaces of input waveguide 201 and output waveguide 204 are flush with the bottom surface of body 203.

[0084] The second modulation arm 202 is connected at both ends to the input waveguide 201 and the output waveguide 204, respectively. The second modulation arm 202 is configured as a SISCAP or a waveguide.

[0085] Here, the second modulation arm 202 can be configured as a simple waveguide structure to form a single SISCAP modulation arm structure in subsequent processes, or it can be configured as a SISCAP and the gate 502 and body 203 can be formed using the method of this case to form a dual SISCAP modulation arm structure.

[0086] like Figures 3-5 As shown, the input waveguide 201 and output waveguide 204 are aligned with SISCAP in the vertical direction. The input waveguide 201, output waveguide 204, and body 203 have the same height. CMP (Continuous Motion Processing) is performed using the height difference between the surrounding dielectric layer 301 and the input waveguide 201, output waveguide 204, and body 203 to control the thickness of the gate 502 and simultaneously reduce the roughness of the top surface of the gate 502. The input waveguide 201, output waveguide 204, and body 203 are all made of monocrystalline silicon; the gate 502 is made of polycrystalline silicon; and the insulating dielectric layer 400 is made of one or more of the following materials in a stacked combination: silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, and bismuth oxide.

[0087] like Figure 5 As shown, there is an insulating dielectric layer 400 of a certain thickness in the groove 302. In the above description of the manufacturing method of the modulator, during the deposition of the insulating dielectric layer 400, part of the insulating dielectric layer 400 may be attached to the sidewall of the groove 302 that is connected to the input waveguide 201 and the output waveguide 204. However, the insulating dielectric layer 400 at the sidewall of the groove 302 has no device function. Therefore, the insulating dielectric layer 400 at the sidewall of the groove 302 can be retained or removed according to the current device process flow.

[0088] In the modulator and its manufacturing method disclosed herein, by reducing the bulk thickness and controlling the gate thickness using CMP (Continuous Metallurgical Processing) based on the height difference between the input waveguide, output waveguide, and bulk, the input / output waveguides can be flush with the top of the gate. This minimizes cross-sectional changes and the resulting interface reflections when light is coupled from the input waveguide into the SISCAP and from the SISCAP into the output waveguide. Modeling and simulation using optoelectronic simulation software, in one example, this interface optimization strategy can reduce optical loss from -8.99 dB to -5.85 dB. Furthermore, CMP can reduce the roughness of the top of the CVD-deposited polycrystalline silicon gate from ~5 nm to below 2.5 nm, significantly reducing interface scattering and thus lowering optical loss.

[0089] The essential feature of this SISCAP MZM design is that the input / output waveguides are aligned with the SISCAP in the vertical direction, while CMP is performed using the height difference between the input / output waveguides and the bulk to reduce the roughness of the gate top surface. Therefore, regardless of whether the SISCAP MZM uses a single or dual SISCAP modulation arm, the thickness of the SOI silicon wafer with the top silicon layer, the thickness difference between the bulk and the input / output waveguides, the type of dielectric material used as the stop layer, the thickness of the dielectric material film used, or whether the doping types of the gate and bulk regions are swapped, none of these exceed the scope of disclosure and protection of this invention.

[0090] It should be noted that the various dimensional parameters of the MZM provided in this disclosure (such as the thickness / width / length of the bulk and gate, the thickness / width / length of the input waveguide and output waveguide, the thickness of the SISCAP ultrathin dielectric, the width and length of the contact electrode, and the width and depth of the doped region) as well as the various process parameters for fabricating the device (such as the material and energy and dosage of ion implantation, the temperature and time of annealing, the reaction source and temperature for CVD deposition of polycrystalline silicon, and the reaction source and temperature for CVD deposition of silicon dioxide) are not limited to the values ​​provided in the specific embodiments, and are all adjustable within a certain range.

[0091] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a modulator, characterized in that, Includes the following steps: A substrate is provided on which an input waveguide, an output waveguide, a volume, and a surrounding dielectric layer are formed, wherein the top surface of the surrounding dielectric layer is not lower than the top surface of the input waveguide, the output waveguide, and the volume; The body and the surrounding dielectric layer in the area where the gate is located are etched and thinned to form a groove; An insulating dielectric layer is formed on the top of the body; A polycrystalline silicon layer is deposited, wherein the thickness of the polycrystalline silicon layer is not less than the depth of the groove; The polysilicon layer is thinned at least to expose the top surface of the input waveguide, output waveguide and surrounding dielectric layer using a CMP process, and a polysilicon pattern is formed in the groove. Continue etching to remove the polysilicon pattern outside the gate region to form the gate.

2. The method for manufacturing a modulator according to claim 1, characterized in that, The substrate has a top silicon layer, wherein forming an input waveguide, an output waveguide, a bulk layer, and a surrounding dielectric layer on the substrate includes: A pad oxide layer and a stop layer are sequentially formed on the top silicon layer; Photolithography and etching are performed on the top silicon layer to the substrate to remove areas other than the bulk, input waveguide, and output waveguide; A dielectric layer is formed on the substrate, and the thickness of the dielectric layer is not less than the thickness of the top silicon layer; The dielectric layer is thinned until the input waveguide, output waveguide, and volume are exposed, and a surrounding dielectric layer is formed.

3. The method for manufacturing a modulator according to claim 2, characterized in that, The thickness of the dielectric layer is greater than the sum of the thicknesses of the top silicon layer, the pad oxide layer, and the stop layer. When thinning the dielectric layer, the dielectric layer is polished using a CMP process until the top surface of the stop layer is exposed. Then, the stop layer and the pad oxide layer are removed by wet etching, thereby exposing the input waveguide, the output waveguide, and the bulk.

4. The method for manufacturing a modulator according to claim 1, characterized in that, After the input waveguide, output waveguide and bulk are formed, and before the polycrystalline silicon layer is deposited, ions of a first conductivity type are implanted into the bulk.

5. The method for manufacturing a modulator according to claim 1, characterized in that, After forming the polysilicon pattern, second conductivity type ions are implanted into the gate region on the polysilicon pattern, and then a rapid thermal annealing process is performed to continue etching away the polysilicon pattern outside the gate region to form the gate.

6. The method for manufacturing a modulator according to claim 1, characterized in that, After the gate is formed, a top capping layer is deposited, and then the top capping layer is thinned to the required thickness by a CMP process. Contact electrodes that are connected to the body and the gate are then fabricated on the top capping layer.

7. The method for manufacturing a modulator according to claim 2, characterized in that, The stop layer is made of silicon nitride, the pad oxide layer is made of silicon oxide, the top silicon layer is made of monocrystalline silicon, and the insulating dielectric layer is made of one or more of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, and bismuth oxide. The substrate includes a stacked silicon substrate and a buried oxide layer. The substrate and the top silicon layer together constitute an SOI wafer.

8. A modulator, characterized in that, The modulator is prepared by the manufacturing method of any one of claims 1-7, comprising: The first modulation arm is configured as a SISCAP, which includes a stacked body and a gate, the body and the gate having a partially overlapping area in the horizontal direction, and the body and the gate being separated by an insulating dielectric layer. An input waveguide, wherein the end of the input waveguide is connected to a partially overlapping region of the body; An output waveguide is provided, the end of which is connected to a partially overlapping area of ​​the body. The upper surfaces of both the input and output waveguides are flush with the top surface of the gate, and the lower surfaces of both the input and output waveguides are flush with the bottom surface of the body.

9. The modulator according to claim 8, characterized in that, It also includes a second modulation arm, the two ends of which are connected to the input waveguide and the output waveguide, respectively. The second modulation arm is configured as a SISCAP or a waveguide.

10. The modulator according to claim 8, characterized in that, The input waveguide, output waveguide, and body are all made of monocrystalline silicon; the gate is made of polycrystalline silicon; and the insulating dielectric layer is made of one or more of silicon oxide, silicon nitride, hafnium oxide, silicon oxynitride, and bismuth oxide in a stacked combination.

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