Edac hardened memory single event upset test method, system, and medium
By reducing the flux rate or increasing the refresh cycle during high-energy pulsed ion beam irradiation, and taking advantage of the intermittent nature of the high-energy pulsed ion beam, the accuracy problem of single-event flip section testing of EDAC ruggedized memory was solved, and accurate testing under drastic fluctuation conditions was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2025-07-11
- Publication Date
- 2026-06-26
AI Technical Summary
Existing technologies make it difficult to accurately test the single-event flip cross section of EDAC ruggedized memory under high-energy pulsed ion beams with drastic fluence rate fluctuations.
By reducing the average flux rate or increasing the EDAC refresh cycle during high-energy pulsed ion beam irradiation, the EDAC hardened memory can complete SEU data processing within the pulse gap time. By utilizing the intermittent characteristics of the high-energy pulsed ion beam, accurate testing of the single-particle flip section of the EDAC hardened memory can be achieved.
Accurate testing of the single-particle flip section of EDAC-hardened memory was achieved under high-energy pulsed ion beams with drastic fluence rate fluctuations. The method is simple and easy to implement.
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Figure CN122290673A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to radiation resistance testing technology in the field of memory, specifically to a single-event upset test method, system, and medium for EDAC-hardened memory. Background Technology
[0002] Single event effect (SEE) refers to the abnormal functioning of electronic devices caused by high-energy particle impacts in a radiation environment. This includes single event upsets (SEUs) and single event functional interruptions (SEFIs). With the widespread application of semiconductor devices in radiation environments such as aerospace and nuclear energy, radiation resistance testing has become a critical step. EDAC-hardened memory refers to memory that uses EDAC (Error Detection and Correction) for single event hardening. When a SEU is detected in the memory, the EDAC circuitry inside the hardened memory corrects the data to ensure its integrity.
[0003] Currently available space environment simulation devices in China include both continuous beam and pulsed beam types. The fluence rate of a continuous beam is relatively stable with no drastic changes, while the fluence rate of a pulsed beam fluctuates dramatically. The fluence rate is zero between pulses, but the instantaneous peak fluence rate at the onset of a pulse can be several times the average fluence rate. For EDAC-hardened memories, fluence rate variations have a significant impact on the SEU cross-section. During single-event experiments, the EDAC refresh cycle is generally no more than 1 second, much shorter than the pulse duration. For pulsed beams with drastically fluence rate fluctuations, the instantaneous fluence rate will be much higher than that of a continuous beam with the same average fluence rate. Under the same irradiation fluence conditions, the measured SEU cross-section will be larger than that measured with a continuous beam. Therefore, how to accurately test the single-event flip cross-section of EDAC-hardened memories has become a critical technical problem that urgently needs to be solved. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a simple and easy-to-implement method, system and medium for single-event flip testing of EDAC ruggedized memory, which addresses the above-mentioned problems of the prior art. The present invention aims to achieve accurate testing of the single-event flip cross section of EDAC ruggedized memory under high-energy pulsed ion beam with drastic fluence rate fluctuations.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A single-event upset test method for EDAC-hardened memory includes the following steps: S1, Run the EDAC hardened memory single-event test system, and initialize the single-event flip SEU count K to 0; S2, Irradiate the EDAC hardened memory with a high-energy pulsed ion beam with an average flux rate F, wherein the pulse duration of the high-energy ion beam is T1 and the pulse gap time is T2, and start to count the total irradiation flux Q. S3. Determine whether the SEU count of the EDAC hardened memory single-event test system can be completed within the pulse gap time T2. If the count can be completed within the pulse gap time T2, keep the conditions unchanged and continue irradiation until the total irradiation fluence Q reaches the preset value. Then, stop the high-energy pulsed ion beam irradiation, stop the operation of the EDAC hardened memory test system, count the single-event reversal SEU count K, and calculate the single-event reversal cross section K / Q of the EDAC hardened memory.
[0006] Optionally, step S3 further includes stopping high-energy pulsed ion beam irradiation and stopping the operation of the EDAC hardened memory test system when the counting cannot be completed within the pulse gap time T2, reducing the average fluence rate F of the high-energy pulsed ion beam or increasing the refresh cycle S of the EDAC hardened memory; restarting the EDAC hardened memory single-event test system, clearing the single-event flip SEU count K to 0 and the total irradiation fluence Q to 0, and jumping to step S2.
[0007] Optionally, before step S1, the refresh cycle S of the EDAC hardened memory is configured, and the average flux rate F is initialized.
[0008] Optionally, when initializing the configuration of the average injection rate F, the value of the average injection rate F is 3000 ions·cm. -2 ·s -1 The average fluence rate F of the high-energy pulsed ion beam was reduced to 2000 ions·cm. -2 ·s -1 .
[0009] Optionally, in step S2, when the EDAC hardened memory is irradiated with a high-energy pulsed ion beam with an average flux rate F, the high-energy ion beam pulse time T1 is 3 seconds and the pulse gap time T2 is 9 seconds.
[0010] Optionally, in step S3, when the total irradiation flux Q reaches a preset value, the preset value is 1×10⁻⁶. 7 ions·cm -2 .
[0011] Optionally, the EDAC circuit in the EDAC-reinforced memory is an extended Hamming code encoding and decoding circuit with correction of one bit error and detection of two bit errors, where correction of one bit error and detection of two bit errors refer to correcting one bit error and detecting two bit errors.
[0012] Furthermore, the present invention also provides an EDAC-hardened memory single-event upset testing system, comprising a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the EDAC-hardened memory single-event upset testing method.
[0013] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the EDAC-reinforced memory single-event flip test method by a processor.
[0014] In addition, the present invention also provides a computer program product, including a computer program or instructions that are programmed or configured to execute the EDAC hardened memory single-event flip test method via a processor.
[0015] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: The method of the present invention utilizes the intermittent characteristics of high-energy pulsed ion beams. By reducing the average fluence rate of the high-energy pulsed ion beam or increasing the EDAC refresh cycle, the EDAC hardened memory can process the SEU data that has occurred completely before the next ion pulse arrives. It can achieve accurate testing of the single-particle flip section of the EDAC hardened memory under high-energy pulsed ion beams with drastic fluence rate fluctuations. It has the advantages of simple implementation method and easy implementation. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the basic process of the method in an embodiment of the present invention.
[0017] Figure 2 This is a detailed flowchart illustrating the method of an embodiment of the present invention. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0019] like Figure 1 As shown, the single-event upset test method for EDAC-hardened memory in this embodiment includes the following steps: S1, Run the EDAC hardened memory single-event test system, and initialize the single-event flip SEU count K to 0; S2, Irradiate the EDAC hardened memory with a high-energy pulsed ion beam with an average flux rate F, wherein the pulse duration of the high-energy ion beam is T1 and the pulse gap time is T2, and start to count the total irradiation flux Q. S3. Determine whether the SEU count of the EDAC hardened memory single-event test system can be completed within the pulse gap time T2. If the count can be completed within the pulse gap time T2, keep the conditions unchanged and continue irradiation until the total irradiation fluence Q reaches the preset value. Then, stop the high-energy pulsed ion beam irradiation, stop the operation of the EDAC hardened memory test system, count the single-event reversal SEU count K, and calculate the single-event reversal cross section K / Q of the EDAC hardened memory.
[0020] As an optional implementation, the EDAC-hardened memory in this embodiment has a capacity of 8Mb. The EDAC circuit is an extended Hamming code encoder-decoder circuit with correction for one bit error and detection for two bit errors. It should be noted that the extended Hamming code encoder-decoder circuit is a known existing encoder-decoder circuit, so its implementation will not be described in detail here.
[0021] See Figure 2 In step S3 of this embodiment, if the counting cannot be completed within the pulse gap time T2, the high-energy pulsed ion beam irradiation is stopped, the EDAC hardened memory test system is stopped, the average fluence rate F of the high-energy pulsed ion beam is reduced or the refresh cycle S of the EDAC hardened memory is increased; the EDAC hardened memory single-event test system is restarted, the single-event flip SEU count K is cleared to 0, the total irradiation fluence Q is cleared to 0, and the process jumps to step S2.
[0022] See Figure 2 Before step S1 in this embodiment, the refresh cycle S of the EDAC hardened memory is configured, and the average injection rate F is initialized. As an optional implementation, in this embodiment, the value of the average injection rate F during initial configuration is 3000 ions·cm. -2 ·s -1 The average fluence rate F of the high-energy pulsed ion beam was reduced to 2000 ions·cm. -2 ·s -1 Among them, ions·cm -2 ·s -1 It is a compound unit used to represent the number of ions passing through an area of one square centimeter per second, where "ions" represents the number of ions, and "s" represents the number of ions. -1 "" indicates per second.
[0023] As an optional implementation, in step S2 of this embodiment, when the EDAC hardened memory is irradiated with a high-energy pulsed ion beam with an average flux rate F, the high-energy ion beam pulse time T1 is 3 seconds and the pulse gap time T2 is 9 seconds. That is, when the EDAC hardened memory is irradiated with a high-energy pulsed ion beam with an average flux rate F, the high-energy ion beam pulse time is 3 seconds and the pulse gap time is 9 seconds, and the total irradiation flux Q is counted. As an optional implementation, in step S3 of this embodiment, the total irradiation flux Q reaches a preset value, which is 1×10⁻⁶. 7 ions·cm -2 Among them, ions·cm -2 It is a composite unit used to represent the number of ions per square centimeter, where "ions" indicates the number of ions. If the counting can be completed within 9 seconds, radiation will continue under unchanged conditions until the total irradiation fluence Q reaches 1 × 10⁻⁶. 7 ions·cm -2 At this time, high-energy pulsed ion beam irradiation is stopped, the EDAC-hardened memory experimental system is shut down, the single-event upset (SEU) count K is counted, and the EDAC-hardened memory SEU cross-section K / Q is calculated. For example, in this embodiment, the specific value of the EDAC-hardened memory SEU cross-section K / Q is 3.53 × 10⁻⁶. -4 cm 2 .
[0024] In summary, the single-event upset (SEU) testing method for EDAC-hardened memory in this embodiment utilizes the intermittent nature of high-energy pulsed ion beams. By reducing the average fluence rate of the high-energy pulsed ion beam or increasing the EDAC refresh cycle, the EDAC-hardened memory can process all the SEU data that has occurred before the next ion pulse arrives. This enables accurate testing of the EDAC-hardened memory's SEU cross-section under high-energy pulsed ion beams with drastically fluctuating fluence rates. This method achieves accurate testing of the EDAC-hardened memory's SEU cross-section under high-energy pulsed ion beams with drastically fluctuating fluence rates, and has the advantages of being simple and easy to implement.
[0025] Furthermore, this embodiment also provides an EDAC-hardened memory single-event upset testing system, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the EDAC-hardened memory single-event upset testing method.
[0026] In addition, this embodiment also provides a computer-readable storage medium storing a computer program or instructions that are programmed or configured to execute the EDAC-reinforced memory single-event flip test method by a processor.
[0027] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the EDAC hardened memory single-event flip test method via a processor.
[0028] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.
Claims
1. A method for single-event upset testing of EDAC-hardened memory, characterized in that, Includes the following steps: S1, Run the EDAC hardened memory single-event test system, and initialize the single-event flip SEU count K to 0; S2, Irradiate the EDAC hardened memory with a high-energy pulsed ion beam with an average flux rate F, wherein the pulse duration of the high-energy ion beam is T1 and the pulse gap time is T2, and start to count the total irradiation flux Q. S3. Determine whether the SEU count of the EDAC hardened memory single-event test system can be completed within the pulse gap time T2. If the count can be completed within the pulse gap time T2, keep the conditions unchanged and continue irradiation until the total irradiation fluence Q reaches the preset value. Then, stop the high-energy pulsed ion beam irradiation, stop the operation of the EDAC hardened memory test system, count the single-event reversal SEU count K, and calculate the single-event reversal cross section K / Q of the EDAC hardened memory.
2. The single-event upset test method for EDAC-hardened memory according to claim 1, characterized in that, Step S3 also includes stopping high-energy pulsed ion beam irradiation and stopping the EDAC hardened memory test system when the counting cannot be completed within the pulse gap time T2, reducing the average fluence rate F of the high-energy pulsed ion beam or increasing the refresh cycle S of the EDAC hardened memory; restarting the EDAC hardened memory single-event test system, clearing the single-event flip SEU count K to 0 and the total irradiation fluence Q to 0, and jumping to step S2.
3. The single-event upset test method for EDAC-hardened memory according to claim 2, characterized in that, Before step S1, the refresh cycle S of the EDAC hardened memory is configured, and the average flux rate F is initialized.
4. The single-event upset test method for EDAC-hardened memory according to claim 3, characterized in that, When initializing the configuration, the average injection rate F is set to 3000 ions·cm. -2 ·s -1 The average fluence rate F of the high-energy pulsed ion beam was reduced to 2000 ions·cm. -2 ·s -1 .
5. The single-event upset test method for EDAC-hardened memory according to claim 1, characterized in that, In step S2, when the EDAC hardened memory is irradiated with a high-energy pulsed ion beam with an average flux rate F, the high-energy ion beam pulse time T1 is 3 seconds and the pulse gap time T2 is 9 seconds.
6. The single-event upset test method for EDAC-hardened memory according to claim 1, characterized in that, In step S3, the total irradiation flux Q reaches a preset value, which is 1 × 10⁻⁶. 7 ions·cm -2 .
7. The single-event upset test method for EDAC-hardened memory according to claim 1, characterized in that, The EDAC circuit in the EDAC-reinforced memory is an extended Hamming code encoding and decoding circuit that corrects one bit error and detects two bit errors.
8. An EDAC-reinforced memory single-event upset testing system, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to perform the EDAC hardened memory single-event flip test method according to any one of claims 1 to 7.
9. A computer-readable storage medium storing a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the EDAC hardened memory single-event flip test method according to any one of claims 1 to 7 via a processor.
10. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions are programmed or configured to execute the EDAC hardened memory single-event flip test method according to any one of claims 1 to 7 via a processor.