Dut testing method, digital board and tester

Abstract

The application relates to a DUT test method, a digital board card and a test machine. An ALPG generates a first test data group of all channels according to test vector data and delivers the first test data group to an FC. The FC determines effective channels and ineffective channels according to the delivered channel mode, encodes or shields each channel, obtains a second test data group of all channels, and sends the second test data group to a TC. The TC calculates data pushing time or data sampling time of each effective channel according to timing parameters, and at each data pushing time, updates a historical test data group locked at a previous data pushing time based on the second test data group to obtain a third test data group. A TG receives the third test data group and sends the third test data group to a device under test to perform a data driving operation, or extracts response data of the device under test at a data sampling time to perform a data sampling operation. The application improves the compatibility of DUT test under a multi-channel mode.

Description

Technical Field

[0001] This application relates to the field of testing equipment technology, and in particular to a DUT testing method, digital board, and testing equipment. Background Technology

[0002] When a tester tests a device under test (DUT), it inputs an excitation signal to the DUT and collects the response signal output by the DUT. The tester acquires the response signal and compares it with the expected signal to generate comparison data. Based on the comparison data, it evaluates whether the function of the DUT is qualified.

[0003] When performing DUT testing, related technologies face NWAY testing (multi-path testing), where different values ​​of N result in multiple path modes. For different path modes, the digital board needs to change its hardware connections or redesign its underlying logic to adapt to the current path mode. However, this approach is not flexible enough, has low compatibility, and indirectly affects testing efficiency.

[0004] Currently, there is a problem of low compatibility of DUT testing in related technologies, and no effective solution has been provided. Summary of the Invention

[0005] Therefore, it is necessary to provide a DUT testing method, digital board, and testing machine that can improve path mode compatibility to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a DUT testing method applied to a digital board, the digital board comprising: an algorithm graphics generation module, a waveform synthesis module, a timing control module, and a timing generation module; the method comprising:

[0007] The algorithm graphics generation module generates a first test data set for the entire path based on the test vector data, and sends the first test data set to the waveform synthesis module;

[0008] The waveform synthesis module determines the valid and invalid paths according to the currently issued path mode, encodes the first test data of the valid path, and masks the first test data of the invalid path to obtain the second test data group of the entire path, and sends the second test data group to the timing control module.

[0009] The timing control module calculates the data push time or data sampling time of each effective path according to the timing parameters. When each data push time arrives, it partially updates the historical test data group latched at the previous data push time based on the second test data group to obtain the third test data group.

[0010] The timing generation module receives the third test data set and sends the third test data set to the device under test to perform a data-driven operation, or extracts the response data of the device under test at the data sampling time to perform a data sampling operation.

[0011] In some embodiments, the waveform synthesis module determines valid and invalid paths based on the currently issued path mode, encodes the first test data of the valid path, and masks the first test data of the invalid path to obtain a second test data set for the entire path, including:

[0012] The waveform synthesis module determines N valid paths from the full path based on the number N of paths in the path mode, and treats the remaining paths as invalid paths.

[0013] In the first test data set, the first test data of each valid path is mapped to encoded data, and the first test data of each invalid path is mapped to the encoded data of the previous valid path closest to the current invalid path.

[0014] In some embodiments, the first test data set includes first test data for all paths, and the first test data for each path includes first leading edge test data and first trailing edge test data; in the first test data set, mapping the first test data of each valid path to encoded data, and mapping the first test data of each invalid path to encoded data of the previous valid path closest to the current invalid path, includes:

[0015] The first leading edge test data and the first trailing edge test data of the effective path are mapped to obtain the first leading edge coding data and the first trailing edge coding data corresponding to the effective path;

[0016] The first leading edge test data and the first trailing edge test data of the invalid path are both mapped to the first trailing edge encoded data of the previous valid path that is closest to the current invalid path.

[0017] In some embodiments, the timing parameters include: leading edge time, trailing edge time, and period; the timing control module calculates the data push time or data sampling time of each effective path based on the timing parameters, including:

[0018] Obtain the periodic signal and the edge signal corresponding to each of the effective paths; wherein the periodic signal carries information about the period, and the edge signal carries information about the leading edge time or the trailing edge time;

[0019] For each of the aforementioned valid paths, the periods of the paths preceding the current valid path are added together to obtain the first cumulative time;

[0020] The first cumulative time is added to the current path's own along-time to obtain the second cumulative time;

[0021] The second cumulative time is used as the data push time or the data sampling time of the currently effective channel.

[0022] In some embodiments, after using the second cumulative time as the data push time or the data sampling time of the currently effective path, the method further includes:

[0023] Compare the current timing value with the calculated data push time or data sampling time;

[0024] When the current timing value is equal to any of the data push times, the timing control module is triggered to perform an update operation on the historical test data group;

[0025] When the current timing value is equal to any of the data sampling times, the timing generation module is triggered to perform the data sampling operation.

[0026] In some embodiments, before acquiring the periodic signal and edge signal corresponding to each of the effective paths, the method further includes:

[0027] The timing control module masks the timing parameters of invalid paths based on the received path mode.

[0028] In some embodiments, at each data push time, based on the second test data group, the historical test data group latched at the previous data push time is partially updated to obtain a third test data group, including:

[0029] Based on the second test data of the path corresponding to the data push time, update the historical test data of the corresponding path in the historical test data group to obtain the third test data group and latch it.

[0030] In some embodiments, the second test data set includes second leading edge test data and second trailing edge test data, the data push time includes data push leading edge time and data push trailing edge time, and the data sampling time includes data sampling leading edge time and data sampling trailing edge time;

[0031] When the current timing value is equal to any of the data push leading edge moments, based on the second leading edge test data of the path corresponding to the data push leading edge moment, update the historical leading edge test data of the corresponding path in the historical test data group to obtain the third test data group and latch it;

[0032] When the current timing value is equal to any of the data push trailing edge times, based on the second trailing edge test data of the path corresponding to the data push trailing edge time, the historical trailing edge test data of the corresponding path in the historical test data group is updated to obtain the third test data group and latched.

[0033] In some embodiments, the method further includes:

[0034] Before each of the aforementioned data push times arrives, based on the second test data of the invalid path in the second test data group, the historical test data of the corresponding path in the historical test data group is updated.

[0035] In some embodiments, the timing generation module receives the third test data set, sends the third test data set to the device under test (DUT) to perform a data-driven operation, or extracts the response data of the DUT at the data sampling time to perform a data sampling operation, including:

[0036] The timing generation module XORs the third test data of each path in the third test data group to obtain a fourth test data, and then outputs the fourth test data to the device under test; or, the timing generation module XORs the third test data of each path in the third test data group to obtain a fourth test data, and then outputs the fourth test data to the device under test after a delay.

[0037] After the timing generation module extracts the response data, it sends the response data as sample data to the next-level module for processing; or, after the timing generation module extracts the response data, it sends the response data as sample data after a delay to the next-level module for processing.

[0038] In some embodiments, the digital board further includes a comparison module corresponding one-to-one with each of the said channels; the timing generation module receives the third test data set and sends the third test data set to the device under test to perform a data-driven operation, or, after extracting the response data of the device under test at the data sampling time to perform a data sampling operation, the method further includes:

[0039] The timing generation module sends the response data as sampled data to each of the comparison modules;

[0040] The comparison module corresponding to the invalid path is masked, so that the comparison module corresponding to the valid path compares the sampled data and the expected data to obtain comparison data.

[0041] Secondly, this application provides a digital board, including: an algorithm graphics generation module, a waveform synthesis module, a timing control module, and a timing generation module connected in sequence;

[0042] The algorithm graph generation module is used to generate a first test data set for the entire path based on the test vector data, and send the first test data set to the waveform synthesis module.

[0043] The waveform synthesis module is used to determine the effective and invalid paths according to the currently issued path mode, encode the first test data of the effective path, mask the first test data of the invalid path, obtain the second test data group of the entire path, and send the second test data group to the timing control module.

[0044] The timing control module is used to calculate the data push time or data sampling time of each effective path according to the timing parameters. When each data push time arrives, it partially updates the historical test data group latched at the previous data push time based on the second test data group to obtain the third test data group.

[0045] The timing generation module is used to receive the third test data group, send the third test data group to the device under test to perform data-driven operations, or extract the response data of the device under test at the data sampling time to perform data sampling operations.

[0046] In some embodiments, the timing control module includes: a plurality of first selectors, a plurality of second selectors, a first adder, a first storage unit, and a second adder. Each first selector corresponds one-to-one with each of the aforementioned paths, and each second selector corresponds one-to-one with each of the aforementioned paths. Each first selector is connected to the first adder, and each second selector is connected to the second adder. The first storage unit is connected to both the first adder and the second adder. The timing parameters include leading edge time, trailing edge time, and period.

[0047] The first selector is used to selectively input a periodic signal or an aperiodic signal, and outputs the selected target periodic signal to the first adder; the periodic signal carries information about the period.

[0048] The second selector is used to selectively input an edge signal or a non-edge signal, and outputs the selected target edge signal to the second adder; the edge signal carries information about the leading edge time or the trailing edge time;

[0049] The first adder is used to accumulate the received target periodic signal and generate a first accumulation time;

[0050] The first storage unit is used to cache the first accumulated time output by the first adder and output the first accumulated time to the second adder;

[0051] The second adder is used to add the first cumulative time to the edge time carried by the edge signal of the current valid path to obtain the second cumulative time, which includes the data push time or the data sampling time.

[0052] In some embodiments, the timing control module further includes: a timer, a first comparator, a second comparator, and a flip-flop. The timer is connected to the first comparator and the second comparator. The first comparator is also connected to the first memory cell. The second comparator is connected to the second adder and the flip-flop. The flip-flop is also connected to the timing generation module.

[0053] The trigger is used to latch the third test data group and periodically push the third test data group to the timing generation module.

[0054] The timer is used to keep time and sends the current time value to the first comparator and the second comparator;

[0055] The first comparator is used to compare the current timing value with the total cumulative value of all valid channels, and reset the timer when the current timing value is equal to the total cumulative value of all valid channels.

[0056] The second comparator is used to compare the current timing value with the calculated data push time or the data sampling time:

[0057] When the current timing value is equal to any of the data push times, a first enable signal is output to the trigger, causing the trigger to update to obtain the third test data set;

[0058] Alternatively, when the current timing value is equal to any of the data sampling times, the timing generation module is triggered to perform the data sampling operation.

[0059] In some embodiments, the timing generation module includes: an XOR unit, a first delay unit, a second delay unit, and a third selector. The XOR unit is connected to the timing control module and the first delay unit, and the third selector is connected to the timing control module and the second delay unit.

[0060] The XOR unit is used to XOR the third test data of each path in the third test data group to obtain a fourth test data.

[0061] The first delay unit is used to delay the fourth test data before outputting it to the device under test;

[0062] The second delay unit is used to delay the response data before outputting it to the third selector to obtain sampled data;

[0063] The third selector is used to extract the sampling data of the currently effective path according to the data sampling time output by the timing control module.

[0064] In some embodiments, the digital board further includes: a comparison module and a fourth selector corresponding one-to-one with each of the said channels, wherein the comparison module is connected to the timing generation module, the fourth selector and the waveform synthesis module respectively;

[0065] The timing generation module is used to output sampled data to the comparison module;

[0066] The fourth selector is used to output a second enable signal or a disable signal to the comparison module;

[0067] The waveform synthesis module is used to output the desired data to the comparison module;

[0068] The comparison module is used to compare the sampled data and the expected data when the second enable signal is received, so as to obtain comparison data.

[0069] In some embodiments, the digital board further includes an enable module, the two ends of which are respectively connected to the algorithm graphics generation module and the fourth selector;

[0070] The enabling module is used to receive a third enabling signal representing the path mode issued by the algorithm graph generation module, and send the third enabling signal to the fourth selector to select the path of the fourth selector.

[0071] The fourth selector compares the received actual path mode with the path mode represented by the third enable signal. If the two are inconsistent, the current path is adjusted based on the received actual path mode.

[0072] Thirdly, this application provides a test machine, including: a host computer, a slave computer, and the digital board described in the second aspect above, wherein the slave computer and the digital board are connected;

[0073] The host computer is used to provide test vector data, path mode and timing parameters, and to send the test vector data, path mode and timing parameters to the digital board through the slave computer;

[0074] The digital board is used to test the device under test based on the test vector data, the path mode, and the timing parameters.

[0075] The aforementioned DUT testing method, digital board, and testing machine utilize a digital board that provides a complete set of full-path test data through an algorithmic graphics generation module. A waveform synthesis module then performs real-time masking and data mapping of invalid paths based on the configured path mode. A timing control module calculates and schedules data push and sampling times based on the independent timing parameters of each valid path. Finally, a timing generation module executes physical layer signal output and acquisition. This approach enables on-demand dynamic allocation and reuse of data paths and timing resources, allowing the digital board to directly adapt to various test programs ranging from single-path to maximum path count simply by switching path modes via software commands. This solution eliminates the need to change hardware connections or redesign underlying logic, thereby improving the path mode compatibility of DUT testing. Attached Figure Description

[0076] Figure 1 This is a schematic diagram of the test machine in one embodiment;

[0077] Figure 2 This is a schematic diagram of the internal structure of a digital board in one embodiment;

[0078] Figure 3 This is a flowchart illustrating a DUT testing method in one embodiment;

[0079] Figure 4 This is a schematic diagram of the data group flow inside the waveform synthesis module in one embodiment;

[0080] Figure 5 This is a schematic diagram of the encoding process inside the waveform synthesis module in one embodiment;

[0081] Figure 6 This is a schematic diagram of the internal structure of the timing control module in one embodiment;

[0082] Figure 7 This is a schematic diagram of the internal structure of the timing generation module in one embodiment;

[0083] Figure 8 This is a schematic diagram of the internal structure of a digital board in another embodiment.

[0084] Reference numerals: 10, Host computer; 20, Sub-computer; 30, Digital board; ALPG, Algorithm graphics generation module; FC, Waveform synthesis module; TC, Timing control module; TG, Timing generation module; MUX1, First selector; MUX2, Second selector; MUX3, Third selector; MUX4, Fourth selector; DSP1, First adder; DSP2, Second adder; R1, First memory unit; R2, Second memory unit; R3, Third memory unit; C1, First comparator; C2, Second comparator; C0, Comparison module; CNT, Timer; D, Flip-flop; XOR, Exclusive OR unit; ODELAY, First delay unit; IDELAY, Second delay unit; CPE, Enable module; DUT, Device under test. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0086] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0087] In one embodiment, Figure 1A schematic diagram of a test machine is provided. The test machine includes a host computer 10, a slave computer 20, and a digital board 30, with the slave computer 20 and the digital board 30 connected together. The host computer 10 provides test vector data, path modes, and timing parameters, and transmits these data to the digital board 30 via the slave computer 20. The digital board 30 performs tests on the device under test (DUT) based on the test vector data, path modes, and timing parameters. The host computer 10 and the slave computer 20 can be terminals, computers, or similar computing devices.

[0088] Specifically, the host computer 10 parses the test pattern file, extracts the test vector data, and identifies the path pattern ("path" is "WAY"). The path pattern can be represented by the NWAY identifier. The host computer 10 sends the test vector data and path pattern to the slave computer 20, which then sends the test vector data and path pattern to the digital board 30. There can be one or more digital boards 30. The user can set multiple sets of timing parameters through the host computer 10. The slave computer 20 will select at least one set of timing parameters and send it to each digital board 30, so that each digital board 30 includes at least one set of timing parameters. A set of timing parameters includes multiple timing parameters. In this embodiment, a set of timing parameters includes 64 timing parameters. Under the multi-path architecture (NWAY architecture) of the digital board 30, each path is configured with a set of timing parameters according to the user configuration, so that each path is equipped with the edge information and cycle period of its own path. The timing information is divided into leading-edge information and trailing-edge information. Leading-edge information represents the leading-edge time (BCLK), and trailing-edge information represents the trailing-edge time (CCLK). A timing parameter set includes the leading-edge time (BCLK), trailing-edge time (CCLK), and cycle for the current path. The cycle refers to the duration of a complete test operation allocated to each path, which can be measured in nanoseconds (ns), seconds (s), etc. The leading-edge time / trailing-edge time refers to the time interval from the start of the test cycle for that path to the transition of the drive signal; it determines when the output signal changes. For each path, each action (data push / data sampling) can have its own leading-edge time and trailing-edge time.

[0089] Specifically, the leading edge time includes the data push leading edge time and the data sampling leading edge time; the trailing edge time includes the data push trailing edge time and the data sampling trailing edge time. The corresponding edge information includes the corresponding leading edge information and trailing edge information, and the edge information carries information about the leading edge time or the trailing edge time.

[0090] Digital board 30 can be implemented using FPGA (Field-Programmable Gate Array). Figure 2 This is a schematic diagram of the internal structure of the digital board 30, as shown below. Figure 2 As shown, the digital board 30 includes: an Algorithm Pattern Generator (ALPG), a Format Controller (FC), a Timing Controller (TC), and a Timing Generator (TG), connected in sequence. The ALPG, FC, and TC are all connected to a lower-level computer 20. The lower-level computer 20 sends test vector data and path patterns to the ALPG, path patterns and at least one set of timing parameters to the FC, and path patterns to the TC. The digital board 30 executes the DUT test method line by line based on the content sent by the lower-level computer 20. Of course, those skilled in the art will know that the lower-level computer can directly send at least one set of timing parameters to the TC, while the FC only receives path patterns. The TC selects the appropriate timing parameters according to the user configuration and then calculates the data push time or data sampling time for each valid path.

[0091] Figure 3 The flowchart of the DUT test method running on this digital board 30 is shown, including the following steps:

[0092] In step S101, the algorithm graph generation module ALPG generates the first test data set of the entire path based on the test vector data, and sends the first test data set to the waveform synthesis module FC.

[0093] "Full path" refers to all paths. Assuming the digital board 30 has a total of 8 paths ("path" is equivalent to "WAY"), and the path mode is 4WAY. The algorithm graphics generation module ALPG generates the first test data set of 8WAY based on the test vector data and transmits it to the waveform synthesis module FC. The first test data set of the full path includes the first test data of each path, and the first test data of each path can be the same or different. In this embodiment, the first test data set of the full path includes the first test data of all 8 paths.

[0094] In one implementation, there are multiple rows of test vector data. The algorithm graph generation module ALPG executes each row of test vector data sequentially and generates the first test data set for the entire path based on each row of test vector data.

[0095] In step S102, the waveform synthesis module FC determines the valid and invalid paths according to the currently issued path mode, encodes the first test data of the valid path, and masks the first test data of the invalid path to obtain the second test data group of the entire path, and sends the second test data group to the timing control module TC.

[0096] The waveform synthesis module FC is responsible for data encoding and format coordination, encoding data in different formats and masking invalid data paths according to different path modes. In some embodiments, the waveform synthesis module FC can also select appropriate timing parameters according to user configuration.

[0097] In this step, the waveform synthesis module FC determines N valid paths from the entire path based on the number N paths in the path mode, and treats the remaining paths as invalid paths. In the first test data group, the first test data of each valid path is mapped to encoded data; the first test data of each invalid path is mapped to the encoded data of the previous valid path closest to the current invalid path. This setting achieves the masking of invalid paths.

[0098] In this embodiment, the path mode can be arbitrarily set. Assume there are a total of 8 paths: path 1, path 2, path 3, path 4, path 5, path 6, path 7, and path 8. If the path mode is 4WAY, then the following methods are possible:

[0099] Paths 1-4 are selected as valid paths. After encoding the data in paths 1-4, the encoded data of path 4 is used to overwrite the first test data of paths 5-8 to mask paths 5-8. Specifically, the first test data of valid paths 1-4 is mapped to obtain encoded data, and the first test data of paths 5-8 is mapped to the encoded data of path 4 to mask paths 5-8.

[0100] Alternatively, select channels 1, 3, 5, and 7 as valid channels. After encoding the data for channels 1, 3, 5, and 7, map the first test data of channel 2 to the encoded data of channel 1, map the first test data of channel 4 to the encoded data of channel 3, map the first test data of channel 6 to the encoded data of channel 5, and map the first test data of channel 8 to the encoded data of channel 7, thereby masking channels 2, 4, 6, and 8.

[0101] Alternatively, select pathways 1, 3, 4, and 6 as valid pathways. After encoding the data of pathways 1, 3, 4, and 6, map the first test data of pathway 2 to the encoded data of pathway 1, map the first test data of pathway 5 to the encoded data of pathway 4, and map the first test data of pathways 7 and 8 to the encoded data of pathway 6, so as to mask pathways 2, 5, 7, and 8.

[0102] The above pathway model is only for illustrative purposes and is not intended to limit the scope of the invention. For those skilled in the art, various modifications and improvements can be made without departing from the concept of this application, and these modifications and improvements are all within the scope of protection of this application.

[0103] In one embodiment, the first test data for each path includes first leading edge test data and first trailing edge test data. The waveform synthesis module FC receives the first test data group of the entire path and maps the first leading edge test data and first trailing edge test data of the effective path based on the path mode to obtain the first leading edge encoded data and first trailing edge encoded data corresponding to the effective path.

[0104] For the first leading edge test data and the first trailing edge test data of the invalid path, they are both mapped to the first trailing edge encoded data of the previous valid path that is closest to the current invalid path.

[0105] refer to Figure 4 The diagram illustrates the data flow within the waveform synthesis module FC. If the channel mode is 4 channels, a mapping operation (data code) is performed, mapping the first test data of the first 4 channels to their actual encoded data. The first test data of channels 5 through 8 are then mapped to the encoded data of channel 4, i.e., a masking operation is performed. If the channel mode changes to 5 channels, the first test data of the first 5 channels are mapped to their actual encoded data, and the data of channels 6 through 8 are mapped to the encoded data of channel 5, i.e., a masking operation is performed. This allows for switching between any number of channels.

[0106] refer to Figure 5The diagram shows the encoding process inside the waveform synthesis module FC. First, it receives the first test data group and determines the N-channel mode, such as 4-channel or 5-channel. It then determines whether masking is enabled. If yes, masking logic is executed; otherwise, masking is skipped, and other states are entered. The masking logic is as follows: When the current number of channels is N, the first test data of the first N channels retains its original encoding (actual encoded data) after mapping; the first test data of channels N+1 to 8 are mapped to the encoded data of channel N (i.e., the content of channel N is copied), thus masking redundant channels. For example, in 4-channel mode, the first test data of channels 5 to 8 are all mapped to the encoded data of channel 4; in 5-channel mode, the first test data of channels 6 to 8 are mapped to the encoded data of channel 5. After the above operations, the first test data of valid channels are encoded, and the first test data of invalid channels are masked, resulting in the second test data group for all channels. Next, it is determined whether a second test data set exists: if a second test data set exists, the subsequent processing continues, and the second test data set and the timing parameters of each channel are sent to the timing control module TC; if there is no second test data set, 0 is output to indicate that there is no valid input, the process ends, and the second test data set and the timing parameters of each channel are not sent to the timing control module TC.

[0107] In this embodiment, the second test data for each pathway includes second leading edge test data and second trailing edge test data.

[0108] In step S103, the timing control module TC calculates the data push time or data sampling time of each effective path according to the timing parameters. When each data push time arrives, it partially updates the historical test data group latched at the previous data push time based on the second test data group to obtain the third test data group.

[0109] Timing parameters can be sent from the waveform synthesis module FC to the timing control module TC, or directly from the host computer 10 to the timing control module TC. Timing parameters include: leading edge time, trailing edge time, and period. The timing control module TC masks the timing parameters of invalid paths based on the received path mode. Specifically, for valid paths, it outputs the timing parameters corresponding to the valid path through a selector; for invalid paths, it outputs 0 to mask the timing parameters corresponding to the invalid path.

[0110] When the timing control module TC calculates the action timing using an adder and a timer CNT, the timing value serves as the trigger for the action. When the timing value equals the data push timing calculated by the adder, the historical test data of the corresponding path in the historical test data group is updated based on the second test data of the path corresponding to the data push timing, resulting in a third test data group which is then latched in preparation for sending the latched third test data group of all paths to the timing generation module TG. When the timing value equals the total accumulated period value, the local timer CNT is reset, and the timer restarts timing. The total accumulated period value is the sum of the periods of the valid paths, and the timing unit of the timer CNT can be nanoseconds (ns).

[0111] The data push time for each valid path includes the data push leading edge time and the data push trailing edge time; the data sampling time includes the data sampling leading edge time and the data sampling trailing edge time. When calculating the action time, the timing control module (TC) acquires the periodic signal and edge signal corresponding to each valid path; the periodic signal carries periodic information, and the edge signal carries leading edge time or trailing edge time information. For each valid path, the periods of the paths preceding the current valid path are added together to obtain a first cumulative time; the first cumulative time is added to the current path's own edge time to obtain a second cumulative time; the second cumulative time is used as the data push time or data sampling time of the current valid path.

[0112] The first cumulative time is 0 for the first valid path and the cumulative period value of the previous (N-1) valid paths for the Nth valid path. The period signal is a signal used to represent the duration of a complete test operation assigned to each path.

[0113] For example, suppose the effective path is 2WAY, namely WAY1 and WAY2, and the timing parameters of 2WAY are as follows:

[0114] WAY1 period T1=30ns, WAY1 data transmission leading edge time B11=10ns, WAY1 data transmission trailing edge time C11=15ns, WAY1 data sampling leading edge time B12=20ns, WAY1 data sampling trailing edge time C12=25ns.

[0115] WAY2 period T2=40ns, WAY2 data transmission leading edge time B21=15ns, WAY2 data transmission trailing edge time C21=20ns, WAY2 data sampling leading edge time B22=25ns, WAY2 data sampling trailing edge time C22=30ns.

[0116] For WAY1, its first cumulative time = 0; for WAY2, its first cumulative time = T1 = 30ns.

[0117] Based on the above timing parameters, the timing of event WAY1 is as follows:

[0118] The leading moment of data push = 0 (starting point) + B11 = 10ns;

[0119] Data push trailing edge time = 0 (starting point) + C11 = 15ns;

[0120] Data sampling leading edge time = 0 + B12 = 20 ns;

[0121] Data sampling trailing edge time = 0 + C12 = 25ns;

[0122] The starting point of the next cycle = 0 + T1 = 30ns.

[0123] Based on the above timing parameters, the timing of the WAY2 event is as follows:

[0124] The data push lead time = T1 + B21 = 45ns;

[0125] Data push trailing edge time = T1 + C21 = 50ns;

[0126] Data sampling leading edge time = T1 + B22 = 55ns;

[0127] Data sampling trailing edge time = T1 + C22 = 60 ns;

[0128] The starting point of the next cycle = 0 + T1 + T2 = 70 ns.

[0129] The total accumulated value of the cycle is T1 + T2 = 70ns. When the count value of the counter equals the total accumulated value of the cycle, the counter is reset and the counter starts counting again.

[0130] In this embodiment, the data push time and the data sampling time each have corresponding leading edge time and trailing edge time, which helps to improve testing efficiency.

[0131] It is important to note that the data transmission leading edge time / trailing edge time in this embodiment is not the same as the data push leading edge time / trailing edge time. The data transmission leading edge time / trailing edge time refers to the time set by the timing parameters, while the data push leading edge time / trailing edge time refers to the action time calculated by the timing control module TC. The relationship between the data sampling leading edge time / trailing edge time and the data sampling leading edge time / trailing edge time is similar.

[0132] In step S104, the timing generation module TG receives the third test data group and sends the third test data group to the device under test (DUT) to perform data-driven operations, or extracts the response data of the DUT at the data sampling time to perform data sampling operations.

[0133] In this step, the timing control module (TC) compares the current timing value with the calculated data push time. When the current timing value matches any data push time, it triggers itself to update the historical test data set to prepare for push. Alternatively, the timing control module (TC) compares the current timing value with the calculated data sampling time. When the current timing value matches any data sampling time, it triggers the timing generation module (TG) to perform data sampling. The timing generation module (TG), as the physical layer interface, implements the final transmission and acquisition of data.

[0134] In one implementation, the timing generation module TG periodically receives the third test data group pushed by the timing control module TC, XORs the third test data of each path in the third test data group to obtain a fourth test data, and then outputs the fourth test data to the device under test.

[0135] In one implementation, the timing generation module TG periodically receives the third test data group pushed by the timing control module TC. The timing generation module XORs the third test data of each path in the third test data group to obtain a fourth test data, and then outputs the fourth test data to the device under test after a delay.

[0136] In one implementation, after the timing generation module extracts the response data, it sends the response data as sampled data to the next-level module for processing.

[0137] In one implementation, after the timing generation module extracts the response data, it uses the response data as sample data and sends it to the next-level module for processing after a delay.

[0138] In steps S101 to S104 above, the digital board 30 provides a complete first test data set across all paths through the algorithmic graphics generation module ALPG. The waveform synthesis module FC then masks invalid paths according to the configured path mode. The timing control module TC calculates and schedules the data push and sampling times based on the independent timing parameters of each valid path. Finally, the timing generation module TG executes the physical layer signal output and acquisition. This achieves on-demand dynamic allocation and reuse of data paths and timing resources, enabling the digital board 30 to directly adapt to various test programs ranging from single-path to maximum number of paths simply by switching path modes via software instructions. This solution eliminates the need to change hardware connections or redesign the underlying logic, thereby improving the path mode compatibility of the DUT test.

[0139] In one embodiment, Figure 6 A schematic diagram of the internal structure of the timing control module (TC) is provided, such as... Figure 6As shown, the timing control module TC includes: multiple first selectors MUX1, multiple second selectors MUX2, a first adder DSP1, a first storage unit R1, and a second adder DSP2. Each first selector MUX1 corresponds to one of the channels, and each second selector MUX2 corresponds to one of the channels. Each first selector MUX1 is connected to the first adder DSP1, and each second selector MUX2 is connected to the second adder DSP2. The first storage unit R1 is connected to both the first adder DSP1 and the second adder DSP2. Timing parameters include leading edge time, trailing edge time, and period. The first storage unit R1 can be a FIFO (First-In-First-Out) memory, RAM (Random Access Memory), or other similar memory. T1 is the first periodic signal, T2 is the second periodic signal, T3 is the third periodic signal, and so on, with en being the first enable signal.

[0140] The first selector MUX1 is used to selectively input periodic or non-periodic signals and outputs the selected target periodic signal to the first adder DSP1; the periodic signal carries periodic information. The second selector MUX2 is used to selectively input edge or non-edge signals and outputs the selected target edge signal to the second adder DSP2; the edge signal carries information about the leading edge time or trailing edge time. Specifically, for valid paths, the periodic signal of the valid path is input through the corresponding first selector MUX1, and the edge signal is input through the corresponding second selector MUX2; for invalid paths, the non-periodic signal is input through the corresponding first selector MUX1, and the non-edge signal is input through the corresponding second selector MUX2, thus masking the timing settings of invalid paths.

[0141] The first adder DSP1 is used to accumulate the received target periodic signal and generate a first accumulated time; the first storage unit R1 is used to buffer the first accumulated time output by the first adder DSP1 and output the first accumulated time to the second adder DSP2; the second adder DSP2 is used to add the first accumulated time to the edge time carried by the edge signal of the current effective path to obtain the second accumulated time, which includes the data push time or the data sampling time.

[0142] Continue to refer to Figure 6 The timing control module TC also includes: a timer CNT, a first comparator C1, a second comparator C2, and a flip-flop D. The timer CNT is connected to the first comparator C1 and the second comparator C2. The first comparator C1 is also connected to the first memory unit R1. The second comparator C2 is connected to the second adder DSP2 and the flip-flop D. The flip-flop D is also connected to the timing generation module TG. The flip-flop D can be a D flip-flop.

[0143] Trigger D is used to latch the third test data group and periodically push the third test data group to the timing generation module TG; timer CNT is used for timing and sends the current timing value to the first comparator C1 and the second comparator C2; the first comparator C1 is used to compare the current timing value with the total cumulative value of all valid paths, and reset timer CNT when the current timing value is equal to the total cumulative value of all valid paths.

[0144] The second comparator C2 is used to compare the current timing value with the calculated data push time or data sampling time:

[0145] When the current time value equals any data push time, the first enable signal is output to flip-flop D, causing flip-flop D to update and obtain the third test data set. The third test data set is not pushed out immediately after generation; instead, it is latched and pushed out only when the time arrives.

[0146] Alternatively, when the current timing value equals any data sampling moment, the timing generation module (TG) is triggered to perform a data sampling operation. The sampled data collected by the timing generation module (TG) is transmitted back through other channels, which are different from the channels used in the data-driven operation.

[0147] In this embodiment, trigger D periodically pushes the latched third test data group to the timing generation module TG. During this process: on the one hand, trigger D retains historical test data groups. On the other hand, when trigger D receives the first enable signal, i.e., when a certain data push time arrives, trigger D updates the retained historical test data group, updating only the bits of the test data in the corresponding valid path, while keeping other bits unchanged. When the next polling cycle (e.g., 5ns) arrives, the current test data group is pushed to the timing generation module TG.

[0148] For ease of understanding, the algorithmic graph generation module ALPG executes the test vector data line by line based on the received test vector data (which can be multiple lines) and the path pattern. For example:

[0149] The first line contains the test vector data Pattern1, and the valid pathways are WAY1~WAY2.

[0150] The second row contains the test vector data Pattern2, and the valid pathways are WAY1~WAY2.

[0151] The algorithmic graph generation module ALPG runs the first row of test vector data and then runs the second row of test vector data. Now, assuming it's time to run the second row of test vector data, an example is given below:

[0152] The algorithm graph generation module ALPG generates the first test data group with 8 channels based on the second row of test vector data Pattern2, and sends it to the waveform synthesis module FC.

[0153] The waveform synthesis module FC determines that channels 1 and 2 are valid, while channels 3-8 are invalid, based on the channel mode. It maps the first test data of channels 1 and 2 to obtain encoded data, and maps the first test data of channels 3-8 to the encoded data of channel 2 to mask the invalid channels 3-8, thus obtaining the second test data set for all channels. The waveform synthesis module FC then sends the second test data set and the timing parameters of all channels to the timing control module TC.

[0154] Before acquiring the periodic and edge signals corresponding to each valid path, the timing control module TC, based on the received path pattern, masks the timing parameters of invalid paths and calculates the data push time based on the timing parameters of the valid paths. This data push time is used to notify the trigger D to update the bits of the historical test data of the corresponding valid path in the latch, obtaining the third test data group to prepare for data push. When the polling cycle time arrives, the third test data group is then pushed to the timing generation module TG.

[0155] At each data push moment, based on the second test data set, the historical test data set latched at the previous data push moment is partially updated to obtain the third test data set, which includes:

[0156] For invalid paths, before each data push time arrives, based on the second test data of the invalid paths in the second test data group, the historical test data of the corresponding paths in the historical test data group is updated. For valid paths, based on the second test data of the path corresponding to the data push time, the historical test data of the corresponding paths in the historical test data group is updated, resulting in the third test data group, which is then latched.

[0157] The second test data set includes the second leading edge test data and the second trailing edge test data. The data push time includes the data push leading edge time and the data push trailing edge time. The data sampling time includes the data sampling leading edge time and the data sampling trailing edge time.

[0158] When the current timing value is equal to any data push front moment, based on the second front moment test data of the path corresponding to the data push front moment, update the front historical test data of the corresponding path in the historical test data group to obtain the third test data group and latch it.

[0159] When the current timing value is equal to the trailing edge of any data push, based on the second trailing edge test data of the path corresponding to the trailing edge of the data push, update the historical trailing edge test data of the corresponding path in the historical test data group to obtain the third test data group and latch it.

[0160] Specifically, assuming Pattern1 has just finished running, for Pattern2, before the data push leading edge moment of path 1 arrives, the historical test data of invalid paths 3-8 in the third test data group of Pattern1 are all updated to the second test data of the corresponding paths 3-8 in Pattern2. That is, the invalid paths are updated together at time 0. When the data push leading edge moment of path 1 arrives, trigger D will update the leading edge test data of path 1, while the test data of other paths remain unchanged, resulting in the current third test data group. When the timer value equals the polling cycle time, trigger D will push the updated test data and the remaining historical test data (i.e., the current third test data group) to the timing generation module TG. Then, when the data push trailing edge moment of path 1 arrives, the current third test data group becomes a latched historical test data group. Trigger D will update the trailing edge test data of path 1 in this historical test data group, while the test data of other paths remain unchanged, resulting in a new third test data group. When the timer value equals the polling cycle time, trigger D will push the new third test data group to the timing generation module TG. And so on.

[0161] It should be noted that the data push time is used to remind trigger D to update and generate the third test data set in preparation for push; while the polling cycle time is used to remind trigger D to push the third test data set.

[0162] In this embodiment, the timing parameters include the leading edge time, trailing edge time, and period. The timing control module TC receives the timing parameters sent by the waveform synthesis module FC and controls the timing input of each channel through the first selector MUX1 and the second selector MUX2. For example, in 4-channel mode, the first 4 channels select the periodic signal and the edge signal, and the rest input zero signal, thereby masking the timing of the unused channels.

[0163] The first adder DSP1 accumulates the cycles of each channel and stores them in the first storage unit R1. The first storage unit R1 is used to cache the first accumulation time (the accumulated value of the first N-1 channel cycles) and the total cycle accumulation value (i.e. the value obtained by accumulating the cycles of all valid channels).

[0164] On one hand, the first storage unit R1 sends the first accumulated time to the second adder DSP2. The second adder DSP2 adds the first accumulated time to the edge signal of the path to obtain the second accumulated time. The second comparator C2 compares the second accumulated time with the timing value of the current timer CNT. If the timing value reaches the second accumulated time, it sends an enable signal to the flip-flop D, causing the flip-flop D to partially update the latched historical test data group to obtain the third test data group, in preparation for data push. When the polling cycle time arrives, the third test data group is then pushed to the timing generation module TG.

[0165] On the other hand, the first storage unit R1 sends the total cycle accumulated value to the first comparator C1. The first comparator C1 compares the total cycle accumulated value with the timing value of the current timer CNT. If the timing value reaches the total cycle accumulated value, the timer CNT is reset.

[0166] In this embodiment, the cumulative value of the previous (N-1) path cycles is added to the leading / falling edge time of the current path to obtain the action time of the current path. Trigger D is used for data latching and periodic pushing, updating the test data only when the time value matches, and rolling out the second test data received from the waveform synthesis module FC when the next polling cycle arrives.

[0167] In one embodiment, Figure 7 A schematic diagram of the internal structure of the timing generation module TG is provided, such as Figure 7 As shown, the timing generation module TG includes: an XOR unit, a first delay unit ODELAY, a second delay unit IDELAY, and a third selector MUX3. The XOR unit is connected to the timing control module TC and the first delay unit ODELAY, and the third selector MUX3 is connected to the timing control module TC and the second delay unit IDELAY.

[0168] The XOR unit is used to XOR the third test data of each path in the third test data group to obtain one fourth test data. The first delay unit ODELAY is used to delay the fourth test data before outputting it to the device under test (DUT). That is, when the timing generation module TG performs its action, it XORs the third test data of each path in the third test data group and then delays the output to the DUT. The second delay unit IDELAY is used to delay the response data before outputting it to the third selector MUX3 to obtain the sampled data. That is, after the timing generation module TG extracts the response data, it uses the response data as sampled data, delays it, and then sends it to the next-level module for processing. The third selector MUX3 is used to extract the sampled data of the currently valid path according to the data sampling time output by the timing control module TC.

[0169] In this embodiment, in the transmission direction, the timing generation module TG uses XOR logic to combine multiple data streams into a single output. Specifically, the timing generation module TG uses combinational logic circuits to perform a logical XOR combination on the third test data group containing multiple parallel paths, generating a single fourth test data stream. This is then adjusted with a delay to ensure the signal is accurately output at the specified time. Furthermore, by combining multiple data streams into a single output, a higher test rate is achieved without increasing the system's operating clock frequency, reducing design complexity and hardware costs.

[0170] In one embodiment, Figure 8 Another internal structure diagram of the digital board 30 is provided, such as Figure 8 As shown, the digital board 30 also includes: a comparison module C0 and a fourth selector MUX4 corresponding to each channel. The comparison module C0 is connected to the timing generation module TG, the fourth selector MUX4, and the waveform synthesis module FC. Specifically, the timing generation module TG outputs sampled data to the comparison module C0; the fourth selector MUX4 outputs a second enable signal or a disable signal to the comparison module C0; the waveform synthesis module FC outputs desired data to the comparison module C0; and the comparison module C0, upon receiving the second enable signal, compares the sampled data and the desired data to obtain comparison data.

[0171] In this embodiment, the timing generation module TG sends the response data as sampled data to each comparison module C0; the in enable signal output by the fourth selector MUX4 shields the comparison module C0 corresponding to the invalid path, so that the comparison module C0 corresponding to the valid path compares the sampled data and the expected data to obtain the comparison data.

[0172] Continue to refer to Figure 8 The digital board 30 also includes an enable module CPE, whose two ends are connected to the algorithm graphics generation module ALPG and the fourth selector MUX4, respectively. The enable module CPE is used to receive the third enable signal representing the path mode issued by the algorithm graphics generation module ALPG, and send the third enable signal to the fourth selector MUX4 to select the path of the fourth selector MUX4. The fourth selector MUX4 compares the received actual path mode with the path mode represented by the third enable signal. If the two are inconsistent, the current path is adjusted based on the received actual path mode.

[0173] In this embodiment, after the host computer 10 parses the Pattern file, the Algorithm Graphics Generation Module (ALPG) sends a third enable signal representing the path mode to the Enable Module CPE. During the data acquisition phase, when the fourth selector MUX4 directly receives the actual path mode, it compares the path mode represented by the third enable signal transmitted from the Enable Module CPE with the directly received actual path mode. If they are inconsistent, the current path is adjusted based on the received actual path mode. For example, if the path mode represented by the third enable signal is 3WAY and the actual path mode is 2WAY, then the third path of the fourth selector MUX4 will be forcibly shut down. The path mode represented by the third enable signal transmitted from the Enable Module CPE indicates that the corresponding valid path enable signal is 1, and the valid path can compare the sampled data with the expected data.

[0174] In one implementation, an enable module CPE, a fourth selector MUX4, and a comparison module C0 can be used. The enable module CPE, the fourth selector MUX4, and the comparison module C0 are connected in sequence to form a single data acquisition path. The sampled NWAY data is compared with the sampled data of the effective path and the expected data. In this single data acquisition path, the sampled data at the leading edge moment or the sampled data at the trailing edge moment are transmitted in sequence according to the data sampling time.

[0175] As another implementation, multiple enable modules CPE, multiple fourth selectors MUX4, and multiple comparison modules C0 can be used according to the number of leading / following edge data to be sampled. These enable modules CPE, fourth selectors MUX4, and comparison modules C0 are connected one-to-one to form multiple data acquisition paths. Each edge sampling data corresponds to one data acquisition path, and the edge sampling data is transmitted separately. Then, the sampling data of the effective path is compared with the expected data.

[0176] In this embodiment, the digital board 30 further includes a second storage unit R2 and a third storage unit R3. The second storage unit R2 is connected to the timing generation module TG and the comparison module C0; the third storage unit R3 is connected to the waveform synthesis module FC and the comparison module C0. The enable module CPE, under the control of the algorithm graphics generation module ALPG, outputs a third enable signal to the fourth selector MUX4; the second storage unit R2 is used to buffer the sampled data output by the timing generation module TG; and the third storage unit R3 is used to buffer the expected data output by the waveform synthesis module FC. Both the second storage unit R2 and the third storage unit R3 can be FIFO (First-In-First-Out) or RAM (Random Access Memory) type of memory.

[0177] In this embodiment, by introducing an enable module CPE, a third enable signal representing the path mode is received. The fourth selector MUX4 compares the path mode represented by the third enable signal with the actual path mode. If they are inconsistent, the current path is automatically adjusted to ensure that the test configuration matches the actual path mode and to prevent false tests caused by mode errors.

[0178] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0179] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0180] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0181] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A DUT testing method, characterized in that, Applied to a digital board, the digital board includes: an algorithm graphics generation module, a waveform synthesis module, a timing control module, and a timing generation module; the method includes: The algorithm graphics generation module generates a first test data set for the entire path based on the test vector data, and sends the first test data set to the waveform synthesis module; The waveform synthesis module determines the valid and invalid paths according to the currently issued path mode, encodes the first test data of the valid path, and masks the first test data of the invalid path to obtain the second test data group of the entire path, and sends the second test data group to the timing control module. The timing control module calculates the data push time or data sampling time for each valid path based on timing parameters. For invalid paths, before the arrival of each data push time, it updates the historical test data of the corresponding path in the historical test data group based on the second test data of the invalid path in the second test data group. For valid paths, it updates the historical test data of the corresponding path in the historical test data group based on the second test data of the path corresponding to the data push time, thereby obtaining a third test data group and latching it. The timing generation module receives the third test data set and sends the third test data set to the device under test to perform a data-driven operation, or extracts the response data of the device under test at the data sampling time to perform a data sampling operation.

2. The DUT testing method according to claim 1, characterized in that, The waveform synthesis module determines the valid and invalid paths based on the currently issued path mode, encodes the first test data of the valid path, and masks the first test data of the invalid path to obtain a second test data set for the entire path, including: The waveform synthesis module determines N valid paths from the full path based on the number N of paths in the path mode, and treats the remaining paths as invalid paths. In the first test data set, the first test data of each valid path is mapped to encoded data, and the first test data of each invalid path is mapped to the encoded data of the previous valid path closest to the current invalid path.

3. The DUT testing method according to claim 2, characterized in that, The first test data set includes first test data for all pathways, and the first test data for each pathway includes first leading edge test data and first trailing edge test data; in the first test data set, the first test data of each valid pathway is mapped to encoded data, and the first test data of each invalid pathway is mapped to encoded data of the previous valid pathway closest to the current invalid pathway, including: The first leading edge test data and the first trailing edge test data of the effective path are mapped to obtain the first leading edge coding data and the first trailing edge coding data corresponding to the effective path; The first leading edge test data and the first trailing edge test data of the invalid path are both mapped to the first trailing edge encoded data of the previous valid path that is closest to the current invalid path.

4. The DUT testing method according to claim 1, characterized in that, The timing parameters include: leading edge time, trailing edge time, and period; the timing control module calculates the data push time or data sampling time for each effective path based on the timing parameters, including: Acquire the periodic signal and the edge signal corresponding to each of the effective paths; wherein the periodic signal carries information about the period, and the edge signal carries information about the leading edge time or the trailing edge time; For each of the aforementioned valid paths, the periods of the paths preceding the current valid path are added together to obtain the first cumulative time; The first cumulative time is added to the current path's own along-time to obtain the second cumulative time; The second cumulative time is used as the data push time or the data sampling time of the currently effective channel.

5. The DUT testing method according to claim 4, characterized in that, After using the second cumulative time as the data push time or the data sampling time of the currently effective path, the method further includes: Compare the current timing value with the calculated data push time or data sampling time; When the current timing value is equal to any of the data push times, the timing control module is triggered to perform an update operation on the historical test data group; When the current timing value is equal to any of the data sampling times, the timing generation module is triggered to perform the data sampling operation.

6. The DUT testing method according to claim 4, characterized in that, Before acquiring the periodic signal and edge signal corresponding to each of the effective paths, the method further includes: The timing control module masks the timing parameters of invalid paths based on the received path mode.

7. The DUT testing method according to claim 1, characterized in that, The second test data set includes second leading edge test data and second trailing edge test data. The data push time includes the data push leading edge time and the data push trailing edge time. The data sampling time includes the data sampling leading edge time and the data sampling trailing edge time. When the current timing value is equal to any of the aforementioned data push leading edge moments, based on the second leading edge test data of the path corresponding to the aforementioned data push leading edge moment, update the historical leading edge test data of the corresponding path in the historical test data group to obtain the third test data group and latch it. When the current timing value is equal to any of the data push trailing edge times, based on the second trailing edge test data of the path corresponding to the data push trailing edge time, update the historical trailing edge test data of the corresponding path in the historical test data group to obtain the third test data group and latch it.

8. The DUT testing method according to claim 1, characterized in that, The timing generation module receives the third test data set and sends the third test data set to the device under test (DUT) to perform a data-driven operation, or extracts the response data of the DUT at the data sampling time to perform a data sampling operation, including: The timing generation module XORs the third test data of each path in the third test data group to obtain a fourth test data, and then outputs the fourth test data to the device under test; or, the timing generation module XORs the third test data of each path in the third test data group to obtain a fourth test data, and then outputs the fourth test data to the device under test after a delay. After the timing generation module extracts the response data, it sends the response data as sample data to the next-level module for processing; or, after the timing generation module extracts the response data, it sends the response data as sample data after a delay to the next-level module for processing.

9. The DUT testing method according to claim 1 or claim 8, characterized in that, The digital board further includes a comparison module corresponding one-to-one with each of the aforementioned paths; the timing generation module receives the third test data set and sends the third test data set to the device under test to perform a data-driven operation, or, after extracting the response data of the device under test at the data sampling time to perform a data sampling operation, the method further includes: The timing generation module sends the response data as sampled data to each of the comparison modules; The comparison module corresponding to the invalid path is masked, so that the comparison module corresponding to the valid path compares the sampled data and the expected data to obtain comparison data.

10. A digital board, characterized in that, include: The algorithm graphics generation module, waveform synthesis module, timing control module, and timing generation module are connected in sequence; among them, The algorithm graph generation module is used to generate a first test data set for the entire path based on the test vector data, and send the first test data set to the waveform synthesis module; The waveform synthesis module is used to determine the effective and invalid paths according to the currently issued path mode, encode the first test data of the effective path, mask the first test data of the invalid path, obtain the second test data group of the entire path, and send the second test data group to the timing control module. The timing control module is used to calculate the data push time or data sampling time of each effective path according to timing parameters. For invalid paths, before the arrival of each data push time, it updates the historical test data of the corresponding path in the historical test data group based on the second test data of the invalid path in the second test data group. For effective paths, it updates the historical test data of the corresponding path in the historical test data group based on the second test data of the path corresponding to the data push time, and obtains and latches the third test data group. The timing generation module is used to receive the third test data group, send the third test data group to the device under test to perform data-driven operations, or extract the response data of the device under test at the data sampling time to perform data sampling operations.

11. The digital board according to claim 10, characterized in that, The timing control module includes: multiple first selectors, multiple second selectors, a first adder, a first storage unit, and a second adder. Each first selector corresponds one-to-one with each of the aforementioned paths, and each second selector corresponds one-to-one with each of the aforementioned paths. Each first selector is connected to the first adder, and each second selector is connected to the second adder. The first storage unit is connected to both the first adder and the second adder. The timing parameters include leading edge time, trailing edge time, and period. The first selector is used to selectively input a periodic signal or an aperiodic signal, and outputs the selected target periodic signal to the first adder; the periodic signal carries information about the period. The second selector is used to selectively input an edge signal or a non-edge signal, and outputs the selected target edge signal to the second adder; the edge signal carries information about the leading edge time or the trailing edge time; The first adder is used to accumulate the received target periodic signal and generate a first accumulation time; The first storage unit is used to cache the first accumulated time output by the first adder and output the first accumulated time to the second adder; The second adder is used to add the first cumulative time to the edge time carried by the edge signal of the current valid path to obtain the second cumulative time, which includes the data push time or the data sampling time.

12. The digital board according to claim 11, characterized in that, The timing control module further includes: a timer, a first comparator, a second comparator, and a flip-flop. The timer is connected to the first comparator and the second comparator. The first comparator is also connected to the first memory unit. The second comparator is connected to the second adder and the flip-flop. The flip-flop is also connected to the timing generation module. The trigger is used to latch the third test data group and periodically push the third test data group to the timing generation module; The timer is used to keep time and sends the current time value to the first comparator and the second comparator; The first comparator is used to compare the current timing value with the total cumulative value of all valid channels, and reset the timer when the current timing value is equal to the total cumulative value of all valid channels. The second comparator is used to compare the current timing value with the calculated data push time or the data sampling time: When the current timing value is equal to any of the data push times, a first enable signal is output to the trigger, causing the trigger to update to obtain the third test data set; Alternatively, when the current timing value is equal to any of the data sampling times, the timing generation module is triggered to perform the data sampling operation.

13. The digital board according to claim 10, characterized in that, The timing generation module includes: an XOR unit, a first delay unit, a second delay unit, and a third selector. The XOR unit is connected to the timing control module and the first delay unit, and the third selector is connected to the timing control module and the second delay unit. The XOR unit is used to XOR the third test data of each path in the third test data group to obtain a fourth test data. The first delay unit is used to delay the fourth test data before outputting it to the device under test; The second delay unit is used to delay the response data before outputting it to the third selector to obtain sampled data; The third selector is used to extract the sampling data of the currently effective path according to the data sampling time output by the timing control module.

14. The digital board according to claim 10, characterized in that, The digital board further includes: a comparison module and a fourth selector corresponding one-to-one with each of the aforementioned paths; the comparison module is connected to the timing generation module, the fourth selector, and the waveform synthesis module, respectively; wherein... The timing generation module is used to output sampled data to the comparison module; The fourth selector is used to output a second enable signal or a disable signal to the comparison module; The waveform synthesis module is used to output the desired data to the comparison module; The comparison module is used to compare the sampled data and the expected data when the second enable signal is received, so as to obtain comparison data.

15. The digital board according to claim 14, characterized in that, The digital board further includes an enable module, the two ends of which are respectively connected to the algorithm graphics generation module and the fourth selector; wherein, The enabling module is used to receive a third enabling signal representing the path mode issued by the algorithm graph generation module, and send the third enabling signal to the fourth selector to select the path of the fourth selector. The fourth selector compares the received actual path mode with the path mode represented by the third enable signal. If the two are inconsistent, the current path is adjusted based on the received actual path mode.

16. A testing machine, characterized in that, include: The system comprises a host computer, a slave computer, and a digital board according to any one of claims 10 to 15, wherein the slave computer and the digital board are connected; wherein... The host computer is used to provide test vector data, path mode and timing parameters, and to send the test vector data, path mode and timing parameters to the digital board through the slave computer; The digital board is used to test the device under test based on the test vector data, the path mode, and the timing parameters.

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