Ceramic electronic component

Abstract

A ceramic electronic component is disclosed, comprising: a body including a dielectric layer and an inner electrode, the dielectric layer having a plurality of dielectric grains; and an outer electrode disposed on the body and connected to the inner electrode. The dielectric grains, having a core-shell structure, comprise titanium (Ti), tin (Sn), and dysprosium (Dy), and have a core and a shell surrounding at least a portion of the core. The core contains less than 0.2 mol of tin (Sn) and less than 0.1 mol of dysprosium (Dy) relative to 100 mol of titanium (Ti). The shell comprises a first region and a second region, wherein in the first region, the amount of Sn relative to Ti is greater than the amount of Dy relative to Ti, and in the second region, the amount of Dy relative to Ti is greater than the amount of Sn relative to Ti. The ratio LC / LG of the Freret diameter of the core to the Freret diameter of the dielectric grains having the core-shell structure is from 0.49 to 0.73.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0195092, filed on December 24, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a ceramic electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs), as ceramic electronic components, are chip capacitors mounted on printed circuit boards in various types of electronic products, such as video display devices (such as liquid crystal displays (LCDs) and plasma display panels (PDPs)), computers, smartphones, mobile phones, and on-board chargers (OBCs) and DC-DC converters for electric vehicles, for charging or discharging.

[0004] As the size of various electronic components incorporating multilayer ceramic capacitors decreases and their integration increases, the size of multilayer ceramic capacitors also needs to decrease. Therefore, it is necessary to increase the capacitance per unit volume.

[0005] A representative approach to achieving miniaturization and high capacitance in multilayer ceramic capacitors is to consider forming a thin dielectric layer; however, in this case, it may be difficult to ensure sufficient dielectric constant and reliability in harsh environments.

[0006] In the case of Korean Patent Application No. 10-2022-0088099 (referred to as Patent Document 1), at least one of the dielectric grains in the dielectric layer has a core-double-shell structure, and a method is proposed to simultaneously ensure high dielectric constant and high reliability by including at least one of Sn, Sb, Ge, Si, Ga, In and Zr as a first element in the first shell of the double-shell structure and including at least one of Ca and Sr as a second element in the second shell.

[0007] However, multilayer ceramic capacitors used in general electronic devices require dielectric properties with capacitance variation within ±15% over a temperature range of -55°C to 85°C, while multilayer ceramic capacitors used in information technology (IT) products require dielectric properties with capacitance variation within ±22% over a temperature range of -55°C to 105°C.

[0008] In addition, such small and high-capacitance multilayer ceramic capacitors may have a tendency for their capacitance to decrease with DC bias.

[0009] Therefore, it is necessary to improve the dielectric grain structure to reduce capacitance changes due to temperature variations (temperature coefficient of capacitance (TCC)) and the phenomenon of capacitance changing with DC voltage (DC bias). Summary of the Invention

[0010] One aspect of this disclosure is to provide a ceramic electronic component with improved TCC characteristics.

[0011] One aspect of this disclosure is to provide a ceramic electronic component with improved DC bias characteristics.

[0012] One aspect of this disclosure is to provide a ceramic electronic component with an improved dielectric constant.

[0013] One aspect of this disclosure is to provide a ceramic electronic component with improved high-temperature reliability.

[0014] According to one aspect of this disclosure, a ceramic electronic component includes: a body comprising a dielectric layer and an inner electrode, the dielectric layer comprising a plurality of dielectric grains; and an outer electrode disposed on the body and connected to the inner electrode. The plurality of dielectric grains, including a core and a shell, comprises titanium (Ti), tin (Sn), and dysprosium (Dy), and the shell surrounds at least a portion of the core. The core has a tin (Sn) content of less than 0.2 moles relative to 100 moles of titanium (Ti) and a dysprosium (Dy) content of less than 0.1 moles relative to 100 moles of titanium (Ti). The shell includes a first region and a second region, in the first region, the number of moles of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti), and in the second region, the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) relative to 100 moles of titanium (Ti). When the maximum Ferete diameter of the dielectric grain including the core and the shell is LG, and the maximum Ferete diameter of the core is LC, LC / LG satisfies greater than or equal to 0.49 and less than or equal to 0.73.

[0015] According to one aspect of this disclosure, a ceramic electronic component includes: a dielectric layer comprising dielectric grains having a core and a shell surrounding at least a portion of the core, the dielectric grains comprising titanium, tin, and dysprosium, wherein, relative to 100 moles of titanium: the tin content in the core is less than 0.2 moles, and the dysprosium content is less than 0.1 moles; in a first region of the shell relatively closer to the core, the tin content is greater than the dysprosium content; and in a second region of the shell relatively further away from the core, the tin content is less than the dysprosium content; and an inner electrode disposed on the dielectric layer and comprising nickel and tin, wherein, at the interface between the inner electrode and the dielectric layer, the peak tin content is 0.55 moles or greater relative to 100 moles of nickel.

[0016] According to one aspect of this disclosure, a ceramic electronic component includes: a dielectric layer comprising vanadium as a fixed-valence element, and comprising dielectric grains having a core and a shell surrounding at least a portion of the core, the dielectric grains comprising titanium, tin, and dysprosium, wherein the ratio of the number of moles of vanadium to the number of moles of rare earth elements in the dielectric layer relative to 100 moles of titanium is in the range of 0.056 to 0.222, the core having a tin content of less than 0.2 moles and a dysprosium content of less than 0.1 moles, a first region of the shell relatively closer to the core having a greater tin content than a dysprosium content, and a second region of the shell relatively farther from the core having a less tin content than a dysprosium content. Attached Figure Description

[0017] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic perspective view of a ceramic electronic component according to an embodiment; Figure 2 It is along Figure 1 A schematic diagram of the cross section intercepted by line I-I'; Figure 3 It is along Figure 1 A schematic diagram of the cross section intercepted by line II-II'; Figure 4 This is a schematic diagram of dielectric grains and grain boundaries according to an embodiment; Figure 5A , Figure 5B and Figure 5C These are images of the core-shell structure of dielectric grains analyzed by transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDX). Figure 6 This is a schematic diagram of the structure of the dielectric grain according to an embodiment; Figure 7 It shows along Figure 6A graph showing the results of line scan analysis of Sn and Dy content measured by line A-A'; Figure 8 yes Figure 3 An enlarged schematic diagram of region P; Figure 9 It shows along Figure 8 A graph showing the results of line scan analysis of Sn and Ni contents measured by line B-B'; and Figure 10 This is an image of the interface between the dielectric layer and the inner electrode, and the mapped Sn element, analyzed by TEM-EDX. Detailed Implementation

[0018] In the following description, embodiments will be illustrated with reference to specific examples and accompanying drawings. However, embodiments may be modified in various other forms, and the scope of this disclosure is not limited to the embodiments described below. Furthermore, embodiments are provided to explain this disclosure more fully to those skilled in the art. Therefore, for clarity, the shapes and dimensions of elements in the drawings may be exaggerated, and elements indicated by the same symbols in the drawings are the same elements.

[0019] Furthermore, to clearly explain this disclosure in the accompanying drawings, parts irrelevant to the explanation have been omitted, and for ease of explanation, the dimensions (e.g., thickness) of each component shown in the drawings have been arbitrarily indicated; therefore, this disclosure is not necessarily limited to the cases shown. Additionally, components having the same function within the scope of the same concept are described using the same reference numerals. Furthermore, throughout the specification, unless specifically stated otherwise, when a part is referred to as "including" a component, this does not mean that other components are excluded, but rather that other components are included.

[0020] In the accompanying drawings, the X direction can be defined as the direction in which the first inner electrode and the second inner electrode are alternately disposed and the dielectric layer is located between the first inner electrode and the second inner electrode, or the first direction. In the Y direction and the Z direction, which are perpendicular to the X direction, the Y direction can be defined as the second direction and the Z direction can be defined as the third direction.

[0021] Figure 1 This is a schematic perspective view of a ceramic electronic component according to an embodiment.

[0022] Figure 2 It is along Figure 1 A schematic diagram of the cross section intercepted by line I-I'.

[0023] Figure 3 It is along Figure 1 A schematic diagram of the cross section taken by line II-II'.

[0024] Figure 4 This is a schematic diagram of dielectric grains and grain boundaries according to an embodiment.

[0025] Figure 5A , Figure 5B and Figure 5C This is an image of the core-shell structure of dielectric grains analyzed by TEM-EDX.

[0026] Figure 6 This is a schematic diagram of the structure of the dielectric grain according to an embodiment.

[0027] Figure 7 It shows along Figure 6 The curves showing the results of line scan analysis of Sn and Dy contents obtained from line A-A'.

[0028] In the following text, refer to Figures 1 to 4 , Figure 5A , Figure 5B , Figure 5C , Figure 6 and Figure 7 The ceramic electronic component 100 according to the embodiments and its various embodiments will be described in detail.

[0029] A ceramic electronic component 100 according to an embodiment includes: a body 110 including a dielectric layer 111 and inner electrodes 121 and 122, the dielectric layer 111 comprising a plurality of dielectric grains; and outer electrodes 130 and 140 disposed on the body 110 and connected to the inner electrodes 121 and 122. One of the plurality of dielectric grains, comprising a core 11 and a shell 12, comprises titanium (Ti), tin (Sn), and dysprosium (Dy), and the shell 12 surrounds at least a portion of the core 11. The core 11 has a tin (Sn) content of less than 0.2 mol per 100 mol of titanium (Ti) and a dysprosium (Dy) content of less than 0.1 mol per 100 mol of titanium (Ti). The shell 12 includes a first region 12a and a second region 12b, in which the molar number of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the molar number of dysprosium (Dy) relative to 100 moles of titanium (Ti), and in the second region 12b, the molar number of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the molar number of tin (Sn) relative to 100 moles of titanium (Ti). When the maximum Ferete diameter of the dielectric grain 10 including the core 11 and the shell 12 is LG and the maximum Ferete diameter of the core 11 is LC, the LC / LG ratio can be in the range of 0.49 to 0.73.

[0030] The body 110 may include a dielectric layer 111 and inner electrodes 121 and 122. The dielectric layer 111 and the inner electrodes 121 and 122 may be alternately disposed within the body 110, and the direction in which the inner electrodes 121 and 122 are alternately disposed with the dielectric layer 111 may be defined as a stacking direction or a first direction.

[0031] There are no particular restrictions on the specific shape of the main body 110, but as Figure 1 As shown, the body 110 can be formed into a hexahedral shape or a similar shape. Furthermore, due to shrinkage during the sintering process or a separate polishing process, the shape of the body 110 may not be a hexahedral shape with perfectly straight edges, but may be generally hexahedral.

[0032] The body 110 may have a first surface 1 and a second surface 2 opposite to each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1 and the second surface 2, connected to the third surface 3 and the fourth surface 4 and opposite to each other in a third direction. The plurality of dielectric layers 111 forming the body 110 are in a sintered state, and adjacent dielectric layers 111 may be integrated to the extent that the boundaries between them are difficult to distinguish without using a scanning electron microscope (SEM).

[0033] like Figure 4 As shown, the dielectric layer 111 may include a plurality of dielectric grains. In addition, grain boundaries 20 may be provided between the plurality of dielectric grains.

[0034] Additionally, the dielectric grain 10, which includes a core 11 and a shell 12, may include a core 11 and a shell 12 surrounding at least a portion of the core 11, and the shell 12 may be divided into a first region 12a and a second region 12b according to the content of tin (Sn) and dysprosium (Dy).

[0035] Reference Figure 5A It can be confirmed that the dielectric layer consists of dielectric grains and grain boundaries, and the tin (Sn) content distribution is shown in the diagram. Figure 5B And showing the content distribution of dysprosium (Dy) Figure 5C It can be confirmed that the shell according to the embodiments of this disclosure includes a region where the content of tin (Sn) is concentrated.

[0036] Reference Figure 6 According to an embodiment, the shell 12 surrounds at least a portion of the core 11, and the shell 12 may include a first region 12a and a second region 12b.

[0037] Reference Figure 7 Core 11 can be a region that simultaneously satisfies the following conditions: the content of tin (Sn) relative to 100 moles of titanium (Ti) is less than 0.2 moles and the content of dysprosium (Dy) relative to 100 moles of titanium (Ti) is less than 0.1 moles.

[0038] See Figure 7, the shell 12 can be the region of the dielectric grains 10 located outside the core 11. The region where the mole number of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the mole number of dysprosium (Dy) relative to 100 moles of titanium (Ti) can be the first region 12a, and the region where the mole number of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the mole number of tin (Sn) relative to 100 moles of titanium (Ti) can be the second region 12b.

[0039] The dielectric grains 10 including the core 11 and the shell 12 in the dielectric layer 111 or the multiple dielectric grains included in the dielectric layer 111 can include titanium (Ti). The titanium (Ti) in the dielectric grains 10 including the core 11 and the shell 12 among the multiple dielectric grains can be a component derived from the titanium (Ti) included in the barium titanate-based material forming the dielectric layer 111.

[0040] There is no particular limitation on the main component of the dielectric composition forming the dielectric layer 111 as long as sufficient electrostatic capacitance can be obtained. For example, barium titanate-based materials, lead composite perovskite-based materials, strontium titanate-based materials, etc. can be used. The barium titanate-based material can include BaTiO3-based ceramic powder. Examples of the BaTiO3-based ceramic powder can include BaTiO3 or (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc.

[0041] In addition to the barium titanate-based main component containing titanium (Ti), the dielectric layer 111 can also include various additives. In the embodiment, in order to achieve the core-shell structure of the dielectric grains 10, the dielectric layer 111 can include tin (Sn) and dysprosium (Dy) in addition to titanium (Ti). Similarly, the dielectric grains 10 including the core 11 and the shell 12 among the multiple dielectric grains can include tin (Sn) and dysprosium (Dy) in addition to titanium (Ti).

[0042] In addition, the average thickness td of the dielectric layer 111 does not need to be particularly limited.

[0043] For example, in order to miniaturize the ceramic electronic component 100 and increase its capacitance, the average thickness td of the dielectric layer 111 can be 0.35 μm or less, and in order to ensure the reliability of the ceramic electronic component 100 under high temperature and high voltage, the average thickness td of the dielectric layer 111 can be 3.0 μm or greater.

[0044] In an embodiment, the average thickness td of dielectric layer 111 may refer to the average thickness of at least one of the plurality of dielectric layers.

[0045] The average thickness td of dielectric layer 111 can be measured by scanning images of cross-sections of the body 110 in the first and second directions using a scanning electron microscope (SEM). For example, the average thickness td of dielectric layer 111 can be obtained by scanning and obtaining images of cross-sections in the length and thickness directions (LT) cut from the center of the width direction of the body 110 using a scanning electron microscope (SEM), and averaging the thickness measured at 1 / 4, 2 / 4, and 3 / 4 points provided by dividing the dielectric layer into four parts along the length direction, based on a dielectric layer adjacent to the point where the length centerline and thickness centerline of the capacitor formation intersect in the obtained images. The average thickness of the dielectric layer can be further generalized by extending this measurement to two upper and two lower dielectric layers with equal spacing between the dielectric layers adjacent to the point where the length centerline and thickness centerline of the capacitor formation intersect.

[0046] The main body 110 may include a capacitor forming portion Ac, which is disposed inside the main body 110, and a capacitor is formed in the capacitor forming portion Ac by a first inner electrode 121 and a second inner electrode 122 that face each other and have a dielectric layer 111 between them.

[0047] Furthermore, the capacitor forming part Ac is a part that contributes to the capacitor forming and can be formed by repeatedly stacking multiple first inner electrodes 121 and second inner electrodes 122 with a dielectric layer 111 between the first inner electrodes 121 and the second inner electrodes 122.

[0048] Reference Figure 2 Cover portions 112 and 113 may be disposed on one surface and another surface of the capacitor forming portion Ac in the first direction. Cover portions 112 and 113 may be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the capacitor forming portion Ac respectively in the thickness direction, and may substantially prevent damage to the internal electrode due to physical stress and / or chemical stress.

[0049] Cover portions 112 and 113 do not include internal electrodes and may include the same material as the dielectric layer 111. For example, cover portions 112 and 113 may include a ceramic material, and may include the same ceramic material as the dielectric layer 111.

[0050] The average thickness tc of the covers 112 and 113 does not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of ceramic electronic components, the average thickness tc of the covers 112 and 113 can be 15 μm or less.

[0051] The average thickness tc of the covers 112 and 113 may refer to the dimensions of the covers 112 and 113 in the first direction, and may be the average of the dimensions of the covers 112 and 113 in the first direction measured at five equally spaced points above or below the capacitor forming portion Ac.

[0052] Reference Figure 3 Edge portions 114 and 115 may be disposed on one surface and another surface of the capacitor forming portion Ac in a third-direction orientation.

[0053] Edge portions 114 and 115 include an edge portion 114 disposed on one surface of the capacitor forming portion Ac (corresponding to the fifth surface 5 of the body 110) and an edge portion 115 disposed on the other surface of the capacitor forming portion Ac (corresponding to the sixth surface 6 of the body 110). For example, edge portions 114 and 115 may be disposed on two side surfaces of the ceramic body 110 in the width direction.

[0054] like Figure 3 As shown, the edges 114 and 115 may refer to the region between the two ends of the first inner electrode 121 and the second inner electrode 122 and the outer surface of the body 110 in a cross section cut along the width-thickness direction (WT) of the body 110.

[0055] The edges 114 and 115 can essentially prevent damage to the internal electrodes due to physical and / or chemical stress.

[0056] Edges 114 and 115 can be formed by coating conductive paste onto the area of ​​the ceramic green sheet other than the area where the edge will be formed to form an internal electrode.

[0057] In some embodiments, in order to suppress the step difference caused by the inner electrodes 121 and 122, the laminate can be cut after stacking so that the inner electrodes are exposed to the two side surfaces of the capacitor forming portion Ac in the width direction (corresponding to the fifth surface 5 and the sixth surface 6 of the body). Then, a single dielectric layer or two or more dielectric layers can be stacked on the two side surfaces of the capacitor forming portion Ac in the width direction to form the edge portions 114 and 115.

[0058] Furthermore, the widths of the edges 114 and 115 do not need to be particularly limited. However, in order to more easily achieve miniaturization and high capacitance of ceramic electronic components, the average width of the edges 114 and 115 can be 15 μm or less.

[0059] The average width of the edges 114 and 115 can refer to the average size of the edges 114 and 115 in the third direction, and can be the average size of the dimensions of the edges 114 and 115 in the third direction measured at five equally spaced points on the side surface of the capacitor forming part Ac.

[0060] Internal electrodes 121 and 122 may be included in the body 110 together with dielectric layer 111.

[0061] The inner electrodes 121 and 122 may include a first inner electrode 121 and a second inner electrode 122, and the first inner electrode 121 and the second inner electrode 122 may be alternately arranged facing each other with a dielectric layer 111 between the first inner electrode 121 and the second inner electrode 122, and the first inner electrode 121 and the second inner electrode 122 may be exposed on the third surface 3 and the fourth surface 4 of the body 110, respectively.

[0062] Reference Figure 1 and Figure 2 The first inner electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second inner electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4.

[0063] At this time, the first inner electrode 121 and the second inner electrode 122 can be electrically separated from each other by the dielectric layer 111 disposed between them.

[0064] There are no particular limitations on the materials used to form the internal electrodes 121 and 122, and materials with excellent electrical conductivity can be used. For example, the internal electrodes 121 and 122 may include at least one of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0065] In addition, there is no need to specifically limit the average thickness te of the inner electrodes 121 and 122.

[0066] For example, in order to miniaturize the ceramic electronic component 100 and increase its capacitance, the average thickness te of the inner electrodes 121 and 122 can be 0.35 μm or less, and in order to ensure the reliability of the ceramic electronic component 100 under high temperature and high voltage, the average thickness te of the inner electrodes 121 and 122 can be 3.0 μm or greater.

[0067] The average thickness te of the inner electrodes 121 and 122 may refer to the average thickness of at least one of the multiple inner electrodes 121 and 122.

[0068] The average thickness te of the inner electrodes 121 and 122 can be measured by scanning images of cross-sections of the body 110 in the first and second directions using a scanning electron microscope (SEM). For example, the average thickness te of the inner electrodes 121 and 122 can be obtained by averaging the thickness measured at the 1 / 4, 2 / 4, and 3 / 4 points when the inner electrodes are divided into four parts along the length direction, based on a layer of inner electrodes adjacent to the point where the length centerline and thickness centerline of the capacitor forming portion intersect. Extending this measurement to two upper and two lower layers of inner electrodes with equal spacing, based on a layer of inner electrodes adjacent to the point where the length centerline and thickness centerline of the capacitor forming portion intersect, can further generalize the average thickness of the inner electrodes.

[0069] Reference Figure 1 External electrodes 130 and 140 can be disposed on the main body 110.

[0070] Reference Figure 1 and Figure 2 The external electrodes 130 and 140 may include a first external electrode 130 that contacts the third surface 3 of the body 110 and a second external electrode 140 that contacts the fourth surface 4.

[0071] In this embodiment, a structure is described in which the ceramic electronic component 100 has two external electrodes 130 and 140, but the number or shape of the external electrodes 130 and 140 may be changed depending on the shape of the internal electrodes 121 and 122 or for other purposes.

[0072] In addition, the external electrodes 130 and 140 can be formed using any conductive material (such as metal), and the specific material can be determined by taking into account electrical properties, structural stability, etc. Furthermore, the external electrodes 130 and 140 can have a multilayer structure.

[0073] For example, the external electrodes 130 and 140 may include electrode layers 131 and 141 disposed on the body 110 and plating layers 132, 133, 142 and 143 formed on the electrode layers 131 and 141.

[0074] For a more specific example of electrode layers 131 and 141, the electrode layers may be sintered electrodes comprising conductive metal and glass, or resin-based electrodes comprising conductive metal and resin.

[0075] Furthermore, electrode layers 131 and 141 can be formed in the form of a sintered electrode and a resin-based electrode sequentially formed on the body. Alternatively, the electrode layers can be formed by transferring a sheet containing conductive metal onto the body, or by transferring a sheet containing conductive metal onto the sintered electrode.

[0076] Materials with excellent conductivity can be used as conductive metals included in electrode layers 131 and 141, and there are no particular limitations. For example, the conductive metal can be at least one of nickel (Ni), copper (Cu), and alloys thereof, and preferably, it can be copper (Cu) to improve adhesion to the substrate.

[0077] The plating layers 132, 133, 142, and 143 serve to improve mounting characteristics. There are no particular limitations on the type of plating layers 132, 133, 142, and 143, and they can be plating layers including at least one of Ni, Sn, Pd, and their alloys, and can be formed from multiple layers.

[0078] For more specific examples of plating layers 132, 133, 142, and 143, the plating layer may be a Ni plating layer or a Sn plating layer, or it may be formed in a manner in which a Ni plating layer and a Sn plating layer are sequentially formed on the electrode layer, or it may be formed in a manner in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are sequentially formed. Additionally, the plating layer may include multiple Ni plating layers and / or multiple Sn plating layers.

[0079] The core-shell structure of dielectric grains can be divided into a core that ensures the dielectric constant and a shell that ensures insulation performance. Therefore, by properly controlling the structure of the core and shell, the capacitance and reliability of ceramic electronic components can be ensured simultaneously.

[0080] In detail, in the case of Patent Document 1, a method is proposed to simultaneously ensure high dielectric constant and high reliability by ensuring that at least one of the dielectric grains has a core-double shell structure. However, it may be difficult to ensure the TCC characteristics and DC bias characteristics of ceramic electronic components by using only the structure proposed in Patent Document 1.

[0081] On the other hand, when ceramic electronic components need to be miniaturized and have high capacitance or operate at high temperatures and high voltages, it may be important not only to ensure dielectric constant and reliability but also to ensure TCC and DC bias characteristics. Therefore, in this disclosure, a dielectric grain 10 comprising a core 11 and a shell 12 of a plurality of dielectric grains includes a core 11 and a shell 12 surrounding at least a portion of the core 11. The shell 12 includes a first region 12a and a second region 12b, in which the content of tin (Sn) is greater than the content of dysprosium (Dy), and in the second region 12b, the content of dysprosium (Dy) is greater than the content of tin (Sn). By controlling the proportion of the core in the dielectric grain, TCC and DC bias characteristics can be ensured, and the degradation of dielectric constant and reliability can be mitigated.

[0082] In detail, according to an embodiment, core 11 may refer to a region where the content of tin (Sn) relative to 100 moles of titanium (Ti) is less than 0.2 moles and the content of dysprosium (Dy) relative to 100 moles of titanium (Ti) is less than 0.1 moles, while shell 12 may be a region in dielectric grain 10 other than core 11. Shell 12 may be configured to surround at least a portion of core 11, and shell 12 may include a first region 12a and a second region 12b, in the first region 12a, the number of moles of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti), and in the second region 12b, the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) relative to 100 moles of titanium (Ti).

[0083] When the dielectric grain 10 has a core-shell structure, in order to improve the TCC and DC bias characteristics, it is necessary to form the core 11 to occupy the largest possible proportion in the dielectric grain 10. However, if the proportion of the core 11 is increased in a typical core-shell structure, the size of the dielectric grain 10 itself may become excessively large, or the shell 12 may not be formed sufficiently. This may reduce the beneficial effects of increasing insulation resistance and suppressing oxygen vacancy movement through the shell 12.

[0084] On the other hand, when Sn replaces the Ti sites in the shell, the potential barrier is strengthened due to the increase in surface energy at the core-shell interface, and an increase in the shell resistance is expected. Therefore, in this disclosure, by providing a first region 12a with Sn concentration between the second region 12b of the shell 12 and the core 11, the proportion of the core 11 in the dielectric grain 10 can be sufficiently increased to improve the TCC and DC bias characteristics, and problems that may occur when increasing the proportion of the core in the dielectric grain in a general core-shell structure can also be mitigated or suppressed.

[0085] In embodiments of this disclosure, the proportion of the core 11 in the dielectric grain 10 can be expressed as the ratio of the maximum Ferete diameter LC of the core to the maximum Ferete diameter LG of the dielectric grain 10 including the core 11 and the shell 12 (LC / LG).

[0086] If LC / LG is less than 0.49, the dielectric characteristic of capacitance variation within ±22% over a range of -55°C to 105°C (X6S) may not be met, and the DC bias characteristics may deteriorate. Therefore, in this disclosure, by adjusting LC / LG to 0.49 or greater, the X6S characteristic is met, and sufficient DC bias characteristics are ensured.

[0087] There is no specific upper limit to the LC / LG value. However, if the LC / LG is greater than 0.73, reliability may degrade when forming a thin dielectric layer 111.

[0088] Therefore, in the embodiments, by adjusting LC / LG to the range of 0.49 to 0.73, the dielectric constant can be improved, the reliability of the ceramic electronic components can be improved, and X6S characteristics and sufficient DC bias characteristics can be ensured.

[0089] Furthermore, if LC / LG is greater than 0.64, the mean time to failure (MTTF) may decrease even if the content of auxiliary components that may be included in dielectric layer 111 is adjusted. Therefore, more specifically, LC / LG can be in the range of 0.49 to 0.64.

[0090] like Figure 6 As shown, the maximum Ferrette diameter can refer to the maximum distance between two points measured on the outer contour line of the dielectric grain 10 or the core 11 (i.e., the maximum distance between the two parallel lines of the projected contour of the dielectric grain 10 or the core 11 measured along a certain direction). The maximum Ferrette diameter can be measured by extracting the outer contour lines of the dielectric grain 10 and the core 11 using image analysis software (such as Image), and then selecting the maximum value from the diameter values ​​measured from the distance between two points on the outer contour lines.

[0091] Alternatively, the outer contour of the dielectric grain 10 or core 11 can be determined by processing a TEM image or TEM-EDS mapping image observed at a magnification of 225,000 in the central part of the capacitor forming portion Ac in the first and second direction sections of the ceramic electronic component 100 polished to the third direction center using image analysis software.

[0092] Specifically, the outer contour of dielectric grain 10 can be identified as grain boundary 20, which is a dark area in the TEM image. Alternatively, the outer contour of dielectric grain 10 can be identified as the boundary line of regions with different crystal structure orientations through diffraction pattern analysis. Furthermore, by overlaying the image mapping tin (Sn) with the image mapping dysprosium (Dy) after TEM-EDS analysis, the outer contour of core 11 can be identified as the boundary of a region that simultaneously satisfies the following conditions: the tin (Sn) content relative to 100 moles of titanium (Ti) is less than 0.2 moles, and the dysprosium (Dy) content relative to 100 moles of titanium (Ti) is less than 0.1 moles.

[0093] After determining the boundaries of dielectric grain 10 and core 11, the maximum Ferrette diameter LG of dielectric grain 10, including core 11 and shell 12, can be measured as the length of the longest line segment connecting two points of the boundary of dielectric grain 10, and the maximum Ferrette diameter LC of core 11 can be measured as the length of the longest line segment connecting two points of the boundary of core 11. This measurement can be repeated for 10 or more dielectric grains including core 11 and shell 12 containing first region 12a and second region 12b, and LG and LC can be more generalized by averaging these measurements.

[0094] In addition, the maximum Feret diameter LC of core 11 can be measured more clearly by performing a line scan analysis on the line segment with the longest length among the line segments connecting two points of the outer contour of core 11, and then measuring the length of the region that simultaneously satisfies the conditions that the content of tin (Sn) relative to 100 moles of titanium (Ti) is less than 0.2 moles and the content of dysprosium (Dy) relative to 100 moles of titanium (Ti) is less than 0.1 moles.

[0095] In an embodiment, the proportion of the core 11 in the dielectric die 10 can also be expressed as the relationship between the area of ​​the core 11, the area of ​​the first region 12a, and the area of ​​the second region 12b. For example, the area of ​​the core 11, the area of ​​the first region 12a, and the area of ​​the second region 12b can be obtained from a scanned image of the dielectric die 10.

[0096] Specifically, in this embodiment, the area of ​​core 11 may be larger than the area of ​​the first region 12a, and the area of ​​the second region 12b may be larger than the area of ​​the first region 12a. Therefore, by maintaining the proportion of core 11 in the dielectric grain 10 to a relatively large extent, the effect of improving TCC characteristics and DC bias characteristics can be more significant. For the same reason, in this embodiment, the area of ​​core 11 may be larger than the sum of the areas of the first region 12a and the second region 12b.

[0097] Dielectric grains 10 were analyzed using TEM-EDS to map tin (Sn) and dysprosium (Dy) elements. A region satisfying the condition that the tin (Sn) content relative to 100 moles of titanium (Ti) is less than 0.2 mol and the dysprosium (Dy) content relative to 100 moles of titanium (Ti) is less than 0.1 mol was designated as core 11. A region where the number of moles of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti) was designated as first region 12a, and a region where the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) relative to 100 moles of titanium (Ti) was designated as second region 12b. The area of ​​each region was then calculated by indicating each region in pixels using the ImageJ program, and the measurements were performed accordingly.

[0098] The tin (Sn) content in the first region 12a can be greater than or equal to 0.2 mol and less than or equal to 4.5 mol relative to 100 mol of titanium (Ti). Therefore, the diffusion of elements included in the second region 12b, described later, into the core 11 can be prevented. Furthermore, a peak in the tin (Sn) content can be formed within the first region 12a throughout the dielectric grain 10, and the peak in the tin (Sn) content can be formed in the range of greater than or equal to 0.2 mol and less than or equal to 4.5 mol relative to 100 mol of titanium (Ti).

[0099] The average tin (Sn) content in the first region 12a relative to 100 moles of titanium (Ti) can be twice or more the average tin (Sn) content in the second region 12b relative to 100 moles of titanium (Ti). By concentrating tin (Sn) in the first region 12a adjacent to the core 11, the potential decrease in reliability that may occur as the size of the core 11 increases can be mitigated.

[0100] By concentrating tin (Sn) in the first region 12a adjacent to the core 11, when the average content of tin (Sn) in the core 11 relative to 100 moles of titanium (Ti) is Sc, the average content of tin (Sn) in the first region 12a relative to 100 moles of titanium (Ti) is S1, and the average content of tin (Sn) in the second region 12b relative to 100 moles of titanium (Ti) is S2, the condition S1>S2>Sc can be satisfied.

[0101] The dysprosium (Dy) in dielectric layer 111 plays a role in improving insulation properties, but the dielectric constant may decrease when it is excessively diffused or substituted into core 11. Therefore, in the embodiments, the content of dysprosium (Dy) can have a maximum value in the second region 12b, and the average content of dysprosium (Dy) can also be maximized in the second region 12b. For example, when the average content of dysprosium (Dy) in core 11 relative to 100 moles of titanium (Ti) is Dc, the average content of dysprosium (Dy) in the first region 12a relative to 100 moles of titanium (Ti) is D1, and the average content of dysprosium (Dy) in the second region 12b relative to 100 moles of titanium (Ti) is D2, the following condition can be satisfied: D2 > D1 > Dc.

[0102] In the embodiments, Dc and D1 can be 0.04 moles or less relative to 100 moles of titanium (Ti), thus suppressing the problem of excessive diffusion or substitution of dysprosium (Dy) into core 11 and the resulting decrease in dielectric constant.

[0103] In an embodiment, dielectric layer 111 may also include at least one other rare earth element besides dysprosium (Dy). For example, dielectric layer 111 may include dysprosium (Dy) and at least one rare earth element other than dysprosium (Dy). Therefore, reliability degradation problems that may occur when dielectric layer 111 includes only dysprosium (Dy) as a rare earth element can be suppressed.

[0104] When the average content of rare earth elements (including dysprosium (Dy)) in core 11 relative to 100 moles of titanium (Ti) is Rec, the average content of rare earth elements (including dysprosium (Dy)) in the first region 12a relative to 100 moles of titanium (Ti) is Re1, and the average content of rare earth elements (including dysprosium (Dy)) in the second region 12b relative to 100 moles of titanium (Ti) is Re2, the condition Re2>Re1>Rec can be satisfied.

[0105] Examples of rare earth elements other than dysprosium (Dy) include lanthanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc.

[0106] The dielectric layer 111 may include a fixed-valence element. There is no specific limitation on the type of fixed-valence element; in this embodiment, the dielectric layer 111 may include vanadium (V) as the fixed-valence element. In this case, when the number of moles of rare earth elements relative to 100 moles of titanium (Ti) in the dielectric layer 111 is Ret and the number of moles of vanadium (V) relative to 100 moles of titanium (Ti) is Vt, Vt / Ret may be greater than or equal to 0.056 and less than or equal to 0.222. If Vt / Ret is less than 0.056, it may be difficult to ensure TCC characteristics and reliability; if Vt / Ret is greater than 0.222, the dielectric constant may decrease or the DC bias characteristics may decrease.

[0107] A portion of the tin (Sn) included in the dielectric layer 111 may diffuse toward the inner electrodes 121 and 122 during the sintering process. Therefore, in addition to nickel (Ni), the inner electrodes 121 and 122 may also include tin (Sn).

[0108] Reference Figure 8 Interface portions 123 and 124 may be disposed between the inner electrodes 121 and 122 and the dielectric layer 111. Interface portions 123 and 124 may be formed by suppressing the diffusion of tin (Sn) included in the dielectric layer 111 using a high concentration of nickel (Ni). Therefore, as... Figure 9As shown, interface portions 123 and 124 can form a peak with the maximum tin (Sn) content. The range of the peak tin (Sn) content is not particularly limited, but when the peak tin (Sn) content is 0.55 moles or greater relative to 100 moles of nickel (Ni), the capacitance improvement effect, the capacitance variation characteristics with temperature, and the effect of improving high-temperature reliability according to the embodiments of this disclosure can be more significant.

[0109] Additionally, refer to Figure 10 It can be confirmed that there is a region with a high tin (Sn) content measurement in the interface region between the dielectric layer and the inner electrode, and in the embodiment, this region is defined as interface portions 123 and 124.

[0110] See Figure 9 The interface region can be defined as the area from the boundary of the inner electrode where the nickel (Ni) content relative to the content of all elements except oxygen (O) decreases to 90 at%, extending to a point within 50 nm in the inward direction of the dielectric layer. Therefore, the inner electrodes 121 and 122 can be regions where the nickel (Ni) content relative to the content of all elements except oxygen (O) is greater than 90 at%. In other words, the region at the boundary between the inner electrode and the dielectric layer where the nickel (Ni) content relative to the content of all elements except oxygen (O) is less than or equal to 90 at% can be classified as the interface region.

[0111] Reference Figure 9 The peak values ​​of tin (Sn) content in interfaces 123 and 124 can be formed to be biased toward the inner electrodes 121 and 122. The capacitance improvement effect, temperature-dependent capacitance variation characteristics, and improved high-temperature reliability of embodiments according to this disclosure are more significant.

[0112] Reference Figure 9 When the average tin (Sn) content in the inner electrodes 121 and 122 relative to the content of all elements except oxygen (O) is S1, and the average tin (Sn) content in the dielectric layer relative to the content of all elements except oxygen (O) is S2, the condition S1 > S2 can be satisfied. Therefore, the shrinkage of the inner electrodes 121 and 122 that occurs during the sintering process can be delayed, thereby improving the connectivity of the inner electrodes 121 and 122.

[0113] (Experimental Example) BaTiO3 particles corresponding to core 11 were synthesized using a hydrothermal synthesis method. In this process, the particle size of BaTiO3 was synthesized to various sizes to account for the size of core 11 in the final product. SnO2 was then added to form the first region 12a, which would become the shell, and rare earth oxides (Re2O3) were added as a first auxiliary component. In some cases, terbium oxide (Tb4O7) was added, and vanadium oxide (V2O3) was added as a second auxiliary component to promote grain growth, thereby forming the second region 12b, which would become the shell. The dielectric powder was then mixed with a dispersant using ethanol and toluene as solvents, and a binder was mixed to fabricate a ceramic green sheet. Ni electrode paste was printed onto the formed ceramic green sheet and laminated. The pressed and cut green sheets were sintered to remove the binder, and then fired to produce sample sheets.

[0114] At this point, the maximum Feret diameter LC of the core 11 and the maximum Feret diameter LG of the entire dielectric grain 10 can vary according to the size of the final dielectric grain, which depends on the size of the initial BaTiO3 particles that will form the core 11 and the grain growth rate.

[0115] Table 1 below shows the maximum Feret diameter LC of core 11, the maximum Feret diameter LG of the entire dielectric grain 10, whether the first region 12a and the second region 12b of the shell are distinguished, and the content of various auxiliary components according to each test number. Table 2 shows the room temperature dielectric constant and loss factor (DF), capacitance as a function of temperature (TCC), mean time to failure (MTTF), and DC bias characteristics of the final ceramic electronic assembly including the dielectric layer that meets the conditions of Table 1.

[0116] The room temperature dielectric constant and loss factor (DF) were measured using an LCR meter at 1 kHz and AC 0.5 V. The dielectric constant of the MLCC wafer was calculated based on capacitance, dielectric layer thickness, internal electrode area, and number of stacked layers. The DC effective capacitance was measured by taking 10 (ten) samples at a time, applying a DC 3 V voltage, and then averaging the results after 60 seconds.

[0117] Electrostatic capacitance was measured according to temperature changes within a temperature range of -55℃ to 105℃ at 1 kHz, 0.15V, and a holding time of 5 minutes. Ten samples were taken at a time for measurement, and the average value was then taken.

[0118] The Mean Time Before Failure (MTTF) was calculated by averaging the time taken to reach failure by applying a voltage corresponding to an electric field of 27 V / μm at 125 °C to 10 samples. A MTTF of 20.1 hours or less was rated as defective (X); MTTF greater than 20.1 hours but less than or equal to 28 hours was rated as acceptable (△); MTTF greater than 28 hours but less than or equal to 30 hours was rated as good (O); and MTTF greater than 30 hours was rated as excellent (◎).

[0119] The DC bias characteristics were determined by applying a low-voltage, high-frequency AC signal to 10 samples using an LCR meter under a 3V DC bias voltage and measuring the capacitance. Capacitance less than or equal to 0.78μF was rated as defective (X), capacitance greater than 0.78μF and less than or equal to 0.82μF was rated as acceptable (△), capacitance greater than 0.82μF and less than 0.87μF was rated as good (O), and capacitance greater than or equal to 0.87μF was rated as excellent (◎).

[0120] If one or more defects are included in the various characteristics of the example, the final comprehensive characteristic judgment is evaluated as defective (X). If no defects are included in the various characteristics of the example but one or more qualified characteristics are included, it is evaluated as qualified (△). If all characteristics of the example are good or better, it is evaluated as excellent (◎).

[0121] [Table 1]

[0122] [Table 2]

[0123] Referring to Tables 1 and 2, for test numbers 8 to 31 where LC / LG is in the range of 0.49 to 0.73, it can be confirmed that regardless of the content of the first and second auxiliary components, the TCC characteristic is qualified (△) or higher, and the DC characteristic is qualified (△) or higher. However, when LC / LG is less than 0.49, regardless of the content of the first and second auxiliary components, at least one of the TCC and DC characteristics is defective (X). Furthermore, in the cases of test numbers 8 to 31, since the room temperature dielectric constant is greater than 3300, it can be confirmed that there is no decrease in dielectric constant.

[0124] Therefore, as in the embodiments, when LC / LG is in the range of 0.49 to 0.73, it can be confirmed that the ceramic electronic component 100 can ensure excellent dielectric constant, TCC characteristics and DC characteristics.

[0125] Furthermore, for tests 29 to 31 with an LC / LG greater than 0.64, it was confirmed that the MTTF (Mean Time To Failure) was defective (X) regardless of the content of the first and second auxiliary components. In contrast, if the LC / LG is less than or equal to 0.64, the Mean Time To Failure (MTTF) can be improved. Therefore, according to the embodiments, when the LC / LG is in the range of 0.49 to 0.64, TCC and DC characteristics can be ensured, and the phenomenon of reduced reliability due to an excessively large proportion of the nucleus occupying the entire grain can be suppressed.

[0126] Furthermore, the characteristic measurement results shown in Table 2 are for ease of understanding only and are not intended to limit this disclosure. The objectives of this disclosure are achieved by ensuring that one or more of the various characteristics are free of defects, thereby improving one or more corresponding characteristics of the ceramic electronic component.

[0127] As described above, according to the embodiments, the dielectric constant of the ceramic electronic component is improved because the dielectric grains, including a core and a shell, comprise a core and a shell surrounding at least a portion of the core. The shell comprises a first region and a second region, wherein in the first region, the number of moles of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti), and in the second region, the number of moles of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the number of moles of tin (Sn) relative to 100 moles of titanium (Ti).

[0128] According to an embodiment, a dielectric grain comprising a core and a shell in a plurality of dielectric grains includes a core and a shell surrounding at least a portion of the core, and the shell includes a first region and a second region, wherein in the first region the molar number of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the molar number of dysprosium (Dy) relative to 100 moles of titanium (Ti), and in the second region the molar number of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the molar number of tin (Sn) relative to 100 moles of titanium (Ti), and when the maximum Ferete diameter of the dielectric grain comprising the core and the shell is LG and the maximum Ferete diameter of the core is LC, LC / LG satisfies greater than or equal to 0.49 and less than or equal to 0.73, thereby improving the TCC characteristics and DC bias characteristics of the ceramic electronic component.

[0129] Although embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and drawings, but is intended to be limited by the appended claims. Therefore, various substitutions, modifications and alterations can be made by those skilled in the art without departing from the technical spirit of the present disclosure described in the claims, and these also fall within the scope of the present disclosure.

[0130] Furthermore, the expression "a certain (one) embodiment" as used in this disclosure does not imply the same embodiment, but is provided to emphasize and explain the distinct features that differ from each other. However, the embodiment presented above does not preclude implementation in combination with features of another embodiment. For example, even if something described in a particular embodiment is not described in another embodiment, it may be understood as a description relating to another embodiment, unless there is a description in another embodiment that contradicts or contradicts that content.

[0131] The terminology used in this disclosure is for describing embodiments only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0132] While exemplary embodiments have been described and illustrated above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A ceramic electronic component, comprising: The main body includes a dielectric layer and an inner electrode, wherein the dielectric layer comprises a plurality of dielectric grains; as well as An external electrode is disposed on the main body and connected to the internal electrode. The plurality of dielectric grains, including cores and shells, comprise titanium (Ti), tin (Sn), and dysprosium (Dy), and the shell surrounds at least a portion of the core. The core has a tin (Sn) content of less than 0.2 moles per 100 moles of titanium (Ti) and a dysprosium (Dy) content of less than 0.1 moles per 100 moles of titanium (Ti). The shell includes a first region and a second region, wherein in the first region, the molar number of tin (Sn) relative to 100 moles of titanium (Ti) is greater than the molar number of dysprosium (Dy) relative to 100 moles of titanium (Ti), and in the second region, the molar number of dysprosium (Dy) relative to 100 moles of titanium (Ti) is greater than the molar number of tin (Sn) relative to 100 moles of titanium (Ti). When the maximum Ferete diameter of the dielectric grain including the core and the shell is LG, and the maximum Ferete diameter of the core is LC, LC / LG is in the range of 0.49 to 0.

73.

2. The ceramic electronic component of claim 1, wherein, The internal electrode comprises nickel (Ni) and tin (Sn), and When the region from the point where the nickel (Ni) content at the boundary of the inner electrode decreases to 90 at% relative to the content of all elements except oxygen (O) to a range of 50 nm in the inward direction of the dielectric layer is defined as the interface region, the peak value of the tin (Sn) content at the interface region is 0.55 mol or greater relative to 100 mol of nickel (Ni).

3. The ceramic electronic package of claim 1, wherein, The internal electrode comprises nickel (Ni) and tin (Sn), and When the average content of tin (Sn) in the inner electrode relative to the content of all elements except oxygen (O) is S1, and the average content of tin (Sn) in the dielectric layer relative to the content of all elements except oxygen (O) is S2, S1>S2 is satisfied.

4. The ceramic electronic package of claim 1, wherein, The nickel (Ni) content in the internal electrode is greater than 90 at, relative to the content of all elements except oxygen (O).

5. The ceramic electronic package of claim 1, wherein, The content of tin (Sn) in the first region ranges from 0.2 mol to 4.5 mol relative to 100 mol of titanium (Ti).

6. The ceramic electronic package of claim 1, wherein, The average content of tin (Sn) in the first region relative to 100 moles of titanium (Ti) is at least twice the average content of tin (Sn) in the second region relative to 100 moles of titanium (Ti).

7. The ceramic electronic package of claim 1, wherein, When the average content of tin (Sn) in the core relative to 100 moles of titanium (Ti) is Sc, the average content of tin (Sn) in the first region relative to 100 moles of titanium (Ti) is S1, and the average content of tin (Sn) in the second region relative to 100 moles of titanium (Ti) is S2, the condition S1>S2>Sc is satisfied.

8. The ceramic electronic component according to claim 1, wherein, When the average content of dysprosium (Dy) in the core relative to 100 moles of titanium (Ti) is Dc, the average content of dysprosium (Dy) in the first region relative to 100 moles of titanium (Ti) is D1, and the average content of dysprosium (Dy) in the second region relative to 100 moles of titanium (Ti) is D2, the condition D2>D1>Dc is satisfied.

9. The ceramic electronic component according to claim 8, wherein, Both Dc and D1 are 0.04 mol or less.

10. The ceramic electronic package of claim 1, wherein, The dielectric layer also includes at least one other rare earth element besides dysprosium (Dy). When the average content of rare earth elements including dysprosium (Dy) in the core relative to 100 moles of titanium (Ti) is Rec, the average content of rare earth elements including dysprosium (Dy) in the first region relative to 100 moles of titanium (Ti) is Re1, and the average content of rare earth elements including dysprosium (Dy) in the second region relative to 100 moles of titanium (Ti) is Re2, then Re2>Re1>Rec.

11. The ceramic electronic package of claim 10, wherein, The other rare earth elements are selected from the group consisting of lanthanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

12. The ceramic electronic package of claim 1, wherein, The dielectric layer includes vanadium (V) as a fixed valence element, and When the number of moles of rare earth elements in the dielectric layer relative to 100 moles of titanium (Ti) is Ret, and the number of moles of vanadium (V) relative to 100 moles of titanium (Ti) is Vt, Vt / Ret is in the range of 0.056 to 0.

222.

13. The ceramic electronic package of claim 1, wherein, In the scanned image of the dielectric grain including the core and the shell, the area of ​​the core is larger than the area of ​​the first region, and the area of ​​the second region is larger than the area of ​​the first region.

14. The ceramic electronic package of claim 1, wherein, In the scanned image of the dielectric grain including the core and the shell, the area of ​​the core is greater than the sum of the areas of the first region and the second region.

15. The ceramic electronic package of claim 1, wherein, LC / LG ranges from 0.49 to 0.

64.

16. A ceramic electronic component, comprising: A dielectric layer comprising dielectric grains having a core and a shell surrounding at least a portion of the core, the dielectric grains comprising titanium, tin, and dysprosium, wherein, relative to 100 moles of titanium: In the core, the tin content is less than 0.2 mol and the dysprosium content is less than 0.1 mol. In a first region of the shell, relatively closer to the core, the tin content is greater than the dysprosium content, and In a second region of the shell, relatively farther from the core, the tin content is less than the dysprosium content; and An inner electrode is disposed on the dielectric layer and comprises nickel and tin, wherein at the interface between the inner electrode and the dielectric layer, the peak tin content is 0.55 mol or greater relative to 100 mol of nickel.

17. The ceramic electronic package of claim 16, wherein, The ratio of the maximum Ferete diameter of the core to the maximum Ferete diameter of the dielectric grain is in the range of 0.49 to 0.

73.

18. The ceramic electronic component according to claim 16, wherein, The interface portion is defined as the region in the range of 50 nm from the point where the nickel content in the inner electrode decreases to 90 at% relative to the content of all elements except oxygen, toward the dielectric layer at the boundary of the inner electrode.

19. The ceramic electronic package of claim 16, wherein, The tin content in the first region ranges from 0.2 mol to 4.5 mol relative to 100 mol of titanium.

20. The ceramic electronic package of claim 16, wherein, The average tin content in the first region relative to 100 moles of titanium is at least twice the average tin content in the second region relative to 100 moles of titanium.

21. The ceramic electronic component according to claim 16, wherein, The average tin content in the second region relative to 100 moles of titanium is greater than the average tin content in the core relative to 100 moles of titanium.

22. A ceramic electronic component, comprising: A dielectric layer comprising vanadium as a fixed valence element and comprising dielectric grains having a core and a shell surrounding at least a portion of the core, the dielectric grains comprising titanium, tin, and dysprosium, wherein, relative to 100 moles of titanium: The ratio of the molar number of vanadium to the molar number of rare earth elements in the dielectric layer is in the range of 0.056 to 0.

222. In the core, the tin content is less than 0.2 mol and the dysprosium content is less than 0.1 mol. In a first region of the shell, relatively closer to the core, the tin content is greater than the dysprosium content, and In a second region of the shell, which is relatively farther from the core, the tin content is less than the dysprosium content.

23. The ceramic electronic component according to claim 22, wherein, The ratio of the maximum Ferete diameter of the core to the maximum Ferete diameter of the dielectric grain is in the range of 0.49 to 0.

64.

24. The ceramic electronic component according to claim 22, wherein, The dielectric layer further includes at least one other rare earth element selected from the group consisting of lanthanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Wherein, relative to 100 moles of titanium, the average total content of rare earth elements in the core is denoted as Rec, the average total content of rare earth elements in the first region is denoted as Re1, and the average total content of rare earth elements in the second region is denoted as Re2, satisfying Re2>Re1>Rec.

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