Normally-off voltage-controlled switching device and method for manufacturing the same

Abstract

This invention discloses a normally-off voltage-controlled switching device and its fabrication method, belonging to the field of semiconductor technology. The device utilizes silicon carbide (SiC) material and innovatively constructs a heterogeneous integrated architecture of "high-voltage bipolar current conduction + low-voltage MOS voltage control." Its structure includes an N+ substrate, a drift layer, a P-well region, an N-channel region, and a dual-gate design. Through unique notch nesting and multilayer metal interconnect processes, bipolar low-resistance conduction of the main current path is achieved, while the base current is controlled by a low-voltage MOS structure. This design effectively overcomes the shortcomings of traditional SiC MOSFETs, such as low channel mobility, high conduction losses, and the unsafety of SiC BJT base floating, significantly improving the device's withstand voltage, short-circuit withstand time, and gate reliability, making it suitable for high-power-density applications.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a normally off voltage-controlled switch device and its fabrication method. Background Technology

[0002] In recent years, silicon carbide (SiC) power switching devices have seen rapid development in the high-power application market due to their excellent high-voltage resistance, high-temperature resistance, and low-loss characteristics. However, existing mainstream technologies still have significant limitations, which restrict their further promotion.

[0003] On the one hand, SiC MOSFETs, as the mainstream application, suffer from high conduction losses under high current conditions due to the low channel mobility beneath the gate dielectric. To reduce specific on-resistance, methods such as increasing the current-carrying area or reducing the gate dielectric thickness are commonly used to lower losses. However, increasing the current-carrying area increases manufacturing costs; reducing the gate dielectric thickness leads to a series of chain problems, including decreased gate reliability, weakened short-circuit withstand capability, and difficulties in designing drive voltage and threshold voltage. Furthermore, SiC MOSFETs require a difficult balance between source / drain breakdown voltage and on-resistance between JFET region width, doping concentration, and channel length, essentially making it difficult to achieve both current conduction capability and system reliability within a given cost.

[0004] On the other hand, although SiC BJTs outperform MOSFETs in terms of current carrying capacity, reliability, and temperature range, as current-controlled devices, they suffer from an inherent limitation: the current amplification factor and voltage withstand requirements are mutually constrained. More critically, while traditional SiC BJTs are labeled as "normally off" devices, in common-emitter circuits, due to the lack of a structure similar to the direct short-circuit of the emitter junction inside a MOSFET, the collector leakage current increases sharply once the base control signal is lost (floating), exhibiting an unstable state similar to "semi-normally open." This poses a serious safety hazard in high bus voltage applications. Replacing them with MOSFETs of the same voltage rating often requires selecting higher voltage ratings or sacrificing other parameters through special designs, leading to a significant increase in cost.

[0005] Therefore, there is an urgent need for a new type of voltage-controlled switching device that can retain the advantages of high current-throughput and high reliability of bipolar devices while overcoming the complexity of flow-controlled drive and the risk of base floating failure. Summary of the Invention

[0006] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a normally off voltage-controlled switch device, which includes, from bottom to top, a stacked electrode 1, an ohmic contact layer 2, an N+ substrate layer 3, an N- buffer layer 4, and an N- drift layer 5.

[0007] The upper part of the N-drift layer 5 is provided with a notch, and a P-well region 51 is provided within the notch. The bottom surface and sidewalls of the P-well region 51 are adjacent to the N-drift layer 5. The upper part of the P-well region 51 is provided with a notch, and an N-channel region 52 is provided within the notch. The bottom surface and sidewalls of the N-channel region 52 are adjacent to the P-well region 51. The upper part of the N-channel region 52 is provided with a notch, and a P-source region 53 is provided within the notch. The bottom surface and sidewalls of the P-source region 53 are adjacent to the N-channel region 52. There are two P-source regions 53, namely P-source region 531 and P-source region 532.

[0008] The N-drift layer is provided with a P-base layer 6, which includes P-base layer 61, P-base layer 62, and P-base layer 63; the thickness of P-base layer 61 is greater than that of P-base layer 62; the right end of P-base layer 62 covers the left P-well region 51; the left end of P-base layer 63 covers the right P-well region 51; an N-emitting layer 7 is provided on P-base layer 61; and a highly doped ohmic contact layer 8 is provided on N-emitting layer 7.

[0009] A layer 9 is provided on the interface of the heavily doped ohmic contact layer 8, P base layer 62, N-drift layer 5, P well region 51, N channel region 52, P source region 53, and P base layer 63; the layer 9 includes a gate dielectric layer 91, an alloyed ohmic contact layer 92, and a polysilicon gate electrode 93.

[0010] The gate dielectric layer 91 includes gate dielectric layer 911, gate dielectric layer 912, gate dielectric layer 913, and gate dielectric layer 914; gate dielectric layer 911 is located on the upper left side above the heavily doped ohmic contact layer 8; gate dielectric layer 912 extends from the upper right side above the heavily doped ohmic contact layer 8 to the P-source region 531; gate dielectric layer 913 extends from the P-source region 532 to the upper left of the P-base layer 63; and gate dielectric layer 914 is located on the upper right of the P-base layer 63.

[0011] The gate dielectric layer 91 is provided with two polysilicon gate electrodes 93, namely polysilicon gate electrode 931 and polysilicon gate electrode 932; the polysilicon gate electrode 931 is located on the gate dielectric layer 912 between the P-substrate 62 and the P-substrate 63; the polysilicon gate electrode 932 is located on the gate dielectric layer 913 between the P-substrate 62 and the P-substrate 63.

[0012] The alloyed ohmic contact layer 92 includes alloyed ohmic contact layers 921, 922, 923, 924, and 925; alloyed ohmic contact layer 921 is located between gate dielectric layers 911 and 912; alloyed ohmic contact layer 922 is located between gate dielectric layers 912 and 913; alloyed ohmic contact layer 923 is located between gate dielectric layers 913 and 914; alloyed ohmic contact layer 924 is located above the polysilicon gate electrode 931; and alloyed ohmic contact layer 925 is located above the polysilicon gate electrode 932.

[0013] An emitter 10, a gate 11, a drain 12, a gate 13, and a base 14 are respectively provided in alloyed ohmic contact layers 921, 922, 923, 924, and 925; and an interlayer dielectric layer 15 and a passivation layer 16 are respectively provided from bottom to top in the intervals between the emitter 10, gate 11, drain 12, gate 13, and base 14.

[0014] A second aspect of the present invention provides a method for fabricating a normally-off voltage-controlled switch device, comprising the following steps:

[0015] Step S1, epitaxial structure growth: An N-buffer layer 4, an N-drift layer 5, a P-base layer 6 and an N-emitting layer 7 are epitaxially grown on an N+ substrate layer 3;

[0016] Step S2, Ion implantation: N-type ion implantation is performed on the surface of the N-emitter region to form a highly doped ohmic contact layer 8;

[0017] Step S3, Etching: Etch from top to bottom on the right side to the P base layer 6, and etch away part of the P base layer 6 in the thickness direction;

[0018] Step S4, P-well ion implantation: P-type ions are implanted in the middle of the N-drift layer 5 to form a P-well region 51;

[0019] Step S5, etching to remove P base layer: etching to remove part of the P base layer 6 above P well area 51;

[0020] Step S6, N-channel region injection: N-type ions are injected into the P-well region 51 to form the N-channel region 52;

[0021] Step S7, P source region implantation and high temperature activation: P-type ions are implanted in the N-channel region 52 and activated at high temperature to form P source region 531 and P source region 532, thus producing a semi-finished device A.

[0022] Step S8, forming the gate dielectric: a gate dielectric layer 91 is grown or deposited on the surface of the semi-finished device A;

[0023] Step S9, gate deposition and patterning and dielectric deposition: deposit gate material and pattern it by combining photolithography and etching processes to form the first polysilicon gate electrode 931 and the second polysilicon gate electrode 932, and then deposit interlayer dielectric to form interlayer dielectric layer 15.

[0024] Step S10, dielectric windowing: Etching the interlayer dielectric to form vias exposes the ohmic contact layer 8, the polysilicon gate electrode 931 and the polysilicon gate electrode 932; the N-channel region 52 between the P-source region 531 and the P-source region 532 is exposed, and the P-base layer 6 on the right side is exposed.

[0025] Step S11, prepare ohmic contact area: form alloyed ohmic contact layer 92 at the bottom of the through hole to make semi-finished device B;

[0026] Step S12, M1 metal layer formation: A first metal layer is deposited on the surface of the semi-finished device B; the first metal layer is patterned by photolithography and etching;

[0027] Step S13, M2 metal layer and interconnect formation: An interlayer dielectric is deposited on the first metal layer to form a passivation layer 16. Then, through photolithography and etching, the interlayer dielectric is used to form vias to expose the emitter 10, gate 11, drain 12, gate 13, and base 14. Next, a second metal layer is deposited over the entire surface, and patterning is completed through photolithography and etching.

[0028] Step S14, backside thinning and metallization: After the N+ substrate layer is thinned, a third metal layer is deposited and formed. The third metal layer is annealed to form an ohmic contact layer 2. A multilayer electrode 1 is deposited on the ohmic metal layer 2.

[0029] As a preferred technical solution, the material of the N+ substrate layer 3 in step S1 is silicon carbide single crystal; the thickness of the N+ substrate layer 3 is 150-750 micrometers, and the N-type doping concentration is 10¹⁸-10²⁰ atoms / cm³; the atoms are N or P; the thickness of the N-buffer layer 4 is 0.2-2 micrometers, and the N-type doping concentration is 10¹⁸-10²⁰ atoms / cm³; the thickness of the N-drift layer 5 is 5-100 micrometers, and the N-type doping concentration is 10¹⁴-10¹⁷ atoms / cm³; the withstand voltage of the N-drift layer 5 is 650V-10KV; the thickness of the P-base layer 6 is 0.5-2 micrometers, and the P-type doping concentration is 10¹⁶-10¹⁸ atoms / cm³; the thickness of the N-emitter layer 7 is 0.5-2 micrometers, and the N-type doping concentration is 10¹⁷-10¹⁹ atoms / cm³; the N-type doped atoms are N or P; the P-type doped atoms are Al or B.

[0030] As a preferred technical solution, the N-type ion implantation energy in step S2 is below 50 keV, and the implantation concentration is above 3 × 10¹⁹ atoms / cm³.

[0031] As a preferred technical solution, the etching process in step S3 is a dry etching process.

[0032] As a preferred technical solution, the P-well doping concentration in step S4 is 5×10¹⁵-2×10¹⁷ atoms / cm³, which is greater than the N drift layer concentration, and the injection depth is 0.4-1.5 micrometers.

[0033] As a preferred technical solution, the doping concentration in step S6 is 5×10¹⁵-1×10¹⁷ atoms / cm³, the implantation depth is 0.3-1.2 micrometers, and the bottom of the N-channel region 52 is 0.3-0.5 micrometers away from the bottom of the P-well region 51; the implantation process is an N-type ion implantation process.

[0034] As a preferred technical solution, the implantation depth in step S7 does not exceed the depth of the N-channel region 52; the implantation depth is 0.2-0.5 micrometers, and the concentration is 5×10¹⁷-3×10¹⁹ atoms / cm³; the high-temperature activation is carried out under surface graphite protection, the activation temperature is 1700℃, and the annealing time is 30 minutes.

[0035] As a preferred technical solution, the forming process in step S8 is a thermal oxidation or deposition process; the gate dielectric material is silicon dioxide, silicon nitride, or a high-K material and its stack; the thickness of the gate dielectric layer is 20-100 nanometers.

[0036] As a preferred technical solution, the gate material in step S9 is polycrystalline silicon or metal; the material of the interlayer dielectric is silicon dioxide, BPSG, PSG or silicon nitride, the thickness of the interlayer dielectric is 0.2-2 micrometers, and it is subjected to heat treatment, planarization or rounding after deposition.

[0037] As a preferred technical solution, the etching process in step S10 is dry etching.

[0038] As a preferred technical solution, the alloyed ohmic contact layer 92 in step S11 is an N-type ohmic contact area or a P-type ohmic contact area; the contact material is nickel, aluminum, titanium or their alloys.

[0039] As a preferred technical solution, the metal mentioned in step S12 is aluminum or an aluminum-copper alloy.

[0040] As a preferred technical solution, the second metal in step S13 is aluminum or an aluminum-copper alloy.

[0041] As a preferred technical solution, the stacked electrode 1 in step S14 is a Ti / Ni / Ag stacked electrode; the thickness after thinning is 100-200 micrometers; the third metal layer is nickel; and the thickness of the ohmic contact layer is 0.05-0.5 micrometers.

[0042] This invention employs a heterogeneous integrated architecture of "high-voltage bipolar current conduction + low-voltage MOS voltage control": by designing the main current path (from the emitter region through the P-base region to the collector region) as a low-resistance bipolar conduction mode, it avoids the channel region with limited mobility in traditional SiC MOSFETs, thereby achieving lower on-resistance and higher current density in the same chip area; at the same time, the gate is only used to control the minority carriers injected into the P-base region (i.e., base current), operating in a low-voltage, low-current state, which not only significantly reduces gate power consumption and thermal stress, but also allows for a thicker gate oxide (20–100nm) because it does not need to withstand high drain-source voltage, significantly improving gate dielectric reliability and surge resistance; in addition, since the voltage-controlled region is independent of the high-voltage drift region, the JFET effect limitation is eliminated, allowing for flexible optimization of threshold voltage and conduction characteristics, ultimately achieving a comprehensive advantage of extended short-circuit withstand time, reduced switching losses, simplified drive circuit, and improved system life without sacrificing withstand voltage, making it particularly suitable for high power density and high reliability applications. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a normally closed voltage-controlled switch device;

[0044] 1. Stacked electrode; 2. Ohmic contact layer; 3. N+ substrate layer; 4. N- buffer layer; 5. N- drift layer;

[0045] 51. P-well region; 52. N-channel region; 53. P-source region; 531. Left P-source region; 532. Right P-source region;

[0046] 6. P-base layer; 61. First P-base layer; 62. Second P-base layer; 63. Third P-base layer;

[0047] 7. N-emitting layer; 8. Highly doped ohmic contact layer;

[0048] 9. Gate layer; 91. Gate dielectric layer; 92. Alloyed ohmic contact layer; 93. Polysilicon gate electrode;

[0049] 911. First gate dielectric layer; 912. Second gate dielectric layer; 913. Third gate dielectric layer; 914. Fourth gate dielectric layer;

[0050] 931. First polysilicon gate electrode; 932. Second polysilicon gate electrode;

[0051] 921. Alloyed ohmic contact layer; 922. Alloyed ohmic contact layer; 923. Alloyed ohmic contact layer; 924. Alloyed ohmic contact layer; 925. Alloyed ohmic contact layer;

[0052] 10. Emitter; 11. First gate; 12. Drain; 13. Second gate; 14. Base; 15. Interlayer dielectric layer; 16. Passivation layer. Detailed Implementation

[0053] Example 1

[0054] Step S1, Epitaxial Structure Growth: An N-buffer layer 4, an N-drift layer 5, a P-base layer 6, and an N-emitter layer 7 are epitaxially grown on an N+ substrate layer 3. The N+ substrate layer 3 is made of silicon carbide single crystal. The thickness of the N+ substrate layer 3 is 150 micrometers, and the N-type doping concentration is 10¹⁸ atoms / cm³. The atoms are N. The thickness of the N-buffer layer 4 is 0.2 micrometers, and the N-type doping concentration is 10¹⁸ atoms / cm³. The thickness of the N-drift layer 5 is 5 micrometers, and the N-type doping concentration is 10¹⁴ atoms / cm³. The withstand voltage of the N-drift layer 5 is 650V. The thickness of the P-base layer 6 is 0.5 micrometers, and the P-type doping concentration is 10¹⁶ atoms / cm³. The thickness of the N-emitter layer 7 is 0.5 micrometers, and the N-type doping concentration is 10¹⁷ atoms / cm³. The N-type doped atoms are N.

[0055] Step S2, Ion implantation: N-type ion implantation is performed on the surface of the N-emitting region to form a highly doped ohmic contact layer 8; the implantation energy is 30 keV and the implantation concentration is 3 × 10¹⁹ atoms / cm³.

[0056] Step S3, Etching: Etching from top to bottom on the right side down to the P base layer 6, and etching away part of the P base layer 6 in the thickness direction; The etching process is a dry etching process;

[0057] Step S4, P-well ion implantation: P-type ions are implanted in the middle of the N-type drift layer 5 to form a P-well region 51; the doping concentration of the P-well is 5 × 10¹⁵ atoms / cm³, which is greater than the doping concentration of the N-type drift layer 5, and the implantation depth is 0.4 micrometers;

[0058] Step S5, etching to remove P base layer: etching to remove part of the P base layer 6 above P well area 51;

[0059] Step S6, N-channel region implantation: N-type ions are implanted into the P-well region 51 to form an N-channel region 52; the doping concentration is 5×10¹⁵ atoms / cm³, the implantation depth is 0.3 micrometers, and the bottom of the N-channel region 52 is 0.3 micrometers away from the bottom of the P-well region 51; the implantation process is an N-type ion implantation process.

[0060] Step S7, P-source region implantation and high-temperature activation: P-type ions are implanted into the N-channel region 52 to form P-source regions 531 and 532, and then activated at high temperature to produce a semi-finished device A; the implantation depth does not exceed the depth of the N-channel region 52; the implantation depth is 0.2 micrometers, and the concentration is 5 × 10¹⁷ atoms / cm³; the high-temperature activation is carried out under surface graphite protection, the activation temperature is 1700℃, and the annealing time is 30 minutes;

[0061] Step S8, forming the gate dielectric: a gate dielectric layer 91 is grown or deposited on the surface of the semi-finished device A; the forming process is thermal oxidation or deposition; the gate dielectric material is silicon dioxide; the thickness of the gate dielectric layer is 20 nanometers;

[0062] Step S9, Gate Deposition and Patterning and Dielectric Deposition: Deposit gate material and pattern it to form a first polysilicon gate electrode 931 and a second polysilicon gate electrode 932, and then deposit interlayer dielectric to form an interlayer dielectric layer 15; the gate material is polysilicon; the interlayer dielectric material is silicon dioxide, the interlayer dielectric thickness is 0.2 micrometers, and after deposition, it is heat-treated and planarized;

[0063] Step S10, dielectric windowing: Etching the interlayer dielectric to form vias exposes the ohmic contact layer 8, the polysilicon gate electrode 931 and the polysilicon gate electrode 932; the N-channel region 52 between the P-source region 531 and the P-source region 532 is exposed, and the P-base layer 6 on the right side is exposed; the etching process is dry etching.

[0064] Step S11, prepare the ohmic contact area: form an alloyed ohmic contact layer 92 at the bottom of the through hole to make a semi-finished device B; the alloyed ohmic contact layer 92 is an N-type ohmic contact; the contact material is a nickel, aluminum, or titanium alloy;

[0065] Step S12, M1 metal layer formation: A first metal layer is deposited on the surface of the semi-finished device B; the metal is an aluminum-copper alloy; the first metal layer is patterned by photolithography and etching;

[0066] Step S13, M2 metal layer and interconnect formation: An interlayer dielectric is deposited on the first metal layer to form a passivation layer 16. Then, through photolithography and etching, the interlayer dielectric is used to form vias, exposing the emitter 10, the first gate 11, the drain 12, the second gate 13, and the base 14. Next, a second metal layer is deposited over the entire surface, and patterning is completed by photolithography and etching. The second metal is an aluminum-copper alloy.

[0067] Step S14, backside thinning and metallization: After the N+ substrate layer is thinned, a third metal layer is deposited and formed. The third metal layer is annealed to form an ohmic contact layer 2. A multilayer electrode 1 is deposited on the ohmic metal layer 2. The multilayer electrode 1 is a Ti / Ni / Ag multilayer electrode. The thickness after thinning is 100 micrometers. The third metal layer is nickel. The thickness of the ohmic contact layer is 0.05 micrometers.

[0068] Example 2

[0069] Step S1, Epitaxial Structure Growth: An N-buffer layer 4, an N-drift layer 5, a P-base layer 6, and an N-emitter layer 7 are epitaxially grown on an N+ substrate layer 3. The N+ substrate layer 3 is made of silicon carbide single crystal; the thickness of the N+ substrate layer 3 is 450 micrometers, and the N-type doping concentration is 10¹⁹ atoms / cm³; the atom is N; the thickness of the N-buffer layer 4 is 1.5 micrometers, and the N-type doping concentration is 10¹⁹ atoms / cm³; the thickness of the N-drift layer 5 is 50 micrometers, and the N-type doping concentration is 10¹⁶ atoms / cm³; the withstand voltage of the N-drift layer 5 is 1 kV; the thickness of the P-base layer 6 is 1 micrometer, and the P-type doping concentration is 10¹⁷ atoms / cm³; the thickness of the N-emitter layer 7 is 1 micrometer, and the N-type doping concentration is 10¹⁸ atoms / cm³; the N-type doped atom is N.

[0070] Step S2, Ion implantation: N-type ion implantation is performed on the surface of the N-emitting region to form a highly doped ohmic contact layer 8; the implantation energy is 40 keV and the implantation concentration is 4 × 10¹⁹ atoms / cm³.

[0071] Step S3, Etching: Etching from top to bottom on the right side down to the P base layer 6, and etching away part of the P base layer 6 in the thickness direction; The etching process is a dry etching process;

[0072] Step S4, P-well ion implantation: P-type ions are implanted in the middle of the N-drift layer 5 to form a P-well region 51;

[0073] The P-well doping concentration is 5 × 10¹⁶ atoms / cm³, which is greater than the N-drift layer concentration, and the injection depth is 1 micrometer.

[0074] Step S5, etching to remove P base layer: etching to remove part of the P base layer 6 above P well area 51;

[0075] Step S6, N-channel region implantation: N-type ions are implanted into the P-well region 51 to form an N-channel region 52; the doping concentration is 5×10¹⁶ atoms / cm³, the implantation depth is 1 micrometer, and the bottom of the N-channel region 52 is 0.4 micrometers away from the bottom of the P-well region 51; the implantation process is an N-type ion implantation process.

[0076] Step S7, P-source region implantation and high-temperature activation: P-type ions are implanted into the N-channel region 52 to form a first P-source region 531 and a second P-source region 532, and then activated at high temperature to produce a semi-finished device A; the implantation depth does not exceed the depth of the N-channel region 52; the implantation depth is 0.4 micrometers, and the concentration is 5 × 10¹⁸ atoms / cm³; the high-temperature activation is carried out under surface graphite protection, the activation temperature is 1700℃, and the annealing time is 30 minutes;

[0077] Step S8, forming the gate dielectric: a gate dielectric layer 91 is grown or deposited on the surface of the semi-finished device A; the forming process is thermal oxidation or deposition; the gate dielectric material is silicon nitride; the thickness of the gate dielectric layer is 60 nanometers;

[0078] Step S9, Gate Deposition and Patterning and Dielectric Deposition: Deposit gate material and pattern it to form a first polysilicon gate electrode 931 and a second polysilicon gate electrode 932, and then deposit interlayer dielectric to form an interlayer dielectric layer 15; the gate material is polysilicon; the interlayer dielectric material is silicon nitride, the interlayer dielectric thickness is 1 micrometer, and after deposition, it is heat treated and rounded.

[0079] Step S10, dielectric windowing: Etching the interlayer dielectric to form vias exposes the ohmic contact layer 8, the polysilicon gate electrode 931 and the polysilicon gate electrode 932; the N-channel region 52 between the P-source region 531 and the P-source region 532 is exposed, and the P-base layer 6 on the right side is exposed; the etching process is dry etching.

[0080] Step S11, prepare ohmic contact area: form alloyed ohmic contact layer 92 at the bottom of the through hole to make semi-finished device B; the alloyed ohmic contact layer 92 is an N-type ohmic contact area or a P-type ohmic contact area; the contact material is nickel, aluminum, or titanium alloy;

[0081] Step S12, M1 metal layer formation: A first metal layer is deposited on the surface of the semi-finished device B; the metal is aluminum or an aluminum-copper alloy; the first metal layer is patterned by photolithography and etching;

[0082] Step S13, M2 metal layer and interconnect formation: An interlayer dielectric is deposited on the first metal layer to form a passivation layer 16. Then, through photolithography and etching, the interlayer dielectric is used to form vias, exposing the emitter 10, the first gate 11, the drain 12, the second gate 13, and the base 14. Next, a second metal layer is deposited over the entire surface, and patterning is completed by photolithography and etching. The second metal is an aluminum-copper alloy.

[0083] Step S14, backside thinning and metallization: After the N+ substrate layer is thinned, a third metal layer is deposited to form the third metal layer, which is then annealed to form an ohmic contact layer 2; a multilayer electrode 1 is deposited on the ohmic metal layer 2; the multilayer electrode 1 is a Ti / Ni / Ag multilayer electrode.

[0084] The thickness after thinning is 150 micrometers; the third metal layer is nickel; and the ohmic contact layer has a thickness of 0.3 micrometers.

[0085] Example 3

[0086] Step S1, epitaxial structure growth: An N-buffer layer 4, an N-drift layer 5, a P-base layer 6 and an N-emitting layer 7 are epitaxially grown on an N+ substrate layer 3;

[0087] The material of the N+ substrate layer 3 is silicon carbide single crystal;

[0088] The N+ substrate layer 3 has a thickness of 750 micrometers and an N-type doping concentration of 1020 atoms / cm³; the atoms are nitrogen.

[0089] The N-buffer layer 4 is 2 micrometers thick and has an N-type doping concentration of 1020 atoms / cm³.

[0090] The N-drift layer 5 has a thickness of 100 micrometers and an N-type doping concentration of 10¹⁷ atoms / cm³; the N-drift layer 5 has a withstand voltage of 10 kV.

[0091] The P-based substrate 6 has a thickness of 2 micrometers and a P-type doping concentration of 10¹⁸ atoms / cm³.

[0092] The N-emitting layer 7 is 2 micrometers thick and has an N-type doping concentration of 10¹⁹ atoms / cm³.

[0093] The N-type doped atom is nitrogen; the P-type doped atom is Al;

[0094] Step S2, Ion implantation: N-type ion implantation is performed on the surface of the N-emitting region to form a highly doped ohmic contact layer 8; the implantation energy is 50 keV and the implantation concentration is 5 × 10¹⁹ atoms / cm³.

[0095] Step S3, Etching: Etching from top to bottom on the right side down to the P base layer 6, and etching away part of the P base layer 6 in the thickness direction; The etching process is a dry etching process;

[0096] Step S4, P-well ion implantation: P-type ions are implanted in the middle of the N-type drift layer 5 to form a P-well region 51;

[0097] The P-well doping concentration is 1×10¹⁷ atoms / cm³, which is greater than the N-drift layer concentration, and the injection depth is 1.5 micrometers.

[0098] Step S5, etching to remove P base layer: etching to remove part of the P base layer 6 above P well area 51;

[0099] Step S6, N-channel region implantation: N-type ions are implanted into the P-well region 51 to form an N-channel region 52; the doping concentration is 1×10¹⁷ atoms / cm³, the implantation depth is 1.2 micrometers, and the bottom of the N-channel region 52 is 0.5 micrometers away from the bottom of the P-well region 51; the implantation process is an N-type ion implantation process.

[0100] Step S7, P-source region implantation and high-temperature activation: P-type ions are implanted into the N-channel region 52 to form P-source regions 531 and 532, and then activated at high temperature to produce a semi-finished device A; the implantation depth does not exceed the depth of the N-channel region 52; the implantation depth is 0.5 micrometers, and the concentration is 3×10¹⁹ atoms / cm³; the high-temperature activation is carried out under surface graphite protection, the activation temperature is 1700℃, and the annealing time is 30 minutes;

[0101] Step S8, forming the gate dielectric: a gate dielectric layer 91 is grown or deposited on the surface of the semi-finished device A;

[0102] The formation process is either thermal oxidation or deposition.

[0103] The gate dielectric material is silicon dioxide, silicon nitride, or a high-K material and its stack-up;

[0104] The thickness of the gate dielectric layer is 100 nanometers;

[0105] Step S9, Gate Deposition and Patterning and Dielectric Deposition: Deposit gate material and pattern it to form a first polysilicon gate electrode 931 and a second polysilicon gate electrode 932, and then deposit interlayer dielectric to form an interlayer dielectric layer 15; the gate material is polysilicon or metal;

[0106] The interlayer medium is made of silicon dioxide, BPSG, PSG or silicon nitride, and the thickness of the interlayer medium is 0.2-2 micrometers. After deposition, it is subjected to heat treatment, planarization or corner rounding.

[0107] Step S10, dielectric windowing: Etching the interlayer dielectric to form vias exposes the ohmic contact layer 8, the polysilicon gate electrode 931 and the polysilicon gate electrode 932; the N-channel region 52 between the P-source region 531 and the P-source region 532 is exposed, and the P-base layer 6 on the right side is exposed; the etching process is dry etching.

[0108] Step S11, prepare ohmic contact area: form alloyed ohmic contact layer 92 at the bottom of the through hole to make semi-finished device B; the alloyed ohmic contact layer 92 is an N-type ohmic contact area or a P-type ohmic contact area; the contact material is nickel, aluminum, titanium or their alloys;

[0109] Step S12, M1 metal layer formation: A first metal layer is deposited on the surface of the semi-finished device B; the metal is aluminum or an aluminum-copper alloy; the first metal layer is patterned by photolithography and etching;

[0110] Step S13, M2 metal layer and interconnect formation: An interlayer dielectric is deposited on the first metal layer to form a passivation layer 16. Then, through photolithography and etching, the interlayer dielectric is used to form vias, exposing the emitter 10, gate 11, drain 12, gate 13, and base 14. Next, a second metal layer is deposited over the entire surface, and patterning is completed by photolithography and etching. The second metal is aluminum or an aluminum-copper alloy.

[0111] Step S14, backside thinning and metallization: After the N+ substrate layer is thinned, a third metal layer is deposited and formed. The third metal layer is annealed to form an ohmic contact layer 2. A multilayer electrode 1 is deposited on the ohmic metal layer 2. The multilayer electrode 1 is a Ti / Ni / Ag multilayer electrode. The thickness after thinning is 200 micrometers. The third metal layer is nickel. The thickness of the ohmic contact layer is 0.5 micrometers.

[0112] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A normally-off voltage-controlled switching device, characterized by, The voltage-controlled switching device comprises, from bottom to top, a stacked electrode (1), an ohmic contact layer (2), an N+ substrate layer (3), an N- buffer layer (4), and an N- drift layer (5). The upper part of the N-drift layer (5) is provided with a notch, and a P-well region (51) is provided in the notch. The bottom surface and sidewall of the P-well region (51) are adjacent to the N-drift layer (5). The upper part of the P-well region (51) is provided with a notch, and an N-channel region (52) is provided in the notch. The bottom surface and sidewall of the N-channel region (52) are adjacent to the P-well region (51). The upper part of the N-channel region (52) is provided with a notch, and a P-source region (53) is provided in the notch. The bottom surface and sidewall of the P-source region (53) are adjacent to the N-channel region (52). There are two P-source regions (53), namely the first P-source region (531) and the second P-source region (532). The N-drift layer (5) is provided with a P-base layer (6), which includes a first P-base layer (61), a second P-base layer (62), and a third P-base layer (63). The first P-base layer (61) is thicker than the second P-base layer (62). The right end of the second P-base layer (62) covers the left P-well region (51). The left end of the third P-base layer (63) covers the right P-well region (51). An N-emitting layer (7) is provided on the first P-base layer (61). A highly doped ohmic contact layer (8) is provided on the N-emitting layer (7). A gate layer (9) is provided on the interface of the heavily doped ohmic contact layer (8), the second P base layer (62), the N-drift layer (5), the P well region (51), the N channel region (52), the P source region (53), and the third P base layer (63); the gate layer (9) includes a gate dielectric layer (91), an alloyed ohmic contact layer (92), and a polycrystalline silicon gate electrode (93). The gate dielectric layer (91) includes a first gate dielectric layer (911), a second gate dielectric layer (912), a third gate dielectric layer (913), and a fourth gate dielectric layer (914); the first gate dielectric layer (911) is located on the left side above the heavily doped ohmic contact layer (8); the second gate dielectric layer (912) extends from the right side above the heavily doped ohmic contact layer (8) to the P source region (531); the third gate dielectric layer (913) extends from the P source region (532) to the upper left of the third P substrate (63); and the fourth gate dielectric layer (914) is located on the upper right of the third P substrate (63). The gate dielectric layer (91) is provided with polysilicon gate electrodes (93), and there are two polysilicon gate electrodes (93), namely a first polysilicon gate electrode (931) and a second polysilicon gate electrode (932); the first polysilicon gate electrode (931) is located on the second gate dielectric layer (912) between the second P substrate (62) and the third P substrate (63); the second polysilicon gate electrode (932) is located on the third gate dielectric layer (913) between the second P substrate (62) and the third P substrate (63); The alloyed ohmic contact layer (92) includes a first alloyed ohmic contact layer (921), a second alloyed ohmic contact layer (922), a third alloyed ohmic contact layer (923), a fourth alloyed ohmic contact layer (924), and a fifth alloyed ohmic contact layer (925); the first alloyed ohmic contact layer (921) is located between the first gate dielectric layer (911) and the second gate dielectric layer (912); the second alloyed ohmic contact layer (922) is located between the second gate dielectric layer (912) and the third gate dielectric layer (913); the third alloyed ohmic contact layer (923) is located between the third gate dielectric layer (913) and the fourth gate dielectric layer (914); the fourth alloyed ohmic contact layer (924) is located above the first polysilicon gate electrode (931); and the fifth alloyed ohmic contact layer (925) is located above the second polysilicon gate electrode (932). An emitter (10), a first gate (11), a drain (12), a second gate (13), and a base (14) are respectively provided on the first alloyed ohmic contact layer (921), the second alloyed ohmic contact layer (922), the third alloyed ohmic contact layer (923), the fourth alloyed ohmic contact layer (924), and the fifth alloyed ohmic contact layer (925); an interlayer dielectric layer (15) and a passivation layer (16) are respectively provided from bottom to top in the interval between the emitter (10), the first gate (11), the drain (12), the second gate (13), and the base (14).

2. A method of fabricating a normally-off voltage-controlled switching device, characterized by, Includes the following steps: Step S1, epitaxial structure growth: An N-buffer layer (4), an N-drift layer (5), a P-base layer (6) and an N-emitting layer (7) are epitaxially grown on an N+ substrate layer (3). Step S2, Ion implantation: N-type ion implantation is performed on the surface of the N-emitting layer (7) to form a highly doped ohmic contact layer (8); Step S3, Etching: Etch from top to bottom on the right side to the P base layer (6), and etch away part of the P base layer (6) in the thickness direction. Step S4, P-well ion implantation: P-type ions are implanted in the middle of the N-drift layer (5) to form a P-well region (51). Step S5, etching to remove P base layer: etching to remove part of the P base layer (6) above the P well area (51); Step S6, N-channel region injection: N-type ions are injected into the P-well region (51) to form an N-channel region (52). Step S7, P source region implantation and high temperature activation: P-type ions are implanted in the N-channel region (52) and activated at high temperature to form P source region (531) and P source region (532) to make semi-finished device A; Step S8, forming gate dielectric growth or deposition: forming a gate dielectric layer (91) on the surface of the semi-finished device A. Step S9, gate deposition and patterning and dielectric deposition: deposit gate material and pattern to form a first polysilicon gate electrode (931) and a second polysilicon gate electrode (932), and then deposit interlayer dielectric to form an interlayer dielectric layer (15). Step S10, dielectric windowing: Etching the interlayer dielectric to form a via, exposing the ohmic contact layer (8), and exposing the first polysilicon gate electrode (931) and the second polysilicon gate electrode (932); The N-channel region (52) between the first P source region (531) and the second P source region (532) is exposed, and the P base layer (6) on the right side is exposed; Step S11, prepare ohmic contact area: form alloyed ohmic contact layer (92) at the bottom of through hole to make semi-finished device B; Step S12, M1 metal layer formation: A first metal layer is deposited on the surface of the semi-finished device B; the first metal layer is patterned by photolithography and etching; Step S13, M2 metal layer and interconnect formation: deposit interlayer dielectric on the first metal layer to form a passivation layer (16), and then form vias in the interlayer dielectric through photolithography and etching to expose the emitter (10), the first gate (11), the drain (12), the second gate (13), and the base (14); then deposit the second metal layer over the entire surface, and complete the patterning through photolithography and etching; Step S14, backside thinning and metallization: After the N+ substrate layer is thinned, a third metal layer is deposited and formed. The third metal layer is annealed to form an ohmic contact layer (2). A multilayer electrode (1) is deposited on the ohmic metal layer (2).

3. The production method according to claim 2, characterized by, The stacked electrode 1 mentioned in step S1 is a Ti / Ni / Ag stacked electrode.

4. The production method according to claim 3, characterized by, The etching process described in step S3 is a dry etching process.

5. The preparation method according to claim 4, characterized in that, The doping concentration of the P-well in step S4 is 5×10¹⁵-1×10¹⁷ atoms / cm³, which is greater than the concentration of the N-drift layer (5), and the injection depth is 0.4-1.5 micrometers.

6. The preparation method according to claim 5, characterized in that, The doping concentration in step S6 is 5×10¹⁵-1×10¹⁷ atoms / cm³, the implantation depth is 0.3-1.2 micrometers, and the bottom of the N-channel region 52 is 0.3-0.5 micrometers away from the bottom of the P-well region 51; the implantation process is an N-type ion implantation process.

7. The preparation method according to claim 6, characterized in that, The implantation depth in step S7 does not exceed the depth of the N-channel region 52; the implantation depth is 0.2-0.5 micrometers, and the concentration is 5×10¹⁷-3×10¹⁹ atoms / cm³.

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