Semiconductor device and method of manufacturing the same, semiconductor package structure, electronic device

Abstract

This application provides a semiconductor device, its fabrication method, a semiconductor packaging structure, and an electronic device. It relates to the field of semiconductor manufacturing technology. The device includes a substrate, a capacitor, a first conductive via, a second conductive via, and a third conductive via. The substrate includes a first protrusion, a second protrusion, and a third protrusion. A portion of the capacitor is located between two adjacent protrusions, and a portion is located on each protrusion. The capacitor includes a stacked first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer. The first conductive via, the second conductive via, and the third conductive via are located on the side of the capacitor facing away from the substrate. The first conductive via is located on the first protrusion and connected to the first electrode layer; the second conductive via is located on the second protrusion and connected to the second electrode layer; and the third conductive via is located on the third protrusion and connected to the third electrode layer. This application can improve the high-frequency response characteristics of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its preparation method, a semiconductor packaging structure, and an electronic device. Background Technology

[0002] With the continuous improvement of chip integration, the use of deep trench capacitors (DTC) to replace surface-mount capacitors has become an inevitable trend. Deep trench capacitors change the area occupied by planar chips to vertical development into the silicon wafer. Due to their excellent energy storage, filtering and decoupling functions, they have been widely used in chip manufacturing and chip packaging.

[0003] Deep trench capacitors consist of a substrate with trenches, a dielectric layer filled within the trenches, and an electrode layer. The trench design increases the surface area of ​​the electrode layer, thereby improving capacitance and optimizing storage performance. However, the high-frequency response characteristics of existing deep trench capacitors still need improvement. Summary of the Invention

[0004] This application provides a semiconductor device, its fabrication method, a semiconductor packaging structure, and an electronic device. The aim is to improve the high-frequency response characteristics of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] On the one hand, this application provides a semiconductor device, which may be an adapter board containing passive capacitors or a chip containing capacitors.

[0007] The semiconductor device includes a substrate, a capacitor, a first conductive via, a second conductive via, and a third conductive via. The substrate includes a first protrusion, a second protrusion, and a third protrusion, which are spaced apart in a first direction perpendicular to the thickness direction of the substrate. A portion of the capacitor is located between two adjacent protrusions of the first, second, and third protrusions, and a portion of the capacitor is located on the first, second, and third protrusions. The capacitor includes a first electrode layer, a second electrode layer, a third electrode layer, a first dielectric layer located between the first and second electrode layers, and a second dielectric layer located between the second and third electrode layers. The first conductive via, the second conductive via, and the third conductive via are each located on the side of the capacitor facing away from the substrate.

[0008] A first conductive via is located on a first protrusion and is connected to a first electrode layer located on the first protrusion. A second conductive via is located on a second protrusion and is connected to a second electrode layer located on the second protrusion. A third conductive via is located on a third protrusion and is connected to a third electrode layer located on the third protrusion.

[0009] This application provides a first, second, and third protrusion spaced apart on a substrate, such that a first conductive via is located on the first protrusion and connected to a first electrode layer located on the first protrusion. A second conductive via is located on the second protrusion and connected to a second electrode layer located on the second protrusion. A third conductive via is located on the third protrusion and connected to a third electrode layer located on the third protrusion. Thus, the first, second, and third conductive vias are all located directly above the unit pattern area of ​​the capacitor (i.e., the area in the capacitor where protrusions and grooves (i.e., the spacing between two adjacent protrusions) are arranged).

[0010] In other words, the first conductive via can lead out the electrical signal of the first electrode layer from above the unit pattern area of ​​the capacitor, the second conductive via can lead out the electrical signal of the second electrode layer from above the unit pattern area of ​​the capacitor, and the third conductive via can lead out the electrical signal of the third electrode layer from above the unit pattern area of ​​the capacitor. This shortens the electrical signal transmission path, effectively reducing the delay in the electrical signal during transmission, and thus improving the high-frequency response speed of the semiconductor device. Furthermore, since a longer electrical signal transmission path is accompanied by a larger parasitic inductance and capacitance, these parasitic effects can adversely affect high-frequency signals, such as causing signal attenuation and phase delay. Therefore, this application can also reduce these parasitic effects by shortening the electrical signal transmission path, thereby improving the high-frequency performance of the capacitor.

[0011] In one possible implementation, the capacitors located on the first protrusion, the second protrusion, and the third protrusion are arranged in sequence along the direction from the capacitor to the substrate, with a first electrode layer, a second electrode layer, and a third electrode layer; along the first direction, the third conductive via has a first spacing with the first electrode layer, and the third conductive via has a second spacing with the second electrode layer; the first spacing is greater than the second spacing.

[0012] This application sets the first spacing to be greater than the second spacing, so that during the fabrication of semiconductor devices, through holes can be opened first on the first electrode layer and then on the second electrode layer. In other words, the first electrode layer and the second electrode layer can be etched separately. The process of fabrication using the layered opening method is relatively mature, which is conducive to forming devices with more stable performance and higher yield and reliability.

[0013] In one possible implementation, the second conductive via has a third spacing with respect to the first electrode layer; the third spacing is equal to the second spacing.

[0014] This application provides a third spacing between the sidewall of the second conductive via along the first direction and the sidewall of the first electrode layer, such that the third spacing is equal to the second spacing. In this way, the etching of the first electrode layer and the second electrode layer can be formed using the same process or the same equipment, which helps to reduce the difficulty of semiconductor device fabrication.

[0015] In one possible implementation, the capacitors located on the first protrusion, the second protrusion, and the third protrusion are arranged in sequence along the direction from the capacitor to the substrate, with a first electrode layer, a second electrode layer, and a third electrode layer; along the first direction, the third conductive via has a first spacing with the first electrode layer, and the third conductive via has a second spacing with the second electrode layer; the first spacing and the second spacing are equal.

[0016] By setting the first and second spacings to be equal, the first and second electrode layers can be simultaneously etched when the hole located at the third conductive via is formed on the capacitor, thereby creating a hole on the capacitor that exposes the third electrode layer or the second dielectric layer. The second electrode layer does not require a pre-reserved enclosure area, saving the area occupied by enclosures between different electrode layers. On the one hand, this allows for a denser arrangement of protrusions per unit area, making the layout of multiple protrusions more compact and facilitating the placement of more protrusions, thus increasing the capacitance density of the capacitor. On the other hand, the elimination of pre-reserved enclosures between different electrode layers further shortens the signal transmission path, effectively reducing signal delay during transmission, improving the high-frequency response speed of semiconductor devices, and reducing the adverse effects of parasitic responses on high-frequency signals, thereby further improving the high-frequency performance of the capacitor.

[0017] In one possible implementation, the second conductive via has a third spacing with respect to the first electrode layer, and the first spacing, the second spacing, and the third spacing are all equal.

[0018] That is, based on the fact that the first spacing and the second spacing are equal, the third spacing can also be equal to the first spacing and the second spacing. In this way, the formation of the third spacing can be carried out using the same process or the same processing equipment as the formation of the first spacing and the second spacing, which helps to reduce the difficulty of semiconductor device fabrication.

[0019] In one possible implementation, the dimensions of the first protrusion along the first direction, the dimensions of the second protrusion along the first direction, and the dimensions of the third protrusion along the first direction are all the same.

[0020] This application sets the dimensions of the first protrusion, the second protrusion, and the third protrusion to be equal along the first direction. This makes the fabrication of each protrusion easier and improves the structural stability of the semiconductor device.

[0021] In one possible implementation, the dimension of the first protrusion along the first direction is smaller than the dimension of the second protrusion along the first direction, and the dimension of the second protrusion along the first direction is smaller than the dimension of the third protrusion along the first direction.

[0022] That is, the dimensions of the first protrusion along the first direction, the second protrusion along the first direction, and the third protrusion along the third direction in this application can be set to be equal or unequal. When the dimensions of the first protrusion along the first direction, the second protrusion along the first direction, and the third protrusion along the third direction are unequal, the dimension of the first protrusion along the first direction can be set to be smaller than the dimension of the second protrusion along the first direction, and the dimension of the second protrusion along the first direction can be set to be smaller than the dimension of the third protrusion along the first direction, according to different enclosure requirements. In this way, more protrusions can be set per unit area, increasing the protrusion density and thus increasing the capacitance density of the capacitor.

[0023] In one possible implementation, the dimension of the first protrusion along the first direction is smaller than the dimension of the second protrusion along the first direction, and the dimension of the second protrusion along the first direction is equal to the dimension of the third protrusion along the first direction.

[0024] This application provides a first conductive via above a first protrusion, a second conductive via above a second protrusion, and a third conductive via above a third protrusion. A third spacing exists between the second conductive via and the first electrode layer. When the third conductive via has a first spacing and a second spacing between it and the first and second electrode layers respectively, the dimension of the first protrusion along the first direction can be set to be smaller than the dimension of the second protrusion along the first direction, and the dimension of the second protrusion along the first direction can be set to be smaller than the dimension of the third protrusion along the first direction. In this way, the number and density of protrusions per unit area can be increased, thereby improving the capacitance density of the capacitor.

[0025] In one feasible approach, the substrate also includes raised structures;

[0026] There is a protrusion structure between any two of the first protrusion, the second protrusion, and the third protrusion; part of the capacitor is located between the protrusion structure and one of the protrusions, part of the capacitor is located between the protrusion structure and another protrusion, and part of the capacitor is located on the protrusion structure.

[0027] This application provides a raised structure that can be used to support the capacitor, allowing more of the capacitor to be embedded in the substrate. This also allows for a larger area of ​​the capacitor's electrode layer, thereby further improving the capacitor's capacitance density.

[0028] In one possible implementation, the dimension of the protrusion structure along the first direction is less than or equal to the dimension of the first protrusion along the first direction;

[0029] The dimension of the protrusion along the first direction is smaller than the dimension of the second protrusion along the first direction;

[0030] The dimension of the second protrusion along the first direction is equal to the dimension of the third protrusion along the first direction.

[0031] This application sets the dimension of the protrusion structure along the first direction to be less than or equal to the dimension of the first protrusion along the first direction, sets the dimension of the first protrusion along the first direction to be less than the dimension of the second protrusion along the first direction, and sets the dimensions of the second and third protrusions along the first direction to be equal. In this way, the protrusion structure can improve the capacitance density of the capacitor to a certain extent; and because the first, second, and third protrusions, and the protrusions without positioning function (i.e., the protrusion structures) use smaller dimensions, the transmission path of the electrical signal can be shortened, thereby improving the high-frequency characteristics of the device. Therefore, this design can achieve a certain improvement in capacitance density while meeting the requirements for device bandwidth or high-frequency response.

[0032] In one possible implementation, the capacitor further includes a fourth electrode layer and a third dielectric layer; the third dielectric layer is located between the third electrode layer and the fourth electrode layer.

[0033] The substrate also includes a fourth protrusion, and the semiconductor device also includes a fourth conductive via;

[0034] The fourth conductive via is located on the side of the capacitor away from the substrate. The fourth conductive via is located on the fourth protrusion and is connected to the fourth electrode layer located on the fourth protrusion.

[0035] This application, by adding a fourth electrode layer to the capacitor, which includes a first, second, and third electrode layer, increases the number of electrode layers, thereby increasing the effective energy storage area inside the capacitor and allowing it to store more charge, thus improving the capacitor's capacity. The fourth conductive via facilitates the extraction of the fourth electrode layer. Positioning the fourth conductive via on the fourth protrusion does not obstruct the effective area of ​​the capacitor and shortens the signal transmission path, which is beneficial for maintaining better high-frequency characteristics while increasing the capacitor's capacity.

[0036] In one possible implementation, the first electrode layer is located on the side of the second electrode layer facing away from the substrate, and the side of the first electrode layer facing away from the first dielectric layer has a dielectric layer.

[0037] This application provides a dielectric layer on the side of the first electrode layer that is opposite to the first dielectric layer. This dielectric layer protects the first electrode layer, preventing oxidation of the first electrode layer due to exposure during subsequent etching processes. The dielectric layer also improves the reliability of the electrical connection between the first electrode layer and the first conductive via.

[0038] In one possible implementation, the semiconductor device also includes an insulating layer located between the substrate and the capacitor.

[0039] This application improves device reliability by placing an insulating layer between the substrate and the capacitor. The insulating layer can isolate the capacitor from other possible conductors, ensuring that the current can flow along the designed path of the capacitor, avoiding short circuits or leakage.

[0040] On the other hand, this application provides a method for fabricating a semiconductor device, the method comprising:

[0041] A first groove and a second groove are formed in the substrate. The first groove and the second groove are arranged at intervals along a direction parallel to the surface of the substrate to form a first protrusion, a second protrusion and a third protrusion.

[0042] A capacitor is formed in the first groove and the second groove, and on the first protrusion, the second protrusion and the third protrusion. The capacitor includes a first electrode layer, a second electrode layer, a third electrode layer, a first dielectric layer located between the first electrode layer and the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer.

[0043] A conductive via is formed on the side of the capacitor away from the substrate. The conductive via includes a first conductive via, a second conductive via, and a third conductive via. The first conductive via is located on a first protrusion and is connected to a first electrode layer located on the first protrusion. The second conductive via is located on a second protrusion and is connected to a second electrode layer located on the second protrusion. The third conductive via is located on a third protrusion and is connected to a third electrode layer located on the third protrusion.

[0044] The fabrication method of this application, by forming conductive vias on corresponding protrusions (i.e., the first conductive via is disposed on the first protrusion, the second conductive via is disposed on the second protrusion, and the third conductive via is disposed on the third protrusion), can shorten the path of electrical signal transmission, thereby effectively reducing the delay of electrical signals during transmission and thus improving the high-frequency response speed of semiconductor devices; at the same time, shortening the electrical signal transmission path can also reduce parasitic effects, thereby improving the high-frequency performance of capacitors.

[0045] In one feasible manner, forming a capacitor on the first protrusion, the second protrusion, and the third protrusion includes:

[0046] The third electrode layer, the second dielectric layer, the second electrode layer, the first dielectric layer, and the first electrode layer are sequentially fabricated.

[0047] Before forming a conductive via on the side of the capacitor away from the substrate, the method further includes;

[0048] A lead-out hole is formed on the capacitor. The lead-out hole includes a first lead-out hole and a second lead-out hole. The first lead-out hole exposes a first dielectric layer, and the second lead-out hole exposes a second dielectric layer. The first lead-out hole is located on a second protrusion, and the second lead-out hole is located on a third protrusion.

[0049] A dielectric layer is formed on the capacitor, and the dielectric layer fills the first lead-out hole and the second lead-out hole;

[0050] A conductive via is formed on the side of the capacitor facing away from the substrate, including:

[0051] A first contact hole, a second contact hole, and a third contact hole are formed on the dielectric layer. The first contact hole exposes the first electrode layer, the second contact hole exposes the second electrode layer, and the third contact hole exposes the third electrode layer. The second contact hole is located inside the first lead-out hole and its radial dimension is smaller than that of the first lead-out hole. The third contact hole is located inside the second lead-out hole and its radial dimension is smaller than that of the second lead-out hole.

[0052] Metal is filled into the first contact hole, the second contact hole, and the third contact hole to form a first conductive through hole, a second conductive through hole, and a third conductive through hole, respectively.

[0053] This application forms a first lead-out hole and a second lead-out hole (i.e., the first lead-out hole exposes the first dielectric layer, and the second lead-out hole exposes the second dielectric layer) through the above-described implementation method. In this way, after the lead-out hole is formed and before the dielectric layer is formed, the second electrode layer can be protected by the first dielectric layer, and the third electrode layer can be protected by the second dielectric layer. This can prevent oxidation of the second electrode layer and the third electrode layer, thereby improving the electrical connection reliability of the subsequent second conductive via and the second electrode layer, as well as improving the electrical connection reliability of the subsequent third conductive via and the third electrode layer.

[0054] In one feasible manner, forming a lead-out hole on the capacitor includes:

[0055] A first lead-out hole and a first through hole are formed on the capacitor, with the first lead-out hole and the first through hole exposing the first dielectric layer respectively;

[0056] A second through-hole is formed on the first dielectric layer, penetrating the second electrode layer. The second through-hole is located inside the first through-hole, and the radial dimension of the second through-hole is smaller than that of the first through-hole. The first through-hole and the second through-hole form a second lead-out hole, which exposes the second dielectric layer.

[0057] This application first opens a first lead-out hole and a first through hole on the first electrode layer, and then opens a second through hole on the second electrode layer. In other words, the first electrode layer and the second electrode layer can be etched separately. The process of fabrication by layering opening holes is relatively mature. This is conducive to forming devices with more stable performance and higher yield and reliability.

[0058] In one feasible manner, forming a lead-out hole on the capacitor includes:

[0059] A first lead-out hole is formed on the capacitor, exposing the first dielectric layer;

[0060] A second lead-out is formed on the capacitor, exposing the second dielectric layer.

[0061] That is, when forming leads on the capacitor, this application can also adopt the method of first forming one lead (e.g., the first lead) and then forming another lead (e.g., the second lead). Using this fabrication method, the enclosure between different electrode layers does not need to be reserved, which can shorten the path of electrical signal transmission and improve high-frequency response characteristics.

[0062] In one feasible manner, forming a capacitor on the first protrusion, the second protrusion, and the third protrusion includes:

[0063] The third electrode layer, the second dielectric layer, the second electrode layer, the first dielectric layer, and the first electrode layer are sequentially fabricated.

[0064] Before forming a conductive via on the side of the capacitor away from the substrate, the method further includes;

[0065] A lead-out hole is formed on the capacitor. The lead-out hole includes a first lead-out hole and a second lead-out hole. The first lead-out hole exposes the second electrode layer, and the second lead-out hole exposes the third electrode layer. The first lead-out hole is located on the second protrusion, and the second lead-out hole is located on the third protrusion.

[0066] A dielectric layer is formed on the capacitor, and the dielectric layer fills the first lead-out hole and the second lead-out hole;

[0067] A conductive via is formed on the side of the capacitor facing away from the substrate, including:

[0068] A first contact hole, a second contact hole, and a third contact hole are formed on the dielectric layer. The first contact hole exposes the first electrode layer, the second contact hole exposes the second electrode layer, and the third contact hole exposes the third electrode layer. The second contact hole is located inside the first lead-out hole and its radial dimension is smaller than that of the first lead-out hole. The third contact hole is located inside the second lead-out hole and its radial dimension is smaller than that of the second lead-out hole.

[0069] Metal is filled into the first contact hole, the second contact hole, and the third contact hole to form a first conductive through hole, a second conductive through hole, and a third conductive through hole, respectively.

[0070] This application forms a first lead-out hole and a second lead-out hole (i.e., the first lead-out hole exposes the second electrode layer, and the second lead-out hole exposes the third electrode layer) through the above-described implementation method. In this way, the corresponding electrode layer can be directly exposed when the lead-out hole is formed. Therefore, it is not necessary to etch the corresponding dielectric layer when forming the subsequent conductive via, making the formation of the conductive via more convenient.

[0071] In one feasible manner, forming a lead-out hole on the capacitor includes:

[0072] A first lead-out hole and a first through hole are formed on the capacitor, with the first lead-out hole and the first through hole exposing the second electrode layer respectively;

[0073] A second through-hole is formed on the second electrode layer, penetrating the second dielectric layer. The second through-hole is located inside the first through-hole, and the radial dimension of the second through-hole is smaller than that of the first through-hole. The first through-hole and the second through-hole form a second lead-out hole, which exposes the third electrode layer.

[0074] This application uses this method to form the first lead-out hole and the second lead-out hole. The first lead-out hole and the first through hole can be formed on the first electrode layer and the first dielectric layer first, and then the second through hole can be formed on the second electrode layer and the second dielectric layer. The process of fabrication by layering opening holes is relatively mature. This is conducive to forming devices with more stable performance and higher yield and reliability.

[0075] In one feasible manner, forming a lead-out hole on the capacitor includes:

[0076] A first lead-out hole is formed on the capacitor, exposing the second electrode layer;

[0077] A second lead-out hole is formed on the capacitor, exposing the third electrode layer.

[0078] That is, the first and second lead-out holes can be formed independently. Specifically, one lead-out hole (e.g., the first lead-out hole) is formed first, followed by the other lead-out hole (e.g., the second lead-out hole). Using this fabrication method, no enclosure needs to be reserved between different electrode layers, which shortens the electrical signal transmission path and improves high-frequency response characteristics.

[0079] In another aspect, this application also provides a semiconductor packaging structure, which includes a substrate and a semiconductor device as described in any of the above implementations, wherein the semiconductor device is disposed on the substrate.

[0080] In the semiconductor packaging structure provided in this application, since the first conductive via, the second conductive via, and the third conductive via can all lead out the electrical signal of the corresponding electrode layer from above the unit pattern area of ​​the capacitor, the path of electrical signal transmission is shortened, thus reducing the delay of electrical signal during transmission and thereby improving the high-frequency response speed of the semiconductor device; at the same time, shortening the electrical signal transmission path can also reduce these parasitic effects, thereby improving the high-frequency performance of the capacitor.

[0081] In one possible implementation, the semiconductor device is an adapter board; the semiconductor package structure also includes multiple chips; the chips are mounted on the adapter board.

[0082] In another aspect, this application provides an electronic device that includes a circuit board and a semiconductor package structure in any of the above-described possible embodiments, the semiconductor package structure being connected to the circuit board.

[0083] Since the electronic device includes a semiconductor packaging structure in any of the aforementioned possible ways, it can achieve the corresponding effects of the semiconductor packaging structure. Attached Figure Description

[0084] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;

[0085] Figure 2A This is one of the schematic diagrams of the semiconductor device provided in the embodiments of this application;

[0086] Figure 2B for Figure 2A A magnified view of a section at point A in the middle;

[0087] Figure 3A for Figure 2A A top view schematic diagram of one type of semiconductor device;

[0088] Figure 3B for Figure 3A A magnified view of a section at point B in the middle;

[0089] Figure 4A for Figure 2A Another top view schematic diagram of a semiconductor device;

[0090] Figure 4B for Figure 4A A magnified view of a section at point C;

[0091] Figure 5 This is a second schematic diagram of the structure of the semiconductor device provided in the embodiments of this application;

[0092] Figure 6 for Figure 5 A top view schematic diagram of one type of semiconductor device;

[0093] Figure 7 for Figure 5 Another top view schematic diagram of a semiconductor device;

[0094] Figure 8 This is the third schematic diagram of the structure of the semiconductor device provided in the embodiments of this application;

[0095] Figure 9 for Figure 8 A top view schematic diagram of one type of semiconductor device;

[0096] Figure 10 for Figure 8 Another top view schematic diagram of a semiconductor device;

[0097] Figure 11 This is the fourth schematic diagram of the structure of the semiconductor device provided in the embodiments of this application;

[0098] Figure 12 for Figure 11 A top view schematic diagram of one type of semiconductor device;

[0099] Figure 13 for Figure 11 Another top view schematic diagram of a semiconductor device;

[0100] Figure 14 This is one of the fabrication process flowcharts of the semiconductor device provided in the embodiments of this application;

[0101] Figure 15A This is a second flowchart illustrating the fabrication process of a semiconductor device provided in an embodiment of this application.

[0102] Figure 15B The third flowchart illustrating the fabrication process of the semiconductor device provided in this application embodiment;

[0103] Figures 16 to 26C For preparation Figure 5 The semiconductor device in the diagram is a structural schematic diagram corresponding to the completion of each step.

[0104] Figures 27A to 34B For preparation Figure 8 The semiconductor device in the diagram is a structural schematic diagram corresponding to the completion of each step.

[0105] Figures 35A to 44B For preparation Figure 11 The semiconductor device in the diagram is a schematic diagram of the corresponding structure after each step is completed.

[0106] Figure label:

[0107] 01-Electronic devices;

[0108] 10-Substrate; 11-First protrusion; 12-Second protrusion; 13-Third protrusion; 14-Fourth protrusion; 15-Protrusion structure; 211-First electrode layer; 212-Second electrode layer; 213-Third electrode layer; 214-Fourth electrode layer; 221-First dielectric layer; 222-Second dielectric layer; 223-Third dielectric layer; 224-Dielectric layer; 231-First lead-out hole; 232-Second lead-out hole; 233-Third lead-out hole; 241-First through hole; 242-Second through hole; 243-Third through hole; 31-First conductive through hole; 32-Second conductive through hole; 33-Third conductive through hole; 34-Fourth conductive through hole; 40-Insulating layer; 50-Dielectric layer; 60-Linear layer; a-First direction; B1-First spacing; B2-Second spacing; B3-Third spacing;

[0109] 210 - Substrate; 220 - Adapter board; 230 - Chip; 300 - Electrical connection structure; 400 - Circuit board. Detailed Implementation

[0110] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0111] The terms "first," "second," "third," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0112] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0113] This application provides an electronic device 01. The electronic device 01 may include a mobile phone, tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, or other equipment such as home appliances, aircraft engine control systems, avionics systems, automotive systems, and downhole oil exploration systems. This application does not impose any special limitations on the specific form of the aforementioned electronic device 01.

[0114] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application, such as... Figure 1 As shown, the aforementioned electronic device 01 may include a circuit board 400, such as a printed circuit board (PCB), on which a semiconductor package structure may be disposed. The semiconductor package structure can be electrically connected to the circuit board 400 via an electrical connection structure 300, thereby enabling the semiconductor package structure to achieve signal interconnection with other chips or other electronic modules on the circuit board 400.

[0115] In alternative embodiments, the electrical connection structure 300 may include a plurality of solder balls, such as a ball grid array (BGA); or, the electrical connection structure 300 may include a plurality of conductive pillars, such as metal pillars.

[0116] The semiconductor packaging structure may include a substrate 210 and a semiconductor device, with the semiconductor device disposed on the substrate 210, for example, on a packaging substrate. The substrate 210 may be disposed on a circuit board 400 via an electrical connection structure 300.

[0117] Semiconductor devices can be integrated passive devices (IPDs), such as any device with internal deep trench capacitors (DTCs), like the silicon interposer in a 2.5D package structure; they can also be fan-out board-level packages (FOPs) with DTCs; or they can be capacitors embedded in a substrate. Alternatively, semiconductor devices can also be artificial intelligence chips, high-performance computing chips, and server logic chips.

[0118] Taking the semiconductor device as an interposer 220 as an example, such as Figure 1 As shown, the semiconductor package structure may also include multiple chips 230, which can be mounted on an adapter board 220 to achieve signal interconnection between the multiple chips 230. This type of package can be referred to as a 2.5D package.

[0119] The number of chips 230 can be two or more. Figure 1 This example uses three chips 230 as an example. It should be understood that the three chips 230 are merely an example and are not intended to limit this application.

[0120] in addition, Figure 1 The chip 230 shown can be a single chip or multiple chips stacked in three dimensions; this application does not impose any restrictions on this.

[0121] In some implementations, chip 230 may include memory, system on chip (SOC), or analog chips, digital chips, etc.

[0122] In semiconductor device packaging processes, deep trench capacitors are introduced to... Figure 1 The adapter board 220 shown can effectively serve as a coupling capacitor for high-frequency signal straighteners and a decoupling capacitor to solve the decoupling problem of bias circuits. For example, by placing the deep-groove capacitor in a silicon substrate, the capacitor can be called a silicon capacitor. Silicon capacitors are suitable for harsh environments, including aircraft engine control, avionics systems, automotive systems, and downhole oil exploration systems. Furthermore, the capacitance of silicon capacitors remains relatively stable under voltage and temperature variations, exhibiting high reliability and low failure rate, and does not change significantly due to changes in external conditions. Silicon capacitors also have excellent anti-aging properties; their capacitance does not decrease significantly over time, ensuring long-term reliability. Additionally, the capacitance of silicon capacitors changes very little with DC bias, making them suitable for high power density applications and meeting the needs of various circuit applications.

[0123] As electronic devices move towards higher frequencies, signals become more frequent and change rapidly, requiring capacitors to respond quickly. This places higher demands on the frequency response characteristics of capacitors.

[0124] This application provides some semiconductor devices with capacitors and methods for manufacturing such semiconductor devices. By leading conductive vias out from above the cell pattern region of the capacitor (i.e., the region opposite the region on the substrate 10 where protrusions are arranged), the transmission path of electrical signals can be shortened, effectively reducing the delay of electrical signals during transmission and thus improving the high-frequency response speed of the semiconductor device. At the same time, shortening the electrical signal transmission path can also reduce parasitic inductance and capacitance, thereby improving the high-frequency performance of the capacitor.

[0125] like Figure 2A As shown, Figure 2A This application provides a schematic diagram of the structure of a semiconductor device, which can be... Figure 1 The adapter board (Interposer) 220 shown, or, could be... Figure 1 The chip 230 shown may also be other semiconductor devices with integrated passive components, etc., and this application does not limit this.

[0126] The semiconductor device may include a substrate 10. The material of the substrate 10 may include one of silicon, silicon carbide, sapphire, etc., and this application does not limit the specific material of the substrate 10.

[0127] The base 10 may include a first protrusion 11, a second protrusion 12, and a third protrusion 13, such as Figure 2A As shown, the first protrusion 11, the second protrusion 12 and the third protrusion 13 are arranged at intervals in the first direction a, which is perpendicular to the thickness direction of the base 10.

[0128] like Figure 2A For example, the arrangement direction of the first protrusion 11, the second protrusion 12, and the third protrusion 13 is parallel to the surface of the substrate 10; or, the arrangement direction of the first protrusion 11, the second protrusion 12, and the third protrusion 13 is perpendicular to the thickness direction of the substrate 10. For instance, in... Figure 2A In the orientation shown, the first protrusion 11, the second protrusion 12 and the third protrusion 13 are arranged in a horizontal direction.

[0129] Along the thickness direction of the base 10, the first protrusion 11, the second protrusion 12 and the third protrusion 13 all have a height dimension. For example, the first protrusion 11, the second protrusion 12 and the third protrusion 13 can extend along the thickness direction of the base 10, and any one of the protrusions has a dimension in the thickness direction of the base 10.

[0130] The first protrusion 11, the second protrusion 12, and the third protrusion 13 are arranged in pairs at intervals, so that there is a gap between any two adjacent protrusions of the first protrusion 11, the second protrusion 12, and the third protrusion 13, which is the groove area of ​​the base 10.

[0131] The radial dimension of the gap region (i.e., the groove region) between two adjacent protrusions is not limited in this application and can be designed according to the number and thickness of the electrode layer and the number and thickness of the dielectric layer.

[0132] In some feasible embodiments, the specific arrangement of the first protrusion 11, the second protrusion 12, and the third protrusion 13 is not limited in this application; the first protrusion 11, the second protrusion 12, and the third protrusion 13 can be spaced apart in pairs. For example, in some examples, such as Figure 2A The third protrusion 13 may be located between the first protrusion 11 and the second protrusion 12. In other examples, the second protrusion 12 may be located between the first protrusion 11 and the third protrusion 13, or the first protrusion 11 may be located between the third protrusion 13 and the second protrusion 12.

[0133] It should be understood that, in addition to the first protrusion 11, the second protrusion 12, and the third protrusion 13, the base 10 may also include a fourth protrusion, a fifth protrusion, etc., in some feasible embodiments. That is, this application does not limit the number of protrusions included in the base 10, and can design them as needed.

[0134] In addition, the specific number of each of the first protrusion 11, the second protrusion 12 and the third protrusion 13 is not limited. For example, there may be multiple first protrusions 11, and multiple first protrusions 11 are arranged at intervals; there may be multiple second protrusions 12, and multiple second protrusions 12 are arranged at intervals; there may be multiple third protrusions 13, and multiple third protrusions 13 are arranged at intervals.

[0135] The semiconductor device may also include a capacitor, with portions of the capacitor located between two adjacent protrusions of the first protrusion 11, the second protrusion 12, and the third protrusion 13, and portions of the capacitor located on the first protrusion 11, the second protrusion 12, and the third protrusion 13.

[0136] That is, the capacitor portion can be located above the first protrusion 11, the second protrusion 12, and the third protrusion 13, and the capacitor portion can fill the space between two adjacent protrusions (i.e., fill the groove in the base 10). For ease of understanding, please refer to... Figure 2A As shown, in Figure 2AThe intermediate substrate 10 includes a first protrusion 11, a second protrusion 12, and a third protrusion 13. The first protrusion 11 and the third protrusion 13 are spaced apart (i.e., there is a groove between the first protrusion 11 and the third protrusion 13), and the third protrusion 13 and the second protrusion 12 are spaced apart (i.e., there is also a groove between the third protrusion 13 and the second protrusion 12). At this time, a portion of the capacitor is located in the groove between the first protrusion 11 and the third protrusion 13, a portion of the capacitor is located in the groove between the third protrusion 13 and the second protrusion 12, a portion of the capacitor is located on the first protrusion 11, a portion of the capacitor is located on the second protrusion 12, and a portion of the capacitor is located on the third protrusion 13.

[0137] The capacitor may include a first electrode layer 211, a second electrode layer 212, a third electrode layer 213, a first dielectric layer 221 located between the first electrode layer 211 and the second electrode layer 212, and a second dielectric layer 222 located between the second electrode layer 212 and the third electrode layer 213.

[0138] In some examples, in addition to the first plate layer 211, the second plate layer 212 and the third plate layer 213, the capacitor may also include a fourth plate layer 214, a fifth plate layer, etc., which can be set as needed, and this application does not impose specific limitations.

[0139] This application provides a substrate 10 with a first protrusion 11, a second protrusion 12, and a third protrusion 13, and a capacitor including a first electrode layer 211, a second electrode layer 212, a third electrode layer 213, a first dielectric layer 221, and a second dielectric layer 222. Furthermore, any two adjacent protrusions among the first protrusion 11, the second protrusion 12, and the third protrusion 13 are spaced apart. This allows a portion of the capacitor to be located on one side of the first protrusion 11, the second protrusion 12, and the third protrusion 13, while the other portion fills the space between any two adjacent protrusions. This increases the surface area of ​​the capacitor's electrode layers, which is beneficial for improving the capacitor's capacitance and optimizing storage performance.

[0140] In one possible implementation, the first electrode layer 211 may be located on the side of the second electrode layer 212 away from the substrate 10, and the side of the first electrode layer 211 away from the first dielectric layer 221 may have a dielectric layer 224.

[0141] In other words, the first electrode layer 211 can be the top electrode layer of the capacitor.

[0142] When the first electrode layer 211 is the top electrode layer of the capacitor, a dielectric layer 224 can also be provided on the side of the first electrode layer 211 away from the first dielectric layer 221. In this way, the dielectric layer 224 can protect the first electrode layer 211 and prevent oxidation of the first electrode layer 211 due to exposure during subsequent etching processes. The provision of the dielectric layer 224 helps to improve the electrical connection reliability between the first electrode layer 211 and the first conductive via 31.

[0143] The provision of dielectric layer 224 on the side of the first electrode layer 211 away from the first dielectric layer 221 is merely an example. In other embodiments, dielectric layer 224 may not be provided or other equivalent layers may be provided.

[0144] In one possible implementation, the semiconductor device may also include an insulating layer 40 (Liner) located between the substrate 10 and the capacitor.

[0145] That is, an insulating layer 40 can be provided between the substrate 10 and the capacitor. Alternatively, an insulating layer 40 can be provided between the substrate 10 and the bottom plate layer of the capacitor. By providing an insulating layer 40 between the substrate 10 and the bottom plate layer of the capacitor, this application can isolate the capacitor from other possible conductors, ensuring that the current can flow along the designed path of the capacitor, avoiding short circuits or leakage, thereby improving the reliability of the device.

[0146] The semiconductor device may also include a first conductive via 31, a second conductive via 32, and a third conductive via 33, wherein the first conductive via 31, the second conductive via 32, and the third conductive via 33 are located on the side of the capacitor away from the substrate 10.

[0147] That is, the first conductive through hole 31, the second conductive through hole 32 and the third conductive through hole 33 are all located above the capacitor.

[0148] The first conductive via 31 can be located on the first protrusion 11, and the first conductive via 31 is connected to the first electrode layer 211 located on the first protrusion 11. In this way, the first electrode layer 211 can be led out through the first conductive via 31.

[0149] The second conductive via 32 can be located on the second protrusion 12, and the second conductive via 32 is connected to the second electrode layer 212 located on the second protrusion 12. In this way, the second electrode layer 212 can be led out through the second conductive via 32.

[0150] The third conductive via 33 can be located on the third protrusion 13, and the third conductive via 33 is connected to the third electrode layer 213 located on the third protrusion 13. In this way, the third electrode layer 213 can be led out through the second conductive via 32.

[0151] By providing a first conductive via 31, a second conductive via 32, and a third via 243, and positioning these vias on the side of the capacitor away from the substrate 10, with the first conductive via 31 located on the first protrusion 11 and connected to the first electrode layer 211 on the first protrusion 11; the second conductive via 32 located on the second protrusion 12 and connected to the second electrode layer 212 on the second protrusion 12; and the third conductive via 33 located on the third protrusion 13 and connected to the third electrode layer 213 on the third protrusion 13, the first electrode layer 211, the second electrode layer 212, and the third electrode layer 213 can be led out through their respective conductive vias, which facilitates circuit design for semiconductor devices.

[0152] For example, the first electrode layer 211 can be electrically connected to the first connection pad in the circuit layer 60 through the first conductive via 31, the second electrode layer 212 can be electrically connected to the second connection pad in the circuit layer 60 through the second conductive via 32, and the third electrode layer 213 can be electrically connected to the first connection pad in the circuit layer 60 through the third conductive via 33. It should be understood that the above connection methods are merely examples and should not be considered as limitations on this application.

[0153] This application, by setting the first conductive via 31 on the first protrusion 11, the second conductive via 32 on the second protrusion 12, and the third conductive via 33 on the third protrusion 13, ensures that the first conductive via 31, the second conductive via 32, and the third conductive via 33 are all located directly above the cell pattern area of ​​the capacitor. The cell pattern area of ​​the capacitor refers to the area in the capacitor where protrusions and grooves are arranged (i.e., the interval area between two adjacent protrusions).

[0154] Furthermore, the first conductive via 31 is disposed on the first protrusion 11, the second conductive via 32 is disposed on the second protrusion 12, and the third conductive via 33 is disposed on the third protrusion 13. In this way, the first protrusion 11, the second protrusion 12, and the third protrusion 13 can also serve as contact hole landing (CT Landing), that is, the positioning function of the conductive vias. The conductive vias can be positioned according to the corresponding protrusions during formation, facilitating rapid positioning of the conductive vias.

[0155] A first conductive through-hole 31 is disposed on a first protrusion 11, a second conductive through-hole 32 is disposed on a second protrusion 12, and a third conductive through-hole 33 is disposed on a third protrusion 13. In this way, the first protrusion 11, the second protrusion 12, and the third protrusion 13 can also serve a supporting function; that is, the first protrusion 11 can support the first conductive through-hole 31, the second protrusion 12 can support the second conductive through-hole 32, and the third protrusion 13 can support the third conductive through-hole 33.

[0156] In some implementations, the cell pattern of the capacitor may include trenches and fins; it may also include pillars and trenches; and it may also include vias and trenches. The protrusions in this application may be at least one of pillars, fins, and vias.

[0157] In addition, this application does not limit the specific shape of the protrusions (including the first protrusion 11, the second protrusion 12 and the third protrusion 13; and other protrusions when they are present). For example, the cross-section of the protrusion can be a circle, a square, a triangle, a polygon or other irregular shape. Figure 3A for Figure 2A A top view schematic diagram of one type of semiconductor device, in Figure 3A In the example, the first protrusion 11, the second protrusion 12 and the third protrusion 13 are illustrated with a circular cross-section, and are not a limitation on the structural shape of the protrusion.

[0158] The first conductive via 31, the second conductive via 32, and the third conductive via 33 can all be located above the cell pattern area of ​​the capacitor. This allows the corresponding electrode layers to be led out from above the cell pattern area. The arrangement of these vias does not occupy the capacitor's area; that is, this arrangement increases the area ratio of the cell pattern area, improves the planar utilization of the capacitor, facilitates the placement of more protrusions, and increases the capacitance density. Especially when the number of electrode layers increases, leading out the corresponding electrode layers directly above the cell pattern area significantly improves the planar utilization and capacitance density of the capacitor.

[0159] In addition, the first conductive via 31, the second conductive via 32, and the third conductive via 33 extend their corresponding electrode layers directly above the unit pattern area of ​​the capacitor, which shortens the path of electrical signal transmission, thereby effectively reducing the delay of electrical signals during transmission and improving the high-frequency response speed of semiconductor devices. Since longer electrical signal transmission paths are often accompanied by larger parasitic inductance and capacitance, these parasitic effects can adversely affect high-frequency signals, such as causing signal attenuation and phase delay. Therefore, this application can also reduce these parasitic effects by shortening the electrical signal transmission path, thereby improving the high-frequency performance of the capacitor.

[0160] In one possible implementation, the semiconductor device may further include a circuit layer 60, which may be located on the side of the first conductive via 31 away from the capacitor. The first conductive via 31, the second conductive via 32, and the third conductive via 33 are respectively connected to the circuit layer 60. In this way, the first electrode layer 211, the second electrode layer 212, and the third electrode layer 213 can be led out through the circuit layer 60 connected to the first conductive via 31, the second conductive via 32, and the third conductive via 33, respectively.

[0161] For example, the circuit layer 60 can be formed using a standard damascus process.

[0162] Line layer 60 may include two layers, such as two redistribution layers (RDL). The arrangement of two redistribution layers allows for the redistribution of signal traces, enabling the routing of different power domains (e.g., VDD and VSS). The redistribution layer in direct contact with the filler material can employ a single damascene structure and process, while the redistribution layer above the single damascene can employ a double damascene structure and process.

[0163] In one possible implementation, the capacitors located on the first protrusion 11, the second protrusion 12, and the third protrusion 13 are arranged in sequence along the direction from the capacitor to the substrate 10, with the first electrode layer 211, the second electrode layer 212, and the third electrode layer 213.

[0164] That is, the first electrode layer 211 can be located on the side of the second electrode layer 212 away from the substrate 10. In other words, the first electrode layer 211 can be disposed above the second electrode layer 212 (for example, the first electrode layer 211 can be the top electrode layer of a capacitor).

[0165] Figure 2B for Figure 2A Please refer to the enlarged view of point A in the middle. Figure 2A and Figure 2BAlong the first direction a, there is a first spacing B1 between the third conductive via 33 and the first electrode layer 211, and a second spacing B2 between the third conductive via 33 and the second electrode layer 212; the first direction a is perpendicular to the thickness direction of the substrate 10, and the first spacing B1 can be greater than the second spacing B2.

[0166] Figure 5 This is a second schematic diagram of the structure of the semiconductor device provided in the embodiments of this application. Figure 5 In the middle, the first spacing B1 (in Figure 5 The first spacing B1 (not shown) can also be greater than the second spacing B2 (in Figure 5 The second spacing B2 is not marked.

[0167] Along the first direction a, the third conductive via 33 and the first electrode layer 211 have a first spacing B1, meaning that along the first direction a, the sidewall of the third conductive via 33 and the sidewall of the first electrode layer 211 have a first spacing B1. The third conductive via 33 and the second electrode layer 212 have a second spacing B2, meaning that along the first direction a, the sidewall of the third conductive via 33 and the sidewall of the second electrode layer 212 have a first spacing B1, such as... Figure 2A and Figure 2B As shown.

[0168] The first spacing B1 is greater than the second spacing B2. In this way, during the fabrication of semiconductor devices, through holes can be opened first on the first electrode layer 211 and then on the second electrode layer 212. That is to say, the first electrode layer 211 and the second electrode layer 212 can be etched separately. The process of fabrication by layering through holes is relatively mature. This is conducive to forming devices with more stable performance and higher yield and reliability.

[0169] Please continue to refer to this. Figure 2A and Figure 2B In one possible implementation, the second conductive via 32 and the first electrode layer 211 may have a third spacing B3; the third spacing B3 may be equal to the second spacing B2.

[0170] That is, there can be a third spacing B3 between the sidewall of the second conductive via 32 and the sidewall of the first electrode layer 211 along the first direction a. The third spacing B3 can be equal to the second spacing B2. In this way, the etching of the first electrode layer 211 and the second electrode layer 212 can be formed by the same process or the same equipment, which helps to reduce the difficulty of semiconductor device fabrication.

[0171] The specific values ​​of the first spacing B1, the second spacing B2, and the third spacing B3 are not limited in this application and can be determined based on the enclosure requirements of the first electrode layer 211 and the second electrode layer 212, the enclosure requirements between the third conductive via 33 and the second electrode layer 212, and the enclosure requirements between the second conductive via 32 and the first electrode layer 211. Enclosure can refer to an enclosed area. For example, the enclosure of the first electrode layer 211 and the second electrode layer 212 refers to the area of ​​the second electrode layer 212 used to enclose the first electrode layer 211, or it can be considered as the area of ​​the second electrode layer 212 exposed from the first electrode layer 211, or in other words, the area of ​​the second electrode layer 212 not covered by the first electrode layer 211.

[0172] In some examples, when the capacitor further includes a fourth electrode layer 214 or more electrode layers, it should also have a fourth conductive via 34 or more conductive vias for leading out the corresponding electrode layers. In this case, the distance between the fourth conductive via 34 and the first electrode layer 211 can be greater than the distance between the fourth conductive via 34 and the second electrode layer 212, and the distance between the fourth conductive via 34 and the second electrode layer 212 can be greater than the distance between the fourth conductive via 34 and the third electrode layer 213. The same principle applies when the capacitor includes a fifth electrode layer or more electrode layers, and this application will not repeat the description. Figure 5 The case where the capacitor has a fourth plate layer 214 is shown.

[0173] In one possible implementation, the capacitors located on the first protrusion 11, the second protrusion 12, and the third protrusion 13 are arranged in sequence along the direction from the capacitor to the substrate 10, with a first electrode layer 211, a second electrode layer 212, and a third electrode layer 213. That is, the first electrode layer 211 may be located on the side of the second electrode layer 212 away from the substrate 10.

[0174] Figure 8 This is the third schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 11 This is the fourth schematic diagram of the semiconductor device provided in the embodiments of this application. Please refer to... Figure 8 and Figure 11 Along the first direction a, the third conductive via 33 and the first electrode layer 211 may have a first spacing B1. Figure 8 and Figure 11 (Not shown in the diagram), a second spacing B2 may be present between the third conductive via 33 and the second electrode layer 212. Figure 8 and Figure 11 (Not marked in the text) The first spacing B1 and the second spacing B2 can be equal.

[0175] In other words, in the semiconductor device of this application, in some examples the first spacing B1 may be greater than the second spacing B2; in some examples the first spacing B1 may also be equal to the second spacing B2.

[0176] When the first spacing B1 is equal to the second spacing B2, the first spacing B1 and the second spacing B2 can be formed simultaneously. That is, the first electrode layer 211 and the second electrode layer 212 can be etched simultaneously to form a hole on the capacitor exposing the third electrode layer 213 or the second dielectric layer 222. In this way, the second electrode layer 212 does not need to reserve an enclosure between itself and the first electrode layer 211. The simultaneous etching of the first electrode layer 211 and the second electrode layer 212 can save fabrication steps, which is beneficial to reducing fabrication processes and improving production efficiency. In addition, the fact that no enclosure needs to be reserved between different electrode layers can also save the area occupied by the enclosure on the capacitor, which can improve the area utilization of the capacitor, facilitate the layout of more protrusions, and improve the capacitance density of the capacitor. Furthermore, the fact that no enclosure needs to be reserved between different electrode layers can further shorten the transmission path of electrical signals, effectively reduce the delay of electrical signals during transmission, effectively improve the high-frequency response speed of semiconductor devices, and reduce the adverse effects of parasitic responses on high-frequency signals, thereby improving the high-frequency performance of the capacitor.

[0177] In one possible approach, please refer to Figure 8 and Figure 11 A third spacing B3 may also exist between the second conductive via 32 and the first electrode layer 211, wherein the first spacing B1, the second spacing B2, and the third spacing B3 are all equal. Figure 8 and Figure 11 In the diagram, the first spacing B1, the second spacing B2, and the third spacing B3 are not marked. Their positions can be found by referring to [reference needed]. Figure 2B As described above.

[0178] In other words, if the first spacing B1 and the second spacing B2 are equal, the third spacing B3 can also be equal to the first spacing B1 and the second spacing B2. In this way, the formation of the third spacing B3 can be carried out using the same process or the same processing equipment as the formation of the first spacing B1 and the second spacing B2, which helps to reduce the difficulty of semiconductor device fabrication.

[0179] In some examples, when the capacitor further includes a fourth electrode layer 214 or more electrode layers, it should also have a fourth conductive via 34 or more conductive vias for leading out the corresponding electrode layers. In this case, the distance between the fourth conductive via 34 and the first electrode layer 211 can be equal to the distance between the fourth conductive via 34 and the second electrode layer 212, and the distance between the fourth conductive via 34 and the second electrode layer 212 can be equal to the distance between the fourth conductive via 34 and the third electrode layer 213. The same principle applies when the capacitor includes a fifth electrode layer or more electrode layers, and this application will not repeat the description. Figure 8 The case with the fourth electrode layer 214 is shown.

[0180] Figure 3B for Figure 3A Please refer to the enlarged view of section B in the middle. Figure 2A , Figure 3A and Figure 3B As shown, in one possible implementation, the dimensions of the first protrusion 11 along the first direction a, the dimensions of the second protrusion 12 along the first direction a, and the dimensions of the third protrusion 13 along the first direction a can all be the same.

[0181] In other words, the dimensions of the first protrusion 11, the second protrusion 12, and the third protrusion 13 along the first direction a can all be equal. This makes the fabrication of each protrusion easier and improves the structural stability of the semiconductor device.

[0182] It should be understood that the dimensions of the first protrusion 11 along the first direction a, the second protrusion 12 along the first direction a, and the third protrusion 13 along the first direction a can all be the same. This can be applied to schemes where an enclosure needs to be reserved between different electrode layers (i.e., the first spacing B1 is greater than the second spacing B2), and also to schemes where no enclosure needs to be reserved between different electrode layers (i.e., the first spacing B1 is equal to the second spacing B2).

[0183] That is, when an enclosure needs to be reserved between different electrode layers (e.g., using...) Figure 5 (as shown in the structure), at this time, Figure 6 for Figure 5 A top view schematic diagram of one type of semiconductor device is shown below. Please refer to the reference. Figure 5 and Figure 6 The dimensions of the first protrusion 11 along the first direction a, the dimensions of the second protrusion 12 along the first direction a, and the dimensions of the third protrusion 13 along the first direction a can all be the same.

[0184] When no enclosure is required between different electrode layers (e.g., using...) Figure 8 (as shown in the structure), at this time, Figure 9 for Figure 8A top view schematic diagram of one type of semiconductor device is shown below. Please refer to the reference. Figure 8 and Figure 9 The dimensions of the first protrusion 11 along the first direction a, the dimensions of the second protrusion 12 along the first direction a, and the dimensions of the third protrusion 13 along the first direction a can all be the same.

[0185] When no enclosure is required between different electrode layers (e.g., using...) Figure 11 (as shown in the structure), at this time, Figure 12 for Figure 11 A top view schematic diagram of one type of semiconductor device is shown below. Please refer to the reference. Figure 11 and Figure 12 The dimensions of the first protrusion 11 along the first direction a, the dimensions of the second protrusion 12 along the first direction a, and the dimensions of the third protrusion 13 along the first direction a can all be the same.

[0186] Furthermore, when the base 10 also includes other protrusions (such as the fourth protrusion 14, the fifth protrusion, etc.), the dimensions of these other protrusions along the first direction a can also be equal to the dimensions of the first protrusion 11 along the first direction a. That is, when the base 10 also includes other protrusions (such as the fourth protrusion 14, the fifth protrusion, etc.), all protrusions can have the same dimensions along the first direction a. Figure 5 and Figure 6 This example illustrates the case where the base 10 also includes a fourth protrusion 14. Figure 6 As can be seen, the dimensions of the first protrusion 11, the second protrusion 12, the third protrusion 13, and the fourth protrusion 14 in the first direction a can all be equal.

[0187] Figure 4A for Figure 2A Another top view schematic diagram of a semiconductor device. Figure 4B for Figure 4A Please refer to the enlarged view of section C in the middle for reference. Figure 2A , Figure 4A and Figure 4B In one possible implementation, the dimension of the first protrusion 11 along the first direction a can be smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a can be smaller than the dimension of the third protrusion 13 along the first direction a.

[0188] For example, in a scheme where an enclosure needs to be reserved between different electrode layers, there is a first conductive via 31 above the first protrusion 11, a second conductive via 32 above the second protrusion 12, and a third conductive via 33 above the third protrusion 13. Since the third conductive via 33 needs to consider the enclosure between the first electrode layer 211 and the second electrode layer 212, the second electrode layer 212 and the third electrode layer 213, and the third electrode layer 213 and the third conductive via 33; and the second conductive via 32 needs to consider the enclosure between the first electrode layer 211 and the second conductive via 32, the size of the third protrusion 13 of the third conductive via 33 can be set larger than the size of the second protrusion 12 where the second conductive via 32 needs to be set, and the size of the second protrusion 12 of the second conductive via 32 can be set larger than the size of the first protrusion 11 where the first conductive via 31 needs to be set.

[0189] In other words, the dimensions of the first protrusion 11 along the first direction a, the second protrusion 12 along the first direction a, and the third protrusion 13 along the third direction can be set to be equal or unequal, such as... Figure 4A and Figure 4B When the dimensions of the first protrusion 11 along the first direction a, the second protrusion 12 along the first direction a, and the third protrusion 13 along the third direction are not equal, the dimension of the first protrusion 11 along the first direction a can be set to be smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a can be set to be smaller than the dimension of the third protrusion 13 along the first direction a, according to different enclosure requirements. In this way, the dimensions of the first protrusion 11, the second protrusion 12, and the third protrusion 13 can all be set as needed, and the number and density of protrusions per unit area can be increased, thereby improving the capacitance density of the capacitor.

[0190] Furthermore, the dimension of the first protrusion 11 along the first direction a is smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a is smaller than the dimension of the third protrusion 13 along the first direction a. This design is applicable to all solutions where an enclosure is required between electrode layers. For example, Figure 7 for Figure 5 Please refer to another top view schematic diagram of the semiconductor device. Figure 5 and Figure 7 The dimension of the first protrusion 11 along the first direction a is smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a is smaller than the dimension of the third protrusion 13 along the first direction a.

[0191] In one feasible way Figure 10 for Figure 8 Another top view of the semiconductor device is shown below. Please refer to the diagram. Figure 8 and Figure 10 The dimension of the first protrusion 11 along the first direction a can be smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a can be equal to the dimension of the third protrusion 13 along the first direction a.

[0192] For example, in a design where no enclosure is required between different electrode layers, a first conductive via 31 is located above the first protrusion 11, a second conductive via 32 is located above the second protrusion 12, and a third conductive via 33 is located above the third protrusion 13. Since there is a first distance B1 between the third conductive via 33 and the first electrode layer 211, a second distance B2 between the third conductive via 33 and the second electrode layer 212, and a third distance B3 between the second conductive via 32 and the first electrode layer 211, the third distance B3, the first distance B1, and the second distance B2 can all be equal. Therefore, the dimension of the first protrusion 11 along the first direction a can be set to be smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a can be set to be equal to the dimension of the third protrusion 13 along the first direction a.

[0193] The arrangement where the dimension of the first protrusion 11 along the first direction a can be smaller than the dimension of the second protrusion 12 along the first direction a, and the dimension of the second protrusion 12 along the first direction a can be equal to the dimension of the third protrusion 13 along the first direction a, is applicable to all designs where no pre-existing enclosure is required between different electrode layers. For example... Figure 13 for Figure 11 Another top view of the semiconductor device is shown below. Please refer to the diagram. Figure 11 and Figure 13 ,exist Figure 11 and Figure 13 The same dimensional requirements mentioned above also apply.

[0194] Figure 12 for Figure 11 A top view schematic diagram of one type of semiconductor device is shown below. Figures 11 to 13 As shown, in one possible implementation, the base 10 may also include a protrusion structure 15.

[0195] A protrusion structure 15 is provided between any two of the first protrusion 11, the second protrusion 12 and the third protrusion 13; a portion of the capacitor is located between the protrusion structure 15 and one of the protrusions, a portion of the capacitor is located between the protrusion structure 15 and another protrusion, and a portion of the capacitor is located on the protrusion structure 15.

[0196] That is, in addition to the first protrusion 11, the second protrusion 12, and the third protrusion 13, this application may also provide a protrusion structure 15. For example... Figure 11 As shown, a protrusion structure 15 may be present between the first protrusion 11 and the third protrusion 13, and a protrusion structure 15 may also be present between the third protrusion 13 and the second protrusion 12.

[0197] In feasible embodiments, a protrusion structure 15 can be provided between any two protrusions with corresponding conductive vias on their upper surfaces.

[0198] A portion of the capacitor is located between the protruding structure 15 and one of the protrusions, a portion of the capacitor is located on the protruding structure 15, and a portion of the capacitor is located between the protruding structure 15 and another protrusion. That is, a portion of the capacitor can be disposed above the protruding structure 15, a portion of the capacitor can also be disposed on the sidewall of the protruding structure 15 near one of the protrusions, and a portion of the capacitor can be disposed on the sidewall of the protruding structure 15 near the other protrusion. Alternatively, a portion of the capacitor can be located on the entire outer peripheral wall of the protruding structure 15.

[0199] This application provides a raised structure 15 that can be used to support the capacitor, allowing more of the capacitor to be embedded in the substrate 10. This allows for a larger area of ​​the capacitor's electrode layer, thereby further improving the capacitor's capacitance density.

[0200] Furthermore, in this embodiment, you can refer to Figure 11 As shown, conductive vias may not be provided above the protruding structure 15. Thus, the protrusions of the substrate 10 can include protrusions with conductive via positioning functions (i.e., the first protrusion 11, the second protrusion 12, and the third protrusion 13), or they can include the protruding structure 15 without conductive via positioning functions. That is, the protrusions of the substrate 10 can adopt a mixed-pillar design.

[0201] In this way, it is not necessary for all protrusions to have conductive via positioning function. The spacing of each conductive via can be designed specifically according to the product's requirements for bandwidth or high-frequency response.

[0202] Among them, the protrusions with conductive via positioning function can be designed to have a relatively larger size in the first direction a, depending on the requirements such as the enclosure between the electrode layer and the conductive via; the protrusions without conductive via positioning function can be designed to have a relatively smaller size in the first direction a. In this way, while meeting the product's requirements for device bandwidth or high-frequency response, the capacitance density can be further improved.

[0203] For example, such as Figure 11 and Figure 12As shown, the protrusion structure 15 between the first protrusion 11 and the third protrusion 13, and the protrusion structure 15 between the third protrusion 13 and the second protrusion 12, can be set to a relatively small size because they do not have the function of positioning conductive vias; while the first protrusion 11, the second protrusion 12 and the third protrusion 13 can be set to a relatively large size because they have the function of positioning conductive vias.

[0204] In one possible approach, please refer to Figure 11 and Figure 13 As shown, the dimension of the protrusion structure 15 along the first direction a can be less than or equal to the dimension of the first protrusion 11 along the first direction a; the dimension of the protrusion structure 15 along the first direction a can be less than the dimension of the second protrusion 12 along the first direction a; the dimension of the second protrusion 12 along the first direction a can be equal to the dimension of the third protrusion 13 along the first direction a.

[0205] That is, the dimension of the protrusion structure 15 along the first direction a can be less than or equal to the dimension of the first protrusion 11 along the first direction a, the dimension of the first protrusion 11 along the first direction a can be less than the dimension of the second protrusion 12 along the first direction a, and the dimensions of the second protrusion 12 and the third protrusion 13 along the first direction a can be equal. In this way, because the arrangement of the protrusion structure 15 can improve the capacitance density of the capacitor to a certain extent; and because the first protrusion 11, the second protrusion 12, the third protrusion 13 and the protrusion structure 15 without positioning function (i.e., the protrusion structure 15) adopt a smaller size, this application can improve the capacitance density of the capacitor and shorten the transmission path of the electrical signal to a certain extent, thereby improving the high-frequency characteristics of the device.

[0206] In one possible approach, please refer to Figures 5 to 13 The capacitor may also include a fourth electrode layer 214 and a third dielectric layer 223; the third dielectric layer 223 is located between the third electrode layer 213 and the fourth electrode layer 214.

[0207] The substrate 10 may also include a fourth protrusion 14, and the semiconductor device may also include a fourth conductive via 34; the fourth conductive via 34 is located on the side of the capacitor away from the substrate 10, the fourth conductive via 34 is located on the fourth protrusion 14, and the fourth conductive via 34 is connected to the fourth electrode layer 214 located on the fourth protrusion 14.

[0208] That is, in addition to the capacitor including the first plate layer 211, the second plate layer 212 and the third plate layer 213, the capacitor may also include a fourth plate layer 214. By setting the fourth plate layer 214, the number of plate layers can be increased, thereby increasing the effective energy storage area inside the capacitor, which can store more charge and thus increase the capacity of the capacitor.

[0209] The fourth electrode layer 214 can be led out by setting the fourth conductive through hole 34, and the fourth protrusion 14 can be set to position and support the fourth conductive through hole 34.

[0210] In addition, the fourth conductive via 34 is disposed on the fourth protrusion 14, which can reduce the occupation of the effective area of ​​the capacitor by the fourth conductive via 34 and shorten the transmission path of the electrical signal, which is beneficial to maintaining better high-frequency characteristics while increasing the capacitor capacity.

[0211] When the capacitor also includes a fourth electrode layer 214 and a third dielectric layer 223, the content mentioned above that does not contradict it can still be applied, and this application will not repeat it here.

[0212] In other embodiments, the capacitor may also include a fifth electrode layer and a fourth dielectric layer, which can be derived from the foregoing content, and will not be listed in detail in this application.

[0213] On the other hand, this application also provides a method for fabricating a semiconductor device. Figure 14 For one of the semiconductor device fabrication process flowcharts provided in the embodiments of this application, please refer to... Figure 14 The method for fabricating the semiconductor device may include steps S100-S300.

[0214] S100. A first groove and a second groove are formed in the base 10. The first groove and the second groove are arranged at intervals along a direction parallel to the surface of the base 10 to form a first protrusion 11, a second protrusion 12 and a third protrusion 13.

[0215] After creating a first groove and a second groove spaced apart within the base 10, a first protrusion 11, a second protrusion 12, and a third protrusion 13 are obtained. The first protrusion 11, the second protrusion 12, and the third protrusion 13 are spaced apart in pairs. For example, the first protrusion 11 may be located between the second protrusion 12 and the third protrusion 13; or the second protrusion 12 may be located between the first protrusion 11 and the third protrusion 13; or the third protrusion 13 may be located between the first protrusion 11 and the second protrusion 12.

[0216] The radial dimensions (i.e., the dimensions along the first direction a mentioned above) of the first protrusion 11 and the second protrusion 12 may be equal or unequal, and this application does not impose any specific restrictions here.

[0217] In addition to the first protrusion 11, the second protrusion 12 and the third protrusion 13, more protrusions such as the fourth protrusion 14 may be provided in the base 10.

[0218] The number of the first protrusion 11, the second protrusion 12, and the third protrusion 13 is not limited. When there are multiple first protrusions 11, multiple second protrusions 12, and multiple third protrusions 13, the arrangement of the multiple first protrusions 11, multiple second protrusions 12, and multiple third protrusions 13 can be set as needed, and this application does not impose specific restrictions.

[0219] Furthermore, this application does not limit the specific method of forming the protrusions; a high aspect ratio etching process, such as dual-layer transfer hard mask etching (DTC HM), can be used. For example, the substrate 10 can be etched to form multiple grooves on the substrate 10, with protrusions formed between adjacent grooves. The multiple grooves can be interconnected.

[0220] S200, a capacitor is formed in the first groove and the second groove, and on the first protrusion 11, the second protrusion 12 and the third protrusion 13. The capacitor includes a first electrode layer 211, a second electrode layer 212, a third electrode layer 213, a first dielectric layer 221 located between the first electrode layer 211 and the second electrode layer 212, and a second dielectric layer 222 located between the second electrode layer 212 and the third electrode layer 213.

[0221] The layer thicknesses of the first electrode layer 211, the second electrode layer 212, the third electrode layer 213, the first dielectric layer 221, and the second dielectric layer 222 can be determined based on factors such as the size of the groove on the substrate 10 and the capacitance requirements of the capacitor, and this application does not impose any restrictions.

[0222] Furthermore, in step S200, a dielectric layer 224 can be formed on the side of the top electrode layer of the capacitor that is away from the substrate 10. In this way, the dielectric layer 224 can protect the top electrode layer and prevent oxidation or other phenomena from occurring in the top electrode layer during subsequent etching processes.

[0223] S300. A conductive via is formed on the side of the capacitor away from the substrate 10. The conductive via includes a first conductive via 31, a second conductive via 32, and a third conductive via 33. The first conductive via 31 is located on the first protrusion 11 and is connected to the first electrode layer 211 located on the first protrusion 11. The second conductive via 32 is located on the second protrusion 12 and is connected to the second electrode layer 212 located on the second protrusion 12. The third conductive via 33 is located on the third protrusion 13 and is connected to the third electrode layer 213 located on the third protrusion 13.

[0224] This application allows the first electrode layer 211 to be led out through the first conductive via 31, the second electrode layer 212 to be led out through the second conductive via 32, and the third electrode layer 213 to be led out through the third conductive via 33 by forming a conductive via on the side of the capacitor away from the substrate 10.

[0225] Since the first conductive via 31 is disposed on the first protrusion 11, the second conductive via 32 is disposed on the second protrusion 12, and the third conductive via 33 is disposed on the third protrusion 13, the first conductive via 31, the second conductive via 32, and the third conductive via 33 can all be located directly above the cell pattern area of ​​the capacitor. The cell pattern area of ​​the capacitor refers to the area in the capacitor where protrusions and grooves are arranged.

[0226] A first conductive through-hole 31 is disposed on a first protrusion 11, a second conductive through-hole 32 is disposed on a second protrusion 12, and a third conductive through-hole 33 is disposed on a third protrusion 13. On the one hand, the conductive through-holes can be positioned according to the corresponding protrusions during formation, facilitating rapid positioning of the conductive through-holes; on the other hand, the first protrusion 11 can be used to support the first conductive through-hole 31, the second protrusion 12 can be used to support the second conductive through-hole 32, and the third protrusion 13 can be used to support the third conductive through-hole 33.

[0227] The first conductive via 31, the second conductive via 32, and the third conductive via 33 of this application can all be located directly above the cell pattern area of ​​the capacitor. This arrangement can increase the area ratio of the cell pattern area of ​​the capacitor, improve the planar utilization of the capacitor, facilitate the layout of more protrusions in the capacitor, and increase the capacitance density of the capacitor. It can also shorten the path of electrical signal transmission, thereby effectively reducing the delay of electrical signals during transmission and thus improving the high-frequency response speed of semiconductor devices. Simultaneously, since a longer electrical signal transmission path is often accompanied by larger parasitic inductance and capacitance, these parasitic effects can adversely affect high-frequency signals, such as causing signal attenuation and phase delay. Therefore, this application can also reduce these parasitic effects by shortening the electrical signal transmission path, thereby improving the high-frequency performance of the capacitor.

[0228] In one possible approach, fabricating a capacitor on the first protrusion 11, the second protrusion 12, and the third protrusion 13 may include the following steps: sequentially fabricating a third electrode layer 213, a second dielectric layer 222, a second electrode layer 212, a first dielectric layer 221, and a first electrode layer 211.

[0229] That is, the first electrode layer 211 of the capacitor can be located on the side of the second electrode layer 212 away from the substrate 10. Alternatively, the first electrode layer 211 can be the top electrode layer of the capacitor.

[0230] Figure 15A For the second flowchart of the semiconductor device fabrication process provided in the embodiments of this application, please refer to... Figure 15AIn one possible implementation, before step S300, which forms a conductive via on the side of the capacitor away from the substrate 10, the method for fabricating the semiconductor device may further include steps S410-S510.

[0231] That is, between step S200 and step S300, the preparation method may also include steps S410-S510.

[0232] S410. A lead-out hole is formed on the capacitor. The lead-out hole may include a first lead-out hole 231 and a second lead-out hole 232. The first lead-out hole 231 exposes the first dielectric layer 221, and the second lead-out hole 232 exposes the second dielectric layer 222. The first lead-out hole 231 is located on the second protrusion 12, and the second lead-out hole 232 is located on the third protrusion 13.

[0233] In step S410, a lead-out hole is formed on the side of the capacitor away from the substrate 10. The lead-out hole includes a first lead-out hole 231 and a second lead-out hole 232.

[0234] In this implementation, the first lead-out hole 231 can expose the first dielectric layer 221, and the second lead-out hole 232 can expose the second dielectric layer 222.

[0235] S510. A dielectric layer 50 is formed on the capacitor, and the dielectric layer 50 fills the first lead-out hole 231 and the second lead-out hole 232.

[0236] The dielectric layer 50 can be a composite thin film layer, such as a stack of oxide layer (OX), silicon nitride layer (SiN) and oxide layer (OX) as the dielectric layer 50.

[0237] That is, a dielectric layer 50 is formed on the entire surface above the capacitor, and a portion of the dielectric layer 50 can fill the first lead-out hole 231 and the second lead-out hole 232.

[0238] Furthermore, since a dielectric layer 50 is formed on the capacitor, and since the capacitor has a first lead-out hole 231 and a second lead-out hole 232, there is a height difference on the side of the capacitor facing away from the substrate 10. Therefore, after the dielectric layer 50 is formed on the capacitor, the side of the dielectric layer 50 facing away from the substrate 10 can be planarized, for example, by using a chemical mechanical polishing (CMP) process to planarize the side of the dielectric layer 50 facing away from the substrate 10.

[0239] Furthermore, when the semiconductor device fabrication method of this application further includes steps S410-S510, the aforementioned step S300, forming a conductive via on the side of the capacitor away from the substrate 10, can be achieved by the following steps:

[0240] Step 1: Form a first contact hole, a second contact hole, and a third contact hole on the dielectric layer 50. The first contact hole exposes the first electrode layer 211, the second contact hole exposes the second electrode layer 212, and the third contact hole exposes the third electrode layer 213. The second contact hole is located inside the first lead-out hole 231 and its radial dimension is smaller than that of the first lead-out hole 231. The third contact hole is located inside the second lead-out hole 232 and its radial dimension is smaller than that of the second lead-out hole 232.

[0241] Step 2: Fill the first contact hole, the second contact hole and the third contact hole with metal respectively to form the first conductive through hole 31, the second conductive through hole 32 and the third conductive through hole 33.

[0242] Since the first lead-out hole 231 formed in step S410 exposes the first dielectric layer 221, and the second lead-out hole 232 exposes the second dielectric layer 222, in step 1, when forming the second contact hole and the third contact hole on the dielectric layer 50, the second contact hole needs to penetrate the first dielectric layer 221 to expose the second electrode layer 212. The third contact hole needs to penetrate the second dielectric layer 222 to expose the third electrode layer 213.

[0243] In some examples, if the first electrode layer 211 has a dielectric layer 224 on the side opposite to the first dielectric layer 221, the first contact hole needs to penetrate the dielectric layer 224 to expose the first electrode layer 211.

[0244] In step 2, filling the first contact hole, the second contact hole, and the third contact hole with metal material can form the first conductive through hole 31, the second conductive through hole 32, and the third conductive through hole 33, respectively.

[0245] In some examples, excess metal material above the dielectric layer 50 can be removed after the metal material is filled.

[0246] This application forms a first lead-out hole 231 and a second lead-out hole 232 through the above implementation method (i.e., the first lead-out hole 231 exposes the first dielectric layer 221, and the second lead-out hole 232 exposes the second dielectric layer 222). In this way, after the lead-out holes are formed and before the dielectric layer 50 is formed, the second electrode layer 212 can be protected by the first dielectric layer 221, and the third electrode layer 213 can be protected by the second dielectric layer 222. This can prevent oxidation of the second electrode layer 212 and the third electrode layer 213, thereby improving the electrical connection reliability of the subsequent second conductive via 32 and the second electrode layer 212, as well as the electrical connection reliability of the subsequent third conductive via 33 and the third electrode layer 213.

[0247] Furthermore, in this embodiment, when the first lead-out hole 231 exposes the first dielectric layer 221 and the second lead-out hole 232 exposes the second dielectric layer 222, the formation methods of the first lead-out hole 231 and the second lead-out hole 232 can include at least the following two methods:

[0248] In the first implementation, step S410, forming a lead-out hole on the capacitor, may include steps 1 and 2:

[0249] Step 3: Form a first lead-out hole 231 and a first through hole 241 spaced apart on the capacitor, with the first lead-out hole 231 and the first through hole 241 exposing the first dielectric layer 221 respectively.

[0250] Step 4: A second through hole 242 is formed on the first dielectric layer 221, penetrating the second electrode layer 212. The second through hole 242 is located inside the first through hole 241, and the radial dimension of the second through hole 242 is smaller than the radial dimension of the first through hole 241. The first through hole 241 and the second through hole 242 form a second lead-out hole 232, which exposes the second dielectric layer 222.

[0251] That is, when it is necessary to form the first lead-out hole 231 and the second lead-out hole 232, in the first implementation, the first lead-out hole 231 and the first through hole 241 can be formed in the corresponding area of ​​the capacitor first, and the first lead-out hole 231 and the first through hole 241 expose the first dielectric layer 221 respectively. At this time, the first lead-out hole 231 is formed; then, the second through hole 242 is formed in the first through hole 241, penetrating the first dielectric layer 221 and the second electrode layer 212. At this time, the second through hole 242 exposes the second dielectric layer 222, and the first through hole 241 and the second through hole 242 together form the second lead-out hole 232.

[0252] The first lead-out hole 231 and the second lead-out hole 232 are formed by using this method. The first lead-out hole 231 and the first through hole 241 can be opened on the first electrode layer 211 first, and then the second through hole 242 can be opened on the second electrode layer 212. That is to say, the first electrode layer 211 and the second electrode layer 212 can be etched separately. The process of fabrication by layering opening is relatively mature. This is conducive to forming devices with more stable performance and higher yield and reliability.

[0253] In the second implementation, step S410, forming a lead-out hole on the capacitor, may include steps 5 and 6:

[0254] Step 5: Form a first lead-out hole 231 on the capacitor, exposing the first dielectric layer 221 through the first lead-out hole 231;

[0255] Step 6: Form a second lead-out hole 232 on the capacitor, exposing the second dielectric layer 222.

[0256] In other words, unlike the first implementation, the second implementation forms each lead-out hole separately; that is, the first lead-out hole 231 and the second lead-out hole 232 are formed independently in sequence. Simply put, in the second implementation, one lead-out hole (e.g., the first lead-out hole 231) is formed first, and then another lead-out hole (e.g., the second lead-out hole 232) is formed. Using this fabrication method, compared to the first implementation, the enclosure between different electrode layers does not need to be reserved, which shortens the electrical signal transmission path and improves high-frequency response characteristics.

[0257] In addition, in this embodiment, the order of steps 5 and 6 is not limited; step 5 can be executed first, or step 6 can be executed first.

[0258] In other words, in this embodiment, when the lead-out hole includes a first lead-out hole 231 and a second lead-out hole 232, with the first lead-out hole 231 exposing the first dielectric layer 221 and the second lead-out hole 232 exposing the second dielectric layer 222, the formation of the lead-out hole on the capacitor can be achieved by steps 3 and 4, or by steps 5 and 6. This application does not impose any specific limitations.

[0259] In some examples, Figure 15B The third flowchart illustrating the fabrication process of the semiconductor device provided in this application embodiment is shown below. Figure 15B In another possible implementation, before forming a conductive via on the side of the capacitor away from the substrate 10 in step S300, the method for fabricating the semiconductor device may also include steps S420-S520.

[0260] That is, between steps S200 and S300, the preparation method may include steps S410-S510 as well as steps S420-S520.

[0261] S420. A lead-out hole is formed on the capacitor. The lead-out hole includes a first lead-out hole 231 and a second lead-out hole 232. The first lead-out hole 231 exposes the second electrode layer 212, and the second lead-out hole 232 exposes the third electrode layer 213. The first lead-out hole 231 is located on the second protrusion 12, and the second lead-out hole 232 is located on the third protrusion 13.

[0262] In step S420, a lead-out hole is formed on the side of the capacitor away from the substrate 10. The lead-out hole includes a first lead-out hole 231 and a second lead-out hole 232.

[0263] In this implementation, the first lead-out hole 231 exposes the second electrode layer 212, and the second lead-out hole 232 exposes the third electrode layer 213.

[0264] That is, compared with step S410, in step S420, the first lead-out hole 231 in step S410 exposes the first dielectric layer 221 (in step S420, the first lead-out hole 231 exposes the second electrode layer 212), and in step S410, the second lead-out hole 232 exposes the second dielectric layer 222 (in step S420, the second lead-out hole 232 exposes the third electrode layer 213).

[0265] In other words, in step S420, the corresponding electrode layer can be directly exposed when the lead-out hole is formed. This eliminates the need to etch the corresponding dielectric layer during subsequent conductive via formation, facilitating the formation of conductive vias.

[0266] S520, A dielectric layer 50 is formed on the capacitor, and the dielectric layer 50 fills the first lead-out hole 231 and the second lead-out hole 232.

[0267] That is, a dielectric layer 50 is formed over the entire surface of the capacitor, and a portion of the dielectric layer 50 can fill the first lead-out hole 231 and the second lead-out hole 232. Similarly,

[0268] Since the capacitor has a first lead-out hole 231 and a second lead-out hole 232, there is a height difference on the side of the capacitor away from the substrate 10. Therefore, after the dielectric layer 50 is formed on the capacitor, the side of the dielectric layer 50 away from the substrate 10 can be planarized, for example, by using a chemical mechanical polishing (CMP) process to planarize the side of the dielectric layer 50 away from the substrate 10.

[0269] Furthermore, when the semiconductor device fabrication method of this application further includes the above-described steps S420-S520, step S300, forming a conductive via on the side of the capacitor away from the substrate 10, can be achieved by the following steps:

[0270] Step 11: Form a first contact hole, a second contact hole, and a third contact hole on the dielectric layer 50. The first contact hole exposes the first electrode layer 211, the second contact hole exposes the second electrode layer 212, and the third contact hole exposes the third electrode layer 213. The second contact hole is located inside the first lead-out hole 231 and its radial dimension is smaller than that of the first lead-out hole 231. The third contact hole is located inside the second lead-out hole 232 and its radial dimension is smaller than that of the second lead-out hole 232.

[0271] Step 12: Fill the first contact hole, the second contact hole and the third contact hole with metal respectively to form the first conductive through hole 31, the second conductive through hole 32 and the third conductive through hole 33.

[0272] The dimensions of the first contact hole, the second contact hole, and the third contact hole are not limited in this application and can be determined as needed. After filling the first contact hole, the second contact hole, and the third contact hole with metal material, excess material on the side of the dielectric layer 50 facing away from the substrate 10 can be removed.

[0273] Furthermore, when the first lead-out hole 231 exposes the second electrode layer 212 and the second lead-out hole 232 exposes the third electrode layer 213, the formation methods of the first lead-out hole 231 and the second lead-out hole 232 can include at least the following two methods:

[0274] In the first possible implementation, step S420, forming a lead-out hole on the capacitor, may include steps 13 and 14:

[0275] Step 13: Form a first lead-out hole 231 and a first through hole 241 spaced apart on the capacitor, with the first lead-out hole 231 and the first through hole 241 exposing the second electrode layer 212 respectively.

[0276] Step 14: A second through hole 242 is formed on the second electrode layer 212, penetrating the second dielectric layer 222. The second through hole 242 is located inside the first through hole 241, and the radial dimension of the second through hole 242 is smaller than the radial dimension of the first through hole 241. The first through hole 241 and the second through hole 242 form a second lead-out hole 232, which exposes the third electrode layer 213.

[0277] That is, when it is necessary to form the first lead-out hole 231 and the second lead-out hole 232, in the first implementation, the first lead-out hole 231 and the first through hole 241 can be formed in the corresponding area of ​​the capacitor first, and the first lead-out hole 231 and the first through hole 241 expose the second electrode layer 212 respectively. At this time, the first lead-out hole 231 is formed; then, the second through hole 242 is formed in the first through hole 241, penetrating the second electrode layer 212 and the second dielectric layer 222. At this time, the second through hole 242 exposes the third electrode layer 213, and the first through hole 241 and the second through hole 242 together form the second lead-out hole 232.

[0278] The first lead-out hole 231 and the second lead-out hole 232 are formed by using this method. The first lead-out hole 231 and the first through hole 241 can be opened on the first electrode layer 211 and the first dielectric layer 221 first, and then the second through hole 242 can be opened on the second electrode layer 212 and the second dielectric layer 222. That is to say, the first electrode layer 211 and the second electrode layer 212 can be etched separately. The process of fabrication by layering opening is relatively mature. This is conducive to forming devices with more stable performance and higher yield and reliability.

[0279] In the second possible implementation, step S420, forming a lead-out hole on the capacitor, may include steps 15 and 16:

[0280] Step 15: Form a first lead-out hole 231 on the capacitor, exposing the second electrode layer 212 through the first lead-out hole 231.

[0281] Step 16: Form a second lead-out hole 232 on the capacitor, exposing the third electrode layer 213.

[0282] That is, each lead-out hole is formed separately in steps 15 and 16, meaning the first lead-out hole 231 and the second lead-out hole 232 are formed independently in sequence. In short, in the second implementation, one lead-out hole (e.g., the first lead-out hole 231) is formed first, and then another lead-out hole (e.g., the second lead-out hole 232) is formed. Compared to the first implementation, this fabrication method eliminates the need for pre-reserved enclosures between different electrode layers, shortening the electrical signal transmission path and improving high-frequency response characteristics.

[0283] In addition, in this embodiment, the order of steps 15 and 16 is not limited; step 15 can be executed first, or step 16 can be executed first.

[0284] In other words, in this embodiment, when the lead-out hole includes a first lead-out hole 231 and a second lead-out hole 232, with the first lead-out hole 231 exposing the second electrode layer 212 and the second lead-out hole 232 exposing the third electrode layer 213, the formation of the lead-out hole on the capacitor can be achieved by steps 13 and 14, or by steps 15 and 16. This application does not impose any specific limitations.

[0285] Figures 16 to 26C For preparation Figure 5 The semiconductor device in the diagram is a schematic diagram of the corresponding structure after each step is completed. Below, this application will combine... Figures 16 to 26C To illustrate the formation Figure 5 The fabrication method of the semiconductor device shown is illustrated by example.

[0286] Please refer to Figure 16 and Figure 17A Photoresist can be used as a mask for patterned etching, and then the process can be switched to High Aspect Ratio Mode (HM) for high aspect ratio deep silicon etching to obtain multiple bumps (e.g., first bump 11, second bump 12, third bump 13, and fourth bump 14) and grooves located between adjacent bumps. The arrangement of the multiple bumps can be referenced. Figure 17B or Figure 17C . Figure 17B for Figure 17AIn the first arrangement of multiple protrusions (i.e., the dimensions of the first protrusion 11, the second protrusion 12, the third protrusion 13, and the fourth protrusion 14 are equal along the first direction a), Figure 17C for Figure 17A A second arrangement of multiple protrusions (i.e., some protrusions of the first protrusion 11, second protrusion 12, third protrusion 13, and fourth protrusion 14 have unequal dimensions along the first direction a). The first protrusion 11, second protrusion 12, and third protrusion 13 can be selected as needed. Figure 17B The state shown can also be set to Figure 17C The state shown.

[0287] refer to Figure 18A , Figure 18B and Figure 18C An insulating layer 40, multiple electrode layers, and a dielectric layer are formed above each protrusion and within the groove. Figure 18A In the process, the electrode layer includes four layers, namely the first electrode layer 211, the second electrode layer 212, the third electrode layer 213 and the fourth electrode layer 214, and the dielectric layer includes four layers, namely the first dielectric layer 221, the second dielectric layer 222, the third dielectric layer 223 and the dielectric layer 224.

[0288] Secondly, multiple photolithography and etching processes are used (the number of etching steps depends on the number of electrode layers and dielectric layers) to expose different electrode layers, as follows: Figures 19A to 22C As shown.

[0289] See Figure 19A The dielectric layer 224 and the first electrode layer 211 can be etched at the locations where the second conductive via 32, the third conductive via 33 and the fourth conductive via 34 need to be formed, so as to form the first lead-out hole 231 at the location where the second conductive via 32 needs to be formed, and the first via 241 at the locations where the third conductive via 33 and the fourth conductive via 34 need to be formed respectively. Figure 19A This is a cross-sectional view of the structure after etching the dielectric layer 224 and the first electrode layer 211. Figure 19B for Figure 19A A top view of the first arrangement of multiple protrusions (i.e., the dimensions of multiple protrusions are equal along the first direction a). Figure 19C for Figure 19A The top view corresponding to the second arrangement of multiple protrusions (i.e., some of the protrusions have different dimensions along the first direction a).

[0290] See Figure 20AThe exposed first dielectric layer 221 and second electrode layer 212 are etched at the locations where the third conductive via 33 and the fourth conductive via 34 need to be formed, so as to form the second via 242 at the locations where the third conductive via 33 and the fourth conductive via 34 need to be formed respectively. The first via 241 and the second via 242 at the third conductive via 33 together form the second lead-out hole 232. Figure 20A This is a cross-sectional view of the structure after etching the first dielectric layer 221 and the second electrode layer 212. Figure 20B for Figure 20A A top view of the first arrangement of multiple protrusions (i.e., the dimensions of multiple protrusions are equal along the first direction a). Figure 20C for Figure 20A The top view corresponding to the second arrangement of multiple protrusions (i.e., some of the protrusions have different dimensions along the first direction a).

[0291] See Figure 21A At the location where the fourth conductive via 34 needs to be formed, the exposed second dielectric layer 222 and third electrode layer 213 are etched to form the third via 243 at the location where the fourth conductive via 34 needs to be formed. The first via 241, the second via 242 and the third conductive via 33 at the location where the fourth conductive via 34 needs to be formed together form the third lead-out via 233. Figure 21A This is a cross-sectional view of the structure after etching the second dielectric layer 222 and the third electrode layer 213. Figure 21B for Figure 21A A top view of the first arrangement of multiple protrusions (i.e., the dimensions of multiple protrusions are equal along the first direction a). Figure 21C for Figure 21A The top view corresponding to the second arrangement of multiple protrusions (i.e., some of the protrusions have different dimensions along the first direction a).

[0292] See Figure 22A After obtaining the first lead-out hole 231, the second lead-out hole 232, and the third lead-out hole 233, the third dielectric layer 223 and the fourth electrode layer 214 are etched. Figure 22A This is a cross-sectional view of the structure after etching the third dielectric layer 223 and the fourth electrode layer 214. Figure 22B for Figure 22A A top view of the first arrangement of multiple protrusions (i.e., the dimensions of multiple protrusions are equal along the first direction a). Figure 22C for Figure 22A The top view corresponding to the second arrangement of multiple protrusions (i.e., some of the protrusions have different dimensions along the first direction a).

[0293] In the etching process of multiple electrode layers and multiple dielectric layers, this preparation method is carried out by etching one electrode layer and dielectric layer, and then continuing to etch another electrode layer and dielectric layer below.

[0294] In this fabrication method, the etching of the first three electrode layers (i.e., the first electrode layer 211, the second electrode layer 212, and the third electrode layer 213) terminates at the corresponding dielectric layers of the capacitor. For example, when etching the first electrode layer 211, the etching termination layer is the first dielectric layer 221; when etching the second electrode layer 212, the etching termination layer is the second dielectric layer 222; and when etching the third electrode layer 213, the etching termination layer is the third dielectric layer 223. The etching of the last electrode layer (i.e., the fourth electrode layer 214) terminates at the insulating layer 40.

[0295] After etching the multilayer electrode layer and the multilayer dielectric layer, such as Figure 23A , Figure 23B and Figure 23C As shown, a dielectric layer 50 is deposited on the exposed surface of the multilayer electrode. This dielectric layer 50 can be a composite thin film, for example, a stacked layer of oxide (OX), silicon nitride (SiN), and oxide (OX). Because the surface of the device obtained after photolithography and etching of the multilayer electrode has a stepped morphology, the dielectric layer 50 grows conformally during deposition, resulting in an uneven surface. To facilitate photolithography of the contact holes, a chemical mechanical polishing (CMP) process can be used to level the surface, resulting in a surface with varying elevations. Figure 23A The state shown.

[0296] Subsequently, photolithography and etching are performed on the leveled surface to obtain the first, second, third, and fourth contact holes. Metal material is then filled into these contact holes, and a chemical mechanical polishing (CMP) process is used to level the surface. This results in the first conductive via 31, the second conductive via 32, the third conductive via 33, and the fourth conductive via 34, allowing the electrode layers of different power domains to be individually led out through the corresponding conductive vias. Figure 24A , Figure 24B and Figure 24C As shown.

[0297] Please refer to Figures 25A to 26C Finally, a circuit layer 60 is formed. For example, using a standard damascene process, two redistribution layers (RDLs) are fabricated to redistribute signal traces, thereby enabling the extraction of different power domains (e.g., VDD and VSS). The redistribution layer in contact with the conductive vias can employ a single damascene structure and process; the other redistribution layer can employ a double damascene structure and process. Figure 25A , Figure 25B and Figure 25C This is a schematic diagram of the structure after forming a single-layer redistribution layer. Figure 26A , Figure 26B and Figure 26C This is a schematic diagram of the structure after forming a double-layer rewiring layer.

[0298] Figures 27A to 34B For preparation Figure 8 The semiconductor device in the diagram is a schematic diagram of the corresponding structure after each step is completed. Below, this application will combine... Figures 27A to 34B To illustrate the formation Figure 8 The fabrication method of the semiconductor device shown is illustrated by example.

[0299] The steps prior to etching the multilayer electrode layer and the multilayer dielectric layer are the same in this fabrication method. That is, the etching of the substrate 10 and the formation of multiple protrusions, as well as the formation steps of the insulating layer 40, the multilayer electrode layer, and the multilayer dielectric layer, can be referred to in the preceding text. Figure 5 The example of the semiconductor device fabrication method shown will not be repeated here.

[0300] After forming an insulating layer 40, multiple electrode layers, and multiple dielectric layers above each protrusion and within the grooves, multiple photolithography and etching processes can be used to expose the different electrode layers. (Refer to...) Figures 27A to 30B As shown.

[0301] See Figure 27A The dielectric layer 224 and the first electrode layer 211 are etched at the locations where the second conductive via 32 needs to be formed to obtain the first lead-out via 231. Figure 27B This is a cross-sectional view of the structure after etching the dielectric layer 224 and the first electrode layer 211. Figure 27B for Figure 27A The top view corresponding to the first arrangement of multiple protrusions (i.e., the dimensions of the first protrusion 11, the second protrusion 12, the third protrusion 13, and the fourth protrusion 14 are equal along the first direction a). In this manufacturing method, the top views of each step corresponding to the second arrangement of multiple protrusions (i.e., some protrusions of the first protrusion 11, the second protrusion 12, the third protrusion 13, and the fourth protrusion 14 are not equal along the first direction a) can be obtained from... Figure 5 The method for fabricating the semiconductor device shown is derived from the corresponding accompanying drawings, therefore the drawings are not used.

[0302] See Figure 28A and Figure 28B At the location where the third conductive via 33 needs to be formed, the dielectric layer 224, the first electrode layer 211, the first dielectric layer 221 and the second electrode layer 212 are etched to form the second lead-out hole 232.

[0303] See Figure 29A and Figure 29B At the location where the fourth conductive via 34 needs to be formed, the dielectric layer 224, the first electrode layer 211, the first dielectric layer 221, the second electrode layer 212, the second dielectric layer 222, and the third electrode layer 213 are etched to form the second lead-out hole 232.

[0304] See Figure 30A and Figure 30B The dielectric layer 224, the first electrode layer 211, the first dielectric layer 221, the second electrode layer 212, the second dielectric layer 222, the third electrode layer 213, the third dielectric layer 223, and the fourth electrode layer 214 are etched at the locations where disconnection is required.

[0305] As can be seen, compared with the previous method, this preparation method can etch N-1 electrode layers and N-1 dielectric layers each time. Here, N is greater than or equal to 2, and N is the number of the electrode layers to be brought out from top to bottom. For example, when it is necessary to bring out the second electrode layer from top to bottom (i.e., the second electrode layer 212), one electrode layer and one dielectric layer can be etched at a time (i.e., etching dielectric layer 224 and the first electrode layer 211); when it is necessary to bring out the third electrode layer from top to bottom (i.e., the third electrode layer 213), two electrode layers and two dielectric layers can be etched at a time (i.e., etching the first electrode layer 211 and the second electrode layer 212, etching dielectric layer 224 and the first dielectric layer 221); when it is necessary to bring out the fourth electrode layer from top to bottom (i.e., the fourth electrode layer 214), three electrode layers and three dielectric layers can be etched at a time (i.e., etching the first electrode layer 211, the second electrode layer 212 and the third electrode layer 213, etching dielectric layer 224, the first dielectric layer 221 and the second dielectric layer 222).

[0306] This etching method eliminates the need for enclosure between electrode layers, which allows for a more compact design of adjacent protrusions, thereby increasing the proportion of deep trenches or protrusions per unit area.

[0307] In this fabrication method, the etching of the first three electrode layers (i.e., the first electrode layer 211, the second electrode layer 212, and the third electrode layer 213) terminates at the corresponding dielectric layers of the capacitor. The etching of the last electrode layer (i.e., the fourth electrode layer 214) terminates at the insulating layer 40.

[0308] After etching the multilayer electrode layer and the multilayer dielectric layer, such as Figure 31A and Figure 31BA dielectric layer 50 is deposited on the exposed surface of the multilayer electrode. This dielectric layer 50 can be a composite thin film, for example, a stacked layer of oxide (OX), silicon nitride (SiN), and oxide (OX). Similarly, since the surface of the device obtained after etching is uneven, the dielectric layer 50 undergoes conformal growth during deposition, resulting in an uneven surface as well. To facilitate photolithography of the contact holes, a chemical mechanical polishing (CMP) process can be used to level the surface, resulting in a surface that is smooth and conformal to the desired shape. Figure 31A The state shown.

[0309] Subsequently, photolithography and etching are performed on the leveled surface to obtain the first, second, third, and fourth contact holes. Metal material is then filled into these contact holes, and a chemical mechanical polishing (CMP) process is used to level the surface. This results in the first conductive via 31, the second conductive via 32, the third conductive via 33, and the fourth conductive via 34, allowing the electrode layers of different power domains to be individually led out through the corresponding conductive vias. Figure 32A and Figure 32B As shown.

[0310] Please refer to Figures 33A to 34B Finally, a circuit layer 60 is formed. For example, using a standard damascene process, two redistribution layers (RDLs) are fabricated to redistribute signal traces, thereby enabling the extraction of different power domains (e.g., VDD and VSS). The redistribution layer in contact with the conductive vias can employ a single damascene structure and process; the other redistribution layer can employ a double damascene structure and process. Figure 33A and Figure 33B This is a schematic diagram of the structure after forming a single-layer redistribution layer. Figure 34A and Figure 34B This is a schematic diagram of the structure after forming a double-layer rewiring layer.

[0311] Figures 35A to 44B For preparation Figure 11 The semiconductor device in the diagram is a schematic diagram of the corresponding structure after each step is completed. Below, this application will combine... Figures 35A to 44B To illustrate the formation Figure 11 The fabrication method of the semiconductor device shown is illustrated by example.

[0312] See Figure 35A and Figure 35BThe process involves using photoresist as a mask for patterned etching, then switching to High Aspect Ratio Mode (HM) for high aspect ratio deep silicon etching to create multiple bumps (such as first bump 11, second bump 12, third bump 13, and bump structure 15) and grooves between adjacent bumps. The arrangement of the multiple bumps can be referenced. Figure 35B . Figure 35B for Figure 35A The top view corresponding to the first arrangement of multiple protrusions (i.e., the dimensions of the first protrusion 11, the second protrusion 12, the third protrusion 13, and the fourth protrusion 14 are equal along the first direction a). In this manufacturing method, the top views of each step corresponding to the second arrangement of multiple protrusions (i.e., some protrusions of the first protrusion 11, the second protrusion 12, the third protrusion 13, and the fourth protrusion 14 are not equal along the first direction a) can be obtained from... Figure 5 The method for fabricating the semiconductor device shown is derived from the corresponding accompanying drawings, therefore the drawings are not used.

[0313] In this step, unlike the aforementioned preparation method example, a raised structure 15 needs to be formed when etching the substrate 10.

[0314] refer to Figure 36A and Figure 36B An insulating layer 40, multiple electrode layers, and multiple dielectric layers are formed above each protrusion and within the grooves. Figure 36A In the process, the electrode layer includes four layers, namely the first electrode layer 211, the second electrode layer 212, the third electrode layer 213 and the fourth electrode layer 214, and the dielectric layer includes four layers, namely the first dielectric layer 221, the second dielectric layer 222, the third dielectric layer 223 and the dielectric layer 224.

[0315] After forming an insulating layer 40, multiple electrode layers, and multiple dielectric layers above each protrusion and protrusion structure 15 and within the groove, multiple photolithography and etching processes can be used to expose the different electrode layers. (Refer to...) Figures 37A to 40B As shown. This implementation method is similar to the formation Figure 8 The fabrication method of the semiconductor device shown is the same as that described in the example, and is briefly described below:

[0316] See Figure 37A and Figure 37B At the location where the second conductive via 32 needs to be formed, the dielectric layer 224 and the first electrode layer 211 are etched to obtain the first lead-out hole 231.

[0317] See Figure 38A and Figure 38BAt the location where the third conductive via 33 needs to be formed, the dielectric layer 224, the first electrode layer 211, the first dielectric layer 221 and the second electrode layer 212 are etched to form the second lead-out hole 232.

[0318] See Figure 39A and Figure 39B At the location where the fourth conductive via 34 needs to be formed, the dielectric layer 224, the first electrode layer 211, the first dielectric layer 221, the second electrode layer 212, the second dielectric layer 222, and the third electrode layer 213 are etched to form the second lead-out hole 232.

[0319] See Figure 40A and Figure 40B The dielectric layer 224, the first electrode layer 211, the first dielectric layer 221, the second electrode layer 212, the second dielectric layer 222, the third electrode layer 213, the third dielectric layer 223, and the fourth electrode layer 214 are etched at the locations where disconnection is required.

[0320] After etching the multilayer electrode layer and the multilayer dielectric layer, such as Figure 41A and Figure 41B A dielectric layer 50 is deposited on the exposed surface of the multilayer electrode. The material of the dielectric layer 50 can be referred to above. Similarly, after depositing the dielectric layer 50, the surface can be leveled using a chemical mechanical polishing (CMP) process.

[0321] Subsequently, photolithography and etching are performed on the leveled surface to obtain the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole, which are then filled with metal material. A chemical mechanical polishing (CMP) process is then used to level the filled device surface to obtain the first conductive via 31, the second conductive via 32, the third conductive via 33, and the fourth conductive via 34. This allows the electrode layers of different power domains to be individually led out through the corresponding conductive vias, such as... Figure 42A and Figure 42B As shown.

[0322] See reference Figures 43A to 44B Finally, standard damascene technology can be used to form the circuit layer 60, for example, by fabricating two redistribution layers (RDL) to redistribute signal traces and thus enable the extraction of different power domains (e.g., VDD and VSS). The redistribution layer in contact with the conductive vias can employ a single damascene structure and process, see [link to documentation]. Figure 43A and Figure 43B The other wiring layer can employ a double damask structure and process, see... Figure 44A and Figure 44B .

[0323] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a first protrusion, a second protrusion, and a third protrusion, the first protrusion, the second protrusion, and the third protrusion being arranged at intervals in a first direction, the first direction being perpendicular to the thickness direction of the substrate; A capacitor, wherein a portion of the capacitor is located between two adjacent protrusions among the first protrusion, the second protrusion, and the third protrusion, and a portion of the capacitor is located on the first protrusion, the second protrusion, and the third protrusion, the capacitor comprising a first electrode layer, a second electrode layer, a third electrode layer, a first dielectric layer located between the first electrode layer and the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer; The first conductive via, the second conductive via, and the third conductive via are respectively located on the side of the capacitor away from the substrate; The first conductive via is located on the first protrusion, the second conductive via is located on the second protrusion, and the third conductive via is located on the third protrusion; The first conductive via is connected to the first electrode layer located on the first protrusion; The second conductive via is connected to the second electrode layer located on the second protrusion; The third conductive via is connected to the third electrode layer located on the third protrusion.

2. The semiconductor device according to claim 1, characterized in that, The capacitor located on the first protrusion, the second protrusion, and the third protrusion has a first electrode layer, a second electrode layer, and a third electrode layer arranged sequentially along the direction from the capacitor to the substrate; Along the first direction, the third conductive via has a first spacing with the first electrode layer, and the third conductive via has a second spacing with the second electrode layer; the first spacing is greater than the second spacing.

3. The semiconductor device according to claim 2, characterized in that, The second conductive via has a third spacing with respect to the first electrode layer; the third spacing is equal to the second spacing.

4. The semiconductor device according to claim 1, characterized in that, The capacitor located on the first protrusion, the second protrusion, and the third protrusion has a first electrode layer, a second electrode layer, and a third electrode layer arranged sequentially along the direction from the capacitor to the substrate; Along the first direction, the third conductive via has a first spacing with the first electrode layer, and the third conductive via has a second spacing with the second electrode layer; the first spacing and the second spacing are equal.

5. The semiconductor device according to claim 4, characterized in that, The second conductive via has a third spacing with respect to the first electrode layer, and the first spacing, the second spacing, and the third spacing are all equal.

6. The semiconductor device according to any one of claims 2-5, characterized in that, The dimensions of the first protrusion along the first direction, the second protrusion along the first direction, and the third protrusion along the first direction are all the same.

7. The semiconductor device according to claim 2 or 3, characterized in that, The dimension of the first protrusion along the first direction is smaller than the dimension of the second protrusion along the first direction, and the dimension of the second protrusion along the first direction is smaller than the dimension of the third protrusion along the first direction.

8. The semiconductor device according to claim 4 or 5, characterized in that, The dimension of the first protrusion along the first direction is smaller than the dimension of the second protrusion along the first direction, and the dimension of the second protrusion along the first direction is equal to the dimension of the third protrusion along the first direction.

9. The semiconductor device according to any one of claims 2-8, characterized in that, The substrate also includes a protruding structure; The protrusion structure is located between any two of the first protrusion, the second protrusion, and the third protrusion; a portion of the capacitor is located between the protrusion structure and one of the protrusions, a portion of the capacitor is located between the protrusion structure and the other protrusion, and a portion of the capacitor is located on the protrusion structure.

10. The semiconductor device according to claim 9, characterized in that, The dimension of the protrusion structure along the first direction is less than or equal to the dimension of the first protrusion along the first direction; The dimension of the protrusion structure along the first direction is smaller than the dimension of the second protrusion along the first direction; The dimension of the second protrusion along the first direction is equal to the dimension of the third protrusion along the first direction.

11. The semiconductor device according to any one of claims 1-10, characterized in that, The capacitor further includes a fourth electrode layer and a third dielectric layer; the third dielectric layer is located between the third electrode layer and the fourth electrode layer; The substrate further includes a fourth protrusion, and the semiconductor device further includes a fourth conductive via. The fourth conductive via is located on the side of the capacitor away from the substrate, the fourth conductive via is located on the fourth protrusion, and the fourth conductive via is connected to the fourth electrode layer located on the fourth protrusion.

12. The semiconductor device according to any one of claims 1-11, characterized in that, The first electrode layer is located on the side of the second electrode layer away from the substrate, and the side of the first electrode layer away from the first dielectric layer has a dielectric layer.

13. The semiconductor device according to any one of claims 1-12, characterized in that, The semiconductor device further includes an insulating layer located between the substrate and the capacitor.

14. A method for fabricating a semiconductor device, characterized in that, include: A first groove and a second groove are formed in the substrate, and the first groove and the second groove are arranged at intervals along a direction parallel to the surface of the substrate to form a first protrusion, a second protrusion and a third protrusion; A capacitor is formed in the first groove and the second groove, and on the first protrusion, the second protrusion and the third protrusion. The capacitor includes a first electrode layer, a second electrode layer, a third electrode layer, a first dielectric layer located between the first electrode layer and the second electrode layer, and a second dielectric layer located between the second electrode layer and the third electrode layer. A conductive via is formed on the side of the capacitor away from the substrate. The conductive via includes a first conductive via, a second conductive via, and a third conductive via. The first conductive via is located on the first protrusion and is connected to the first electrode layer located on the first protrusion. The second conductive via is located on the second protrusion and is connected to the second electrode layer located on the second protrusion. The third conductive via is located on the third protrusion, and the third conductive via is connected to the third electrode layer located on the third protrusion.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The capacitor is formed on the first protrusion, the second protrusion, and the third protrusion, comprising: The third electrode layer, the second dielectric layer, the second electrode layer, the first dielectric layer, and the first electrode layer are sequentially fabricated. Before forming a conductive via on the side of the capacitor facing away from the substrate, the method further includes; A lead-out hole is formed on the capacitor. The lead-out hole includes a first lead-out hole and a second lead-out hole. The first lead-out hole exposes the first dielectric layer, and the second lead-out hole exposes the second dielectric layer. The first lead-out hole is located on the second protrusion, and the second lead-out hole is located on the third protrusion. A dielectric layer is formed on the capacitor, and the dielectric layer fills the first lead-out hole and the second lead-out hole; A conductive via is formed on the side of the capacitor facing away from the substrate, including: A first contact hole, a second contact hole, and a third contact hole are formed on the dielectric layer. The first contact hole exposes the first electrode layer, the second contact hole exposes the second electrode layer, and the third contact hole exposes the third electrode layer. The second contact hole is located inside the first lead-out hole and its radial dimension is smaller than that of the first lead-out hole. The third contact hole is located inside the second lead-out hole and its radial dimension is smaller than that of the second lead-out hole. Metal is filled into the first contact hole, the second contact hole, and the third contact hole respectively to form the first conductive through hole, the second conductive through hole, and the third conductive through hole.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, Forming a lead-out hole on the capacitor includes: A first lead-out hole and a first through hole are formed on the capacitor at intervals, the first lead-out hole and the first through hole respectively exposing the first dielectric layer; A second through-hole is formed on the first dielectric layer, penetrating the second electrode layer. The second through-hole is located inside the first through-hole, and the radial dimension of the second through-hole is smaller than the radial dimension of the first through-hole. The first through-hole and the second through-hole form a second lead-out hole, which exposes the second dielectric layer.

17. The method for fabricating a semiconductor device according to claim 15, characterized in that, Forming a lead-out hole on the capacitor includes: A first lead-out hole is formed on the capacitor, the first lead-out hole exposing the first dielectric layer; A second lead-out hole is formed on the capacitor, the second lead-out hole exposing the second dielectric layer.

18. The method for fabricating a semiconductor device according to claim 14, characterized in that, The capacitor is formed on the first protrusion, the second protrusion, and the third protrusion, comprising: The third electrode layer, the second dielectric layer, the second electrode layer, the first dielectric layer, and the first electrode layer are sequentially fabricated. Before forming a conductive via on the side of the capacitor facing away from the substrate, the method further includes; A lead-out hole is formed on the capacitor. The lead-out hole includes a first lead-out hole and a second lead-out hole. The first lead-out hole exposes the second electrode layer, and the second lead-out hole exposes the third electrode layer. The first lead-out hole is located on the second protrusion, and the second lead-out hole is located on the third protrusion. A dielectric layer is formed on the capacitor, and the dielectric layer fills the first lead-out hole and the second lead-out hole; A conductive via is formed on the side of the capacitor facing away from the substrate, including: A first contact hole, a second contact hole, and a third contact hole are formed on the dielectric layer. The first contact hole exposes the first electrode layer, the second contact hole exposes the second electrode layer, and the third contact hole exposes the third electrode layer. The second contact hole is located inside the first lead-out hole and its radial dimension is smaller than that of the first lead-out hole. The third contact hole is located inside the second lead-out hole and its radial dimension is smaller than that of the second lead-out hole. Metal is filled into the first contact hole, the second contact hole, and the third contact hole respectively to form the first conductive through hole, the second conductive through hole, and the third conductive through hole.

19. The method for fabricating a semiconductor device according to claim 18, characterized in that, Forming a lead-out hole on the capacitor includes: A first lead-out hole and a first through hole are formed at intervals on the capacitor, and the first lead-out hole and the first through hole respectively expose the second electrode layer; A second through-hole is formed on the second electrode layer, penetrating the second dielectric layer. The second through-hole is located inside the first through-hole, and the radial dimension of the second through-hole is smaller than the radial dimension of the first through-hole. The first through-hole and the second through-hole form a second lead-out hole, which exposes the third electrode layer.

20. The method for fabricating a semiconductor device according to claim 18, characterized in that, Forming a lead-out hole on the capacitor includes: A first lead-out hole is formed on the capacitor, the first lead-out hole exposing the second electrode layer; A second lead-out hole is formed on the capacitor, the second lead-out hole exposing the third electrode layer.

21. A semiconductor packaging structure, characterized in that, include: substrate; The semiconductor device according to any one of claims 1-13, wherein the semiconductor device is disposed on the substrate.

22. The semiconductor packaging structure according to claim 21, characterized in that, The semiconductor device is an adapter board; The semiconductor packaging structure also includes multiple chips; The chip is mounted on the adapter board.

23. An electronic device, characterized in that, include: Circuit board; The semiconductor packaging structure as described in claim 21 or 22, wherein the semiconductor packaging structure is connected to the circuit board.

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