Display device and electronic device including the same

Abstract

A display device and an electronic device including the display device are disclosed. The display device includes: a substrate, a circuit layer comprising a plurality of transistors, and a first light-emitting diode (LED) and a second LED. The first LED overlaps with a first light-emitting region and includes a first pixel electrode, a first light-emitting layer, and a common electrode. The second LED overlaps with a second light-emitting region and includes a second pixel electrode, a second light-emitting layer, and a common electrode. The first pixel electrode includes a first lower metal layer, a first inorganic layer, a first hard mask layer, and a first upper metal layer. The second pixel electrode includes a second lower metal layer, a second inorganic layer, a second hard mask layer, a third inorganic layer, and a second upper metal layer. The first inorganic layer and the second inorganic layer have substantially the same thickness, and the first pixel electrode and the second pixel electrode have different thicknesses.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0197699, filed on December 26, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device, an electronic device, and a method for manufacturing the display device. More specifically, this disclosure relates to a display device, an electronic device, and a method for manufacturing the display device, wherein the display device includes a hard mask to achieve different resonant distances for each pixel by differentiating the thickness of the pixel electrodes, while preventing damage to the underlying metal layer during the etching process. Background Technology

[0004] Typically, display devices are manufactured through a multi-step process, which includes etching processes used to form thin-film patterns.

[0005] Research is underway on methods that utilize some components within the display device as masks instead of using external masks for patterning. Summary of the Invention

[0006] This disclosure provides a display device with improved reliability and improved device efficiency.

[0007] This disclosure also provides an electronic device with improved reliability and improved device efficiency.

[0008] Furthermore, this disclosure aims to provide a method for manufacturing a display device with improved reliability and device efficiency.

[0009] According to embodiments of this disclosure, a display device includes a substrate having a plurality of light-emitting regions defined therein. A circuit layer is disposed on the substrate. The circuit layer includes a plurality of transistors. A first light-emitting diode and a second light-emitting diode are disposed on the circuit layer. The first light-emitting diode overlaps with a first light-emitting region among the plurality of light-emitting regions and includes a first pixel electrode, a first light-emitting layer, and a common electrode. The second light-emitting diode overlaps with a second light-emitting region among the plurality of light-emitting regions and includes a second pixel electrode, a second light-emitting layer, and a common electrode. The first pixel electrode includes a first lower metal layer, a first inorganic layer, a first hard mask layer, and a first upper metal layer in a sequentially stacked order, and has a first contact hole defined in the first pixel electrode, the first contact hole penetrating the first inorganic layer and the first hard mask layer. The second pixel electrode includes a second lower metal layer, a second inorganic layer, a second hard mask layer, a third inorganic layer, and a second upper metal layer in a sequentially stacked order, and has a second contact hole defined in the second pixel electrode. The second contact hole penetrates the second inorganic layer, the second hard mask layer, and the third inorganic layer. The first inorganic layer and the second inorganic layer have substantially the same thickness in the vertical direction. The first pixel electrode and the second pixel electrode have different thicknesses in the vertical direction.

[0010] In an embodiment, the thickness of the second pixel electrode in the vertical direction may be greater than the thickness of the first pixel electrode in the vertical direction.

[0011] In an embodiment, the first hard mask layer and the second hard mask layer may have substantially the same thickness in the vertical direction.

[0012] In an embodiment, the first hard mask layer and the second hard mask layer may each have an etch selectivity that is different from the etch selectivity of the third inorganic layer.

[0013] In an embodiment, the second contact hole may include: a first sub-contact hole penetrating the second inorganic layer and the second hard mask layer; and a second sub-contact hole penetrating the third inorganic layer. The first contact hole and the first sub-contact hole may have substantially the same depth as each other.

[0014] According to an embodiment, the display device may further include a third light-emitting diode disposed on a circuit layer. The third light-emitting diode may overlap with a third light-emitting region among a plurality of light-emitting regions, and may include a third pixel electrode, a third light-emitting layer, and a common electrode. The third pixel electrode may include a third lower metal layer, a fourth inorganic layer, a third hard mask layer, a fifth inorganic layer, a sixth inorganic layer, and a third upper metal layer in a sequentially stacked order. The third pixel electrode may have a third contact hole penetrating the fourth inorganic layer, the third hard mask layer, the fifth inorganic layer, and the sixth inorganic layer. The fourth inorganic layer may have substantially the same thickness in the vertical direction as the first and second inorganic layers.

[0015] In an embodiment, the first hard mask layer, the second hard mask layer, and the third hard mask layer may have substantially the same thickness in the vertical direction.

[0016] In one embodiment, the second contact hole includes a first sub-contact hole penetrating the second inorganic layer and the second hard mask layer. The second sub-contact hole penetrates the third inorganic layer. The third contact hole may include: a third sub-contact hole penetrating the fourth inorganic layer and the third hard mask layer; and a fourth sub-contact hole penetrating the fifth inorganic layer and the sixth inorganic layer. The third sub-contact hole, the first contact hole, and the first sub-contact hole may have substantially the same depth as each other.

[0017] In this embodiment, a first lower metal layer may be spaced apart from a first contact hole, and a second lower metal layer may be spaced apart from a second contact hole. A first upper metal layer may be electrically connected to a corresponding transistor in a transistor via the first contact hole. A second upper metal layer may be electrically connected to a corresponding transistor in a transistor via the second contact hole.

[0018] According to an embodiment, the display device may further include a pixel defining layer disposed between the first pixel electrode and the second pixel electrode. The pixel defining layer may be in direct contact with the first inorganic layer and the second inorganic layer.

[0019] According to an embodiment, the first hard mask layer and the second hard mask layer may contain amorphous carbon (aC).

[0020] According to an embodiment, the third inorganic layer may comprise silicon oxide (SiO2). x ).

[0021] According to embodiments of this disclosure, a method for manufacturing a display device includes preparing a preliminary display panel by forming a circuit layer on a substrate. A plurality of lower metal layers are formed on the circuit layer and spaced apart from each other. An intermediate layer is formed by the following steps: forming a first intermediate inorganic layer and a first intermediate hard mask layer on a first lower metal layer among the plurality of lower metal layers; and forming a second intermediate inorganic layer, a second intermediate hard mask layer, and a third intermediate inorganic layer on a second lower metal layer among the plurality of lower metal layers. A first etching is performed to form a first upper contact hole penetrating the third intermediate inorganic layer. A second etching is performed to form a first lower contact hole penetrating the first intermediate hard mask layer and the first intermediate inorganic layer, and to form a second lower contact hole penetrating the second intermediate hard mask layer and the second intermediate inorganic layer and overlapping the first upper contact hole in a plan view. Upper metal layers are formed corresponding to the plurality of lower metal layers respectively. In the step of preparing the preliminary display panel, a circuit layer may be formed on the substrate. In the step of forming the lower metal layers, a plurality of lower metal layers spaced apart from each other may be formed on the circuit layer.

[0022] In this embodiment, during the step of forming the intermediate layer, a fourth intermediate inorganic layer, a third intermediate hard mask layer, a fifth intermediate inorganic layer, and a sixth intermediate inorganic layer may be further formed on the third lower metal layer within the lower metal layer. During the step of performing the first etching process, a second upper contact hole penetrating the sixth intermediate inorganic layer and a third upper contact hole penetrating the fifth intermediate inorganic layer may be further formed. During the step of performing the second etching process, a third lower contact hole penetrating the third intermediate hard mask layer may be further formed.

[0023] In an embodiment, the first to third intermediate hard mask layers may have an etch selectivity different from that of the third intermediate inorganic layer, and may contain amorphous carbon (aC).

[0024] In an embodiment, the third inorganic layer may comprise silicon oxide (SiO2). x ).

[0025] According to an embodiment of this disclosure, a display device includes a substrate. A circuit layer is disposed on the substrate. The circuit layer includes a plurality of transistors. A first light-emitting diode (LED) and a second LED are disposed on the circuit layer. The first LED includes a first pixel electrode, a first light-emitting layer, and a common electrode. The second LED includes a second pixel electrode, a second light-emitting layer, and a common electrode. The first pixel electrode includes, in a sequentially stacked order, a first lower metal layer, a first lower inorganic layer, a first upper inorganic layer, a first hard mask layer, and a first upper metal layer. A first lower contact hole is defined that penetrates the first lower inorganic layer and the first upper inorganic layer. A first upper contact hole is defined that penetrates the first hard mask layer. The first lower contact hole and the first upper contact hole overlap in a plan view. The second pixel electrode includes, in a sequentially stacked order, a second lower metal layer, a second lower inorganic layer, a second upper inorganic layer, a second hard mask layer, and a second upper metal layer. A second lower contact hole is defined to penetrate the second lower inorganic layer and the second upper inorganic layer. A second upper contact hole is defined that penetrates the second hard mask layer. The second lower contact hole and the second upper contact hole overlap in a plan view. The first lower inorganic layer and the second lower inorganic layer have substantially the same thickness in the vertical direction. The first hard mask layer and the second hard mask layer have substantially the same thickness in the vertical direction. The first upper inorganic layer and the second upper inorganic layer have different thicknesses in the vertical direction. The first pixel electrode and the second pixel electrode have different thicknesses in the vertical direction.

[0026] In an embodiment, the first hard mask layer and the second hard mask layer may each contain amorphous carbon (aC).

[0027] In this embodiment, the first upper inorganic layer and the second upper inorganic layer may each comprise silicon oxide (SiO2). x ).

[0028] In an embodiment, the first hard mask layer and the second hard mask layer may have substantially the same thickness in the vertical direction.

[0029] In an embodiment, the first hard mask layer and the second hard mask layer may have substantially the same etch selectivity as each other. The first hard mask layer may have an etch selectivity different from that of each of the first upper inorganic layer and the second upper inorganic layer.

[0030] In an embodiment, the first lower contact hole and the second lower contact hole may have substantially the same depth, while the first upper contact hole and the second upper contact hole may have different depths.

[0031] According to embodiments of this disclosure, an electronic device includes a processor for controlling a display device. A memory stores data required for operating the display device or the processor. A power conversion module generates or supplies power. The display device includes a substrate having a plurality of light-emitting regions defined therein. A circuit layer is disposed on the substrate. The circuit layer includes a plurality of transistors. A first light-emitting diode and a second light-emitting diode are disposed on the circuit layer. The first light-emitting diode overlaps with a first light-emitting region among the plurality of light-emitting regions and includes a first pixel electrode, a first light-emitting layer, and a common electrode. The second light-emitting diode overlaps with a second light-emitting region among the plurality of light-emitting regions and includes a second pixel electrode, a second light-emitting layer, and a common electrode. The first pixel electrode includes a first lower metal layer, a first inorganic layer, a first hard mask layer, and a first upper metal layer in a sequentially stacked order, and has a first contact hole defined in the first pixel electrode. The first contact hole penetrates the first inorganic layer and the first hard mask layer. The second pixel electrode includes a second lower metal layer, a second inorganic layer, a second hard mask layer, a third inorganic layer, and a second upper metal layer in a sequentially stacked order, and has a second contact hole defined in the second pixel electrode. The second contact hole penetrates the second inorganic layer, the second hard mask layer, and the third inorganic layer. The first inorganic layer and the second inorganic layer have substantially the same thickness in the vertical direction. The first pixel electrode and the second pixel electrode have different thicknesses in the vertical direction.

[0032] According to embodiments of this disclosure, a display device, an electronic device, and a method for manufacturing a display device with improved reliability and improved device efficiency can be provided by forming contact holes of the same depth for each pixel during the etching process and varying the thickness of the pixel electrode for each pixel. Attached Figure Description

[0033] These and / or other features will become apparent and more readily understood from the following description of non-limiting embodiments taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1This is a schematic diagram illustrating a plan view of a display device according to an embodiment of the present disclosure;

[0035] Figure 2 This is an exemplary map showing a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0036] Figure 3 According to embodiments of this disclosure Figure 2 A magnified view of area AA in the image;

[0037] Figure 4 This is a cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure;

[0038] Figure 5 This is a cross-sectional view illustrating another portion of a display device according to an embodiment of the present disclosure;

[0039] Figure 6 This is a cross-sectional view illustrating another portion of a display device according to an embodiment of the present disclosure;

[0040] Figure 7 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment of the present disclosure;

[0041] Figure 8 This is a flowchart illustrating specific steps of a method for manufacturing a display device according to an embodiment of the present disclosure;

[0042] Figures 9A to 9N This is a schematic diagram illustrating the steps of a method for manufacturing a display device according to an embodiment of the present disclosure;

[0043] Figure 10 A block diagram of an electronic device according to embodiments of the present disclosure; and

[0044] Figures 11 to 13 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0045] Reference will now be made in detail to certain non-limiting embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals always refer to like elements. Embodiments of this disclosure may have various forms and combinations, and this disclosure should in no way be construed as limited to the described embodiments. Rather, embodiments of this disclosure should be construed as encompassing all forms, combinations, equivalents, and alternatives covered by the technical concept and scope of this disclosure. Accordingly, the features of this disclosure are explained below by referring only to the accompanying drawings and describing non-limiting embodiments.

[0046] When an element (or area, layer, section, etc.) is described as being “set on,” “placed on,” “arranged on,” “connected to,” or “coupled to” another element, it should be interpreted as being directly set on, placed on, arranged on, directly connected to, or coupled to that other element, but there may also be another element in between. On the other hand, if an element is described as being “directly set on,” “directly placed on,” “directly arranged on,” “directly connected to,” or “directly coupled to” another element, it should be interpreted as having no other element in between.

[0047] Identical or similar reference numerals refer to identical or similar elements. Furthermore, in the drawings, the thickness, scale, and dimensions of elements may not be precise and may be exaggerated to effectively interpret the technical features associated with these elements. Thus, this disclosure should not be limited to the thicknesses, scales, dimensions, etc., illustrated in the drawings.

[0048] Various elements may be described using terms such as “first” and “second”, but the elements thereon should not be limited to these terms. The terms may be used only to distinguish one element from others. For example, a first element may be named a second element and vice versa, without departing from the scope of the claims of this disclosure. Unless expressly used otherwise, any singular form may include the meaning of the plural form. The term “and / or” shall include a combination of or any one of the listed items.

[0049] Furthermore, relative terms such as “below,” “under,” “below,” “bottom,” “top,” “above,” “above,” “upper,” and “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It should be understood that these relative terms are intended to cover different orientations of the device, in addition to those depicted in the drawings. For example, if a device in one of the figures is flipped, an element described as being “below” to another element will subsequently be oriented “above” that other element. Thus, depending on the specific orientation of the figure, the term “below” can encompass both “below” and “upper” orientations. Similarly, if a device in one of the figures is flipped, an element described as being “below” or “below” to another element will subsequently be oriented “above” that other element. Thus, the terms “below” or “below” can encompass both “upper” and “lower” orientations.

[0050] Expressions such as “comprising” or “including” are intended to specify the presence of a feature, quantity, step, operation, element, part or combination thereof, and should not be construed as excluding any possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, parts or combinations thereof.

[0051] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as they would normally be understood by one of ordinary skill in the art to which this disclosure pertains. Any term defined in a general dictionary shall be interpreted as having the same meaning in the context of the relevant art, and shall not be construed as having an idealized or overly formal meaning unless expressly defined otherwise.

[0052] In this specification, the described process sequence can be performed in different orders when a particular process sequence can be implemented differently. For example, two processes described in sequence can be performed substantially simultaneously, or the order in which they are described can be reversed.

[0053] This disclosure relates to a display device having pixel electrodes, each pixel electrode including a contact hole defined therein. By varying the number of inorganic layers included in the stacked structure of each pixel electrode, the pixel electrodes in different light-emitting areas can have different thicknesses in the vertical direction. The thickness of the pixel electrodes can be varied so that light emitted by the corresponding light-emitting diodes can resonate, thereby improving the efficiency of the display device.

[0054] Furthermore, in the method of manufacturing a display device, contact holes of equal depth can be formed for each of the multiple pixel electrodes by arranging a single hard mask layer on an inorganic layer having the same thickness as each other. This process prevents damage to the underlying metal layer and improves the reliability of the display device.

[0055] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment of the present disclosure. Reference Figure 1 The display device DD may have a display area DA and a non-display area NDA defined therein. In an embodiment, the non-display area NDA may at least partially surround the display area DA (e.g., in a plan view). The display device DD may include a substrate SS, and the display area DA and the non-display area NDA may be defined as regions of the substrate SS. The substrate SS may have a plurality of light-emitting areas defined therein.

[0056] The display area DA is an area for displaying an image, and multiple pixels can be arranged within it. In embodiments, the display area DA can (e.g., in a plan view) have various shapes such as circles, ellipses, polygons, or other specific geometries.

[0057] Multiple pixels (PX) can be disposed in the display area (DA) of the substrate (SS). Each pixel (PX) includes a light-emitting diode (LED), such as an organic light-emitting diode (OLED), which overlaps with the light-emitting area. Each pixel (PX) may include a transistor configured to control the LED. A single pixel (PX) may include one or more transistors.

[0058] In the non-display area NDA of the substrate SS, various wirings configured to transmit electrical signals applied to the display area DA can be arranged. In an embodiment, a transistor can be disposed in the non-display area NDA, and the transistor can be part of a circuit unit configured to control the electrical signals applied to the display area DA.

[0059] In the following description, an organic light-emitting display device will be used as an example of a display device DD according to an embodiment of the present disclosure. However, the display device DD of the present disclosure is not limited thereto. In some embodiments, the display device DD may be an inorganic light-emitting display device or a quantum dot light-emitting display device. For example, the light-emitting layer of the light-emitting diode provided in the display device DD may include organic materials, inorganic materials, quantum dots, a combination of organic materials and quantum dots, or a combination of inorganic materials and quantum dots.

[0060] Figure 2 This is a cross-sectional view illustrating a display device according to an embodiment of the present disclosure. Figure 3 yes Figure 2 A magnified view of area AA in the image. (See reference) Figure 2 and Figure 3 According to embodiments of the present disclosure, the display device DD may include a substrate SS, a circuit layer CL, a pixel defining layer PDL, an encapsulation layer EN, and a first light-emitting diode ED1, a second light-emitting diode ED2, and a third light-emitting diode ED3 that overlap with the first light-emitting area to the third light-emitting area, respectively.

[0061] The substrate SS can be made of various materials such as glass, metal, or plastic. In embodiments, the substrate SS can be a flexible substrate. For example, the substrate SS may include polymer resins such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0062] The circuit layer CL can be disposed on the substrate SS (e.g., directly disposed on the third-party DR3), and can include a buffer layer BF, a transistor TFT, a gate insulating layer GI, an interlayer insulating layer LI, and a planarization layer PL.

[0063] A transistor TFT may include an active layer AL, a gate electrode GE, a source electrode SE, and a drain electrode DE. A gate insulating layer GI may be disposed between the gate electrode GE and the active layer AL (e.g., on a third-direction DR3) to provide electrical insulation between the gate electrode GE and the active layer AL.

[0064] The active layer AL can be disposed on the buffer layer BF (e.g., directly disposed on the third-direction DR3) and can be formed of inorganic semiconductors (such as amorphous silicon or polycrystalline silicon) or organic semiconductors. In some embodiments, the active layer AL can be formed of oxide semiconductors (e.g., oxides of elements selected from Groups 12, 13, and 14 of the periodic table, including zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), or hafnium (Hf)), or combinations of oxides of these elements).

[0065] The gate insulating layer GI can be disposed on the buffer layer BF (e.g., directly disposed thereon) and cover the active layer AL. The gate electrode GE can be disposed on the gate insulating layer GI (e.g., directly disposed thereon on the third-direction DR3).

[0066] The interlayer insulating layer LI can be disposed on the gate insulating layer GI and the gate electrode GE (e.g., directly disposed on both), and cover the gate electrode GE. In an embodiment, the source electrode SE and the drain electrode DE can be formed on the interlayer insulating layer LI and can be in direct contact with the active layer AL through contact holes.

[0067] The structure of the transistor TFT is not limited to the described example and can take various configurations. For example, in some embodiments, the transistor TFT may have a top gate structure or a bottom gate structure with the gate electrode GE disposed below the active layer AL.

[0068] The planarization layer PL can be disposed on the source electrode SE, drain electrode DE, and interlayer insulating layer LI (e.g., directly on these three). The first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 can be disposed on the planarization layer PL. The planarization layer PL can provide a relatively flat upper surface, allowing the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 to be formed relatively flat. The planarization layer PL can be formed as a single layer or multiple layers from organic or inorganic materials.

[0069] In embodiments, the planarization layer PL may include materials such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene (PS), or polymer derivatives having phenolic groups, as well as acrylic, imide, aryl ether, amide, fluorine, p-xylene, vinyl alcohol polymers, and blends thereof. Alternatively, the planarization layer PL may include silicon oxide (SiO2), silicon nitride (SiN), etc. x ), silicon oxynitride (SiO) x N y Materials include aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). After forming the planarization layer PL, chemical and / or mechanical polishing can be performed to achieve a relatively flat upper surface.

[0070] In an embodiment, the planarization layer PL may include an opening that exposes the source electrode SE or drain electrode DE of the transistor TFT, and the pixel electrodes PE1, PE2, PE3 may be electrically connected to the transistor TFT by directly contacting the source electrode SE or drain electrode DE through the opening.

[0071] The buffer layer BF included in the display device DD according to an embodiment may be disposed between the active layer AL and the substrate SS (e.g., on the third-direction DR3). The buffer layer BF may be configured to prevent the diffusion of impurity ions from the upper surface of the substrate SS, inhibit the permeation of moisture or external air, and planarize the surface. In some embodiments, the buffer layer BF may be formed of inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, titanium oxide, or titanium nitride) or organic materials (e.g., polyimide, polyester, or acrylic acid), or a laminate of the above materials.

[0072] The first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 can be disposed on the planarization layer PL and can overlap with the first to third light-emitting areas, respectively. Each of the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 may include a corresponding pixel electrode PE1, PE2, PE3, a corresponding light-emitting layer EML1, EML2, EML3, and a common electrode CE.

[0073] In embodiments, the light-emitting layers EML1, EML2, and EML3 may comprise organic materials containing fluorescent or phosphorescent substances for emitting red, green, blue, or white light. The light-emitting layers EML1, EML2, and EML3 may be made of low-molecular-weight or high-molecular-weight organic materials. In embodiments, functional layers such as hole transport layers and hole injection layers may be further disposed beneath the light-emitting layers EML1, EML2, and EML3. The light-emitting layers EML1, EML2, and EML3 may be configured to correspond to the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively.

[0074] The first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 can be configured to emit light in different wavelength bands. For example, in an embodiment, the first light-emitting diode ED1 can be configured to emit light in a wavelength band corresponding to red, the second light-emitting diode ED2 can be configured to emit light in a wavelength band corresponding to green, and the third light-emitting diode ED3 can be configured to emit light in a wavelength band corresponding to blue. However, the embodiments of this disclosure are not limited to this, and any two of the light-emitting diodes ED1, ED2, and ED3 can be configured to emit light in the same wavelength band. In some embodiments, a fourth light-emitting diode may be included to emit light in a wavelength band different from that of the first light-emitting diodes ED1, ED2, and ED3.

[0075] The common electrode CE can be a transparent electrode or a semi-transparent electrode. The common electrode CE can be disposed across both the display area DA and the non-display area NDA, and is positioned above the light-emitting layers EML1, EML2, EML3 and the pixel definition layer PDL. In embodiments, the common electrode CE can be integrally configured (e.g., collectively configured) to correspond to the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0076] In an embodiment, the common electrode CE may include at least one material selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, or a compound, mixture, or oxide comprising at least two of these materials.

[0077] The following provides a detailed description of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, as well as the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3.

[0078] A pixel defining layer (PDL) can be disposed on pixel electrodes PE1, PE2, PE3 and a planarization layer PL (e.g., directly on both). The PDL can be used to define pixels overlapping with the light-emitting area by having openings OP corresponding to each pixel. Furthermore, the PDL can be configured to prevent arcing between the edges of pixel electrodes PE1, PE2, PE3 and the common electrode CE by increasing the distance between them. In embodiments, the PDL can be formed from an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0079] The encapsulation layer EN can be disposed on the common electrode CE (e.g., directly disposed on the third-party DR3). The encapsulation layer EN can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The encapsulation layer EN can be configured to protect components disposed beneath the encapsulation layer EN from external moisture or contaminants.

[0080] In this embodiment, the first light-emitting diode ED1 may include a first pixel electrode PE1, a first light-emitting layer EML1, and a common electrode CE. The first light-emitting diode ED1 may overlap with the first light-emitting area. The second light-emitting diode ED2 may include a second pixel electrode PE2, a second light-emitting layer EML2, and a common electrode CE. The second light-emitting diode ED2 may overlap with the second light-emitting area. The third light-emitting diode ED3 may include a third pixel electrode PE3, a third light-emitting layer EML3, and a common electrode CE. The third light-emitting diode ED3 may overlap with the third light-emitting area.

[0081] In an embodiment, the first pixel electrode PE1 may include a first lower metal layer LM1, a first inorganic layer IL1, a first hard mask layer HM1, and a first upper metal layer UM1 in a sequentially stacked order.

[0082] The first lower metal layer LM1 can be disposed on the circuit layer CL (e.g., directly disposed on the third-party DR3). In an embodiment, the first lower metal layer LM1 can be a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof.

[0083] The first inorganic layer IL1 may be disposed on the first lower metal layer LM1 (e.g., directly disposed thereon) and may have insulating properties. In an embodiment, the first inorganic layer IL1 may comprise an inorganic material. In an embodiment, the first inorganic layer IL1 may comprise silicon oxide (SiO2). x ).

[0084] In embodiments of this disclosure, the thickness of the first inorganic layer IL1 (e.g., on the third-direction DR3 in the vertical direction) can be adjusted correspondingly to the thickness of the first pixel electrode PE1 (e.g., on the third-direction DR3). A detailed description of this will be provided later.

[0085] The first hard mask layer HM1 may be disposed on the first inorganic layer IL1 (e.g., directly disposed thereon). The first contact hole CNT1 may be defined in the first hard mask layer HM1 and the first inorganic layer IL1, the first contact hole CNT1 penetrating the first hard mask layer HM1 and the first inorganic layer IL1.

[0086] In an embodiment, the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 may include amorphous carbon (aC).

[0087] In embodiments of this disclosure, the first hard mask layer HM1 may have an etch selectivity different from that of the third inorganic layer IL3, which will be described later. In the context of this disclosure, having different etch selectivity means that the degree of etching of the two components can differ significantly from each other under the same etching process. For example, because the first hard mask layer HM1 has an etch selectivity different from that of the third inorganic layer IL3, the first hard mask layer HM1 may be substantially unetched or etched to a significantly small extent during the etching process that forms the third inorganic layer IL3, thereby protecting the components disposed beneath the first hard mask layer HM1.

[0088] In embodiments of this disclosure, the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 may have substantially the same etch selectivity, and may protect components disposed under each of the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 during the etching process for forming the third inorganic layer IL3, the fifth inorganic layer IL5, and the sixth inorganic layer IL6.

[0089] The first upper metal layer UM1 can be disposed on the first hard mask layer HM1 (e.g., directly disposed on the third-party DR3) and can be electrically connected to the first lower metal layer LM1 through the first contact hole CNT1. However, this configuration is not limited to this, and in some embodiments, the first upper metal layer UM1 can be insulated from the first lower metal layer LM1 and directly connected to the transistor TFT (see [link to relevant documentation]). Figure 2 ).

[0090] In an embodiment, the first upper metal layer UM1 can be a transparent electrode or a semi-transparent electrode, and can be formed from a metal thin film comprising Yb, Li, Ca, Al, Ag, Mg or compounds thereof (e.g., LiF) or a material having a bilayer structure such as LiF / Ca or LiF / Al. Furthermore, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO or In2O3 can be further disposed on the metal thin film.

[0091] In an embodiment, the second pixel electrode PE2 may include a second lower metal layer LM2, a second inorganic layer IL2, a second hard mask layer HM2, a third inorganic layer IL3, and a second upper metal layer UM2 in a sequentially stacked order.

[0092] Any redundant descriptions of substantially identical components will be omitted below. A second inorganic layer IL2 may be disposed between the second lower metal layer LM2 and the second hard mask layer HM2 (e.g., directly therebetween), while a third inorganic layer IL3 may be disposed between the second hard mask layer HM2 and the second upper metal layer UM2 (e.g., directly therebetween). The third inorganic layer IL3 may be configured, together with the second inorganic layer IL2, to adjust the thickness of the second pixel electrode PE2 (e.g., on the third-direction DR3).

[0093] In embodiments of this disclosure, the second inorganic layer IL2 may be formed in substantially the same process steps as the first inorganic layer IL1. As will be described later, in embodiments the first inorganic layer IL1 and the second inorganic layer IL2 may each be formed by partially removing the initial inorganic layer.

[0094] The second contact hole CNT2 can be defined within the second pixel electrode PE2. In an embodiment, the second upper metal layer UM2 can be electrically connected to the second lower metal layer LM2 through the second contact hole CNT2. However, this configuration is not limited to this, and in some embodiments, the second upper metal layer UM2 can be electrically insulated from the second lower metal layer LM2 and directly connected to the transistor TFT (see [link to relevant documentation]). Figure 2 ).

[0095] In an embodiment, the second contact hole CNT2 may include a first sub-contact hole SCNT1 and a second sub-contact hole SCNT2. The first sub-contact hole SCNT1 can penetrate the second inorganic layer IL2 and the second hard mask layer HM2, while the second sub-contact hole SCNT2 can penetrate the third inorganic layer IL3. The first sub-contact hole SCNT1 and the second contact hole SCNT2 may overlap each other in a planar view.

[0096] In an embodiment, the first pixel electrode PE1 may include a single inorganic layer (e.g., a first inorganic layer IL1), while the second pixel electrode PE2 may include two inorganic layers (e.g., a second inorganic layer IL2 and a third inorganic layer IL3). The thicknesses of the first inorganic layer IL1 and the second inorganic layer IL2 (e.g., on a third direction DR3 as a vertical direction) may be substantially the same as each other, and the thicknesses of the first hard mask layer HM1 and the second hard mask layer HM2 (e.g., on a third direction DR3 as a vertical direction) may also be substantially the same as each other. For example, a first thickness T1, which is the sum of the thicknesses of the first inorganic layer IL1 and the first hard mask layer HM1, may be substantially the same as a second thickness T2, which is the sum of the thicknesses of the second inorganic layer IL2 and the second hard mask layer HM2.

[0097] In an embodiment, the depth D1 of the first contact hole CNT1 (e.g., on the third-direction DR3) and the depth D2 of the first sub-contact hole SCNT1 (e.g., on the third-direction DR3) can be substantially the same as each other.

[0098] In an embodiment, the thickness ET1 of the first pixel electrode PE1 (e.g., on the third-direction DR3) may be different from the thickness ET2 of the second pixel electrode PE2 (e.g., on the third-direction DR3). The thickness ET2 of the second pixel electrode PE2 may be greater than the thickness ET1 of the first pixel electrode PE1.

[0099] In embodiments of this disclosure, the thickness ET1 of the first pixel electrode PE1 and the thickness ET2 of the second pixel electrode PE2 may be different from each other.

[0100] In embodiments of this disclosure, the wavelengths of the light emitted by the first light-emitting diode ED1 and the wavelengths of the light emitted by the second light-emitting diode ED2 may be different from each other. The thickness ET1 of the first pixel electrode PE1 for enabling the light emitted by the first light-emitting diode ED1 to resonate may be different from the thickness ET2 of the second pixel electrode PE2 for enabling the light emitted by the second light-emitting diode ED2 to resonate. In embodiments of this disclosure, the thickness ET1 of the first pixel electrode PE1 can be adjusted to enable the light emitted by the first light-emitting diode ED1 to resonate, and the thickness ET2 of the second pixel electrode PE2 can be adjusted to enable the light emitted by the second light-emitting diode ED2 to resonate.

[0101] In an embodiment, the third pixel electrode PE3 may include a third lower metal layer LM3, a fourth inorganic layer IL4, a third hard mask layer HM3, a fifth inorganic layer IL5, a sixth inorganic layer IL6, and a third upper metal layer UM3 in a sequentially stacked order.

[0102] In embodiments of this disclosure, the fourth inorganic layer IL4 can be formed in substantially the same process steps as the first inorganic layer IL1 and the second inorganic layer IL2. Similarly, the fifth inorganic layer IL5 can be formed in substantially the same process steps as the third inorganic layer IL3.

[0103] In an embodiment, the third contact hole CNT3 may include a third sub-contact hole SCNT3 and a fourth sub-contact hole SCNT4. The third sub-contact hole SCNT3 can penetrate the fourth inorganic layer IL4 and the third hard mask layer HM3, while the fourth sub-contact hole SCNT4 can penetrate the fifth inorganic layer IL5 and the sixth inorganic layer IL6. The third sub-contact hole SCNT3 and the fourth sub-contact hole SCNT4 may overlap each other in a planar view.

[0104] In an embodiment, the first pixel electrode PE1 may include a single inorganic layer (e.g., a first inorganic layer IL1), the second pixel electrode PE2 may include two inorganic layers (e.g., a second inorganic layer IL2 and a third inorganic layer IL3), and the third pixel electrode PE3 may include three inorganic layers (e.g., a fourth inorganic layer IL4, a fifth inorganic layer IL5, and a sixth inorganic layer IL6). The fourth inorganic layer IL4, the fifth inorganic layer IL5, and the sixth inorganic layer IL6 may be configured to adjust the thickness of the third pixel electrode PE3.

[0105] The wavelengths of the light emitted by the first light-emitting diode ED1, the second light-emitting diode ED2, and the third light-emitting diode ED3 can be different from each other. The thickness ET1 of the first pixel electrode PE1 for enabling the light emitted by the first light-emitting diode ED1 to resonate (e.g., on the third-direction DR3), the thickness ET2 of the second pixel electrode PE2 for enabling the light emitted by the second light-emitting diode ED2 to resonate (e.g., on the third-direction DR3), and the thickness ET3 of the third pixel electrode PE3 for enabling the light emitted by the third light-emitting diode ED3 to resonate (e.g., on the third-direction DR3) can be different from each other.

[0106] In embodiments of this disclosure, the thickness ET1 of the first pixel electrode PE1 (e.g., on the third-direction DR3) can be adjusted to enable the light emitted by the first light-emitting diode ED1 to resonate, the thickness ET2 of the second pixel electrode PE2 (e.g., on the third-direction DR3) can be adjusted to enable the light emitted by the second light-emitting diode ED2 to resonate, and the thickness ET3 of the third pixel electrode PE3 (e.g., on the third-direction DR3) can be adjusted to enable the light emitted by the third light-emitting diode ED3 to resonate.

[0107] In embodiments of this disclosure, the thickness of the pixel electrodes PE1, PE2, PE3 (e.g., on the third-direction DR3) can be adjusted so that the light emitted by the corresponding light-emitting diodes ED1, ED2, ED3 can resonate, thereby improving the device efficiency of the display device.

[0108] In an embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 (e.g., on the third-direction DR3) may have different thicknesses than each other.

[0109] In an embodiment, the first inorganic layer IL1, the second inorganic layer IL2, and the fourth inorganic layer IL4 (e.g., on the third-direction DR3) may have substantially the same thickness as each other.

[0110] In an embodiment, the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 can be formed in substantially the same process steps. In an embodiment, the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 (e.g., on a third-direction DR3) can have substantially the same thickness as each other.

[0111] In an embodiment, the first thickness T1, the second thickness T2, and the third thickness T3, which is the sum of the thicknesses of the fourth inorganic layer IL4 and the third hard mask layer HM3, can be substantially the same as each other (e.g., on the third-direction DR3).

[0112] In an embodiment, the depth D1 of the first contact hole CNT1 (e.g., on the third-direction DR3), the depth D2 of the first sub-contact hole SCNT1 (e.g., on the third-direction DR3), and the depth D3 of the third sub-contact hole SCNT3 (e.g., on the third-direction DR3) can be substantially the same as each other.

[0113] According to embodiments of this disclosure, a method for manufacturing a display device, described later, may include forming first contact holes CNT1, second contact holes CNT2, and third contact holes CNT3 for connecting a first upper metal layer UM1, a second upper metal layer UM2, and a third upper metal layer UM3 to corresponding transistor TFTs. This step may include a first etching step and a second etching step. In the first etching step, the first intermediate hard mask layer MHM1, the second intermediate hard mask layer MHM2, and the third intermediate hard mask layer MHM3, described later (see [link to documentation]). Figure 9J The component is positioned above the first etching step. Once the first etching step is completed, the second sub-contact hole SCNT2 and the fourth sub-contact hole SCNT4 can then be formed.

[0114] In the second etching step, the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 can be formed. The component is etched in the second etching step to form the thickness of the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 in the first preliminary pixel electrode PPE1, the second preliminary pixel electrode PPE2, and the third preliminary pixel electrode PPE3 (see...). Figure 9J The layers can be essentially the same. Therefore, damage to the first lower metal layer LM1, the second lower metal layer LM2, and the third lower metal layer LM3 can be prevented during the second etching step, thereby improving the reliability of the display device.

[0115] The methods for manufacturing the display device will be described in more detail later.

[0116] In the comparative example, the display device does not include contact holes within the pixel electrodes. In this comparative embodiment, a hard mask disposed within the pixel electrodes serves as an etch stop layer to form an inorganic layer of varying thickness for each light-emitting diode. The hard mask consists of multiple layers depending on the number of inorganic layers disposed within each pixel electrode.

[0117] According to embodiments of this disclosure, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may each include a single hard mask layer HM1, HM2, and HM3. The first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 (e.g., on the third-direction DR3) may have substantially the same thickness. Among the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, the components disposed beneath each of the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 (e.g., on the third-direction DR3) may have substantially the same thickness.

[0118] According to embodiments, the pixel defining layer PDL can be in direct contact with the first inorganic layer IL1 and the second inorganic layer IL2. In embodiments of this disclosure, the first upper metal layer UM1 can be electrically connected to the transistor TFT through the first contact hole CNT1 and can not cover the entire first inorganic layer IL1. Similarly, the second upper metal layer UM2 can be electrically connected to the transistor TFT through the second contact hole CNT2 and can not cover the entire second inorganic layer IL2. One side (e.g., the lateral end) of the first inorganic layer IL1 and one side (e.g., the lateral end) of the second inorganic layer IL2 can be exposed toward the pixel defining layer PDL disposed between the first pixel electrode PE1 and the second pixel electrode PE2.

[0119] Figure 4 This is a cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure. Figure 5This is a cross-sectional view illustrating another portion of a display device according to an embodiment of the present disclosure. Figure 6 This is a cross-sectional view illustrating another portion of a display device according to an embodiment of the present disclosure.

[0120] refer to Figure 4 In an embodiment, the first lower metal layer LM1' of the first pixel electrode PE1' may be spaced apart from and electrically insulated from the first upper metal layer UM1' (e.g., on the third-direction DR3). The first lower metal layer LM1' may serve as a reflective layer and may not be associated with the transistor TFT (see [link to TFT]). Figure 2 The first upper metal layer UM1' can be electrically connected to the transistor TFT. In an embodiment, the second light-emitting diode ED2 can have the same characteristics as the first upper metal layer UM1'. Figure 4 The first light-emitting diode ED1' shown has a similar structure, in which the second lower metal layer LM2 can be spaced apart from the second contact hole CNT2 and the second upper metal layer UM2 can be electrically connected to the transistor TFT through the second contact hole CNT2.

[0121] refer to Figure 5 In an embodiment, the third inorganic layer IL3' may (e.g., on the third-direction DR3) have a different thickness than the fifth inorganic layer IL5'. The third pixel electrode PE3' and the second pixel electrode PE2' may have different thicknesses and different resonant distances from each other.

[0122] refer to Figure 6 In an embodiment, the first pixel electrode PE1' may further include a first lower inorganic layer LL1 disposed between the first lower metal layer LM1 and the first inorganic layer IL1 (e.g., on the third-direction DR3). The second pixel electrode PE2' may further include a second lower inorganic layer LL2 disposed between the second lower metal layer LM2 and the second inorganic layer IL2 (e.g., on the third-direction DR3). The third pixel electrode PE3' may further include a third lower inorganic layer LL3 disposed between the third lower metal layer LM3 and the fourth inorganic layer IL4 (e.g., on the third-direction DR3). The first lower inorganic layer LL1, the second lower inorganic layer LL2, and the third lower inorganic layer LL3 (e.g., on the third-direction DR3) may have substantially the same thickness as each other. In this embodiment, the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be referred to as the first upper inorganic layer, the second upper inorganic layer, and the third upper inorganic layer, respectively.

[0123] Figure 7 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment of the present disclosure. Figure 8 This is a flowchart illustrating specific steps of a method for manufacturing a display device according to an embodiment of the present disclosure. Figures 9A to 9NThis is a schematic diagram illustrating the steps of a method for manufacturing a display device according to an embodiment of the present disclosure.

[0124] refer to Figure 7 A method for manufacturing a display device according to an embodiment of the present disclosure may include: preparing a preliminary display panel in frame S100; forming a pixel electrode in frame S200; forming a pixel defining layer in frame S300; forming a light-emitting layer in frame S400; forming a common electrode in frame S500; and forming an encapsulation layer in frame S600.

[0125] refer to Figure 8 In an embodiment, the step of forming a pixel electrode in frame S200 may include: forming a lower metal layer in frame S201; forming a first preliminary inorganic layer in frame S202; forming a preliminary hard mask layer in frame S203; forming a second preliminary inorganic layer in frame S204; forming a third preliminary inorganic layer in frame S205; forming an intermediate layer in frame S206; performing a first etching in frame S207; performing a second etching in frame S208; and forming an upper metal layer in frame S209.

[0126] refer to Figure 7 , Figure 8 and Figure 9A The step of fabricating a preliminary display panel in frame S100 may involve forming a circuit layer CL comprising a plurality of transistor TFTs on a substrate SS. The step of forming pixel electrodes in frame S200 may involve forming lower metal layers LM1, LM2, and LM3 on the circuit layer CL in frame S201.

[0127] refer to Figure 8 and Figure 9B The step of forming the first preliminary inorganic layer in block S202 may involve forming a first preliminary organic layer PIL1 on the first lower metal layer LM1, the second lower metal layer LM2, and the third lower metal layer LM3, and the circuit layer CL (e.g., directly thereon). The step of forming the preliminary hard mask layer in block S203 may involve forming a preliminary hard mask layer PHM on the first preliminary inorganic layer PIL1 (e.g., directly thereon).

[0128] refer to Figure 8 and Figure 9C In an embodiment, the method for manufacturing a display device may further include: after forming a preliminary hard mask layer in frame S203, and then, with the first pixel electrode PE1 (see...) Figure 2 A first etch stop layer ES1 is formed on the corresponding area (e.g., directly thereon). The first etch stop layer ES1 can be configured to prevent inorganic layer residue from remaining on the first intermediate hard mask layer MHM1 during the step of forming the intermediate layer in block S206, which will be described later (see [link to block S206]). Figure 9H )superior.

[0129] refer to Figure 8 and Figure 9D In the step of forming the second preliminary inorganic layer PIL2 in frame S204, the second preliminary inorganic layer PIL2 can be formed on the preliminary hard mask layer PHM (e.g., directly on it).

[0130] refer to Figure 8 and Figure 9E In an embodiment, the method for manufacturing a display device may further include: after forming a second preliminary inorganic layer in frame S204, and then, with the second pixel electrode PE2 (see... Figure 2 A second etch stop layer ES2 is formed on the corresponding area (e.g., directly thereon). The second etch stop layer ES2 can be configured to prevent inorganic layer residue from remaining on the second intermediate hard mask layer MHM2 during the step of forming the intermediate layer in block S206, which will be described later (see [link to documentation]). Figure 9H )superior.

[0131] refer to Figure 8 and Figure 9F In the step of forming the third preliminary inorganic layer in frame S205, the third preliminary inorganic layer PIL3 can be formed on the second preliminary inorganic layer PIL2 (for example, directly on it).

[0132] refer to Figure 8 and Figure 9G The step of forming an intermediate layer in frame S206 may include first forming an intermediate layer with the third pixel electrode PE3 (see [link to image]). Figure 2 The corresponding area forms a photoresist PR.

[0133] refer to Figure 9H The first intermediate inorganic layer MIL1, the second intermediate inorganic layer MIL2, the third intermediate inorganic layer MIL3, the fourth intermediate inorganic layer MIL4, the fifth intermediate inorganic layer MIL5, and the sixth intermediate inorganic layer MIL6, as well as the first intermediate hard mask layer MHM1, the second intermediate hard mask layer MHM2, and the third intermediate hard mask layer MHM3, can be formed by etching process.

[0134] refer to Figure 9I It can remove the first etch stop layer ES1, the second etch stop layer ES2, and the photoresist PR.

[0135] refer to Figure 8 , Figure 9I and Figure 9JIn the first etching step performed in block S207, portions of the intermediate inorganic layers MIL3, MIL5, and MIL6 disposed on the second intermediate hard mask layer MHM2 and the third intermediate hard mask layer MHM3 can be removed to form upper contact holes UCNT1, UCNT2, and UCNT3. For example, in an embodiment, a portion of the third intermediate inorganic layer MIL3 located in the region corresponding to the second pixel electrode PE2 can be removed to form the first upper contact hole UCNT1 and the third inorganic layer IL3. Furthermore, in the first etching step performed in block S207, the sixth intermediate inorganic layer MIL6 located in the region corresponding to the third pixel electrode PE3 can be removed to form the second upper contact hole UCNT2, and the fifth intermediate inorganic layer MIL5 can be removed to form the third upper contact hole UCNT3, thereby forming the sixth inorganic layer IL6 and the fifth inorganic layer IL5.

[0136] In embodiments of this disclosure, the step of performing the first etching in block S207 may involve removing portions of the intermediate inorganic layers MIL3, MIL5, MIL6 that have different etch selectivity from the intermediate hard mask layers MHM1, MHM2, MHM3, in preparation for performing the second etching in block S208, which will be described later.

[0137] refer to Figure 8 , Figure 9K and Figure 9L In the second etching step performed in frame S208, lower contact holes LCNT1, LCNT2, and LCNT3 penetrating the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 can be formed first. The first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 (e.g., on the third-direction DR3) can have substantially the same thickness, and the first lower contact hole LCNT1, the second lower contact hole LCNT2, and the third lower contact hole LCNT3 (e.g., on the third-direction DR3) can have substantially the same depth. Next, a fourth lower contact hole LCNT4, a fifth lower contact hole LCNT5, and a sixth lower contact hole LCNT6 penetrating the first inorganic layer IL1, the second inorganic layer IL2, and the fourth inorganic layer IL4, respectively, can be formed.

[0138] In embodiments of this disclosure, the first hard mask layer HM1, the second hard mask layer HM2, and the third hard mask layer HM3 may comprise amorphous carbon (aC), and the first inorganic layer IL1, the second inorganic layer IL2, and the fourth inorganic layer IL4 may comprise silicon oxide (SiO2). x ).

[0139] In an embodiment, the formation of the first lower contact hole LCNT1, the second lower contact hole LCNT2, and the third lower contact hole LCNT3 can be performed by oxygen ashing (e.g., O2 ashing).

[0140] In this embodiment, the fourth lower contact hole LCNT4, the fifth lower contact hole LCNT5, and the sixth lower contact hole LCNT6 can be formed by using an etching process with a fluorine-based dry etching gas.

[0141] refer to Figure 8 and Figure 9M In the step of forming the upper metal layer in frame S209, the metal layer can be formed at the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 (see [reference]). Figure 2 A first upper metal layer UM1, a second upper metal layer UM2, and a third upper metal layer UM3 are formed in the corresponding regions. The first upper metal layer UM1 can be electrically connected to the first lower metal layer LM1. The second upper metal layer UM2 can be electrically connected to the second lower metal layer LM2. The third upper metal layer UM3 can be electrically connected to the third lower metal layer LM3. However, as described above, the embodiments of this disclosure are not limited thereto, and in some embodiments, the first upper metal layer UM1, the second upper metal layer UM2, and the third upper metal layer UM3 can be electrically insulated from the first lower metal layer LM1, the second lower metal layer LM2, and the third lower metal layer LM3, respectively.

[0142] refer to Figure 7 and Figure 9N In the step of forming the pixel defining layer in frame S300, the pixel defining layer PDL can be formed between the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In the step of forming the light-emitting layer in frame S400, the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 can be formed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively. In the step of forming the common electrode in frame S500, the common electrode CE can be formed on the pixel defining layer PDL and the light-emitting layers EML1, EML2, and EML3. In the step of forming the encapsulation layer in frame S600, the encapsulation layer EN can be formed on the common electrode CE.

[0143] Using the method for manufacturing a display device according to embodiments of the present disclosure, contact holes of equal depth can be formed for each of a plurality of pixel electrodes by arranging a single hard mask layer on an inorganic layer having the same thickness. During this process, damage to the underlying metal layer can be prevented, thereby improving the reliability of the display device. Furthermore, since the pixel electrodes have different thicknesses, light emitted from the light-emitting diodes included in the pixels can resonate, thereby improving the device efficiency of the display device.

[0144] The display device according to embodiments of this disclosure can be applied to various electronic devices. The electronic device according to embodiments may include the display device described above and may further include modules or devices having additional functions beyond the display device.

[0145] Figure 10 This is a block diagram of an electronic device according to embodiments of the present disclosure. Reference Figure 10 The electronic device 10 according to embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 10 may further include an input module 15, a non-display output module 16, and / or a communication module 17.

[0146] Electronic device 10 can be configured to output various types of information in the form of images via display module 11. When processor 12 executes an application stored in memory 13, the application can provide visual information to the user via display module 11. Power module 14 can generate or supply power to electronic device 10. Power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module configured to convert the supplied power into the form required for the operation of electronic device 10. Input module 15 can be configured to provide input information to processor 12 and / or display module 11. Non-display output module 16 can be configured to receive non-visual information such as sound, haptic feedback, or lighting signals from processor 12 and provide it to the user. Communication module 17 may include a receiver and transmitter configured to facilitate communication between electronic device 10 and external devices.

[0147] At least one of the components of electronic device 10 may be included within the display device DD described in the foregoing embodiments. Furthermore, some of the aforementioned modules may be integrated into the display device DD, while other modules may be provided separately from the display device DD. For example, the display device DD may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided as independent components within electronic device 10, rather than being integrated into the display device DD.

[0148] Figures 11 to 13 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Figures 11 to 13 The figure illustrates examples of various electronic devices 10 in which a display device DD according to embodiments of the present disclosure may be applied.

[0149] Figure 11 The figures show a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a television (TV) 10_1d, and a desktop monitor 10_1e as examples of electronic devices 10.

[0150] The smartphone 10_1a may include a display module 11, a communication module 17, and an input module 15, such as a touch sensor. The smartphone 10_1a may be configured to process information received via the communication module 17 or other input modules and display that information via the display module 11 of the display device DD.

[0151] Similar to smartphone 10_1a, tablet PC 10_1b, laptop computer 10_1c, TV 10_1d and desktop monitor 10_1e may also include display module 11 and input module 15, and in some cases may further include communication module 17.

[0152] Figure 12 The figure illustrates an example of an electronic device 10, including a display module 11, being applied to a wearable electronic device. Examples of such wearable electronic devices may include smart glasses 10_2a, a head-mounted display 10_2b, and a smartwatch 10_2c. However, embodiments of this disclosure are not limited thereto, and the electronic device 10 may be a variety of different, small, medium, or large electronic devices.

[0153] The smart glasses 10_2a and head-mounted display 10_2b may include a display module 11 configured to output images and a reflector configured to reflect the displayed images toward the user's eyes. Through these components, these wearable electronic devices can provide users with virtual reality or augmented reality visual effects.

[0154] The smartwatch 10_2c may include a biometric sensor as an input device and may be configured to display biometric information detected by the sensor via a display module 11.

[0155] Figure 13 The figure illustrates an example in which an electronic device 10, including a display module 11, is used in a vehicle. For example, the electronic device 10_3 can be applied to the vehicle's instrument panel, center console, or dashboard display. It can also be applied to a central information display (CID) mounted on the dashboard or to an interior rearview mirror display that replaces traditional side mirrors.

[0156] Up to this point, certain non-limiting embodiments of the present disclosure have been described, but these are merely examples and are not intended to limit the embodiments of the present disclosure. Those skilled in the art to which this disclosure pertains may make various modifications and alterations to the described embodiments by adding, changing, deleting, or supplementing certain elements without departing from the scope of the technical spirit of the present disclosure, and such modifications and alterations should also be considered within the scope of this disclosure.

Claims

1. A display device, comprising: A substrate having a plurality of light-emitting regions defined therein; A circuit layer is disposed on the substrate, and the circuit layer includes a plurality of transistors; as well as The first and second light-emitting diodes are disposed on the circuit layer. The first light-emitting diode overlaps with the first light-emitting region among the plurality of light-emitting regions and includes a first pixel electrode, a first light-emitting layer, and a common electrode. The second light-emitting diode overlaps with the second light-emitting region among the plurality of light-emitting regions and includes a second pixel electrode, a second light-emitting layer, and the common electrode. The first pixel electrode comprises a first lower metal layer, a first inorganic layer, a first hard mask layer, and a first upper metal layer, stacked sequentially, and has a first contact hole defined within the first pixel electrode, the first contact hole penetrating the first inorganic layer and the first hard mask layer. The second pixel electrode comprises, in a sequentially stacked order, a second lower metal layer, a second inorganic layer, a second hard mask layer, a third inorganic layer, and a second upper metal layer, and has a second contact hole defined within the second pixel electrode, the second contact hole penetrating the second inorganic layer, the second hard mask layer, and the third inorganic layer. Wherein, the first inorganic layer and the second inorganic layer have the same thickness in the vertical direction, and The first pixel electrode and the second pixel electrode have different thicknesses in the vertical direction.

2. The display device according to claim 1, wherein, The thickness of the second pixel electrode in the vertical direction is greater than the thickness of the first pixel electrode in the vertical direction.

3. The display device according to claim 1, wherein, The first hard mask layer and the second hard mask layer have the same thickness in the vertical direction.

4. The display device according to claim 1, wherein, Each of the first hard mask layer and the second hard mask layer has an etch selectivity that is different from the etch selectivity of the third inorganic layer.

5. The display device according to claim 1, wherein, The second contact hole includes: The first sub-contact hole penetrates the second inorganic layer and the second hard mask layer; and The second sub-contact hole penetrates the third inorganic layer. The first contact hole and the first sub-contact hole have the same depth.

6. The display device according to claim 1, further comprising: The third light-emitting diode is disposed on the circuit layer. The third light-emitting diode overlaps with the third light-emitting region among the plurality of light-emitting regions. The third light-emitting diode includes a third pixel electrode, a third light-emitting layer, and a common electrode. The third pixel electrode, stacked sequentially, comprises a third lower metal layer, a fourth inorganic layer, a third hard mask layer, a fifth inorganic layer, a sixth inorganic layer, and a third upper metal layer. The third pixel electrode has a third contact hole that penetrates the fourth inorganic layer, the third hard mask layer, the fifth inorganic layer, and the sixth inorganic layer. The fourth inorganic layer, the first inorganic layer, and the second inorganic layer have the same thickness in the vertical direction.

7. The display device according to claim 6, wherein, The first hard mask layer, the second hard mask layer, and the third hard mask layer have the same thickness in the vertical direction.

8. The display device according to claim 6, wherein, The second contact hole includes: The first sub-contact hole penetrates the second inorganic layer and the second hard mask layer; and The second sub-contact hole penetrates the third inorganic layer. The third contact hole includes: The third sub-contact hole penetrates the fourth inorganic layer and the third hard mask layer; and The fourth sub-contact hole penetrates the fifth and sixth inorganic layers. The third sub-contact hole, the first contact hole, and the first sub-contact hole have the same depth.

9. The display device according to claim 1, wherein, The first lower metal layer is spaced apart from the first contact hole. The second lower metal layer is spaced apart from the second contact hole. The first upper metal layer is electrically connected to a corresponding transistor among the plurality of transistors through the first contact hole, and The second upper metal layer is electrically connected to a corresponding transistor among the plurality of transistors through the second contact hole.

10. The display device according to claim 1, further comprising: A pixel defining layer is disposed between the first pixel electrode and the second pixel electrode. The pixel defining layer is in direct contact with the first inorganic layer and the second inorganic layer.

11. The display device according to claim 1, wherein, Each of the first hard mask layer and the second hard mask layer contains amorphous carbon.

12. The display device according to claim 1, wherein, The third inorganic layer comprises silicon oxide.

13. An electronic device, the electronic device comprising: The display device according to any one of claims 1 to 12; The processor controls the display device; The memory stores data required to operate the display device or the processor; as well as Power conversion module, which generates or supplies power.

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