Ion energy analysis device for plasma treatment

Abstract

This disclosure provides an ion energy analysis apparatus for plasma processing. An apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system includes a substrate for placement in the plasma processing system and exposure to plasma, and an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the surface of the substrate during plasma processing. The analyzer includes a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collector C. Each gate is separated by an insulating layer integrated in the substrate, a battery power supply, and control circuitry for providing and controlling voltages to each gate and collector of the ion energy analyzer; wherein at least one insulating layer includes a peripheral portion with a reduced thickness relative to the remaining portion of the insulating layer.

Description

[0001] This application is a divisional application of the invention patent application filed on September 10, 2021, with application number 202111059795.X and invention title "Ion Energy Analysis Device for Plasma Processing". Technical Field

[0002] This application relates to an apparatus and method for measuring the current density and energy distribution of incident charged particles arriving at a substrate or surface during plasma processing. Background Technology

[0003] Plasma processing has a wide range of applications in modern industry. A well-known example is the manufacture of integrated circuits in the semiconductor industry. Plasma processing is also used in the production of solar panels, flat panel displays, thin film coatings, and medical devices.

[0004] The current density (ion flux) and energy distribution of ions reaching the substrate surface strongly influence the performance of plasma-based processes. In semiconductor manufacturing, the substrate is a silicon wafer, while in other industries, it can be a glass panel or various alternatives. Wafers and substrates can be used interchangeably throughout this document, but should be understood as any type of substrate used in plasma processing. Throughout the process, the substrate surface is bombarded by plasma species (including high-energy ions) to remove (etch) and / or deposit layers of material, thereby forming structures or features on the workpiece surface. Ion bombardment can directly drive etching and deposition, or it can be used to activate the surface, allowing more reactive plasma particles to perform this work. For example, in plasma etching, a characteristic feature of the semiconductor industry, ion flux and associated parameters (IEDs) determine important parameters such as etch rate, etch selectivity, and etch anisotropy. Therefore, IEDs are key plasma parameters that are measured, understood, and controlled to ensure optimal processing performance.

[0005] As the critical dimensions of transistors continue to shrink, more stringent control over IEDs (In-Edge Devices) on the wafer surface is required. The repeatability and uniformity of IEDs are crucial for optimal throughput. Therefore, IED sensors integrating wafers and substrates are essential for advancements in nanotechnology fabricated using plasma processing.

[0006] For decades, various ion energy analyzers have been developed to measure IEDs in plasma processing. The planar deceleration field analyzer (RFA) design is well-known. In many RFA embodiments, a stack of conductive gates, individually separated by an insulator, is used to separate ions based on their energy, thereby determining the IED. A plasma-facing aperture allows ion samples to enter the device for analysis. A series of gates serves to a) prevent plasma from penetrating the device interior, b) repel plasma electrons, c) distinguish ions based on their energy, and d) prevent secondary electron emission from the collector. The collector terminates the stack and is used to detect the ion current signal used for measurement. The ion current at each delay voltage applied to the ion energy identification gate is recorded to give an integral form of the energy distribution. The ion current is numerically differentiated from the list of discriminator gate voltages to determine the IED.

[0007] IEDs have been extensively measured on various plasma tool platforms with varying degrees of success. Advances in ion energy analyzer technology have enabled IED measurements in an increasing number of applications and a wider parameter space. In particular, the ability to deploy ion energy analyzers on RF bias substrates (typically used in semiconductor manufacturing) has greatly increased the demand for these devices. Kawamura et al. (Plasma Source Science & Technology 8 (1999) R45–R64) provided a comprehensive review of the advances in IED measurements and delay field analyzer technology for handling plasma prior to 1999. Gahan et al. (Scientific Instruments 79, 033502 (2008)) invented a wired RF amplifier in 2008, based on the most well-known approach and compatible with RF bias over a wide frequency range. The sensor stack is embedded in an aluminum dummy wafer, 5 mm thick, with various diameter options. The sensor consists of three active gates: one to block plasma penetration, one to repel plasma electrons, and one to distinguish ion energies. Their later design modification added a fourth gate for secondary electron suppression. The virtual chip has a signal-carrying cable bundle extending from its circumferential edge. The cable bundle is shielded with a protective ceramic sleeve and terminated with a multi-pin connector. A vacuum feedthrough with an integrated RF filter module is mounted on the chamber vacuum port, featuring a receiver port that mates with the cable connector. Thus, the RFA signal is transmitted from the sensor within the vacuum chamber to the air side through the feedthrough containing the measurement electronics, controller, and gate power supply. The authors demonstrate successful measurements of the IED under a range of base bias conditions, including RF bias. However, several issues remain that hinder wider adoption of this technology, including but not limited to: (a) existing RF amplifiers connected to remote electronic control systems that add parasitic impedance to the ground, artificially influencing pedestal RF bias conditions and generated IEDs; (b) wiring that prevents easy loading of the ion energy analyzer into the plasma processing chamber using standard robotic loading systems; (c) the typically high height of the ion energy analyzer structure (often several millimeters), making deployment on substrates with similar thickness to the processing wafer difficult and limiting the range of vacuum pressures within which the device can operate; and (d) the energy range of several kiloelectron volts (eV) required to make RFA truly useful for measuring the IEDs expected in typical plasma processing. Wafer or substrate-integrated wireless RFA designs for IED measurements are essential to eliminate pedestal disturbances and enable robotic loading. Numerous technical challenges need to be overcome, including the fabrication of wafer-integrated gate sensor stacks, achieving sufficient kiloelectron volt scanning capability for the ion energy range, and meeting the high-temperature requirements of integrated sensor power supplies and circuitry.

[0008] Analog substrates with embedded sensors have become the subject of numerous patents. Some of these inventions focus on novel sensor designs and constructions, while others focus on electronic control platforms for processing, storing, and transmitting sensor data. The electronic platform is either fully integrated into the analog substrate via its own power supply or separated from the air-side electronic control platform using interconnects running through the chamber walls (using vacuum feedthrough).

[0009] In U.S. Patent No. 5,969,639, the inventors describe a silicon wafer probe with multiple integrated temperature sensors for monitoring the temperature uniformity of a substrate in various processing applications. Power and control electronics are fully integrated, including a transmitter that sends data to an external receiver. Data is stored in memory for later retrieval. While temperature is a useful parameter, it is not as critical a processing driver as ion energy distribution.

[0010] U.S. Patent No. 6,830,650 B2 describes a wafer probe device for measuring ion currents during plasma processing. The device consists of an analog substrate with integrated sensors, a power supply, and a microprocessor for storing sensor data. The power supply uses stacked capacitors to collect and store energy from the plasma to power the electronic circuitry. It also has an integrated wireless transmitter for sending sensor data to a wireless receiver mounted on a vacuum port in the chamber wall. The ion sensors are simple dual-Langmuir probes, consisting of flat metal disks exposed to the plasma above. These sensors provide measurements of surface ion currents with limited accuracy. This type of sensor cannot measure ion energy distribution, which is crucial for wafer processing. Its accuracy is limited because it does not include any suppression of secondary electron emission from the sensor surface, which can be caused by collisional ions being measured. The voltage range required to drive the sensor is more than an order of magnitude lower than that required by a deceleration field analyzer.

[0011] In U.S. Patent No. 2005 / 0115673A1, the inventors describe a silicon-based substrate with multiple integrated sensors, including an ion energy analyzer, a VUV photon detector, and a radical ion emission spectrophotometer. The device features fully integrated power and control electronics. It communicates bidirectionally with a receiver mounted in a viewport via optical means. The ion energy analyzer consists of four gates: a plasma blocking gate, an incident electron delay gate, an ion energy separation gate, and a secondary electron suppression gate. It also includes a collector for recording the ion current as a function of ion energy. The gate layers and inter-gate isolation layers are formed using standard plasma etching and deposition processes. The gates and collector are made of aluminum, while aluminum oxide is used for electrical isolation. Gate holes or “holes” extend vertically downwards through the structure, from the top of the wafer surface facing the plasma to the bottom collector, to allow ion samples to pass through the device for analysis. A voltage is applied to each gate to generate the electric field required to operate the sensor. For this analyzer design, it is assumed that the potential in the free space forming the gate holes or “holes” is the same as the potential on the metal frame. Talley et al. (Plasma Source Science and Technology, 26, 12, 2017) have demonstrated the effects of electric field "droop" (reduction) in the cavity and require a gate spacing much larger than the aperture size to minimize the impact of electric field droop on functionality, especially with perfectly aligned apertures in this invention. Given the dimensions mentioned in the description, it is doubtful whether the stated criteria have been considered. The inventors also insulate the gate sidewalls exposed to the aperture channel. This will further exacerbate the magnetic field droop effect. If this is overcome with a sufficiently thin layer, resulting in the correct voltage on the outer surface of said layer, the likelihood of voltage flashover through the insulator surface to adjacent gates is high, particularly from the high-voltage ion energy separation gate. The inventors have not explicitly described how the high-voltage ion energy separation voltage scan is generated, nor have they shown any examples of measurement data. The ability to use this invention relies on line-of-sight communication with a receiver located at a remote position on the chamber wall, which may not always be practical in modern plasma processing tools.

[0012] Mahoney et al., in patent WO 2005 / 017937 A2 and other related patents, describe an invention comprising a dual Langmuir probe for measuring ion currents near plasma boundaries. In this invention, the sensor can be embedded in a dielectric isolation ring around a chuck of a processed wafer. The sensor is connected to processing electronics via vacuum-sealed leads in the chamber wall. The device has the same limitations in terms of the measured parameters. The wired connection also limits the ease of deployment. A subsequent invention by Roche et al., published in US Patent 2005 / 0034812 A1, describes a wafer-like probe with an embedded sensor, a stacked capacitor power supply mechanism, a microprocessor, and a wireless transceiver for transmitting data to a receiver mounted in a chamber. The inventors described a similar type of dual Langmuir probe for sensing ion currents in plasma processing, but this time embedded in a wireless analog wafer.

[0013] In U.S. Patent 7,151,366 B2, Renken et al. describe an invention comprising an analog chip equipped with a battery power source, a CPU, and a transmitter for transmitting data to an analog front-end open-circuit box (FOUP), etc., and retrieving data from the chip using integrated transmitter / receiver technology. The chip can be accessed by a user via a computer connection or used to report directly to a factory host server. Although the sensor design is not documented in this patent, the analog chip platform is designed for managing sensor data.

[0014] In U.S. Patent 7,960,670 B2, Mundt et al. describe another wafer-like or substrate-like device with embedded sensors for sensing plasma processing parameters. The authors describe multiple capacitive sensing elements configurable to sense various plasma processing parameters, although a specific sensor design is not described. The capacitive sensing elements are powered by a sensor that generates a DC voltage proportional to the radio frequency power used to process the wafer and is coupled to an information processor. The device also has a transceiver for sending and receiving data. The patent envisions a remote communication device for retrieving data from the device, but this is not described.

[0015] In U.S. Patent 7,875,859, Chen et al. describe a method for fabricating and using a wafer-like device with an integrated ion energy analyzer for measuring IEDs in processed plasma during radio frequency bias. The ion energy is comprised of three gates: one for plasma blocking, one for ion energy separation, and one for electron suppression, terminating with a collector for detecting the ion current signal. The authors mention that the spacing between the gates is millimeters, which limits the device's usability to low processing pressures. The design also places the ion separation gate directly below the plasma-facing sampling aperture through which ions and electrons pass. Best practice would place the electron repulsion gate directly below the plasma-facing aperture to remove electrons as a first priority. When the ion separation gate is placed directly below the sampling aperture, the aperture must be positively biased to separate ions based on their incident energy, with electrons accelerated to high energies deep within the analyzer structure before being repelled. In practice, this configuration often results in unwanted ionization within the analyzer due to accelerated electrons, damaging the measured IED. The measurement electronics and power supply are contained in a separate module connected to the main wafer structure. Therefore, RF filtering between the wafer gate and power supply is crucial. The additional module cannot be loaded by the robot, and its location during processing is unclear. Since the system is not fully integrated into the wafer structure, the placement of the device risks interfering with actual processing conditions.

[0016] In U.S. Patent 8,816,281 B2, Funk et al. describe a process for fabricating a wafer-like ion energy analyzer device consisting of multiple substrate sandwich layers. They use a light source embedded in the bottom layer to align an array of sampling apertures between each layer. The ion energy analyzer has a very simple structure with two gates and one collector. The ion energy separator gate is adjacent to the inlet aperture, while the collector is biased to provide a repulsive force to the incident electrons while simultaneously detecting the ion current. The simplicity of this configuration is appealing, but it is not the preferred configuration because a) the collector lacks secondary electron suppression, and b) due to the positive bias of the gate near the inlet aperture, electrons are accelerated deep into the device, which can lead to undesirable ionization within the structure, thereby damaging the measured IED.

[0017] It is clear from the above that existing technologies have many shortcomings. It is necessary to address these shortcomings. Summary of the Invention

[0018] This invention describes an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system. The apparatus includes a substrate for placement in the plasma processing system and exposure to plasma, and an ion energy analyzer disposed within the substrate for measuring the ion energy distribution at the substrate surface during plasma processing. The analyzer includes a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collector C. Each gate is separated by an insulating layer integrated in the substrate, a battery power supply, and control circuitry for providing and controlling voltages to each gate and the collector of the ion energy analyzer. At least one insulating layer includes a peripheral portion with a reduced thickness relative to the remaining portion of the insulating layer.

[0019] The outer portion can protrude from the remaining portion of the insulation layer.

[0020] Recessed sections can be provided above and below the outer perimeter.

[0021] Optionally, the outer portion includes two protruding portions with a recessed portion in between.

[0022] The apparatus for obtaining IED measurements may also include a Faraday shield that surrounds the ion energy analyzer, power supply, and control circuitry.

[0023] The apparatus for obtaining IED measurements may also include a gap in a Faraday shield and a transponder for transmitting the IED measurements from the apparatus through the gap.

[0024] The apparatus for obtaining IED measurements may also include a battery manager within a substrate, the battery manager being configured to regulate the battery output voltage to a fixed voltage level.

[0025] The apparatus for obtaining IED measurements may further include a first high-voltage generating circuit within the substrate, the high-voltage generating circuit including a low-voltage to high-voltage transformer that feeds a voltage multiplier, wherein the high-voltage generating circuit acquires the output voltage of the battery manager and provides a voltage scan to the third conductive gate G2.

[0026] Alternatively, the voltage multiplier is based on a Cockcroft-Walton type voltage multiplier.

[0027] The apparatus for obtaining IED measurements may also include a microcontroller within the substrate, and the first high-voltage generating circuit further includes an H-bridge for generating a low-voltage AC signal to be input to the primary side of the transformer, wherein the frequency and amplitude of the AC signal are controlled by the microcontroller.

[0028] Optionally, the first high-voltage generating circuit also includes a high-voltage switch for discharging the third gate to the floating ground of the device.

[0029] The apparatus for obtaining IED measurement values ​​may also include a second high-voltage generating circuit within the substrate for providing a voltage scan to the third gate using the voltage output of the battery manager. The high-voltage generating circuit includes a DC-DC converter and a boost section followed by a voltage multiplier section.

[0030] Optionally, the boost section includes an inductor L1, a transistor Q1, a diode D2, and a capacitor C1, and the boost circuit is configured to boost the voltage output of the DC-DC converter.

[0031] The apparatus for obtaining IED measurements may also include a microprocessor within the substrate, wherein the transistors are controlled by pulse-width modulation signals from the microprocessor.

[0032] Alternatively, the voltage multiplier is based on a Croft-Walton type voltage multiplier.

[0033] Optionally, the voltage multiplier circuit has multiple stages, and each stage increases the voltage applied to the input of the corresponding stage.

[0034] Optionally, the second high-voltage generating circuit also includes a high-voltage switch for discharging the third gate to the floating ground of the device.

[0035] The apparatus for obtaining IED measurements may also include a resistor connected in series between each gate and the control circuit.

[0036] The present invention also relates to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus comprising a substrate for placement in the plasma processing system and exposure to plasma; an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the surface of the substrate during plasma processing; the analyzer comprising a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collector C, each gate being separated by an insulating layer, a battery power supply, and a battery manager integrated in the substrate for providing and controlling voltages to each gate and the collector of the ion energy analyzer; and a high-voltage generating circuit within the substrate, the high-voltage generating circuit comprising a low-to-high-voltage transformer feeding a voltage multiplier, wherein the high-voltage generating circuit acquires the output voltage of the battery manager and provides a voltage scan to the third conductive gate.

[0037] The voltage scan applied to the third conductive gate can increase.

[0038] The device’s ion energy analyzer is configured to sample the ion current as the voltage scan rises.

[0039] The voltage scan applied to the third conductive gate may decrease.

[0040] The device’s ion energy analyzer is configured to sample the ion current as the voltage scan rises.

[0041] The battery manager can be configured to regulate the battery output voltage to a fixed voltage level.

[0042] Voltage multipliers can be based on the Cocroft-Walton type voltage multiplier.

[0043] The device for obtaining IED measurements may also include a microcontroller within the substrate, and the high-voltage generation circuit may also include an H-bridge for generating a low-voltage AC signal to be input to the primary side of the transformer, wherein the frequency and amplitude of the AC signal are controlled by the microcontroller.

[0044] The high-voltage generating circuit can be configured to determine the voltage applied to the third conductive gate by controlling the frequency and amplitude of the AC signal applied to the primary winding of the transformer.

[0045] The high-voltage generating circuit may also include a high-voltage switch for discharging the third gate to the floating ground of the device.

[0046] The high-voltage generating circuit may also include a resistor connected in parallel with the high-voltage switch.

[0047] When the voltage generation circuit is configured to apply a falling voltage scan to the third gate, the resistor determines the discharge time of the voltage.

[0048] The apparatus for obtaining IED measurements can be further configured such that the voltage scan applied to the third conductive gate is continuous.

[0049] The device for obtaining IED measurements can be further configured such that the voltage scan applied to the third conductive gate is a step function.

[0050] The apparatus for obtaining IED measurements may also include a resistor connected in series between each gate and the control circuit.

[0051] The present invention also relates to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus comprising a substrate for placement in the plasma processing system and exposure to plasma, an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the surface of the substrate during plasma processing, the analyzer comprising a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collector C, each gate being separated by an insulating layer integrated in the substrate, a battery power supply, and a battery manager for providing and controlling voltages to each gate and the collector of the ion energy analyzer, and a high-voltage generating circuit within the substrate, the high-voltage generating circuit comprising a DC-DC converter and a boost section, the boost section subsequently being a voltage multiplier section, wherein the high-voltage generating circuit acquires the output voltage of the battery manager and provides a voltage scan to the third conductive gate.

[0052] The voltage scan applied to the third conductive gate can increase.

[0053] The device’s ion energy analyzer can be configured to sample the ion current as the voltage scan rises.

[0054] The voltage scan applied to the third conductive gate may decrease.

[0055] The device’s ion energy analyzer can be configured to sample the ion current as the voltage scan rises.

[0056] The battery manager can be configured to regulate the battery output voltage to a fixed voltage level.

[0057] Optionally, the voltage multiplier section is based on a Cocroft-Walton type voltage multiplier.

[0058] The boost section may include an inductor L1, a transistor Q1, a diode D2, and a capacitor C1. The boost circuit is configured to boost the voltage output of the DC-DC converter.

[0059] The apparatus for obtaining IED measurements may also include a microprocessor within the substrate, wherein the transistors are controlled by pulse-width modulation signals from the microprocessor.

[0060] The high-voltage generating circuit may also include a high-voltage switch for discharging the third gate to the floating ground of the device.

[0061] The high-voltage generating circuit may also include a resistor connected in parallel with the high-voltage switch.

[0062] When the voltage generation circuit is configured to apply a falling voltage scan to the third gate, the resistor determines the discharge time of the voltage.

[0063] The apparatus for obtaining IED measurements can be further configured such that the voltage scan applied to the third conductive gate is continuous.

[0064] The device for obtaining IED measurements can be further configured such that the voltage scan applied to the third conductive gate is a step function.

[0065] The apparatus for obtaining IED measurements may also include a resistor connected in series between each gate and the control circuit.

[0066] The present invention also relates to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus comprising a substrate for placement in the plasma processing system and exposure to plasma, an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the surface of the substrate during plasma processing, the analyzer comprising a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collection electrode C, each gate being separated by an insulating layer integrated in the substrate, a battery power supply, and a battery manager for providing and controlling voltages to each gate and the collection electrode of the ion energy analyzer, and a high-voltage generating circuit within the substrate, the high-voltage generating circuit comprising a high-voltage pulse generator feeding a voltage multiplier, wherein the high-voltage generating circuit is configured to acquire the output voltage of the battery manager and provide a voltage scan to the third gate.

[0067] The voltage pulse generator can be configured to acquire the output voltage of the battery manager and provide a high-voltage pulse sequence to the voltage multiplier.

[0068] The voltage multiplier can be configured to output a multiple of the voltage received from the pulse generator.

[0069] The device for obtaining IED measurements may also include a high-voltage switch for discharging a third gate to the floating ground of the device.

[0070] Optionally, the voltage generating circuit may also include a resistor connected in parallel with the high-voltage switch.

[0071] The present invention also relates to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system. The apparatus includes a substrate for placement in the plasma processing system and exposure to plasma, an ion energy analyzer disposed within the substrate for measuring the ion energy distribution at the substrate surface during plasma processing, the analyzer including a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collector C. Each gate is separated by an insulating layer integrated in the substrate, a battery power supply, and a battery manager for providing and controlling voltages to each gate and the collector of the ion energy analyzer, and a high-voltage generating circuit within the substrate configured to acquire the output voltage of the battery manager and provide a decreasing voltage scan to the third conductive gate, wherein the ion energy analyzer is configured to sample the ion current as the voltage scan decreases.

[0072] The high-voltage generating circuit may also include a high-voltage switch for discharging the third gate to the floating ground of the device.

[0073] The voltage generating circuit may also include a resistor connected in parallel with the high-voltage switch.

[0074] The present invention also relates to an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, the apparatus comprising a substrate for placement in the plasma processing system and exposure to plasma, an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the surface of the substrate during plasma processing, the analyzer comprising a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collector C, each gate being separated by an insulating layer integrated in the substrate, a battery power supply, and control circuitry for providing and controlling voltages to each gate and the collector of the ion energy analyzer, and a resistor disposed between the control circuitry and one of the conductive gates to prevent plasma formation between one of the conductive gates and an adjacent conductive gate.

[0075] The control circuit may include a high-voltage generating circuit configured to acquire the battery's output voltage and provide a voltage scan to a third conductive gate.

[0076] The device may further include a resistor disposed between the high voltage generating circuit and the third conductive gate to prevent plasma from forming between the third conductive gate and the adjacent conductive gate.

[0077] This invention describes an apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system. The apparatus includes a substrate for placement in the plasma processing system and exposure to plasma, an ion energy analyzer disposed in the substrate for measuring the ion energy distribution at the substrate surface during plasma processing, and the analyzer including a first conductive gate G0, a second conductive gate G1, a third conductive gate G2, a fourth conductive gate G3, and a collection electrode C. Each gate is separated by an insulating layer integrated in the substrate and a battery power supply including control circuitry for providing and controlling voltage to each gate and the collector electrode of the ion energy analyzer, as well as a Faraday shielding encapsulating the ion energy analyzer, power supply, and control circuitry.

[0078] Optionally, the first gate G0 is electrically connected to the Faraday shield and forms part of it.

[0079] Optionally, the substrate is silicon, and the Faraday shielding layer is formed by a conductive layer within the silicon, the conductive layer surrounding the ion energy analyzer, power supply, and electronic control circuitry. Attached Figure Description

[0080] This application will now be described with reference to the accompanying drawings, in which:

[0081] Figure 1 An overview of a system according to the invention is shown, which is capable of measuring the ion energy distribution arriving at the surface of a wafer probe during plasma processing;

[0082] Figure 2(a) shows a sensor array used to measure IEDs distributed on the surface of a wafer probe;

[0083] Figure 2(b) shows one arrangement of the gates within the sensor of Figure 2(a);

[0084] Figure 2(c) shows another arrangement of the gate within the sensor of Figure 2(a);

[0085] Figure 2(d) shows a further arrangement of the gate inside the sensor in Figure 2(a);

[0086] Figure 3(a) shows one configuration for powering the sensor;

[0087] Figure 3(b) shows another configuration for powering the sensor;

[0088] Figure 4(a) shows a possible configuration of the insulating layer within the sensor;

[0089] Figure 4(b) shows another possible configuration of the insulating layer inside the sensor;

[0090] Figure 5(a) shows a cross-section of a wafer probe with Faraday shielding according to the present invention;

[0091] Figure 5(b) also shows a cross-section of the wafer probe according to the invention;

[0092] Figure 6 The preferred potential configuration of the sensor's gate is shown;

[0093] Figure 7 Two graphs are shown: one illustrates the relationship between the ion current applied to the sensor gate and the voltage, and the other illustrates the generated IED.

[0094] Figure 8(a) shows the configuration of the high-voltage generating circuit according to the present invention;

[0095] Figure 8(b) shows another configuration of the high-voltage generating circuit according to the present invention;

[0096] Figure 9 A circuit configuration for providing a high-voltage scan to a specific gate of a sensor is shown;

[0097] Figure 10 Another circuit configuration for supplying voltage to a specific gate of the sensor is shown; and

[0098] Figure 11 The use of a quenched resistor according to this instruction is shown. Detailed Implementation

[0099] Now refer to Figure 1 Describe the current invention. Figure 1 An overview of a system 100 capable of measuring the ion energy distribution arriving at the surface of a wafer probe 101 during plasma processing is provided. In this particular illustration, the diagnostic system 100 includes an analog wafer probe with an integrated ion energy analyzer, electronic control circuitry, battery power, and wireless communication. The diagnostic system also includes an extension docking station 102 with an integrated wireless transceiver 103 for charging, configuring, and retrieving data from the analog wafer probe 101. The extension docking station 102 is equipped with an Ethernet connection for communication with a host PC 104. Application software is provided to display and analyze the retrieved data. The application software provides a control panel for scheduling experimental tasks. A high-level programming interface (API) is also provided to allow direct interaction between the extension docking station and the factory control software.

[0100] The four-chamber plasma processing system 105 is also like this. Figure 1As shown. This is one of many different types of plasma processing systems used to illustrate the function of the simulated wafer probe 101 according to the present invention. The plasma processing system 105 may have one or more interconnected processing chambers 106. Each processing chamber 106 is equipped with a vacuum pump for evacuating the processing chamber, a gas flow control device for setting the processing recipe, a vacuum gauge and sensors for regulating the processing operating pressure, a power delivery mechanism for exciting the chemical recipe to a plasma state, and a pedestal for fixing the substrate during processing. A load-locking chamber 108 with a machine transfer mechanism 107 is used for transporting the substrate to and from the processing chamber. Batches of substrates are transported to the load-locking chamber 108 via a cassette or FOUP.

[0101] In a preferred embodiment, wafer probe 101 is placed in extension base 102 and communicates with it via application software on host PC 104. The battery power on wafer probe 101 is charged, stored data is retrieved, and the next experimental task is scheduled to charge and discharge wafer probe 101. The simulated wafer probe 101 is then placed in an available slot in a FrontOpening Universal Pod (FOUP), which is subsequently conveyed to load-locking chamber 108. Robotic arm 107 conveys the simulated wafer probe 101 to processing chamber 106 and positions it on a processing pedestal in preparation for plasma exposure. With chamber 106 already under vacuum, the processing recipe is prepared and plasma is ignited. As plasma is formed, the plasma species begins to bombard wafer probe 101, and its sample enters the sensor of probe 101 for analysis. If the loaded pressure sensor reports that a threshold for high-pressure application has been reached, the analysis will be performed at the time configured in the schedule. This safety mechanism prevents accidental application of high pressure at atmospheric pressure, which could damage the sensor due to arcing. If the pressure threshold is met, the wafer probe 101 is activated at a predetermined time. Appropriate voltages are applied to all gates and collectors, and the collector current is recorded as a function of the ion recognition potential by a microcontroller (MCU) (not shown), with the resulting data stored in memory. The wafer probe 101 returns to sleep mode until the next predetermined measurement, at which point the process is repeated. When the experiment assignment is complete, the plasma processing can be terminated to allow the wafer probe 101 to be removed from the processing base using a robotic arm that transports the wafer probe back to the FOUP via the load-locking chamber 108. The user retrieves the wafer probe 101 from the FOUP and places it back into the expansion base 102 for data retrieval, charging, and scheduling of the next experimental task. Alternatively, the wafer probe can transmit sensor data in real time from its position within the processing chamber to the expansion base using known wireless communication devices and methods.

[0102] The configuration of the wafer probe 101 will now be described in more detail. In a preferred embodiment, the wafer probe 101 may be fabricated on a silicon substrate to simulate a standard semiconductor workpiece. It may also be fabricated on other materials such as ceramic, metal, or glass to simulate other types of substrates used in plasma processing, and may have the same geometry as a standard substrate, with substantially the same size and weight. An example of such a configuration is shown in Figure 2(a), depicting an array of sensors (or sensor stacks) 201 distributed on the surface of the semiconductor wafer probe 101. Specifically, Figure 2(a) shows a plan view of a 300 mm wafer probe 101 with nine sensors 201. Alignment slots 202 are also shown. As will be explained in more detail below, these sensors 201 are preferably ion energy analyzers for measuring the ion energy distribution at the substrate surface of the wafer probe 101.

[0103] Figure 3(a) shows a possible architecture in which each sensor 201 of the wafer probe 101 is modular, with its own dedicated power supply, signal conditioning circuitry, MCU, pressure sensor and wireless transceiver.

[0104] In another configuration, the electronic control circuitry is centralized, and the individual collector current from each sensing element is multiplexed to a centralized measurement circuit, as shown in Figure 3(b).

[0105] The ion energy analyzer 201 is of particular interest for measuring the ion energy distribution at the substrate surface during plasma processing. Turning to Figure 2(b), it can be seen that the ion energy analyzer 201 comprises alternating layers of planar, parallel, conductive metal gates and insulators, with the gates systematically polarized to filter out plasma electrons, separate positive ions based on their energy, suppress secondary electron emission, and collect ion currents for measurement.

[0106] In Figure 2(b), the plasma-facing top surface 203 of sensor 201 is flush with the substrate surface and made of the same material. An array of sampling apertures 204 is formed in the top surface 203 through which plasma species enter the device for analysis. The diameter of the sampling apertures 204 can be submillimeter and must provide sufficient open area to provide sufficient charged particle flux for detection. As plasma begins to form in the processing chamber, a plasma sheath forms near the substrate surface and all other surfaces exposed to the plasma. A voltage applied to the sheath is used to manipulate the ion energy reaching the substrate surface. The presence of sensor apertures 204 may suppress localized sheath formation near the apertures. The size of any aperture exposed to the plasma should be smaller than the plasma Debye length (λ). D This allows for the formation of a sheath above the aperture, preventing plasma from penetrating the aperture. λ DThe following formula can be used to calculate:

[0107] (1)

[0108] Where ε₀ is the vacuum permittivity, kT e It is the electron temperature, n e Here, e is the electron density, and e is the electron charge. Under typical plasma processing conditions, the electron temperature is 3 eV, and the electron density is 10-1. 17 m -3 The sub-Debye length is approximately 40 micrometers. Therefore, an aperture typically measured in millimeters may not meet the sub-Debye length standard on its own.

[0109] In the embodiment shown in Figure 2(b), the first conductive gate (or gate), hereinafter referred to as G0, is connected to the bottom surface of the aperture 204 via a good electrical connection between the two surfaces. The gate G0 is manufactured with an Adby length aperture size to ensure plasma shielding and has a sufficient open area ratio to transmit sufficient ion flux for detection.

[0110] In another embodiment, G0 can be connected to the plasma-facing side of the hole to achieve the same function as shown in Figure 2(c).

[0111] In an alternative embodiment, aperture 204 is fabricated directly in a surface having an Adeby length dimension and a sufficient number of plasma-facing surfaces to maintain adequate ion flux for detection, thereby eliminating the need for a separate GO. This embodiment is illustrated in Figure 2(d).

[0112] In each of the configurations 2(a), 2(b), and 2(c), G0 employs the same potential as the wafer probe body, which is determined by the excitation potential applied to the processing substrate and the plasma characteristics. This potential serves as a reference potential for the sensor circuitry and the electric field formed between the gates.

[0113] A first insulating layer 205 is disposed close to G0 to provide electrical isolation from other gates (e.g., G1, G2, and G3). The insulating layer 205 may consist of one or more insulators. The insulators may have an aperture array that matches the ion sampling aperture array to allow ions to pass through unimpeded. The insulators may also have a single large-diameter aperture whose opening region spans the entire aperture array.

[0114] Figure 4(a) illustrates a suitable insulating layer structure. The insulating layer 205 is stepped, protruding further in the central region and recessed at its contact points with adjacent gates. That is, the insulating layer includes a peripheral portion with decreasing thickness relative to the remaining portion of the insulating layer. The design of the insulating layer structure should ensure the shortest path along the insulating surface between adjacent gates, also known as the creepage distance (d). creep ), greater than the voltage flashover distance (d) of the insulating material. flash Therefore, as shown in Figure 3, d creep The maximum potential difference applied between the gates is predetermined. Although the distance between the gates across the air gap region is short, there is no voltage breakdown issue because the sensor will operate at low voltages, where the breakdown voltage across the air gap is tens of kilovolts, as defined by Paschen's law. The thickness of the insulating layer 205 is in the millimeter or sub-millimeter range, depending on the application, and is typically several hundred micrometers. The total ion transport distance through the analyzer should be less than the ion mean free path to avoid collisions and thus maintain the integrity of the measured IED.

[0115] Figure 4(a) shows the protruding central region for extending the path length. As shown in Figure 4(b), the same result can be obtained using a slightly different structure. That is, Figure 4(b) shows another configuration of the insulating layer to prevent voltage flashover between the gates, which depends on two protrusions on the periphery of the insulating layer and a recess between the two protrusions.

[0116] The protruding portions in Figures 4(a) and 4(b) can be considered as tongues, while the recessed portions can be considered as grooves. Each embodiment may include multiple tongues and / or grooves to achieve the same effect.

[0117] It should be understood that the present invention is not limited to the stepped insulating layer described above with reference to Figures 4(a) and 4(b). The gate stack can operate without the stepped insulating layer. However, to operate at high voltages, the spacing between the gates must be increased. Furthermore, the stepped insulating layer can also be used in the previously described wired IED analyzers. It is suitable for analyzers that do not include an integrated power supply, i.e., analyzers that receive power from an external power source. Adding a stepped insulator can extend the energy range without sacrificing the pressure range. Alternative shapes with a stepped configuration can also be used, which also provide a reduced thickness in the peripheral portions or regions of the insulating layer.

[0118] Returning to Figure 2(b), a second gate (hereinafter referred to as G1) is disposed near the first insulator 205 and has the same or similar geometry to G0 in terms of aperture size and opening area ratio. G1 is coupled to a first voltage source and negatively biased relative to G0, thereby generating a decelerating electric field required to repel incident plasma electrons. A second insulating layer 206 having the same or similar dimensions as the first insulating layer is disposed near G1. A third gate (hereinafter referred to as G2) having the same or similar geometry as the other gates is disposed near the second insulating layer. G2 is coupled to a second voltage source and positively biased relative to G0, thereby generating an electric field required for ion energy discrimination. A third insulating layer 207 having the same or similar dimensions as the other insulating layers is disposed near G2. A fourth gate (hereinafter referred to as G3) is disposed near the third insulating layer 207 and has the same or similar geometry as the other gates. G3 is coupled to a third voltage source and negatively biased relative to the collector, thereby generating an electric field required to suppress secondary electron emission from the collector. A fourth insulating layer 208, having the same or similar dimensions to the other insulating layers, is positioned near G3. An ion collecting electrode, the collector C, is positioned near the fourth insulating layer 208. The collector is coupled to a fourth voltage source via a current measurement circuit and negatively biased relative to G0 to establish an attractive electric field, drawing ions to the collector for detection. A final insulating layer 209 is positioned between the collector electrode and the backplane of the sensor chassis. The gate is typically made of a metal such as nickel or stainless steel, but any other processing-compatible conductive material may be used. The insulator is typically made of ceramic, mica, or other processing-compatible insulating materials.

[0119] Returning to Figures 3(a) and 3(b), it can be seen that signal conditioning provides voltage sources for each gate G1, G2, and G3, as well as the aforementioned collector. The voltage supplied to G2 is variable. Regarding Figure 8 and... Figure 9 This describes a more detailed configuration for generating the voltage supplied to G2. However, it should be understood that any known signal conditioning circuitry combined with a battery can be used to provide a variable voltage to the gate G2.

[0120] According to the invention, a key feature of this invention is the integration of all electronic circuitry within a carefully constructed Faraday cage near the ion energy analyzer (gate stack) 201, wherein the G0 gate is electrically connected to and forms part of a continuous conductive shield that completely encloses the ion energy analyzer stack, control electronics, and battery, as shown in Figure 5(a). Specifically, Figure 5(a) shows a cross-sectional view of the wafer probe 101 through a diameter (not to scale). Figure 5(a) shows the Faraday cage surrounding the sensor or ion energy analyzer 201 and the associated electronics, including a power supply (not shown). Figure 5(a) shows the machined cavity in which all electronic components are mounted.

[0121] In Figure 5(a), the Faraday shield is shown relative to the silicon substrate. For silicon, an additional conductive layer (metal) 501 is added within the structure to create the Faraday shield. Once the gate stack and circuitry are mounted in the substrate, a cover (cap or backplate) is used to seal it. For a silicon cap, a metal layer will be present on one side to form the Faraday shield.

[0122] The substrate does not need to be silicon; it can also be a metal. In this case, it will be processed in the same way, but without the need for an additional Faraday shielding layer. This looks essentially similar to the configuration in Figure 5(a), without the additional conductive layer 501. The substrate itself will act as the Faraday shield. In this case, the cover is a metal layer made of the same material as the substrate. Typical metals that may be used include aluminum, stainless steel, and nickel.

[0123] The Faraday shield floats at the same potential as its surface and serves as the reference potential for all electronic circuitry within it. The Faraday shield prevents the formation of unwanted electric fields within the ion energy analyzer gate stack 201 due to electromagnetic interference, which could distort IED measurements.

[0124] In existing designs, Faraday shielding cannot be perfectly maintained when the control electronics are in a remote location. Cables must be connected between the analyzer and the remote location to transmit electrical signals. This is a significant problem for RF bias applications. For precise operation, all gates within the ion energy analyzer structure must float at the RF bias potential. Once the Faraday shielding is compromised due to connection to the remote location, the gates will decouple from the RF bias potential. Unlike the infinite ground impedance in fully Faraday shielded embodiments, wired gates have finite ground impedance. Gahan et al., mentioned earlier, described a solution in their 2008 publication. First, a high-impedance low-pass filter is connected in series with all cables, positioned between the analyzer gate and the remote location, as close to the gate as possible. Second, the capacitance between each gate and the aperture surface is maximized to optimize RF coupling. These requirements make remote designs difficult to implement; the gates can never be perfectly coupled to the RF bias, and the filter impedance can never be infinitely large to prevent parasitic loads on the base impedance.

[0125] This invention avoids these design complexities by removing wiring, ensuring a near-perfect floating solution that closely matches the conditions at the substrate when using unobstructed silicon.

[0126] In existing technology designs, the control electronics and power supply are fully integrated into the analog wafer probe, which can lead to the formation of unwanted electric fields that distort IED measurements.

[0127] Returning to Figures 2(b) and 2(c), the aperture 204 is fabricated on the plasma-facing surface of the wafer probe 101 substrate and forms the upper surface of the ion energy analyzer 201. In one embodiment, the substrate is a silicon wafer with a diameter of 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm, but any other material, geometry, or size may be used in the fabrication of the wafer probe, depending on application requirements. The simulated wafer probe 101 may include a single-point measurement sensor 201 or a plurality of spatially distributed measurement sensors 201.

[0128] To fabricate the analog wafer probe 101, a base substrate with the desired geometry and dimensions is machined to form cavities therein for mounting sensing and electronic components. In one embodiment, the circuit package outline and components are directly disposed on the base substrate. In another embodiment, the circuit package outline and components are disposed on separate panels and mounted in machined cavities within the base substrate and held in place. A conductive plane is disposed on the bottom surface of the wafer probe aperture plane, a portion of which is formed by GO elements for plasma shielding. Alternating gate and insulating layers are formed independently in each individual ion energy analyzer field. In one embodiment, the ion energy analyzer 201 is a replaceable component mounted on the wafer probe assembly, which necessarily increases the height of the analog wafer probe 101 but is more convenient. In another embodiment, the ion energy analyzer 201 is a permanently integrated part of the analog wafer probe 101 and is not replaceable, allowing for the fabrication of a lower profile wafer probe 101. The gate and insulator are mechanical components placed and held in place. One manufacturing method involves embedding layers into a ceramic-based printed circuit board (PCB) using PCB manufacturing technology. Another manufacturing method involves printing gate and insulating layers using thick-film printing technology. Electronic circuitry is arranged near the ion energy analyzer gate stack. Electronic components, in bare mold form, are connected to positions via wires, if necessary and subject to given height limitations. Sealing compounds are used to seal components to prevent outgassing during plasma processing. Once the probe assembly is assembled, the wafer probe 101 is sealed on the back side with a suitably manufactured wafer or panel to complete the manufacturing. A conductive metal layer may be disposed on the inner plane of the packaged wafer or panel to complete the previously described Faraday shielding, or the Faraday shielding may be completed on the mounted component board.

[0129] A small battery powers the electronic control system. The battery is rechargeable, but not limited to this configuration. A pressure sensor can be incorporated, serving as a safety mechanism to indicate when it is safe to output high voltage to the gates. At atmospheric pressure, several hundred volts can cause electrical breakdown between the gates due to typical separation. Before initiating high-voltage output, the pressure sensor indicates when the pressure drops to a safe level defined by the Paschen curve. Once the pressure drops, it can be safely assumed that the wafer probe 101 is located in the plasma chamber and under vacuum. A microcontroller with an integrated flash memory module and analog-to-digital converter (ADC) controls the signal conditioning circuitry, records the ion current as a function of the identification voltage, stores the data in memory, and configures the wireless transceiver for data transmission.

[0130] Accurate measurement of the ion energy distribution reaching the substrate surface during plasma processing is crucial for processing analysis and control. The ion energy analyzer 201 described in this invention provides such a measurement. The ion energy analyzer sensing element 201, including the aforementioned gate stack, is configured with an electric field distribution suitable for ion energy distribution measurement. The preferred potential configuration and basic operating principle are as follows: Figure 6 As shown. G1 is biased with a constant negative potential relative to G0. This generates an electric field that repels plasma electrons entering the analyzer. G2 is biased with a positive voltage scan to reflect ions with higher energies in turn. At each voltage step within the scan, only ions with sufficiently high energy can pass through the detector. At each step of the voltage scan, the ion current reaching the collector is recorded. This provides a current-voltage characteristic equivalent to the integral form of the ion energy distribution.

[0131] Figure 6 The potential diagram of the gate is shown, where G0 is the reference, G1 is negative, and it repels electrons. G2 starts at 0V and sweeps across the positive electrode, gradually repelling ions with increasingly higher energies. G3 is negative to suppress secondary electrons emitted from the collector. The collector is slightly negative to attract ions for detection.

[0132] Taking the first derivative of the current-voltage characteristics to reveal the ion energy distribution, such as... Figure 7 As shown. A more scientific and correct name for this distribution is "ion current and energy distribution," but it is referred to as ion energy distribution in published literature.

[0133] in particular, Figure 7 The figure above shows the relationship between the ion current applied to the gate G2 and the voltage. This generates the integrated output of the IED. Figure 7 The chart below shows the first derivative of the top curve of the synthesized IED. The X-axis converts voltage to energy.

[0134] Another feature of the invention is the method and configuration for generating a sufficiently high G2 voltage scan range to adequately measure IEDs found in common plasma processes. Many plasma processes encountered produce ions with energies ranging from tens to thousands of electron volts. This necessitates extending the G2 voltage scan range from zero volts relative to G0 to adequately detect IEDs in a variety of industrial processes.

[0135] However, it should be understood that the configuration described herein for powering the gate G2 need not be used to provide the previously described voltage scan to the gate G2. Instead, a known battery-powered power supply can be used, and other features of the invention can be used in conjunction with such a known battery-powered power supply.

[0136] Figure 8(a) illustrates a general configuration of a high-voltage generation circuit 800, which can be used to generate the required high-voltage scan. The circuit comprises two stages: receiving the low voltage from the battery and generating the required high-voltage scan. See below for further details. Figure 9 and Figure 10 Describe the specific details of the possible configurations for each stage. However, it should be understood that each stage is not limited to... Figure 9 and / or Figure 10 Details.

[0137] In Figure 8(a), the circuit includes a low-voltage power supply B1, a high-voltage pulse generator 801 (first stage), and a voltage multiplier 802 (second stage). The voltage multiplier 802 is also referred to in the art as a charge pump. The high-voltage pulse generator 801 provides a sequence of high-voltage pulses to the voltage multiplier 802. The voltage multiplier 802 uses the pulse sequence to charge a series of internal capacitors to charge the output to a multiple, typically 4 to 5 times, of the pulse voltage from the pulse generator 801.

[0138] It should be understood that the high-voltage generating circuit may be included in the signal conditioning circuit outlined with respect to Figures 3(a) and 3(b). It should also be understood that the battery manager circuit shown in Figures 3(a) and 3(b) (explained in more detail below) may be provided in circuit 800. The battery manager circuit regulates the battery output voltage to a fixed voltage level. In an exemplary embodiment, the low-voltage power supply may be a single-cell LiPo battery with a 3VDC regulator.

[0139] The circuit in Figure 8(a) generates a voltage scan starting from zero and gradually increases to a maximum value, i.e., voltage scan increment. As the scan increases, the ion current is sampled. However, it has been found that a rapid rise and slow release of voltage improves battery performance, meaning less power is drawn from the battery with each scan. Therefore, the sensor can be used for a longer period before the battery needs to be replaced or recharged.

[0140] Figure 8(b) shows a high-voltage generating circuit 900, used to rapidly ramp up the voltage to its maximum level and then slowly sweep it back to zero. It is very similar to the circuit in Figure 8(a), but requires some additional components, as shown in Figure 8(b). A discharge resistor R1 is added to control the discharge rate of the voltage sweep, i.e., the timing. When the voltage sweep is applied to V... G2 Previously, a discharge switch S1 was added to discharge V. G2 In other words, the switch between the high-voltage output of G2 and the floating ground is used to discharge G2 immediately before the voltage scan process begins. The ion current is sampled as the voltage decreases.

[0141] In an exemplary embodiment, circuit 900 allows V G2 Fast charging to slightly above 2kV within 5 milliseconds, then allowing V G2 The discharge is slow and continuous through R1 for up to 1 second.

[0142] In another configuration of the high-voltage generation circuit, a battery-powered microcontroller (the microcontrollers in Figures 3(a) and 3(b)) is programmed to output a sinusoidal AC voltage that sweeps across a series of frequencies. The output is coupled to the primary winding of a step-up transformer. The number of turns in the secondary winding is selected to raise the voltage to the maximum level required for a specific frequency applied to the primary winding input. At the secondary winding output, the voltage is rectified to produce a direct current (DC) voltage, which can be coupled to a voltage multiplier (second stage) to further multiply the voltage, thereby increasing the voltage range as needed. The DC voltage generated at the secondary winding output is frequency-dependent. By scanning the frequency and / or amplitude of the AC signal applied to the primary winding, the DC voltage at the secondary winding or multiplier output is scanned across the desired voltage range, from zero volts to several kilovolts, depending on the transformer turns ratio used. During the high-voltage scan, an onboard digital analog-to-digital converter (ADC) samples the current with regular voltage separation to establish a current-voltage characteristic. This method is as follows: Figure 9 As shown, but will be explained in more detail below. It should be understood that although a four-stage voltage multiplier (quadrupole) is used in the exemplary embodiment, those skilled in the art can select any number of stages as needed.

[0143] In another method or configuration for generating voltage sweeps, the principles of boost conversion and / or charge pumps can be applied. A hybrid solution is provided, but it should be clear that various variations of current technology can be applied. Figure 10This describes the circuitry used to generate a high-voltage sweep using this technique. A battery delivers a 3V output to the input of a low-profile DC-DC converter to boost the voltage to approximately 80V. The 80V signal is coupled to a voltage multiplier circuit via a series boost inductor and diode (boost circuit). A field-effect transistor (FET), controlled by a pulse-width modulation (PWM) signal, is coupled to the system floating ground after the series diode to modulate the 80V supply and drive the voltage multiplier circuit. At the input of the voltage multiplier circuit, the boost circuit has already boosted the voltage to approximately 250V, but the voltage may be higher depending on the application requirements. In this example, the voltage multiplier has four stages, but more stages can be used to provide progressively higher voltages. Each voltage multiplier stage has a typical design where each stage increases the voltage applied to the input. After a sufficient number of cycles of the PWM signal, the first capacitor C1 will charge to its maximum level of 500V. Similarly, C3 will reach 1000V, C5 will reach 1500V, and C7 will reach 2000V. At each stage, a series of diodes are configured to prevent the charge storage capacitors from discharging during the PWM off state, thus providing the "multiplication" effect required to generate the high-voltage scan. During the high-voltage scan, an ADC is used to sample the ion current at regular voltage separations to establish the current-voltage characteristics.

[0144] The following text provides Figure 10 A more detailed explanation of how the high-voltage generating circuit works accurately.

[0145] Regardless of the mechanism used to generate the high-voltage scan, the ion current can be sampled as the voltage applied to G2 rises and / or falls. If the scan is a step function, the current is sampled at each voltage step. If the scan is continuous, the current is sampled continuously to record the number of samples (N), the sum of current values, the sum of the squares of current values, the sum of voltage values, and the sum of the squares of voltage values, thereby allowing the average value and slope of all points in the selected bin to be recovered.

[0146] When the analog wafer probe is in idle mode, the ion current flowing into the analyzer can cause undesirable charging of G2. A switch between the high-voltage output and floating ground of G2 is used to discharge G2 immediately before the voltage scan process begins. The collector is negatively biased relative to G0 to attract incoming ions, ensuring they reach the collector for detection. The collector current flows through a measurement circuit where it is sampled and digitized as a function of the voltage applied to G2 using a high-speed ADC.

[0147] G3 is relative to the negative bias voltage of the collector, such as Figure 6As shown, any secondary electrons emitted from the collector surface due to ion collisions are repelled back to the collector. Otherwise, escaped electrons would be considered as additional ions detected in the measurement circuit, thus distorting the measurement of the IED. The IED, or as previously described, the ion current and energy distribution, is represented by the following equation.

[0148] ...(2)

[0149] Where f(v) is the ion velocity distribution, M i It is the ionic mass, T eff It is the effective transmission of the gate stack, A is the area of ​​the sampling aperture, and I is the effective transmission of the gate stack. C It is the collector current, V G2 This is the ion energy recognition voltage applied to G2. When plotting, it is multiplied by the electron charge in eV. G2 The discriminator voltage can be easily converted into ion energy. However, the ion current is still a function of ion velocity. Therefore, this is not a true ion energy distribution, but rather a relationship between ion current and energy distribution. Nevertheless, the measured distribution is more important for plasma processing because the two key parameters driving the process are ion current (also known as ion flux) and ion collision energy at the surface. It should be noted that the ion energy referred to is the energy perpendicular to the substrate surface.

[0150] As mentioned above Figure 1 Once the simulated wafer probe 101 is transferred to the processing base and the chamber pressure criterion is met, the IED scan will proceed as planned. Each IED measurement is stored in the flash memory module of the microcontroller. Once the experimental task is complete, the robotic arm transfers the IWP from the processing base to the FOUP, where it can be removed by the user. It is then placed in the extension base for data retrieval. The transponders on the wafer probes communicate wirelessly with the extension base using RF or IR technology. There may be a centralized wafer probe repeater for transmitting data from all sensors, or there may be localized wafer probe repeaters for transmitting data from each sensor individually. The transponders are located near the IWP backplane. For each transponder, a small gap is formed in the Faraday shield of the simulated wafer probe 101 to allow the wireless signal to be detected by the transceiver in the extension base aligned with the wafer probe transponder. This configuration can be seen in Figures 5(a) and 5(b). Specifically, Figure 5(a) shows only the use of RF communication, while Figure 5(b) shows the wafer probe 101 configured for both RF and IR communication. Of course, the wafer probe 101 can also be configured for IR communication only. In practical applications, people have found that infrared communication is much faster than radio frequency communication.

[0151] The transceiver serves a dual purpose: providing a wireless charging path for the wafer detector battery. The form factor of the extension base can be designed to closely resemble any standard wafer or substrate carrier for easy access to cleanroom environments. The extension base transceiver is controlled by a microcontroller, which in turn is controlled by a computer embedded in the extension base. Data retrieved from the wafer probe 101 is stored in a database on the computer, and for convenience, the user can access this data via an Ethernet connection. A web browser is used to interact with the extension base computer to configure and charge the sensors and export data from the database. The application displays time-ion current versus energy curves for a single-point wafer probe, as well as spatiotemporal ion current versus energy curves for multi-point wafer probes, to determine the time-varying and / or spatial uniformity of wafer surface treatment for each experimental task. Multiple high-level programming interfaces (APIs) can also communicate with the extension base using various industry protocols, such as the SECS / GEM protocol commonly used in the semiconductor industry.

[0152] As previously mentioned, the ion energy analyzer 201 requires an appropriate high-voltage scan signal to G2 for proper operation. To operate within the complex environment of the plasma processing chamber, the high-voltage circuitry and physical sensors must be encapsulated in Faraday shielding to prevent electromagnetic interference, as shown in Figure 5(a). Once the plasma is ignited, it provides an ion current source to the wafer probe surface. This charges the gate surface within the ion energy analyzer when the wafer probe 101 is in idle mode. Therefore, before each ion energy scan is performed, the output of the high-voltage scan generator circuit must include a high-voltage switch to discharge G2 to the wafer floating ground.

[0153] The wafer probe can be a silicon wafer design, with stringent requirements on wafer thickness, meaning a height of less than 3mm or 4mm is necessary for mounting into the main processing chamber through the transfer chamber window. The wafer probe can also be fabricated on certain alternative substrates that do not have these height limitations for other applications. Therefore, depending on height limitations, required scan voltage profiles, and power consumption constraints, the high-voltage scan generator can be configured in two different ways.

[0154] Figure 9 and Figure 10 A circuit variation for generating a high-voltage DC scan generator from a low-voltage DC power supply is shown. In an exemplary embodiment, the low-voltage DC power supply may be a low-voltage solid-state battery with a DC voltage output range of 2.75V to 4.5V. A battery manager is used to prevent overcharging and over-discharging of the battery. It is configured to disconnect the battery when the voltage is depleted below a certain threshold. This, in turn, disconnects the power supply to the main circuitry. Power to the main circuitry will not be restored until the battery voltage has charged above the threshold level. The battery manager also draws charging power from an RF antenna (which forms part of the receiver in the extension dock).

[0155] The battery manager circuit also regulates the battery output voltage to a fixed voltage level, which is 3.2V in this exemplary embodiment. Figure 9 The high-voltage generating circuit shown includes a low-to-high-voltage transformer (T1) (first stage), which supplies power to a voltage multiplier (second stage). The voltage multiplier is a Cocroft-Walton type voltage multiplier circuit consisting of capacitor elements C1, C2, C3, and C4, and diode elements D1, D2, D3, and D4. A low-voltage AC signal is generated on the primary side of T1 using an H-bridge switch. An H-bridge, or any similar switching topology, is used to allow bipolar current to flow from a single-rail power supply through the primary winding of T1. The frequency and amplitude of the AC signal are controlled by a microcontroller. The 1:N turns ratio transformer T1 generates a high-voltage AC signal on the secondary side. During the positive half-cycle, C2 is charged through C1 and D2, and C4 is charged through C1, C3, and D4. During the negative half-cycle, C1 is charged through D1, and C3 is charged through C2 and D3. After a predetermined number of AC cycles, the voltage across all capacitors is equal, and VG2 reaches a maximum level four times the voltage across C2. Clearly, by controlling the frequency and amplitude of the AC signal applied to the primary winding of T1, VG2 can be gradually increased from zero to its maximum value. Therefore, a typical incremental voltage ramp (sawtooth or step function) for driving ion energy discrimination in a deceleration field analyzer can be achieved. Once the maximum voltage in the voltage scan is reached and the generated ion current is measured, the AC voltage applied to the primary winding of T1 is turned off to reset VG2 to zero, preparing for the next voltage scan. At this time, switch S1 also closes to help G2 and the capacitor discharge rapidly.

[0156] Although Figure 9 The voltage scan curve generated by the circuit shown is similar to that commonly used in wired deceleration field analyzer designs, but it may not be suitable for all types of analog substrate probes. A limiting factor is the transformer's height profile. Off-the-shelf transformers that meet the requirements do not have a sufficiently low profile to fit analog silicon wafer probes; for example, their maximum total height is limited to 3mm to 4mm, with a required height of <1mm. While such a transformer could be designed, the cost would likely be prohibitively high.

[0157] An alternative solution was designed to meet the following requirements. Figure 10 The height requirement is shown.

[0158] Battery and battery manager components such as Figure 9As shown. The battery manager powers a readily available, lightweight DC-DC converter with an integrated voltage multiplier to boost the DC voltage to 80V. The high-voltage generation circuit consists of a boost section and a subsequent voltage multiplier section. The boost section is a typical DC-DC boost converter topology, using an inductor L1, a MOSFET transistor Q1 (turned on and off via a pulse width modulator), a diode D2, and a capacitor C1. This makes the voltage across the circuit load C1 greater than the DC-DC output voltage of 80V in the exemplary embodiment. The multiplier section is connected to... Figure 9 The circuit for the Croft-Walton voltage multiplier is very similar, with capacitors C2, C3, C4, C5, C6, and C7, and diodes D3, D4, D5, D6, D7, and D8. It is similar to... Figure 9 Compared to the circuit, Figure 10 The circuit generates a voltage scan in a different way. Instead of gradually increasing the voltage from zero to the maximum value, the circuit is used to quickly ramp up the voltage to the maximum value and then slowly sweep it back to zero. However, it can also be used to gradually scan the voltage from zero to the maximum voltage.

[0159] Those skilled in the art will understand that the present invention is not limited to MOSFET transistors. Rather, any suitable transistor, such as a bipolar transistor, can be selected.

[0160] For the operation of the ion energy analyzer 201, it is not important whether the voltage scan applied to the gate G2 rises from zero to a maximum value or falls from a maximum value to zero. However, this method of generating a voltage scan using a rapid rise and slow discharge (falling voltage scan) is more efficient than... Figure 9 The continuous mode consumes much less power. Figure 9 The method described above gradually increases the voltage from zero to its maximum. It should be noted that... Figure 9 The circuit can be Figure 10 The discontinuous mode described herein allows the voltage to rapidly increase to its maximum value before slowly discharging back to zero. As will be apparent to those skilled in the art, this would require the addition of a discharge resistor R1, as shown in Figure 8(b) and Figure 10 A more detailed description.

[0161] because Figure 10 The circuit shown operates discontinuously, so D1 is added to prevent current from flowing back to the floating ground through L1 from C2 after the energy stored in L1 is depleted.

[0162] Switch S1 connects the boost circuit to the 80V output of the DC-DC converter. S1 remains closed when VG2 is charged to its maximum level. The switching rate of MOSFET transistor Q1 is controlled by the microprocessor output. When Q1 is open, C1 charges from the 80V output of the DC-DC converter and the energized inductor through D1 and D2. Then C3 is charged from C2 through D4, C5 from C4 through D6, and C7 from C6 through D8. When Q1 is closed, L1 is energized by the current flowing from the DC-DC converter through Q1 to the floating ground. Due to the closure of Q1, the voltage between capacitors C2, C4, and C6 relative to the floating ground decreases and becomes lower than the voltage between capacitors C1, C3, and C5, respectively. Now, C2 is charged from C1 through D3, C4 from C3 through D5, and C6 from C5 through D7. When the boost stage operates in discontinuous mode, the energy (E) stored in L1 is given by the following formula.

[0163] ,

[0164] V is the voltage across L1, T on Q1 is the duration the transistor switch is closed, and L is the inductance of L1. After multiple Q1 switching cycles, the voltage across all capacitors becomes equal to achieve the desired maximum VG2. In this example, VG2 is approximately four times the voltage across C1. More stages can be added as needed to increase VG2. Once the maximum VG2 is reached, switch S2 closes to initiate VG2 discharge, slowly reducing it to zero volts. Resistor R1 is placed in parallel with S2. The combination of R1 and the capacitor sets the VG2 discharge scan rate.

[0165] Figure 10 The voltage multiplier (stage 2 of the high-voltage generation circuit) has two parallel capacitor strings (C1, C3, C5, and C7) and (C2, C4, and C6). When transistor switch Q1 is open, the multiplier input is high, charging C1, C2 charging C3, C4 charging C5, and C6 charging C7. When Q1 is closed, the input is low, charging C1 charging C2, C3 charging C4, and C5 charging C6. Switch Q1 repeatedly turns on and off, ensuring that the charging voltage of all capacitors equals the input voltage. Therefore, the output VG2 is four times the input voltage. Considering efficiency, using the voltage multiplier directly from an 80V line will produce a maximum voltage of approximately 300V.

[0166] To further increase the voltage, a boost circuit is placed before the voltage multiplier. Energy is stored in inductor L1 and transferred to capacitor C1, where diode D1 prevents energy from returning to the input via the inductor. The input to the boost circuit is 80V. When the transistor is turned on, the inductor is short-circuited to ground, increasing the inductor current and storing energy. When the transistor is turned off, the current continues to flow through the inductor to capacitor C7 via D8 and D1. The voltage across capacitor C7 increases with the amount of energy stored. With an input voltage of 80V, a MOSFET transistor shorts the inductor and voltage multiplier input to ground. The transistor releases after a few microseconds, generating the current required to achieve the charge pump effect, producing the maximum voltage VG2.

[0167] Those skilled in the art will understand that the voltage values ​​provided with respect to the exemplary embodiments of Figures 8(a), 8(b), 9, and 10 are merely exemplary. The invention should not be construed as being limited to these values. Rather, these circuits can be configured as needed to provide the required voltage.

[0168] about Figure 11 Another advantageous feature of the invention is illustrated. The figure shows a schematic diagram of short arc 1001 or plasma formation between the gates of the ion energy analyzer 201. In practice, this is found to be most likely to occur between G2 and one gate on either side. However, it can occur between any two gates. There are several reasons for this phenomenon. Paschen's law states that, under ideal conditions, a high voltage on G2 should not cause electrical breakdown between gates using a spacing within the relevant pressure range. However, microscopic particles can enter from plasma or sputter from the gate surface and can trigger a sudden arc 1001 or a brief plasma impact.

[0169] If a breakdown occurs, G2 may suddenly discharge to one of the other gates. This sudden discharge could also last for a longer period by drawing an unlimited amount of current from the battery. If a discharge occurs, the G2 voltage (and the accumulated energy) immediately discharges, rendering the scan invalid.

[0170] To address the issue of arcing between the gates, a set of current-limiting resistors 1002 is added in series with the gates to immediately stop a breakdown event in the event of a breakdown. The resistors are placed between the gates and the power supplies for each gate. This also prevents sudden discharge of the G2 power supply, thus preventing scan data loss.

[0171] It should be understood that it is not necessary to provide Figure 11 The complete set of resistors is shown. For example, only one resistor can be provided between any conductive gate and the corresponding power supply. Since most plasma formation has been found to occur on gate G2, a resistor can be provided only to that gate.

[0172] This function is not limited to use with the high-voltage generating circuits shown in Figures 8(a), 8(b), 9, or 10. This feature can also be used with known sensors that have the integrated power supply described in the prior art.

[0173] Although we discuss IED measurements in this paper, it is clear that the electron energy distribution can also be measured by changing the polarity of the gate potential.

[0174] This invention is not limited to the embodiments described herein, but can be improved or modified without departing from the scope of this invention.

Claims

1. An apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, comprising: A substrate having a first main surface configured to be exposed to plasma; An ion energy analyzer, disposed within a substrate, comprises: A stack of at least four planar conductive gates arranged parallel to the first main surface. Each gate is separated from the adjacent gate by a corresponding insulating layer, and The collector located below the stack; A power module is mounted within a cavity in the substrate, the power module being electrically connected to each gate and the collector via conductive traces; A high-voltage generating circuit is disposed adjacent to the power supply module. The high-voltage generating circuit includes: a converter, a voltage multiplier, and an output terminal connected to at least one of the gates. Multiple resistors, each physically connected in series between a corresponding gate and a corresponding output terminal of the high-voltage generating circuit, wherein each resistor is located on a printed circuit board embedded in the substrate and electrically coupled to the gate via wires or conductive vias.

2. The apparatus of claim 1, wherein each resistor is a surface mount assembly soldered to the printed circuit board, and the printed circuit board is encapsulated within a hermetically sealed compartment in the substrate.

3. The apparatus according to any one of claims 1 to 2, wherein the resistors are arranged such that the physical spacing between each resistor and its corresponding gate is less than 5 mm.

4. The apparatus according to any one of claims 1 to 3, wherein the insulating layer separating the gate comprises ceramic sheets with holes aligned to allow ions to pass through, and the resistor is positioned adjacent to the edge of each ceramic sheet.

5. The apparatus according to any one of claims 1 to 4, wherein the collector is formed as a planar metal plate, and the resistor is radially disposed around the periphery of the plate.

6. An apparatus for obtaining ion energy distribution (IED) measurements in a plasma processing system, comprising: A substrate configured to be placed in the plasma processing system and exposed to plasma; An ion energy analyzer is disposed in a substrate, the ion energy analyzer including multiple conductive gates and collectors, each gate being separated by an insulating layer; A power supply and control circuitry configured to apply a voltage to each of the conductive gate and the collector; A high-voltage generating circuit is configured to scan and supply voltage to at least one of the conductive gates; as well as A resistor, disposed in series between at least one of the conductive gates and the power source, is configured to limit current flow and suppress plasma formation between adjacent gates during operation.

7. The apparatus of claim 6, wherein the resistor is configured to suppress electrical breakdown between conductive gates.

8. The apparatus according to any one of claims 6 to 7, wherein the resistor prevents the discharge of accumulated voltage on the ion energy recognition gate.

9. The apparatus according to any one of claims 6 to 8, wherein a plurality of resistors are provided, each resistor being arranged in series between a respective conductive gate and the power supply.

10. The apparatus according to any one of claims 6 to 9, wherein the resistor is configured to prevent plasma formation between the ion energy recognition gate and an adjacent gate.

11. The apparatus according to any one of claims 6 to 10, wherein the resistor comprises a resistance value sufficient to limit the current below a threshold level during arc formation.

12. The apparatus according to any one of claims 6 to 11, wherein the resistor is integrated within the substrate and electrically coupled to the gate via a printed circuit or wire connection.

13. The apparatus of any one of claims 6 to 12, wherein the resistor is used in combination with a high-voltage switch configured to discharge the gate to floating ground before a voltage scan begins.

14. The apparatus according to any one of claims 6 to 13, wherein the resistor is used in combination with a pressure sensor configured to prevent activation of the high-pressure generating circuit unless a vacuum threshold is reached.

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