A register data transfer system, method, electronic device, storage medium, and computer program product.

Abstract

This disclosure relates to the field of computer and graphics processor technology, and discloses a register data transfer system, method, electronic device, storage medium, and computer program product. The system includes: an instruction issuing module for sending N data transfer instructions, the BL of each data transfer instruction, and the IA of each thread included in each instruction to an instruction control module in parallel; the instruction control module for determining the execution order of the N data transfer instructions, and sending the BL of the currently to-be-executed data transfer instruction and the IA of each thread included in each instruction to a register read / write module according to the execution order; and the register read / write module for executing the data transfer instruction according to its BL and the IA of each thread included in each instruction. This disclosure can realize register data transfer based on indirect addressing, improve the overall timing performance of the register data transfer system, reduce data transfer latency, and increase the flexibility of data transfer.

Description

Technical Field

[0001] This disclosure relates to the field of computer and graphics processor technology, and in particular to a register data transfer system, method, electronic device, storage medium, and computer program product. Background Technology

[0002] In the design of critical computer architectures such as Graphics Processing Units (GPUs), data transfer between their internal registers is required. This can include data transfer between vector registers and scalar registers, between vector registers, and between scalar registers. To improve the flexibility and efficiency of data transfer, inter-register data transfer typically needs to support indirect addressing, meaning that the source and destination operand addresses for each thread in an instruction can be obtained through the contents of the vector registers. However, in common GPU architectures of the present technology, the sending and execution efficiency of data transfer instructions is usually low when performing inter-register data transfer based on indirect addressing, limiting the flexibility and efficiency of data transfer within the GPU. Summary of the Invention

[0003] In view of this, this disclosure proposes a technical solution for a register data transmission system, method, electronic device, storage medium, and computer program product.

[0004] According to one aspect of this disclosure, a register data transmission system is provided, comprising: an instruction issuing module, an instruction control module, and a register read / write module; the instruction issuing module is configured to send N data transmission instructions, the continuous data transmission length BL of each data transmission instruction, and the indirect addressing content IA of each thread included in each data transmission instruction to the instruction control module in parallel, wherein N is a positive integer; the instruction control module is configured to determine the execution order of the N data transmission instructions, and according to the execution order, send the BL of the currently to-be-executed data transmission instruction and the IA of each thread included in the to-be-executed data transmission instruction to the register read / write module; the register read / write module is configured to execute the to-be-executed data transmission instruction according to the BL of the to-be-executed data transmission instruction and the IA of each thread included in the to-be-executed data transmission instruction.

[0005] In one possible implementation, the instruction issuing module includes: at least one instruction count counter and N instruction issuing interfaces, wherein any instruction count counter corresponds to M instruction issuing interfaces, and M is a positive integer less than or equal to N; any instruction issuing interface is used to send the data transmission instruction to the instruction control module when the count value of the instruction count counter corresponding to the instruction issuing interface is greater than a preset abort threshold.

[0006] In one possible implementation, any instruction count counter is used to: after any instruction issuing interface corresponding to the instruction count counter sends a data transmission instruction, decrease the count value of the instruction count counter by a first count value.

[0007] In one possible implementation, any instruction count counter is used to: increment the count value of the instruction count counter by a second count value when a data transmission instruction sent by any instruction dispatch interface corresponding to the instruction count counter is transmitted to the register read / write module.

[0008] In one possible implementation, the instruction control module includes: at least one instruction cache unit, N BL cache units, at least one IA cache unit, an instruction arbitration unit, an instruction-to-be-executed cache unit, and a distribution control unit; the at least one instruction cache unit is used to receive and store the N data transmission instructions; the N BL cache units are used to receive and store the BL of each data transmission instruction respectively; the at least one IA cache unit is used to receive and store the IA of each thread included in each data transmission instruction; the instruction arbitration unit is used to poll and arbitrate the N data transmission instructions to determine the execution order of the instruction-to-be-executed and the N data transmission instructions; the instruction-to-be-executed cache unit is used to store the N data transmission instructions sequentially according to the execution order; the distribution control unit is used to send the BL of the instruction-to-be-executed and the IA of each thread included in the instruction-to-be-executed to the register read / write module.

[0009] In one possible implementation, the instruction control module further includes: a receive sequence counter corresponding to each instruction transmission interface; any one of the receive sequence counters is configured to: when at least one instruction buffer unit receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter, and the count value of the receive sequence counter is less than a first preset threshold, increment the count value of the receive sequence counter by a third count value, wherein the first preset threshold is determined based on a preset value of the instruction quantity counter corresponding to the instruction transmission interface.

[0010] In one possible implementation, any one of the receive sequence counters is further configured to: reset the count value of the receive sequence counter to its initial value when the at least one instruction buffer unit receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter, and the count value of the receive sequence counter is equal to the first preset threshold.

[0011] In one possible implementation, the instruction control module further includes: a processing sequence counter corresponding to each instruction issuing interface; any processing sequence counter is used to: increase the count value of the processing sequence counter by a fourth count value when the processing sequence counter corresponds to the instruction issuing interface corresponding to the data transmission instruction to be executed, and the count value of the processing sequence counter is less than a second preset threshold, wherein the second preset threshold is determined according to the preset value of the instruction quantity counter corresponding to the instruction issuing interface.

[0012] In one possible implementation, any processing sequence counter is further configured to: reset the count value of the processing sequence counter to its initial value when the processing sequence counter corresponds to the instruction transmission interface corresponding to the data transmission instruction to be executed, and the count value of the processing sequence counter is equal to the second preset threshold.

[0013] In one possible implementation, each data transmission instruction includes X thread blocks, each thread block includes at least one thread, and each thread corresponds to its own IA, where X is a positive integer; the register read / write module includes X vector processing units; the distribution control unit is used to send the BL of the data transmission instruction to be executed, and the IA of each thread in a thread block included in the data transmission instruction to be executed, to a vector processing unit, and different vector processing units correspond to different thread blocks included in the data transmission instruction to be executed.

[0014] In one possible implementation, each vector processing unit includes: a source operand address calculation subunit and a read timing control subunit; the source operand address calculation subunit of any vector processing unit is used to determine the source operand address of each thread in the thread block according to the IA of each thread in the thread block corresponding to the vector processing unit; the read timing control subunit of any vector processing unit is used to determine BL source operand read requests of the thread block in sequence according to the source operand address of each thread in the thread block corresponding to the vector processing unit and the BL of the data transmission instruction to be executed, wherein the i-th source operand read request is used to read the i-th source operand of each thread in the thread block, and i is a positive integer greater than or equal to 1 and less than or equal to BL.

[0015] In one possible implementation, each data transfer instruction includes Y threads in each thread block, where Y is a positive integer; any vector processing unit is configured to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, merge and read threads with the same IA in the thread block to determine Z register read requests of the thread block, where Z is a positive integer less than or equal to Y; execute the Z register read requests to determine the i-th source operand of each thread in the thread block.

[0016] In one possible implementation, any vector processing unit is configured to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, if the IA of the (j+a)-th thread in the thread block is the same as that of the j-th thread, determine the j-th register read request, the j-th register read request is used to read the i-th source operand of the j-th thread and the (j+a)-th thread, where j and a are both positive integers, and j+a is less than or equal to Y.

[0017] In one possible implementation, each vector processing unit includes: a vector register read arbitration subunit; the vector register read arbitration subunit of any vector processing unit is used to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, when the source operand address of each thread in the thread block is a vector register address, arbitrate one vector register read request that needs to be executed from the Z vector register read requests of the thread block according to the preset thread priority.

[0018] In one possible implementation, each vector processing unit further includes: a scalar register read arbitration subunit; the scalar register read arbitration subunit of any vector processing unit is used to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, when the source operand address of each thread in the thread block is a scalar register address, arbitrate the preset number of scalar register read requests that need to be executed in parallel from the Z scalar register read requests of the thread block according to the preset thread priority.

[0019] In one possible implementation, the register read / write module further includes: a scalar processing unit, which includes: a scalar register read subunit; a scalar register read arbitration subunit included in any vector processing unit, configured to: send a preset number of scalar register read requests that need to be executed in parallel to the scalar register read subunit; the scalar register read subunit is configured to: generate at least one burst transmission request for each thread block according to all the scalar register read requests that need to be executed currently sent by the scalar register read arbitration subunit included in each vector processing unit; and synchronously execute all burst transmission requests of any thread block.

[0020] In one possible implementation, each vector processing unit further includes a destination register write subunit; the destination register write subunit of any vector processing unit is used to: determine the destination operand address of each thread in the thread block according to the IA of each thread in the corresponding thread block of the vector processing unit; and determine the register write request of each thread in the thread block according to the destination operand address of each thread in the thread block.

[0021] In one possible implementation, the register read / write module further includes: a write-out-preserving unit; the destination register write-out subunit included in any vector processing unit is further configured to: send the vector register write request of each thread in the thread block corresponding to the vector processing unit to the write-out-preserving unit when the register write request of each thread in the thread block corresponding to the vector processing unit is a vector register write request; and send the scalar register write request of each thread in the thread block corresponding to the vector processing unit to the scalar processing unit when the register write request of each thread in the thread block corresponding to the vector processing unit is a scalar register write request; the scalar processing unit is configured to: send the scalar register write requests of each thread block corresponding to each vector processing unit to the write-out-preserving unit respectively; and the write-out-preserving unit is configured to: execute the register write request of each thread in the thread block corresponding to any vector processing unit.

[0022] In one possible implementation, the scalar processing unit includes a scalar register write subunit; the scalar register write subunit is configured to: when any thread block corresponding to a vector processing unit is a thread block that is in a valid state in the data transmission instruction to be executed, send the scalar register write request of each thread in the thread block to the write-preserving unit.

[0023] According to another aspect of this disclosure, a register data transfer method is provided, the method being applied to a register data transfer system, the register data transfer system comprising: an instruction issuing module, an instruction control module, and a register read / write module; the method comprising: using the instruction issuing module to send N data transfer instructions, the continuous data transfer length BL of each data transfer instruction, and the indirect addressing content IA of each thread included in each data transfer instruction in parallel to the instruction control module, wherein N is a positive integer; using the instruction control module to determine the execution order of the N data transfer instructions, and according to the execution order, sending the BL of the currently to-be-executed data transfer instruction and the IA of each thread included in the to-be-executed data transfer instruction to the register read / write module; using the register read / write module to execute the to-be-executed data transfer instruction according to the BL of the to-be-executed data transfer instruction and the IA of each thread included in the to-be-executed data transfer instruction.

[0024] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned register data transfer system.

[0025] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0026] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0027] The register data transmission system of this disclosure includes an instruction issuing module, an instruction control module, and a register read / write module. The instruction issuing module can send N data transmission instructions in parallel to the instruction control module, simultaneously sending the continuous transmission data length BL of each instruction and the indirect addressing content IA of each thread included in each instruction. This eliminates the need to handshake with the instruction control module after sending the data transmission instructions to send the BL of each instruction and the IA of each thread included in each instruction. Therefore, it optimizes the transmission timing of each data transmission instruction, reduces the overall latency of data transmission, increases the data throughput of data transmission instructions, and thus improves the overall timing performance of the register data transmission system. The instruction control module can determine the execution order of the N data transmission instructions and, according to the execution order, sends the BL of the currently to-be-executed data transmission instructions and the IA of each thread included in the to-be-executed data transmission instructions to the register read / write module, achieving intelligent scheduling of data transmission instructions and avoiding execution conflicts between different data transmission instructions and resource scheduling conflicts within the system. The register read / write module can execute the data transfer instruction according to the BL of the data transfer instruction to be executed and the IA of each thread included in the data transfer instruction to be executed, thereby realizing different types of register data transfer based on indirect addressing content; and, based on the flexible setting of the BL, the register data transfer system of this disclosure can flexibly and efficiently handle continuous data transfer of different lengths, enhancing the flexibility of data transfer.

[0028] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0029] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0030] Figure 1 A block diagram of a register data transfer system according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A block diagram of an instruction control module according to an embodiment of the present disclosure is shown.

[0032] Figure 3 A block diagram of a vector processing unit according to an embodiment of the present disclosure is shown.

[0033] Figure 4 A block diagram of a scalar processing unit according to an embodiment of the present disclosure is shown.

[0034] Figure 5A flowchart illustrating a register data transfer method according to an embodiment of the present disclosure is shown.

[0035] Figure 6 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0036] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0037] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0038] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0039] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0040] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0041] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0042] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0043] In the design of critical computer architectures such as Graphics Processing Units (GPUs), data transfer between internal registers is required. This can include data transfer between vector and scalar registers, between vector registers, and between scalar registers. To improve the flexibility and efficiency of data transfer, inter-register data transfer typically needs to support indirect addressing, meaning that the source and destination operand addresses for each thread within an instruction can be obtained from the contents of vector registers. However, in current GPUs, when performing inter-register data transfer based on indirect addressing, the sending and execution efficiency of data transfer instructions is usually low, limiting the flexibility and efficiency of internal GPU data transfer.

[0044] In view of this, the present disclosure provides a register data transfer system that can improve the overall timing performance of the register data transfer system, reduce data transfer latency, and enhance data transfer flexibility. The register data transfer system provided in this disclosure will be described in detail below.

[0045] Figure 1 A block diagram of a register data transfer system according to an embodiment of the present disclosure is shown. Figure 1 As shown, system 100 includes: instruction issuing module 101, instruction control module 102, and register read / write module 103.

[0046] The instruction issuing module 101 is used to send N data transmission instructions, the continuous data transmission length BL of each data transmission instruction, and the indirect addressing content IA of each thread included in each data transmission instruction to the instruction control module 102 in parallel, where N is a positive integer.

[0047] The instruction control module 102 is used to determine the execution order of N data transmission instructions, and according to the execution order, send the BL of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction to be executed to the register read / write module 103.

[0048] The register read / write module 103 is used to execute the data transfer instruction according to the BL of the data transfer instruction to be executed and the IA of each thread included in the data transfer instruction to be executed.

[0049] The specific form of the data transmission instructions can be flexibly set according to actual usage requirements. For example, each data transmission instruction may include 32 threads, with every 8 threads forming a thread block (TB), and including instruction information such as thread identifier information and thread block validity information. This disclosure does not impose specific limitations on this. The number N of data transmission instructions sent in parallel can be flexibly set according to actual usage requirements. This disclosure does not impose specific limitations on this.

[0050] The instruction issuing module 101 can automatically read the continuous transmission data length (BL) of each data transmission instruction and the indirect addressing (IA) of each thread included in each data transmission instruction from an instruction generation device or storage device outside the system 100. When sending N data transmission instructions in parallel to the instruction control module 102, the BL of each data transmission instruction and the IA of each thread included in each data transmission instruction are synchronously sent to the instruction control module 102. This eliminates the need to perform a handshake with the instruction control module 102 after sending the data transmission instructions to send the BL of each data transmission instruction and the IA of each thread included in each data transmission instruction. This optimizes the transmission timing of each data transmission instruction, improves the data throughput of data transmission instructions, and enhances the overall timing performance of the system 100. Optionally, the BL of each data transmission instruction and the IA of each thread included in each data transmission instruction can be synchronously sent according to the sending order of each data transmission instruction, thereby ensuring accurate alignment between any data transmission instruction and its BL and the IA of each thread included in the instruction transmission process.

[0051] The structure of the instruction issuing module 101 will be described in detail later in conjunction with the possible implementation methods of this disclosure, and will not be repeated here.

[0052] After receiving and storing each data transmission instruction, its BL (Blank Line) and the IA (Internal Component) of each thread included in each data transmission instruction, the instruction control module 102 can determine the execution order of the N data transmission instructions through polling arbitration, thereby flexibly scheduling the execution of each data transmission instruction and avoiding conflicts or waste in the use of processing resources. According to the execution order, the instruction control module 102 can send the BL of the currently pending data transmission instructions and the IA of each thread included in the pending data transmission instructions to the register read / write module 103. The specific method by which the instruction control module 102 polls and arbitrates the N data transmission instructions to determine their execution order can be found in related technical implementations, and this disclosure does not specifically limit it.

[0053] The structure of the instruction control module 102 will be described in detail later in conjunction with the possible implementation methods of this disclosure, and will not be repeated here.

[0054] In inter-register data transfer based on indirect addressing, the source operand address and destination operand address of each thread included in the same data transfer instruction may be different. Therefore, the register read / write module 103 can determine the source operand address and destination operand address of each thread included in the data transfer instruction based on the IA of each thread, and then read the source operand and write the destination operand for each thread to complete the execution of the data transfer instruction. This enables different types of register data transfer based on indirect addressing.

[0055] The structure and function of the register read / write module 103 will be described in detail later in conjunction with the possible implementation methods of this disclosure, and will not be repeated here.

[0056] The register data transmission system of this disclosure includes an instruction issuing module, an instruction control module, and a register read / write module. The instruction issuing module can send N data transmission instructions in parallel to the instruction control module, simultaneously sending the continuous transmission data length BL of each instruction and the indirect addressing content IA of each thread included in each instruction. This eliminates the need to handshake with the instruction control module after sending the data transmission instructions to send the BL of each instruction and the IA of each thread included in each instruction. Therefore, it optimizes the transmission timing of each data transmission instruction, reduces the overall latency of data transmission, and increases the data throughput of data transmission instructions, thereby improving the overall timing performance of the register data transmission system. The instruction control module can determine the execution order of the N data transmission instructions and, according to the execution order, sends the BL of the currently to-be-executed data transmission instructions and the IA of each thread included in the to-be-executed data transmission instructions to the register read / write module, achieving intelligent scheduling of data transmission instructions and avoiding execution conflicts between different data transmission instructions and resource scheduling conflicts within the system. The register read / write module can execute the data transfer instruction according to the BL of the data transfer instruction to be executed and the IA of each thread included in the data transfer instruction to be executed, thereby realizing different types of register data transfer based on indirect addressing content; and, based on the flexible setting of the BL, the register data transfer system of this disclosure can flexibly and efficiently handle continuous data transfer of different lengths, enhancing the flexibility of data transfer.

[0057] In one possible implementation, the instruction issuing module 101 includes: at least one instruction count counter and N instruction issuing interfaces, wherein any instruction count counter corresponds to M instruction issuing interfaces, and M is a positive integer less than or equal to N; any instruction issuing interface is used to send a data transmission instruction to the instruction control module when the count value of the instruction count counter corresponding to the instruction issuing interface is greater than a preset abort threshold.

[0058] The specific form of the instruction quantity counter and the instruction issuance interface can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on them.

[0059] If the instruction issuing module 101 continuously sends data transmission instructions to the instruction control module 102, it may cause instruction accumulation in the instruction control module 102, thereby affecting the stability of the system 100. In order to avoid the occurrence of instruction accumulation, the instruction issuing module 101 can limit the number of data transmission instructions sent by the instruction issuing module 101 through at least one instruction data counter.

[0060] Specifically, the count value of any instruction count counter can be used to indicate the total number of data transmission instructions that can currently be sent from the M instruction sending interfaces. The specific value of M can be flexibly set according to actual usage requirements and is related to the value of N; this disclosure does not impose specific limitations on it.

[0061] In one example, with N equal to 4, M can be set to 4 so that each instruction sending interface corresponds to an instruction count counter, thereby independently controlling the number of data transmission instructions that each instruction sending interface can send.

[0062] In one example, when N equals 4, M can be set to 2, and the number of data transmission commands that can be sent by the two command issuing interfaces can be controlled simultaneously by an instruction quantity counter, thereby saving resources of the instruction issuing module 101 and the system 100.

[0063] If the count value of any instruction count counter is greater than the preset abort threshold, it can be assumed that the instruction control module 102 still has available processing resources. Therefore, any instruction issuing interface corresponding to the instruction count counter can continue to send data transmission instructions to the instruction control module. If the count value of the instruction count counter is equal to the preset abort threshold, it can be assumed that the instruction control module 102 has no available processing resources. All instruction issuing interfaces corresponding to the instruction count counter should no longer send data transmission instructions to the instruction control module to avoid instruction backlog. The specific value of the preset abort threshold can be flexibly set according to actual usage requirements. For example, the preset abort threshold can be set to 0. This disclosure does not specifically limit this.

[0064] In one possible implementation, any instruction count counter is used to: after any instruction issuing interface corresponding to the instruction count counter sends a data transmission instruction, decrease the count value of the instruction count counter by a first count value.

[0065] After any instruction sending interface sends a data transmission instruction to the instruction control module 102, the instruction control module 102 needs to consume resources to process the data transmission instruction. At this time, the instruction count counter corresponding to the instruction sending interface needs to reduce its count value by a first count value to reduce the number of subsequent data transmission instructions sent to the instruction control module 102. The specific value of the first count value can be flexibly set according to actual usage requirements. For example, the first count value can be set to 1. This disclosure does not impose a specific limitation on this.

[0066] In one possible implementation, any instruction count counter is used to increment the count value of the instruction count counter by a second count value when a data transmission instruction is transmitted to the register read / write module 103 via any instruction issue interface corresponding to the instruction count counter.

[0067] After a data transmission instruction sent from any instruction dispatch interface is transmitted by the instruction control module 102 to the register read / write module 103, it indicates that the instruction control module 102 has released the resources occupied by processing the data transmission instruction. Therefore, the instruction count counter corresponding to that instruction dispatch interface can increment its count value by a second count value to increase the number of subsequent data transmission instructions sent to the instruction control module 102. The specific value of the second count value can be flexibly set according to actual usage requirements, and is usually set to be equal to the first count value. For example, the second count value can be set to equal the first count value, which is 1. This disclosure does not impose specific limitations on this.

[0068] In one possible implementation, the instruction control module 102 includes: at least one instruction cache unit, N BL cache units, at least one IA cache unit, an instruction arbitration unit, an instruction cache unit to be executed, and a distribution control unit; the at least one instruction cache unit is used to receive and store N data transmission instructions; the N BL cache units are used to receive and store the BL of each data transmission instruction respectively; the at least one IA cache unit is used to receive and store the IA of each thread included in each data transmission instruction; the instruction arbitration unit is used to poll and arbitrate the N data transmission instructions to determine the data transmission instructions to be executed and the execution order of the N data transmission instructions; the instruction cache unit to be executed is used to store the N data transmission instructions sequentially according to the execution order; and the distribution control unit is used to send the BL of the data transmission instructions to be executed and the IA of each thread included in the data transmission instructions to the register read / write module.

[0069] The number of instruction cache units is equal to the number of instruction count counters, and the storage depth of each instruction cache unit (i.e., the total number of data transmission instructions that each instruction cache unit can store) is equal to the preset value of each instruction count counter. Here, the preset value of each instruction count counter can represent the maximum number of data transmission instructions that can be sent by the M instruction dispatch interfaces corresponding to each instruction count counter. The specific form of each instruction cache unit can be flexibly set according to actual usage requirements; for example, it can be set as a buffer or other forms, and this disclosure does not specifically limit it.

[0070] Figure 2 A block diagram of an instruction control module according to an embodiment of the present disclosure is shown. In the case where the instruction issuing module 101 includes two instruction count counters and four instruction issuing interfaces, and each instruction count counter has a preset value of 6, as follows... Figure 2 As shown, the instruction control module 102 includes two instruction cache units. Each instruction cache unit is used to receive and store data transmission instructions sent in parallel by two instruction transmission interfaces, and each instruction cache unit can store six data transmission instructions.

[0071] Each BL cache unit corresponds to one instruction issuance interface of the instruction issuance module 101. It can directly receive and store the BL of each data transmission instruction without requiring a handshake between the instruction control module 102 and the instruction issuance module 101. This optimizes the transmission timing of the BL of each data transmission instruction, improves the data throughput of data transmission instructions, and enhances the overall timing performance of the system 100. The specific form of any BL cache unit can be flexibly set according to actual usage requirements. For example, it can be set as a First-In First-Out (FIFO) queue memory, etc. This disclosure does not impose specific limitations on this. The total number of BLs that each BL cache unit can store can be flexibly set according to actual usage requirements. It can usually be set to be equal to the preset value of the instruction counter, and this disclosure does not impose specific limitations on this.

[0072] Based on the above Figure 2 For example, in the case where the instruction issuing module 101 includes 2 instruction count counters and 4 instruction issuing interfaces, and the preset value of each instruction count counter is 6, such as... Figure 2 As shown, the instruction control module 102 includes 4 BL cache units. Each BL cache unit can store a total of 6 BLs, that is, each BL cache unit can store 6 BLs of data transmission instructions.

[0073] Each IA buffer unit corresponds to multiple instruction issuance interfaces of the instruction issuance module 101, and can receive and store multiple data transmission instructions, including the IA of each thread. The specific form of any IA buffer unit can be flexibly set according to actual usage requirements; for example, it can be set as a BUFFER or other forms, and this disclosure does not impose a specific limitation on it. The specific number of IA buffer units can be flexibly set according to actual usage requirements, and this disclosure does not impose a specific limitation on it.

[0074] Based on the above Figure 2 For example, in the case where the instruction issuing module 101 includes two instruction count counters and four instruction issuing interfaces, such as... Figure 2 As shown, the instruction control module 102 includes two IA cache units. Each IA cache unit corresponds to two instruction issuing interfaces and can store the IA of each thread included in the data transmission instructions sent by the two instruction issuing interfaces.

[0075] The instruction arbitration unit can poll and arbitrate N data transmission instructions to determine the execution order of the N data transmission instructions, and determine the data transmission instructions awarded in each round of arbitration as data transmission instructions to be executed; the specific form of the instruction arbitration unit can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it; the specific method of polling arbitration can refer to the implementation methods in related technologies, and this disclosure does not impose specific limitations on it.

[0076] Based on the above Figure 2 For example, Figure 2 As shown, the instruction control module 102 also includes an instruction arbitration unit, an instruction cache unit to be executed, and a distribution control unit; after the instruction arbitration unit arbitrates the instruction to be executed for data transmission, it can send the instruction to be executed for data transmission to the instruction cache unit and the distribution control unit respectively.

[0077] The pending instruction cache unit can be used to store pending data transmission instructions, as well as instruction information such as thread identifiers and thread block validity information for these instructions. Based on the polling arbitration of N data transmission instructions by the instruction arbitration unit, the pending instruction cache unit can store each data transmission instruction sequentially according to the execution order. The specific form of the pending instruction cache unit can be flexibly set according to actual usage requirements; for example, it can be set as a FIFO, etc., and this disclosure does not impose specific limitations on it.

[0078] After receiving the data transmission instruction to be executed, the distribution control unit can automatically read the BL of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction from the BL cache unit and IA cache unit corresponding to the data transmission instruction to be executed, and send this information together with the data transmission instruction to be executed to the register read / write module.

[0079] After the data transfer instruction to be executed, the BL of the data transfer instruction to be executed, and the IA of each thread included therein are all sent to the register read / write module 103, the BL cache unit storing the data transfer instruction to be executed, the IA cache unit storing the IA of each thread included in the data transfer instruction to be executed, and the instruction cache unit to be executed will all release their corresponding storage resources.

[0080] Meanwhile, the distribution control unit will send a transmission response of the data transmission instruction to be executed to the instruction control module 102. The transmission response can indicate that the instruction control module 102 has transmitted the data transmission instruction to be executed to the register read / write module 103, so as to reflect that the instruction control module 102 has released the resources occupied by processing the data transmission instruction to be executed, so that the instruction count counter corresponding to the instruction dispatch interface that sends the data transmission instruction to be executed can adjust its count value in real time according to the transmission response.

[0081] In one example, the data transmission instruction 1 sent by instruction issue interface 1 is arbitrated by instruction control module 102 as a data transmission instruction to be executed. After the data transmission instruction BL and the IA of each thread included therein are sent to register read / write module 103, the distribution control unit will feed back the transmission response of data transmission instruction 1 to the instruction count counter corresponding to instruction issue interface 1. The instruction count counter corresponding to instruction issue interface 1 can determine that data transmission instruction 1 has been transmitted to register read / write module 103 based on the transmission response of data transmission instruction 1, indicating that instruction control module 102 has released the resources occupied by processing the data transmission instruction. Therefore, the instruction count counter corresponding to instruction issue interface 1 can increase its own count value by a second count value to increase the number of subsequent data transmission instructions sent to instruction control module 102.

[0082] In one possible implementation, the instruction control module 102 further includes: a receive sequence counter corresponding to each instruction transmission interface; any one of the receive sequence counters is used to: when at least one instruction buffer unit receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter, and the count value of the receive sequence counter is less than a first preset threshold, increment the count value of the receive sequence counter by a third count value, wherein the first preset threshold is determined based on the preset value of the instruction quantity counter corresponding to the instruction transmission interface.

[0083] For any instruction sending interface sending multiple data transmission instructions, in order to ensure that the processing order of the multiple data transmission instructions in the instruction arbitration unit is consistent with the receiving order of the multiple data transmission instructions received by the instruction buffer unit, it is necessary to first ensure that the instruction buffer unit stores the multiple data transmission instructions sent by the instruction sending interface in the receiving order.

[0084] Therefore, the instruction control module 102 also includes a receive sequence counter corresponding to each instruction transmission interface; the count value of each receive sequence counter (REQ_ID) can represent the receiving order of data transmission instructions sent by the corresponding instruction transmission interface; wherein, the initial value of each receive sequence counter can be flexibly set according to actual usage requirements, for example, the initial value of each receive sequence counter can be set to be equal to 0, and this disclosure does not make specific limitations on this; the specific value of the third count value can be flexibly set according to actual usage requirements, and this disclosure does not make specific limitations on this. The instruction buffer unit can receive and store multiple data transmission instructions sent by the instruction transmission interface in sequence according to the receive sequence counter of any one of its corresponding instruction transmission interfaces.

[0085] In one example, each receive sequence counter has an initial value of 0 and a third count value of 1. The command transmission module 101 includes command transmission interfaces 1 to 4. When the count value of the receive sequence counter corresponding to command transmission interface 1 is 0, the data transmission command sent by command transmission interface 1 is the first data transmission command received by the command buffer unit from command transmission interface 1. The command buffer unit can identify this data transmission command as data transmission command 0 and store it. After the command buffer unit receives data transmission command 0, the receive sequence counter corresponding to command transmission interface 1 increments its count value by 1. When the count value of the receive sequence counter corresponding to command transmission interface 1 is 1, the data transmission command sent by command transmission interface 1 is the second data transmission command received by the command buffer unit from command transmission interface 1. The command buffer unit can identify this data transmission command as data transmission command 1 and store it. Furthermore, after the command buffer unit receives data transmission command 1, the receive sequence counter corresponding to command transmission interface 1 increments its count value by 1, and so on, until the count value of the receive sequence counter corresponding to command transmission interface 1 equals a first preset threshold. The command buffer unit receives and stores multiple data transmission commands sent by command transmission interface 1 in sequence according to the receiving order.

[0086] The first preset threshold can be determined based on the preset value of the instruction quantity counter corresponding to each instruction issuance interface, and can be specifically expressed as formula (1):

[0087] REQ limit =CK-1 (1)

[0088] Among them, REQ limit CK represents the first preset threshold; CK represents the preset value of the instruction count counter corresponding to each instruction issuing interface.

[0089] For any given command issuing interface, if all other command issuing interfaces sharing the same command count counter are unable to send data transmission commands, the maximum number of data transmission commands that this command issuing interface can send is CK; therefore, by setting the first preset threshold REQ... limit Setting it to CK-1 ensures that, even in extreme usage scenarios, all data transmission commands sent by the command transmission interface can be received and stored in sequence by the command buffer unit.

[0090] In one possible implementation, any one of the receive sequence counters is further configured to: reset the count value of the receive sequence counter to its initial value when at least one instruction buffer unit receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter, and the count value of the receive sequence counter is equal to a first preset threshold.

[0091] When a data transmission instruction sent by the instruction transmission interface corresponding to any one of the receive sequence counters is received by the instruction cache unit, and the count value of the receive sequence counter is equal to the first preset threshold, it indicates that all CK data transmission instructions sent by the instruction transmission interface corresponding to the receive sequence counter have been stored in order by the instruction cache unit. At this time, the count value of the receive sequence counter can be reset to the initial value so that the instruction cache unit can sort the new data transmission instructions sent by the instruction transmission interface in the future.

[0092] In one possible implementation, the instruction control module 102 further includes: a processing sequence counter corresponding to each instruction issuing interface; any processing sequence counter is used to: increase the count value of the processing sequence counter by a fourth count value when the processing sequence counter corresponds to the instruction issuing interface of the data transmission instruction to be executed and the count value of the processing sequence counter is less than a second preset threshold, wherein the second preset threshold is determined according to the preset value of the instruction quantity counter corresponding to the instruction issuing interface.

[0093] The instruction control module 102 also includes a processing sequence counter corresponding to each instruction issuing interface. The count value of each processing sequence counter (SENT_ID) indicates the processing order of data transmission instructions sent by its corresponding instruction issuing interface. The initial value of each processing sequence counter can be flexibly set according to actual usage requirements; for example, the initial value of each processing sequence counter can be set to 0. This disclosure does not specifically limit this. The specific value of the fourth count value can also be flexibly set according to actual usage requirements; for example, the fourth count value can be set to 1. This disclosure does not specifically limit this. The instruction arbitration unit can read the data transmission instructions indicated by the count value of each processing sequence counter from the instruction cache unit based on the count value of the processing sequence counter corresponding to each instruction issuing interface, and perform polling arbitration.

[0094] In one example, the instruction issuing module 101 includes instruction issuing interfaces 1 to 4. When the count value of the processing sequence counter corresponding to instruction issuing interface 1 is 0, the count value of the processing sequence counter corresponding to instruction issuing interface 2 is 1, the count value of the processing sequence counter corresponding to instruction issuing interface 3 is 2, and the count value of the processing sequence counter corresponding to instruction issuing interface 4 is 2, the instruction arbitration unit reads the data transmission instruction 0 sent by instruction issuing interface 1, the data transmission instruction 1 sent by instruction issuing interface 2, the data transmission instruction 2 sent by instruction issuing interface 3, and the data transmission instruction 2 sent by instruction issuing interface 4 from the instruction cache unit, and performs polling arbitration on these four data transmission instructions.

[0095] If any data transmission instruction is determined by the instruction arbitration unit to be a data transmission instruction to be executed, and the count value of the processing sequence counter corresponding to the instruction sending interface that sent the data transmission instruction is less than the second preset threshold, the count value of the processing sequence counter is increased by a fourth count value to instruct the instruction arbitration unit to read the next data transmission instruction received from the instruction sending interface from the instruction cache unit in the next round of polling arbitration; and so on, until the count value of the processing sequence counter is equal to the second preset threshold.

[0096] Taking the instruction issuing module 101, which includes instruction issuing interfaces 1 to 4, as an example, where the instruction arbitration unit polls and arbitrates the data transmission instruction 0 sent by instruction issuing interface 1, the data transmission instruction 1 sent by instruction issuing interface 2, the data transmission instruction 2 sent by instruction issuing interface 3, and the data transmission instruction 2 sent by instruction issuing interface 4; the initial value of each processing order counter is set to 0, and the fourth count value is set to 1; after the data transmission instruction 0 sent by instruction issuing interface 1 is determined to be a data transmission instruction to be executed, the count value of the processing order counter corresponding to instruction issuing interface 1 is incremented by 1. In the new round of polling and arbitration, the count value of the processing order counter corresponding to instruction issuing interface 1 is 1, the count value of the processing order counter corresponding to instruction issuing interface 2 is 1, the count value of the processing order counter corresponding to instruction issuing interface 3 is 2, and the count value of the processing order counter corresponding to instruction issuing interface 4 is 2; the instruction arbitration unit reads the data transmission instruction 1 sent by instruction issuing interface 1, the data transmission instruction 1 sent by instruction issuing interface 2, the data transmission instruction 2 sent by instruction issuing interface 3, and the data transmission instruction 2 sent by instruction issuing interface 4 from the instruction cache unit, and polls and arbitrates these four data transmission instructions.

[0097] The second preset threshold can be determined based on the preset value of the instruction quantity counter corresponding to each instruction issuance interface, and can be specifically expressed as formula (2):

[0098] SENT limit =CK-1 (2)

[0099] Among them, SENT limit This indicates the second preset threshold.

[0100] The maximum number of data transmission commands that any single command transmission interface can send is CK; therefore, by setting the second preset threshold SENT... limit Setting it to CK-1 ensures that, in the event that CK data transmission commands have been sent sequentially from any command transmission interface, the command arbitration unit can read and process the CK data transmission commands from the command buffer unit in the order in which they were received.

[0101] In one possible implementation, any processing sequence counter is further configured to: reset the count value of the processing sequence counter to its initial value when the processing sequence counter corresponds to the instruction transmission interface corresponding to the data transmission instruction to be executed, and the count value of the processing sequence counter is equal to a second preset threshold.

[0102] If a data transmission instruction sent by the instruction issuing interface corresponding to any processing sequence counter is determined by the instruction arbitration unit to be a data transmission instruction to be executed, and the count value of the processing sequence counter is equal to the second preset threshold, it can be determined that all CK data transmission instructions sent by the instruction issuing interface have been arbitrated by the instruction arbitration unit and sequentially sent to the register read / write module 103 as data transmission instructions to be executed. Therefore, the count value of the processing sequence counter can be reset to the initial value so as to facilitate polling and arbitration of new data transmission instructions sent by the instruction issuing interface in the future.

[0103] In one possible implementation, each data transfer instruction includes X thread blocks, each thread block includes at least one thread, and each thread corresponds to its own IA, where X is a positive integer; the register read / write module 103 includes: X vector processing units; and a distribution control unit, used to send the BL of the data transfer instruction to be executed, and the IA of each thread in a thread block included in the data transfer instruction to be executed, to a vector processing unit, and different vector processing units correspond to different thread blocks included in the data transfer instruction to be executed.

[0104] Based on the above Figure 1 For example, Figure 1 As shown, the register read / write module 103 includes X independent vector processing units that are not dependent on each other. The specific value of X can be flexibly set according to actual usage requirements, depending on the actual situation of each data transfer instruction, and should be greater than or equal to the number of thread blocks included in each data transfer instruction. This disclosure does not impose specific limitations on this. The specific form of any vector processing unit can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on this.

[0105] The distribution control unit can send the BL of the data transmission instruction to be executed, as well as the IA of each thread in a thread block included in the data transmission instruction to be executed, to a vector processing unit, so that each vector processing unit can independently process a thread block of the data transmission instruction to be executed.

[0106] In one possible implementation, each vector processing unit includes: a source operand address calculation subunit and a read timing control subunit; the source operand address calculation subunit of any vector processing unit is used to determine the source operand address of each thread in the thread block according to the IA of each thread in the thread block corresponding to the vector processing unit; the read timing control subunit of any vector processing unit is used to determine BL source operand read requests of the thread block in sequence according to the source operand address of each thread in the thread block corresponding to the vector processing unit and the BL of the data transfer instruction to be executed, wherein the i-th source operand read request is used to read the i-th source operand of each thread in the thread block, and i is a positive integer greater than or equal to 1 and less than or equal to BL.

[0107] Figure 3 A block diagram of a vector processing unit according to an embodiment of the present disclosure is shown. Figure 3 As shown, the vector processing unit 300 includes: a source operand address calculation subunit 301 and a read timing control subunit 302.

[0108] Any vector processing unit includes a source operand address calculation subunit, which can determine the source operand address of each thread in the corresponding thread block based on the IA of each thread in that thread block. The specific form of the source operand address calculation subunit can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0109] In one possible implementation, any vector processing unit may include a source operand address calculation subunit, which may include multiple address calculators. Each address calculator corresponds to at least one thread in the thread block corresponding to the vector processing unit. Any address calculator can determine the source operand address of each thread based on the IA of that thread. The specific form of each address calculator can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it. The specific number of address calculators and the number of threads corresponding to each address calculator can also be flexibly set according to actual usage requirements and is related to the number of threads included in each thread block; this disclosure does not impose specific limitations on this either.

[0110] In one example, the data transfer instruction to be executed includes four thread blocks, and each thread block includes threads 0 to 7. The source operand address calculation subunit of any vector processing unit includes address calculators 1 to 4. Address calculator 1 is used to calculate the source operand addresses of threads 0 and 4 in the corresponding thread block of the vector processing unit; address calculator 2 is used to calculate the source operand addresses of threads 1 and 5 in the corresponding thread block of the vector processing unit; address calculator 3 is used to calculate the source operand addresses of threads 2 and 6 in the corresponding thread block of the vector processing unit; and address calculator 4 is used to calculate the source operand addresses of threads 3 and 7 in the corresponding thread block of the vector processing unit.

[0111] Furthermore, for any address calculator, if the IA of any two threads corresponding to the address calculator is the same, the source operand address calculations of the two threads can be merged, reducing the number of address calculations that the address calculator needs to perform and improving the efficiency of source operand address calculation.

[0112] Taking the above-mentioned data transmission instruction to be executed as having 4 thread blocks, and each thread block having threads 0 to 7, and any vector processing unit having source operand address calculation subunits including address calculator 1 to address calculator 4 as an example, if the IA of thread 0 and the IA of thread 4 are the same in the corresponding thread block of the vector processing unit, address calculator 1 can merge the source operand address calculations of thread 0 and thread 4, and only one address calculation is needed to determine the source operand addresses of thread 0 and thread 4.

[0113] Any vector processing unit includes a source operand address calculation subunit, which can send the source operand address of each thread in the corresponding thread block of the vector processing unit to the read timing control subunit of the vector processing unit. The read timing control subunit of the vector processing unit can, based on the source operand address of each thread in the corresponding thread block and the BL of the data transfer instruction to be executed, sequentially determine the BL source operand read requests for the thread block. The i-th source operand read request is used to read the i-th source operand of each thread in the thread block, where i is a positive integer greater than or equal to 1 and less than or equal to BL. The specific form of the read timing control subunit can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0114] After the read timing control subunit of any vector processing unit determines the read request for the i-th source operand of the corresponding thread block, the vector processing unit will read the i-th source operand of each thread in the thread block by executing the read request for the i-th source operand of its corresponding thread block; after the vector processing unit has executed all the read requests for the source operand, it can be determined that the vector processing unit has completed the read of all the source operands for the thread block.

[0115] In one possible implementation, each data transfer instruction includes Y threads in each thread block, where Y is a positive integer; any vector processing unit is configured to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, merge and read threads with the same IA in the thread block to determine Z register read requests of the thread block, where Z is a positive integer less than or equal to Y; execute the Z register read requests to determine the i-th source operand of each thread in the thread block.

[0116] During the execution of the i-th source operand read request of the corresponding thread block by any vector processing unit, the vector processing unit can merge the reads of threads with the same IA (same source operand address) in the corresponding thread block, and use a single register read request to synchronously read the i-th source operand of these threads with the same IA, thereby reducing the number of register accesses. The specific method for merging the reads of threads with the same IA in any thread block and determining the Z register read requests for that thread block can be flexibly set according to actual usage requirements and is related to the type of the source operand address of each thread; this disclosure does not impose specific limitations on this.

[0117] The process by which any vector processing unit sequentially executes each source operand read request of its corresponding thread block can be called the top-level loop for source operand reads. Based on this, the vector processing unit can determine the i-th source operand of each thread in the thread block by determining the Z register read requests of the thread block and sequentially executing the Z register read requests of the thread block, thereby completing the execution of the i-th source operand read request of the thread block. Therefore, the process by which the vector processing unit sequentially executes the Z register read requests of the thread block can also be called the bottom-level loop for source operand reads.

[0118] Each vector processing unit can read data through a double loop consisting of a top-level loop and a bottom-level loop, as well as by merging reads from different threads within the bottom-level loop. This reduces the number of register read requests required for source operand reading, improves register access efficiency, achieves efficient source operand reading, and enhances the overall data transmission performance of the system.

[0119] In one possible implementation, any vector processing unit is configured to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, if the IA of the (j+a)-th thread in the thread block is the same as that of the j-th thread, determine the j-th register read request, the j-th register read request is used to read the i-th source operand of the j-th thread and the (j+a)-th thread, where j and a are both positive integers, and j+a is less than or equal to Y.

[0120] Specifically, for the j-th thread of any vector processing unit corresponding to a thread block, the IA of the j-th thread can be compared with the IA of the (j+1)-th thread, the IA of the (j+2)-th thread, ..., the IA of the Y-th thread in sequence. If the IA of the (j+a)-th thread is the same as the IA of the j-th thread, the j-th register read request can be determined so as to synchronously read the i-th source operand of the j-th thread and the (j+a)-th thread.

[0121] In one example, the data transfer instruction to be executed includes four thread blocks, and each thread block includes threads 0 to 7. For any given thread block, polling arbitration is performed on threads 0 to 7 of that thread block. In the first round of polling arbitration, the IA of thread 0 is compared for consistency with the IA of thread 1, the IA of thread 2, ..., the IA of thread 7 in sequence. If the IA of thread 1 is the same as that of thread 0, the source operand reads of thread 1 and thread 0 can be merged and processed. If the IA of thread 2 is also the same as that of thread 0, the source operand reads of thread 2 can also be merged and processed with the source operand reads of thread 0, and so on, to determine register read request 0 that can synchronously read the i-th source operand of all threads that have the same IA as thread 0. In the second round of polling arbitration, if the source operand read of thread 1 has been merged with the source operand read of thread 0, the third round of polling arbitration can proceed directly. If the source operand read of thread 1 has not been merged with the source operand read of thread 0, the IA of thread 1 can be compared for consistency with the IA of thread 2, thread 3, ..., thread 7 in sequence. If the IA of thread 2 is the same as that of thread 1, the source operand reads of thread 2 and thread 1 can be merged. If the IA of thread 3 is also the same as that of thread 1, the source operand read of thread 3 can be merged with the source operand read of thread 1, and so on, until the register read request 1 that can synchronously read the i-th source operand of all threads that have the same IA as thread 1 is determined.

[0122] By merging the source operand reads of all threads with the same IA, the number of register read requests that any vector processing unit actually needs to issue is less than the number of threads in the corresponding thread block of that vector processing unit. This eliminates the need to perform a register access independently for each thread, thereby effectively reducing the number of register accesses.

[0123] In one possible implementation, each vector processing unit includes: a vector register read arbitration subunit; the vector register read arbitration subunit of any vector processing unit is used to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, when the source operand address of each thread in the thread block is a vector register address, arbitrate one vector register read request that needs to be executed from the Z vector register read requests of the thread block according to the preset thread priority.

[0124] Based on the above Figure 3 For example, Figure 3 As shown, the vector processing unit 300 includes a vector register read arbitration subunit 303.

[0125] The specific format for reading the arbitration subunit from any vector register can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it. Similarly, the specific content of the preset thread priority can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0126] In one example, any vector processing unit corresponds to a thread block including threads 0 to 7. The preset thread priority can be set so that thread 0 has the highest priority, thread 1 has the next highest priority, and so on, with thread 7 having the lowest priority.

[0127] Based on the preset thread priority, any vector processing unit, including its vector register read arbitration subunit, can arbitrate one vector register read request that needs to be executed from the Z vector register read requests of the corresponding thread block. The specific method for arbitrating the Z vector register read requests can be flexibly configured according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0128] In one example, any vector processing unit corresponds to a thread block comprising threads 0 through 7, with the preset thread priority being highest for thread 0, followed by thread 1, and so on, with thread 7 having the lowest priority. When there are 8 vector register read requests in the thread block corresponding to this vector processing unit (i.e., each thread has a different source operand address), according to the preset thread priority, the vector register read request of thread 0 is arbitrated first as the currently needed vector register read request; after the execution of the vector register read request of thread 0 is completed, the vector register read request of thread 1 is arbitrated as the currently needed vector register read request, and so on, until the execution of the vector register read request of thread 7 is completed.

[0129] In one example, any vector processing unit corresponds to a thread block including threads 0 to 7, with the preset thread priority being thread 0 having the highest priority, thread 1 having the next highest priority, and so on, with thread 7 having the lowest priority. If the thread block corresponding to this vector processing unit contains a vector register read request 0 for reading the i-th source operand of threads 0 and 7, and a vector register read request 1 for reading the i-th source operand of threads 1 to 6, then according to the preset thread priority, vector register read request 0 can be arbitrated as the currently required vector register read request; after completing the execution of vector register read request 0, vector register read request 1 is arbitrated as the currently required vector register read request and executed.

[0130] In one example, any vector processing unit corresponds to a thread block including threads 0 through 7, with the default thread priority being thread 0 having the highest priority, thread 1 having the next highest priority, and so on, with thread 7 having the lowest priority. If there is only one vector register read request 0 in the thread block corresponding to this vector processing unit (i.e., each thread has the same source operand address), this vector register read request can be executed directly.

[0131] In one possible implementation, each vector processing unit further includes: a scalar register read arbitration subunit; the scalar register read arbitration subunit of any vector processing unit is used to: for the i-th source operand read request of the thread block corresponding to the vector processing unit, when the source operand address of each thread in the thread block is a scalar register address, arbitrate the preset number of scalar register read requests that need to be executed in parallel from the Z scalar register read requests of the thread block according to the preset thread priority.

[0132] Based on the above Figure 3 For example, Figure 3As shown, the vector processing unit 300 includes a scalar register read arbitration subunit 304, the specific form of which can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0133] Considering that different data banks of scalar registers may be independent and do not support cross-bank data transfer, data transfer can only be performed based on a fixed data bank mapping relationship. Therefore, any scalar register read arbitration subunit included in any vector processing unit needs to arbitrate the preset number of parallel scalar register read requests to be executed from the Z scalar register read requests of the corresponding thread block of the vector processing unit according to the preset thread priority. This ensures that the vector processing unit can read the i-th source operand of each thread according to the data bank mapping relationship of the scalar register. Here, the preset number of parallel requests is equal to the number of data banks of the scalar register; the specific content of the preset thread priority is related to the number of data banks of the scalar register and can be flexibly set according to actual usage requirements. This disclosure does not limit it in this regard.

[0134] In one example, the thread block corresponding to any scalar register read arbitration subunit includes: threads 0 to 7. When the scalar register has 4 data channels, the preset parallel quantity can be 4, and the preset thread priority can be set as: the priority of threads 0 to 3 is higher than the priority of threads 4 to 7.

[0135] The specific method for arbitrating Z scalar register read requests can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0136] In one example, any scalar register read arbitration subunit corresponds to a thread block comprising threads 0 to 7, with a preset parallel count of 4 and a preset thread priority: threads 0 to 3 have a higher priority than threads 4 to 7. When there are 8 scalar register read requests in the thread block corresponding to this vector processing unit (i.e., each thread has a different source operand address), according to the preset thread priority, the scalar register read requests of threads 0 to 3 are arbitrated first, becoming the 4 scalar register read requests that need to be executed currently. After the execution of the scalar register read requests of threads 0 to 3 is completed, the scalar register read requests of threads 4 to 7 are arbitrated and executed.

[0137] In one example, any scalar register read arbitration subunit corresponds to a thread block including threads 0 to 7, with a preset parallel quantity of 4 and a preset thread priority: threads 0 to 3 have a higher priority than threads 4 to 7. If the corresponding thread block of this vector processing unit contains scalar register read request 0 (reading the i-th source operand of threads 0 and 4), scalar register read request 1 (reading the i-th source operand of threads 1 and 5), scalar register read request 2 (reading the i-th source operand of threads 2 and 6), and scalar register read request 3 (reading the i-th source operand of threads 3 and 7), then scalar register read requests 0 to 3 can be executed directly.

[0138] In one possible implementation, the register read / write module further includes: a scalar processing unit, which includes: a scalar register read subunit; a scalar register read arbitration subunit included in any vector processing unit, used to: send a preset number of scalar register read requests that need to be executed in parallel to the scalar register read subunit; the scalar register read subunit is used to: generate at least one burst transmission request for each thread block according to all the scalar register read requests that need to be executed currently sent by the scalar register read arbitration subunit included in each vector processing unit; and synchronously execute all burst transmission requests of any thread block.

[0139] Based on the above Figure 1 For example, Figure 1 As shown, the register read / write module 103 also includes a scalar processing unit for processing data reading and writing of scalar registers.

[0140] Figure 4 A block diagram of a scalar processing unit according to an embodiment of the present disclosure is shown. Figure 4 As shown, the scalar processing unit 400 includes a scalar register read subunit.

[0141] Any vector processing unit that includes a scalar register read arbitration subunit can send a preset number of scalar register read requests that need to be executed in parallel to the scalar register read subunit.

[0142] Because the processing of their respective thread blocks by each vector processing unit is out of order, and the processing efficiency of each vector processing unit may vary, the source operand addresses that scalar register read requests sent to the scalar register read subunit need to read are scattered and discontinuous. Therefore, the scalar register read subunit can first perform two-level synchronization on all received scalar register read requests, merging all scalar register read requests with contiguous source operand addresses, thereby reducing the number of scalar register accesses and improving the scalar register read efficiency.

[0143] Specifically, in the first-level synchronization of scalar register read requests, the scalar register read subunit generates at least one burst transfer request for each thread block based on all scalar register read requests that need to be executed currently sent by the scalar register read arbitration subunit included in each vector processing unit. The scalar register read subunit will only perform the second-level synchronization after each thread block has generated a burst transfer request. If any thread block does not generate a burst transfer request, the scalar register read subunit will suspend the burst transfer requests of other thread blocks until each thread block generates a burst transfer request.

[0144] In the second-level synchronization of scalar register read requests, for any given thread block, the scalar register read subunit determines all burst transfer requests for that thread block and executes all burst transfer requests synchronously, efficiently executing the i-th source operand read request of the thread block with fewer register accesses.

[0145] In one possible implementation, each vector processing unit further includes a destination register write subunit; the destination register write subunit of any vector processing unit is used to: determine the destination operand address of each thread in the thread block according to the IA of each thread in the corresponding thread block of the vector processing unit; and determine the register write request of each thread in the thread block according to the destination operand address of each thread in the thread block.

[0146] Based on the above Figure 3 For example, Figure 3 As shown, the vector processing unit 300 includes a destination register write subunit 305.

[0147] Any vector processing unit includes a destination register write-out subunit, which can determine the destination operand address of each thread in the corresponding thread block based on the IA of each thread in that thread block. The specific form of the destination register write-out subunit can be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it.

[0148] In one possible implementation, any vector processing unit may include a destination register write subunit that may include multiple address calculators, with different address calculators corresponding to multiple threads in the thread block corresponding to the vector processing unit. Any address calculator may determine the destination operand address of each thread corresponding to it based on the IA of each thread. The specific form of each address calculator may be flexibly set according to actual usage requirements, and this disclosure does not impose specific limitations on it. The specific number of address calculators and the number of threads corresponding to each address calculator may be flexibly set according to actual usage requirements and are related to the number of threads included in each thread block, and this disclosure does not impose specific limitations on it.

[0149] In one example, when the data transfer instruction to be executed includes four thread blocks, and each thread block includes threads 0 to 7, the destination register write subunit of any vector processing unit may include address calculators 1 to 4; address calculator 1 is used to calculate the destination operand addresses of threads 0 and 4 in the corresponding thread block of the vector processing unit; address calculator 2 is used to calculate the destination operand addresses of threads 1 and 5 in the corresponding thread block of the vector processing unit; address calculator 3 is used to calculate the destination operand addresses of threads 2 and 6 in the corresponding thread block of the vector processing unit; and address calculator 4 is used to calculate the destination operand addresses of threads 3 and 7 in the corresponding thread block of the vector processing unit.

[0150] Furthermore, for any address calculator, if the IA of any two threads corresponding to the address calculator is the same, the destination operand address calculations of the two threads can be merged, reducing the number of address calculations that the address calculator needs to perform and improving the efficiency of destination operand address calculation.

[0151] Taking the above-mentioned data transmission instruction to be executed as having 4 thread blocks, and each thread block having threads 0 to 7, and any vector processing unit having a destination register write subunit including address calculator 1 to address calculator 4 as an example, if the IA of thread 0 and the IA of thread 4 are the same in the corresponding thread block of the vector processing unit, address calculator 1 can calculate and merge the destination operand addresses of thread 0 and thread 4, and only one address calculation is needed to determine the destination operand addresses of thread 0 and thread 4.

[0152] In one possible implementation, the register read / write module 103 further includes: a write-out-preserving unit; the destination register write-out subunit included in any vector processing unit is further configured to: when the register write request of each thread in the thread block corresponding to the vector processing unit is a vector register write request, send the vector register write request of each thread in the thread block to the write-out-preserving unit; when the register write request of each thread in the thread block corresponding to the vector processing unit is a scalar register write request, send the scalar register write request of each thread in the thread block to the scalar processing unit; the scalar processing unit is configured to: send the scalar register write requests of each thread block corresponding to each vector processing unit to the write-out-preserving unit respectively; the write-out-preserving unit is configured to: execute the register write request of each thread in the thread block corresponding to any vector processing unit.

[0153] Based on the above Figure 1 For example, Figure 1 As shown, the register read / write module 103 further includes a write-preserving unit, which is used to execute the register write request of each thread in the thread block corresponding to the vector processing unit.

[0154] Any vector processing unit that includes a destination register write subunit can directly send the vector register write request of each thread in the corresponding thread block to the write-preserving unit if the register write request of each thread in the corresponding thread block of the vector processing unit is a vector register write request.

[0155] The write-out-keeping unit can obtain instruction information such as thread block validity information of the data transmission instruction to be executed through the distribution control unit, and store the instruction information of the data transmission instruction to be executed in the FIFO of the write-out-keeping unit. Among them, the thread block validity information can be used to indicate the thread blocks in the data transmission instruction to be executed that are in a valid state, thereby reflecting the execution status of the data transmission instruction to be executed. The specific form of the thread block validity information can be flexibly set according to actual usage requirements. For example, it can be set as an enable signal of one-hot encoding, etc., and this disclosure does not make specific limitations on it.

[0156] When any vector processing unit corresponds to a thread block that is valid in the data transfer instruction to be executed, the write-preserve-order unit can perform BL register write operations sequentially according to the vector register write request of each thread in the thread block corresponding to that vector processing unit. In the i-th register write operation, the write-preserve-order unit will write the i-th source operand of each thread in the thread block to the destination register. After each thread block that is valid in the data transfer instruction to be executed has completed its respective BL register write operations, the write-preserve-order unit can pop the instruction information stored in its FIFO.

[0157] When the register write request of each thread in the thread block corresponding to the vector processing unit is a scalar register write request, the scalar processing unit needs to process the scalar register write request of each thread in the thread block. Therefore, the vector processing unit needs to first send the scalar register write request of each thread in the thread block to the scalar processing unit, and then the scalar processing unit sends the scalar register write request of each thread block corresponding to the vector processing unit to the write-preserving unit respectively.

[0158] In one possible implementation, the scalar processing unit includes: a scalar register write subunit; the scalar register write subunit is used to: send the scalar register write request of each thread in any vector processing unit to the write-preserving unit when the thread block corresponding to any vector processing unit is a thread block in a valid state in the data transmission instruction to be executed.

[0159] Based on the above Figure 4 For example, Figure 4 As shown, the scalar processing unit 400 includes a scalar register write subunit, and the scalar register write subunit and the scalar register read subunit are independent of each other; the scalar register write subunit can receive and store the scalar register write request of the thread block corresponding to each vector processing unit.

[0160] Furthermore, the scalar register write-out subunit can obtain the thread block validity information of the data transfer instruction to be executed by the dispatch control unit, thereby determining the thread block in the data transfer instruction to be executed that is in a valid state.

[0161] For any vector processing unit corresponding to a thread block that matches a thread block in a valid state in the data transfer instruction to be executed, the scalar register write subunit will send the scalar register write request of each thread in that thread block to the write order preservation unit; for a vector processing unit corresponding to a thread block that does not match a thread block in a valid state in the data transfer instruction to be executed, the scalar register write subunit will first suspend the scalar register write request of each thread in that thread block until the thread block is indicated to be in a valid state.

[0162] Through the above processing, the scalar register write subunit can ensure that the sending of scalar register write requests for each thread in each thread block meets the execution requirements of the transmission instruction to be executed, even when each vector processing unit executes its corresponding thread block out of order and the processing efficiency of each vector processing unit is different, thus achieving the ordered sending of scalar register write requests.

[0163] After receiving the scalar register write request from each thread in any thread block sent by the scalar register write subunit, the write-preserve-order unit performs BL register write operations sequentially according to the scalar register write request from each thread in that thread block. In the i-th register write operation, the write-preserve-order unit writes the i-th source operand of each thread in that thread block to the destination register. After completing BL register write operations, the write-preserve-order unit pops the instruction information stored in its FIFO.

[0164] The register data transmission system of this disclosure includes an instruction issuing module, an instruction control module, and a register read / write module. The instruction issuing module can send N data transmission instructions in parallel to the instruction control module, simultaneously sending the continuous transmission data length BL of each instruction and the indirect addressing content IA of each thread included in each instruction. This eliminates the need to handshake with the instruction control module after sending the data transmission instructions to send the BL of each instruction and the IA of each thread included in each instruction. Therefore, it optimizes the transmission timing of each data transmission instruction, reduces the overall latency of data transmission, and increases the data throughput of data transmission instructions, thereby improving the overall timing performance of the register data transmission system. The instruction control module can determine the execution order of the N data transmission instructions and, according to the execution order, sends the BL of the currently to-be-executed data transmission instructions and the IA of each thread included in the to-be-executed data transmission instructions to the register read / write module, achieving intelligent scheduling of data transmission instructions and avoiding execution conflicts between different data transmission instructions and resource scheduling conflicts within the system. The register read / write module can execute the data transfer instruction according to the BL of the data transfer instruction to be executed and the IA of each thread included in the data transfer instruction to be executed, and realize different types of register data transfer based on indirect addressing; and, based on the flexible setting of the BL, the register data transfer system of this disclosure can flexibly and efficiently handle continuous data transfer of different lengths, enhancing the flexibility of data transfer.

[0165] It should be noted that, although... Figures 1 to 4 The above-described register data transfer system serves as an example, but those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly configure the component composition and structure of the register data transfer system according to their personal preferences and / or actual application scenarios, as long as it can achieve register data transfer based on indirect addressing based on the above principles, improve the overall timing performance of the register data transfer system, reduce data transfer latency, and enhance the flexibility of data transfer.

[0166] Furthermore, according to another aspect of this disclosure, a register data transmission method is provided, which is applied to a register data transmission system, the register data transmission system including: an instruction issuing module, an instruction control module, and a register read / write module. Figure 5 A flowchart illustrating a register data transfer method according to an embodiment of the present disclosure is shown. Figure 5 As shown, the method includes:

[0167] In step S501, the instruction issuing module is used to send N data transmission instructions, the continuous data transmission length BL of each data transmission instruction, and the indirect addressing content IA of each thread included in each data transmission instruction to the instruction control module in parallel, where N is a positive integer.

[0168] In step S502, the instruction control module is used to determine the execution order of N data transmission instructions, and according to the execution order, the BL of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction to be executed are sent to the register read / write module.

[0169] In step S503, the register read / write module is used to execute the data transfer instruction according to the BL of the data transfer instruction to be executed and the IA of each thread included in the data transfer instruction to be executed.

[0170] In one possible implementation, the instruction issuing module includes: at least one instruction count counter and N instruction issuing interfaces, wherein any instruction count counter corresponds to M instruction issuing interfaces, and M is a positive integer less than or equal to N; the method further includes: when any instruction issuing interface sends a data transmission instruction to the instruction control module when the count value of the instruction count counter corresponding to the instruction issuing interface is greater than a preset abort threshold.

[0171] In one possible implementation, the method further includes: after any instruction count counter sends a data transmission instruction through any instruction issuing interface corresponding to the instruction count counter, the count value of the instruction count counter is reduced by a first count value.

[0172] In one possible implementation, the method further includes: when any instruction count counter is sent by any instruction issue interface corresponding to the instruction count counter to the register read / write module, the count value of the instruction count counter is increased by a second count value.

[0173] In one possible implementation, the instruction control module includes: at least one instruction cache unit, N BL cache units, at least one IA cache unit, an instruction arbitration unit, an instruction cache unit to be executed, and a distribution control unit. The instruction control module determines the execution order of N data transmission instructions and, according to the execution order, sends the BL of the currently to-be-executed data transmission instructions and the IA of each thread included in the to-be-executed data transmission instructions to the register read / write module. This includes: at least one instruction cache unit receiving and storing N data transmission instructions; N BL cache units respectively receiving and storing the BL of each data transmission instruction; at least one IA cache unit receiving and storing the IA of each thread included in each data transmission instruction; the instruction arbitration unit polling and arbitrating the N data transmission instructions to determine the execution order of the to-be-executed data transmission instructions; the instruction cache unit to be-executed storing the N data transmission instructions sequentially according to the execution order; and the distribution control unit sending the BL of the to-be-executed data transmission instructions and the IA of each thread included in the to-be-executed data transmission instructions to the register read / write module.

[0174] In one possible implementation, the instruction control module further includes: a receive sequence counter corresponding to each instruction transmission interface; the method further includes: when any receive sequence counter receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter in at least one instruction buffer unit, and the count value of the receive sequence counter is less than a first preset threshold, the count value of the receive sequence counter is increased by a third count value, wherein the first preset threshold is determined according to the preset value of the instruction quantity counter corresponding to the instruction transmission interface.

[0175] In one possible implementation, the method further includes: when any one of the receive sequence counters receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter in at least one instruction buffer unit, and the count value of the receive sequence counter is equal to a first preset threshold, the count value of the receive sequence counter is reset to an initial value.

[0176] In one possible implementation, the instruction control module further includes: a processing sequence counter corresponding to each instruction issuing interface; the method further includes: if any processing sequence counter corresponds to the instruction issuing interface of the data transmission instruction to be executed, and the count value of the processing sequence counter is less than a second preset threshold, the count value of the processing sequence counter is increased by a fourth count value, wherein the second preset threshold is determined according to the preset value of the instruction quantity counter corresponding to the instruction issuing interface.

[0177] In one possible implementation, the method further includes: resetting the count value of any processing sequence counter to its initial value when the processing sequence counter corresponds to the instruction transmission interface of the data transmission instruction to be executed and the count value of the processing sequence counter is equal to a second preset threshold.

[0178] In one possible implementation, each data transfer instruction includes X thread blocks, each thread block includes at least one thread, and each thread corresponds to its own IA, where X is a positive integer; the register read / write module includes X vector processing units; the distribution control unit sends the BL of the data transfer instruction to be executed, and the IA of each thread included in the data transfer instruction to be executed to the register read / write module, including: the distribution control unit sends the BL of the data transfer instruction to be executed, and the IA of each thread in a thread block included in the data transfer instruction to be executed to a vector processing unit, and different vector processing units correspond to different thread blocks included in the data transfer instruction to be executed.

[0179] In one possible implementation, each vector processing unit includes: a source operand address calculation subunit and a read timing control subunit; the register read / write module executes the data transfer instruction to be executed based on the BL of the data transfer instruction to be executed and the IA of each thread included in the data transfer instruction to be executed, including: the source operand address calculation subunit of any vector processing unit determines the source operand address of each thread in the thread block according to the IA of each thread in the thread block corresponding to the vector processing unit; the read timing control subunit of any vector processing unit determines the BL source operand read requests of the thread block in sequence based on the source operand address of each thread in the thread block corresponding to the vector processing unit and the BL of the data transfer instruction to be executed, wherein the i-th source operand read request is used to read the i-th source operand of each thread in the thread block, and i is a positive integer greater than or equal to 1 and less than or equal to BL.

[0180] In one possible implementation, each data transfer instruction includes Y threads in each thread block, where Y is a positive integer; the method further includes: for any vector processing unit to read the i-th source operand of the thread block corresponding to the vector processing unit, merging and reading the threads with the same IA in the thread block to determine Z register read requests of the thread block, where Z is a positive integer less than or equal to Y; executing the Z register read requests to determine the i-th source operand of each thread in the thread block.

[0181] In one possible implementation, the method further includes: for any vector processing unit to read the i-th source operand of the thread block corresponding to the vector processing unit, if there is an IA of the (j+a)-th thread and the IA of the j-th thread in the thread block, a j-th register read request is determined, and the j-th register read request is used to read the i-th source operand of the j-th thread and the (j+a)-th thread, where j and a are both positive integers, and j+a is less than or equal to Y.

[0182] In one possible implementation, each vector processing unit includes a vector register read arbitration subunit; the method further includes: for the i-th source operand read request of the thread block corresponding to the vector processing unit, if the source operand address of each thread in the thread block is a vector register address, the vector register read request to be executed is arbitrated from the Z vector register read requests of the thread block according to the preset thread priority.

[0183] In one possible implementation, each vector processing unit further includes a scalar register read arbitration subunit; the method further includes: for the i-th source operand read request of the thread block corresponding to the vector processing unit, if the source operand address of each thread in the thread block is a scalar register address, the scalar register read arbitration subunit arbitrates the preset number of scalar register read requests that need to be executed in parallel from the Z scalar register read requests of the thread block according to the preset thread priority.

[0184] In one possible implementation, the register read / write module further includes a scalar processing unit, which includes a scalar register read subunit. The method further includes: a scalar register read arbitration subunit included in any vector processing unit sends a preset number of scalar register read requests that need to be executed in parallel to the scalar register read subunit; the scalar register read subunit generates at least one burst transmission request for each thread block based on all the scalar register read requests that need to be executed currently sent by the scalar register read arbitration subunit included in each vector processing unit; and for any thread block, all burst transmission requests of that thread block are executed synchronously.

[0185] In one possible implementation, each vector processing unit further includes a destination register write subunit; the method further includes: the destination register write subunit of any vector processing unit determines the destination operand address of each thread in the thread block according to the IA of each thread in the corresponding thread block of the vector processing unit; and determines the register write request of each thread in the thread block according to the destination operand address of each thread in the thread block.

[0186] In one possible implementation, the register read / write module further includes a write-out-preserving unit; the method further includes: if the register write request of each thread in the corresponding thread block of any vector processing unit is a vector register write request, the destination register write subunit sends the vector register write request of each thread in that thread block to the write-out-preserving unit; if the register write request of each thread in the corresponding thread block of the vector processing unit is a scalar register write request, the scalar register write request of each thread in that thread block is sent to the scalar processing unit; the scalar processing unit sends the scalar register write requests of each thread block corresponding to each vector processing unit to the write-out-preserving unit respectively; the write-out-preserving unit executes the register write request of each thread in that thread block for any given thread block of the vector processing unit.

[0187] In one possible implementation, the scalar processing unit includes a scalar register write subunit; the method further includes: when the thread block corresponding to any vector processing unit is a thread block that is in a valid state in the data transmission instruction to be executed, the scalar register write subunit sends the scalar register write request of each thread in the thread block to the write-preserving unit.

[0188] This disclosure also provides an electronic device including the register data transmission system described above.

[0189] This disclosure also provides a non-volatile computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0190] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0191] Figure 6 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. For example, electronic device 1900 may be provided as a server or terminal device. (Refer to...) Figure 6 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0192] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). Electronic device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM Mac OS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0193] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0194] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0195] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0196] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0197] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0198] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0199] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0200] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0201] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A register data transmission system, characterized in that, The system includes: an instruction issuing module, an instruction control module, and a register read / write module; The instruction issuing module is used to send N data transmission instructions, the continuous data transmission length of each data transmission instruction, and the indirect addressing content IA of each thread included in each data transmission instruction to the instruction control module in parallel, where N is a positive integer; The instruction control module is used to determine the execution order of the N data transmission instructions, and according to the execution order, send the continuous data transmission length of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction to be executed to the register read / write module. The register read / write module is used to execute the data transmission instruction to be executed based on the continuous data transmission length of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction to be executed.

2. The system according to claim 1, characterized in that, The instruction issuing module includes: at least one instruction count counter and N instruction issuing interfaces, wherein any instruction count counter corresponds to M instruction issuing interfaces, and M is a positive integer less than or equal to N; Any instruction sending interface is used to send the data transmission instruction to the instruction control module when the count value of the instruction quantity counter corresponding to the instruction sending interface is greater than a preset abort threshold.

3. The system according to claim 2, characterized in that, Any instruction count counter is used for: After a data transmission command is sent from any command transmission interface corresponding to the command count counter, the count value of the command count counter is reduced by the first count value.

4. The system according to claim 2, characterized in that, Any instruction count counter is used for: When a data transmission instruction sent by any instruction dispatch interface corresponding to the instruction count counter is transmitted to the register read / write module, the count value of the instruction count counter is increased by a second count value.

5. The system according to any one of claims 1 to 4, characterized in that, The instruction control module includes: at least one instruction cache unit, N consecutive data transmission length cache units, at least one IA cache unit, an instruction arbitration unit, an instruction cache unit to be executed, and a distribution control unit; The at least one instruction cache unit is used to receive and store the N data transmission instructions; The N consecutive data length buffer units are used to receive and store the consecutive data length of each data transmission instruction, respectively. The at least one IA cache unit is used to receive and store the IA of each thread included in each data transmission instruction; The instruction arbitration unit is used to poll and arbitrate the N data transmission instructions to determine the execution order of the data transmission instructions to be executed and the N data transmission instructions. The instruction cache unit is used to store the N data transmission instructions sequentially according to the execution order; The distribution control unit is used to send the continuous transmission data length of the data transmission instruction to be executed, and the IA of each thread included in the data transmission instruction to the register read / write module.

6. The system according to claim 5, characterized in that, The instruction control module also includes: a receive sequence counter corresponding to each instruction transmission interface; Any receive sequence counter is used for: When at least one instruction buffer unit receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter, and the count value of the receive sequence counter is less than a first preset threshold, the count value of the receive sequence counter is increased by a third count value, wherein the first preset threshold is determined based on the preset value of the instruction quantity counter corresponding to the instruction transmission interface.

7. The system according to claim 6, characterized in that, Any receiver sequence counter is also used for: When at least one instruction buffer unit receives a data transmission instruction sent by the instruction transmission interface corresponding to the receive sequence counter, and the count value of the receive sequence counter is equal to the first preset threshold, the count value of the receive sequence counter is reset to the initial value.

8. The system according to claim 5, characterized in that, The instruction control module also includes: a processing sequence counter corresponding to each instruction transmission interface; Any processing sequence counter is used for: If the processing sequence counter corresponds to the instruction transmission interface corresponding to the data transmission instruction to be executed, and the count value of the processing sequence counter is less than the second preset threshold, the count value of the processing sequence counter is increased by a fourth count value, wherein the second preset threshold is determined according to the preset value of the instruction quantity counter corresponding to the instruction transmission interface.

9. The system according to claim 8, characterized in that, Any processing sequence counter is also used for: If the processing sequence counter corresponds to the instruction transmission interface corresponding to the data transmission instruction to be executed, and the count value of the processing sequence counter is equal to the second preset threshold, the count value of the processing sequence counter is reset to the initial value.

10. The system according to claim 5, characterized in that, Each data transmission instruction includes X thread blocks, each thread block includes at least one thread, and each thread corresponds to its own IA, where X is a positive integer; The register read / write module includes: X vector processing units; The distribution control unit is used to send the continuous transmission data length of the data transmission instruction to be executed, and the IA of each thread in a thread block included in the data transmission instruction to be executed, to a vector processing unit, wherein different vector processing units correspond to different thread blocks included in the data transmission instruction to be executed.

11. The system according to claim 10, characterized in that, Each vector processing unit includes: a source operand address calculation subunit and a read timing control subunit; Any vector processing unit includes a source operand address calculation subunit, which is used to determine the source operand address of each thread in the thread block according to the IA of each thread in the corresponding thread block of the vector processing unit; Any vector processing unit includes a read timing control subunit, which is used to determine the continuous data transmission length of the source operand read request of the thread block in sequence according to the source operand address of each thread in the thread block corresponding to the vector processing unit and the continuous data transmission length of the data transmission instruction to be executed. The i-th source operand read request is used to read the i-th source operand of each thread in the thread block, where i is a positive integer greater than or equal to 1 and less than or equal to the continuous data transmission length.

12. The system according to claim 11, characterized in that, Each data transmission instruction includes Y threads in each thread block, where Y is a positive integer; Any vector processing unit is used for: For the i-th source operand read request of the thread block corresponding to the vector processing unit, the threads with the same IA in the thread block are merged for read, and the Z register read requests of the thread block are determined, where Z is a positive integer less than or equal to Y; Execute the Z register read requests to obtain the i-th source operand for each thread in the thread block.

13. The system according to claim 12, characterized in that, Any vector processing unit is used for: For the i-th source operand read request of the thread block corresponding to the vector processing unit, if the IA of the (j+a)-th thread is the same as that of the j-th thread in the thread block, the j-th register read request is determined. The j-th register read request is used to read the i-th source operand of the j-th thread and the (j+a)-th thread, where j and a are both positive integers and j+a is less than or equal to Y.

14. The system according to claim 12, characterized in that, Each vector processing unit includes: a vector register read arbitration subunit; Any vector processing unit includes a vector register read arbitration subunit, used for: For the i-th source operand read request of the thread block corresponding to the vector processing unit, if the source operand address of each thread in the thread block is a vector register address, the vector register read request that needs to be executed is arbitrated from the Z vector register read requests of the thread block according to the preset thread priority.

15. The system according to claim 12, characterized in that, Each vector processing unit also includes: a scalar register read arbitration subunit; Any vector processing unit includes a scalar register read arbitration subunit, used for: For the i-th source operand read request of the thread block corresponding to the vector processing unit, if the source operand address of each thread in the thread block is a scalar register address, the preset number of scalar register read requests that need to be executed in parallel is arbitrated from the Z scalar register read requests of the thread block according to the preset thread priority.

16. The system according to claim 15, characterized in that, The register read / write module further includes a scalar processing unit, which includes a scalar register read subunit. Any vector processing unit includes a scalar register read arbitration subunit, used for: Send the preset number of scalar register read requests that need to be executed in parallel to the scalar register read subunit; The scalar register read subunit is used for: Based on all scalar register read requests that need to be executed currently sent by the scalar register read arbitration subunit included in each vector processing unit, at least one burst transmission request is generated for each thread block. For any given thread block, execute all burst transmission requests for that thread block synchronously.

17. The system according to claim 16, characterized in that, Each vector processing unit also includes: a destination register write-out subunit; Any vector processing unit includes a destination register write-out subunit, used for: Based on the IA of each thread in the thread block corresponding to the vector processing unit, determine the destination operand address of each thread in the thread block; Based on the destination operand address of each thread in the thread block, determine the register write request of each thread in the thread block.

18. The system according to claim 17, characterized in that, The register read / write module further includes: a write-out order-preserving unit; Any vector processing unit, including its destination register write-out subunit, is also used for: If the register write request of each thread in the corresponding thread block of the vector processing unit is a vector register write request, the vector register write request of each thread in the thread block is sent to the write-out order-preserving unit. If the register write request of each thread in the thread block corresponding to the vector processing unit is a scalar register write request, the scalar register write request of each thread in the thread block is sent to the scalar processing unit. The scalar processing unit is used for: The scalar register write request for each thread block corresponding to the vector processing unit is sent to the write-out order-preserving unit respectively. The write-out order-preserving unit is used for: For any given vector processing unit corresponding to a thread block, execute the register write request for each thread in that thread block.

19. The system according to claim 18, characterized in that, The scalar processing unit further includes: a scalar register write-out subunit; The scalar register write subunit is used for: If any vector processing unit corresponds to a thread block that is in a valid state in the data transmission instruction to be executed, the scalar register write request of each thread in the thread block is sent to the write-preserving unit.

20. A register data transfer method, characterized in that, The method is applied to a register data transmission system, which includes: an instruction issuance module, an instruction control module, and a register read / write module; the method includes: Using the instruction issuing module, N data transmission instructions, the continuous transmission data length of each data transmission instruction, and the indirect addressing content IA of each thread included in each data transmission instruction are sent to the instruction control module in parallel, where N is a positive integer; Using the instruction control module, the execution order of the N data transmission instructions is determined, and according to the execution order, the continuous data transmission length of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction to be executed are sent to the register read / write module. Using the register read / write module, the data transmission instruction to be executed is executed according to the continuous data transmission length of the data transmission instruction to be executed and the IA of each thread included in the data transmission instruction to be executed.

21. An electronic device, characterized in that, Includes the register data transfer system according to any one of claims 1 to 19.

22. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 20.

23. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 20.

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