Method for improving zeroth layer interlayer medium layer bow and gate height difference
By enhancing the density of the interlayer dielectric layer, the problems of butterfly defects and height differences in high-k metal gate processes were solved, ensuring device performance stability and expanding the process window of the polished metal layer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-07
AI Technical Summary
In high-k metal gate technology, butterfly-shaped defects appear after grinding the interlayer dielectric layer, and there is a significant height difference between the metal gates of different CDs after grinding the metal layer, which leads to device test failure.
By enhancing the density of the interlayer dielectric layer, including high aspect ratio filling processes and annealing, a dense interlayer dielectric layer is formed, which is then ground to expose the dummy gate structure and metal layer, forming a capping layer and other functional layers.
It effectively improves butterfly defects in the interlayer dielectric layer, reduces the height difference of the metal gate, expands the process window of the polished metal layer, and ensures stable device performance.
Smart Images
Figure CN122349243A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and specifically to a method for improving butterfly defects in the zeroth interlayer dielectric layer and gate height difference. Background Technology
[0002] In high-k metal gate technology, after forming the dummy gate on the substrate, an interlayer dielectric layer (the zeroth interlayer dielectric layer) is deposited to completely cover the dummy gate. Then, the zeroth interlayer dielectric layer is polished (performing the first polishing) to expose the top of the dummy gate. Sidewalls and silicide barrier layers are formed on both sides of the dummy gate. The sidewalls and silicide barrier layers are made of silicon nitride, while the zeroth interlayer dielectric layer is made of oxide. Compared to silicon nitride, the polishing slurry used in the first polishing has a high selectivity for oxides. After polishing, butterfly defects are prone to appear on the surface of the zeroth interlayer dielectric layer in areas where the dummy gate spacing on the substrate is relatively large, affecting the isolation of the gate.
[0003] After removing the dummy gate, a metal layer is deposited to fill the trench, and then the metal layer is polished (performing a second polishing) to expose the zeroth interlayer dielectric layer, forming the metal gate. To completely remove the metal layer located within the butterfly defect, the polishing time needs to be increased, resulting in a decrease in the height of the metal gate with a larger CD (with a long channel below the gate). After the second polishing, the height difference between the metal gate with a larger CD and the metal gate with a smaller CD (with a short channel below the gate) is significantly greater than after the first polishing. The lower height of the metal gate with a larger CD will lead to device final test (FT) failure. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for improving the butterfly defect and gate height difference of the zeroth interlayer dielectric layer, so as to solve the problems of butterfly defects appearing on the surface of the zeroth interlayer dielectric layer after grinding and the obvious height difference between metal gates with different CD after grinding the metal layer in the prior art.
[0005] To achieve the above and other related objectives, this application provides a method for improving butterfly defects in the zeroth interlayer dielectric layer and gate height difference, comprising: Step 1: Provide a substrate and form multiple dummy gate structures on the substrate; Step 2: While forming an interlayer dielectric layer that fills the gaps between multiple dummy gate structures, the density of the interlayer dielectric layer is enhanced. Step 3: Grind the interlayer dielectric layer until the top of the dummy gate structure is exposed; Step four: After removing the dummy gate structure, a metal layer is formed on the substrate; Step 5: Grind the metal layer until the interlayer dielectric layer is exposed.
[0006] Preferably, in step two, an interlayer dielectric layer is first formed by a high aspect ratio filling process to fill the gaps between multiple pseudo-gate structures, and then the interlayer dielectric layer is annealed to enhance the density of the interlayer dielectric layer.
[0007] Preferably, the annealing temperature is 400℃-500℃ and the duration is 5h-6h.
[0008] Preferably, in step two, a first interlayer dielectric layer is first formed by a high aspect ratio filling process, and then a second interlayer dielectric layer is formed by a plasma-enhanced chemical vapor deposition process. The first and second interlayer dielectric layers constitute an interlayer dielectric layer that fills the gaps between multiple dummy gate structures, thereby enhancing the density of the interlayer dielectric layer.
[0009] Preferably, the thickness of the first interlayer dielectric layer and the second interlayer dielectric layer are the same.
[0010] Preferably, the dummy gate structure includes a gate oxide layer and a dummy gate stacked from bottom to top. Preferably, before forming the metal layer, the method further includes the step of sequentially forming a high-k dielectric layer, a capping layer, a work function metal layer, and a titanium nitride barrier layer on the sidewalls and bottom of the trench formed after removing the dummy gate structure.
[0011] Preferably, the material of the coating layer includes titanium nitride.
[0012] Preferably, the material of the work function metal layer includes titanium nitride or titanium aluminum.
[0013] Preferably, the material of the metal layer includes tungsten.
[0014] As described above, the method for improving the butterfly defect and gate height difference in the zeroth interlayer dielectric layer provided in this application has the following beneficial effects: forming a denser interlayer dielectric layer can effectively improve the butterfly defect in the interlayer dielectric layer, reduce the height difference between metal gates with different CDs, and expand the process window of the polished metal layer. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 The flowchart shown is a method for improving butterfly defects and gate height differences in the zeroth interlayer dielectric layer provided in an embodiment of this application. Detailed Implementation
[0017] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.
[0018] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0022] Please see Figure 1 The diagram illustrates a flowchart of a method for improving butterfly defects and gate height differences in the zeroth interlayer dielectric layer provided by an embodiment of this application.
[0023] like Figure 1 As shown, the method for improving the butterfly-shaped defects in the zeroth interlayer dielectric layer and the gate height difference includes the following steps: Step 1: Provide a substrate and form multiple dummy gate structures on the substrate; Step 2: While forming an interlayer dielectric layer that fills the gaps between multiple dummy gate structures, the density of the interlayer dielectric layer is enhanced. Step 3: Grind the interlayer dielectric layer until the top of the dummy gate structure is exposed; Step four: After removing the dummy gate structure, a metal layer is formed on the substrate; Step 5: Grind the metal layer until the interlayer dielectric layer is exposed.
[0024] In step one, the substrate material includes silicon, silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0025] Multiple dummy gate structures are formed in different regions of the substrate. For example, the dummy gate structures located in different regions of the substrate have different CDs. As an example, the dummy gate structure includes at least a gate oxide layer and a dummy gate stacked from bottom to top, and sidewalls are formed on the sidewalls of the dummy gate structure.
[0026] In step two, the material of the interlayer dielectric layer may be, but is not limited to, silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).
[0027] To enhance the density of the interlayer dielectric layer, there are two main approaches: The first approach involves first forming an interlayer dielectric layer that fills the gaps between multiple dummy gate structures using a high aspect ratio fill process (HARP), and then annealing the interlayer dielectric layer. For example, the annealing temperature is 400℃-500℃ and the duration is 5h-6h. The second approach involves first forming a first interlayer dielectric layer using a high aspect ratio fill process (HARP), and then forming a second interlayer dielectric layer (PEOX) using a plasma-enhanced chemical vapor deposition process. The first and second interlayer dielectric layers constitute an interlayer dielectric layer that fills the gaps between multiple dummy gate structures. The first and second interlayer dielectric layers have the same thickness, and the sum of the thicknesses of the first and second interlayer dielectric layers is the preset thickness of the interlayer dielectric layer required to fill the gaps between multiple dummy gate structures.
[0028] Due to the increased density of the interlayer dielectric layer, after implementing step three, the surface of the interlayer dielectric layer is basically free of butterfly-shaped defects.
[0029] In step four, after removing the dummy gate structure by dry etching, a metal layer is formed on the substrate by deposition to fill the trench formed after removing the dummy gate structure.
[0030] Before forming the metal layer, the process also includes the steps of sequentially forming a high dielectric constant (high k) dielectric layer, a capping layer, a work function metal layer, and a titanium nitride barrier layer on the sidewalls and bottom of the trench.
[0031] For example, the high-k dielectric layer may be made of hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium silicate (HfSiOx), zirconium dioxide (ZrO2), or hafnium zirconium oxide (HfZrOx), the capping layer may be made of titanium nitride (TiN), the work function metal layer may be made of titanium nitride or titanium aluminum (TiAl), and the metal layer may be made of tungsten.
[0032] Due to the increased density of the interlayer dielectric layer, after implementing step five, the height of the metal gates with different CDs (with long channels below the gates) will not decrease significantly, and the height difference between the metal gates located in different regions of the substrate is within an acceptable range.
[0033] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0034] In summary, the method provided in this application for improving the butterfly defect in the zeroth interlayer dielectric layer and the gate height difference forms a denser interlayer dielectric layer. This effectively improves the butterfly defect in the interlayer dielectric layer, reduces the height difference between metal gates with different CD values, and expands the process window for polishing the metal layer. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0035] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.
Claims
1. A method for improving butterfly defects and gate height differences in the zeroth interlayer dielectric layer, characterized in that, The method includes: Step 1: Provide a substrate and form a plurality of dummy gate structures on the substrate; Step 2: While forming an interlayer dielectric layer that fills the gaps between the plurality of dummy gate structures, the density of the interlayer dielectric layer is enhanced. Step 3: Grind the interlayer dielectric layer until the top of the dummy gate structure is exposed; Step four: After removing the dummy gate structure, a metal layer is formed on the substrate; Step 5: Grind the metal layer until the interlayer dielectric layer is exposed.
2. The method according to claim 1, characterized in that, In step two, an interlayer dielectric layer is first formed by a high aspect ratio filling process to fill the gaps between the multiple pseudo-gate structures, and then the interlayer dielectric layer is annealed to enhance the density of the interlayer dielectric layer.
3. The method according to claim 2, characterized in that, The annealing process is performed at a temperature of 400℃-500℃ for a duration of 5-6 hours.
4. The method according to claim 1, characterized in that, In step two, a first interlayer dielectric layer is first formed by a high aspect ratio filling process, and then a second interlayer dielectric layer is formed by a plasma-enhanced chemical vapor deposition process. The first interlayer dielectric layer and the second interlayer dielectric layer constitute the interlayer dielectric layer that fills the gaps between the multiple pseudo-gate structures, thereby enhancing the density of the interlayer dielectric layer.
5. The method according to claim 4, characterized in that, The first interlayer dielectric layer and the second interlayer dielectric layer have the same thickness.
6. The method according to claim 1, characterized in that, The dummy gate structure includes a gate oxide layer and a dummy gate stacked from bottom to top.
7. The method according to claim 1, characterized in that, Before forming the metal layer, the process further includes the step of sequentially forming a high-k dielectric layer, a capping layer, a work function metal layer, and a titanium nitride barrier layer on the sidewalls and bottom of the trench formed after removing the dummy gate structure.
8. The method according to claim 7, characterized in that, The material of the coating layer includes titanium nitride.
9. The method according to claim 7, characterized in that, The material of the work function metal layer includes titanium nitride or titanium aluminum.
10. The method according to claim 7, characterized in that, The material of the metal layer includes tungsten.