A memory controller, a memory, a storage module and a memory access method

Abstract

A memory controller, a memory, a memory module, and a memory access method are disclosed. The memory controller includes a memory control module and an ECC encoder. The memory control module is configured to generate an access command based on a received access request and send the access command to the memory. The access command carries a first physical address. The ECC encoder is configured to encode the first physical address to generate a first ECC code. The memory control module is further configured to generate an ECC verification command based on the first ECC code and send the ECC verification command to the memory. The ECC verification command carries the first ECC code. By adding an ECC encoder to the memory controller, generating an ECC verification command based on ECC encoding, and enabling the checking of the memory access address based on the ECC verification command, the reliability of memory access is improved.

Description

Technical Field

[0001] This article relates to the field of memory access, and in particular to a memory controller, memory, memory module, and memory access method. Background Technology

[0002] In the process of reading and writing memory, in order to reduce the probability of errors when writing or reading data, ECC (Error-Correcting Code) verification is commonly used to verify and correct the written or read data. As the read and write speed of memory increases, it is necessary to match it with faster command and address transmission speeds. Correspondingly, the reliability requirements of the memory's command address interface (CA interface, Command / Address interface) are also increased. Summary of the Invention

[0003] This application provides a memory controller, a memory, a memory module, and a memory access method. An ECC encoder is added to the memory controller to generate ECC verification commands based on the ECC encoding. The memory access address can be checked based on the ECC verification commands, thereby improving the reliability of memory access.

[0004] In a first aspect, embodiments of this application provide a memory controller, including: The memory control module is configured to generate an access command based on a received access request and send the access command to the memory, the access command carrying a first physical address; An ECC encoder is configured to encode the first physical address using an error correction algorithm capable of correcting at least a single bit error, thereby generating a first ECC code. The memory control module is further configured to generate an ECC verification command based on the first ECC code and send the ECC verification command to the memory, wherein the ECC verification command carries the first ECC code.

[0005] Secondly, embodiments of this application provide a memory, including: peripheral circuitry and a memory cell array; The peripheral circuitry includes a command parsing unit, an ECC verification module, and an address decoding unit. The command parsing unit is configured to receive access commands and ECC verification commands sent by the memory controller, parse the access commands to obtain the second physical address, and parse the ECC verification commands to obtain the second ECC code of the second physical address. The ECC verification module is configured to perform ECC verification on the second physical address based on the second physical address and the second ECC code, return an indication signal of the ECC verification result to the memory controller, and output the physical address based on the ECC verification result. The address decoding unit is configured to generate an address selection signal based on the physical address output by the ECC verification module, and output the address selection signal to the memory cell array. The storage cell array is configured to select a corresponding storage cell according to the address selection signal, and to store or retrieve data in the selected storage cell.

[0006] Thirdly, embodiments of this application provide a storage module, including a memory controller and a memory; The memory controller is the memory controller described in the above embodiments; The memory is the memory described in the above embodiments.

[0007] Fourthly, embodiments of this application provide a memory access method, including: The memory controller receives an access request, obtains a first physical address, generates an access command based on the first physical address, and encodes the first physical address to generate an ECC verification command. The memory controller sends the access command and the ECC verification command to the memory; The memory performs ECC verification based on the second physical address carried by the received access command and the second ECC code carried by the received ECC verification command, and returns an indication signal of the ECC verification result to the memory controller. The memory controller performs data transmission control according to the indication signal.

[0008] Compared with related technologies, the memory controller, memory, memory module and memory access method of the present application embodiment add an ECC encoder to the memory controller, generate ECC verification commands based on ECC encoding, and can realize the checking and error correction of memory access addresses on the memory side based on ECC verification commands, thereby improving the reliability of memory access.

[0009] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0011] Figure 1 This is a schematic diagram of a memory controller according to an embodiment of this application; Figure 2a Timing diagram for sending read commands and ECC verification commands in embodiments of this application; Figure 2b Timing diagram for sending write commands and ECC verification commands in embodiments of this application; Figure 3 This is a schematic diagram of a memory according to an embodiment of this application; Figure 4 This is a schematic diagram of a storage module according to an embodiment of this application; Figure 5 This is a schematic diagram of a DRAM access system according to an embodiment of this application; Figure 6 This is a flowchart of a memory access method according to an embodiment of this application; Figure 7 This is a schematic diagram illustrating the conversion of the device physical address in a CXL message to the first HEC code, as shown in Example 1 of this application. Figure 8 This is a schematic diagram illustrating HEC verification using the CRC8 algorithm in an embodiment of this application. Detailed Implementation

[0012] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0013] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0014] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0015] CA interface errors refer to problems with the interface used to transmit addresses and commands between the memory controller and the memory. These problems can cause data to fail to be written to the memory correctly or to fail to read data stored in the memory correctly, affecting normal memory access. CA interface errors may be caused by poor wiring, signal interference, or other hardware failures. When these problems are not detected in time, they can lead to incorrect access address transmission, seriously affecting the reliability of memory access.

[0016] Therefore, embodiments of this application provide a memory controller, such as... Figure 1 As shown, it includes: The memory control module is configured to generate an access command based on a received access request and send the access command to the memory, the access command carrying a first physical address; An ECC encoder is configured to encode the first physical address using an error correction algorithm capable of correcting at least a single bit error, thereby generating a first ECC code. The memory control module is further configured to generate an ECC verification command based on the first ECC code and send the ECC verification command to the memory, wherein the ECC verification command carries the first ECC code.

[0017] In this embodiment, the access request can be a read request or a write request sent by the processor. The processor and the memory control module can be connected via an AXI (Advanced eXtensible Interface) bus. The AXI bus includes a read address channel, a write address channel, a write data channel, and a read data channel. Each channel has its specific control signals. These control signals ensure the correct transmission of read address, write address, write data, and read data through a handshake mechanism. The write data channel and the read data channel can each include a FIFO (First-In-First-Out) buffer. The device physical address carried by the read request can be transmitted to the memory control module through the read address channel. The device physical address carried by the write request can be transmitted to the memory control module through the write address channel. The write data carried by the write request can be temporarily stored in the first FIFO buffer of the write data channel. The read data obtained from the memory can be temporarily stored in the second FIFO buffer of the read data channel. The write data channel and the read data channel connect the memory and the processor.

[0018] In this embodiment, the access commands generated by the memory control module may include write commands and read commands. Both write commands and read commands carry a first physical address. The first physical address is a memory access address generated based on the device's physical address, and may include the memory's row address, column address, and bank address, etc.

[0019] In this embodiment, the memory controller includes an ECC encoder, which can verify and correct errors that occur during transmission by executing the ECC (Error Checking and Correction) algorithm. The ECC code can be a Cyclic Redundancy Check (CRC) code, Hamming code, Reed-Muller code, or convolutional code. When using a CRC code, CRC8, CRC16, CRC32, or other CRC algorithms can be used. The above ECC codes are all exemplary descriptions and are not intended to limit this application. They will not be described in detail here.

[0020] In this embodiment, the memory control module can add a command identifier (Command ID) reserved in the memory interface-related standard to the ECC code to generate an ECC verification command. Through timing control, the access command and ECC verification command are sequentially sent to the memory via the Command / Address interface (CA interface).

[0021] In this embodiment, the memory controller adds an ECC encoder to the memory controller, generates ECC verification commands based on ECC encoding, and can check the memory access address based on the ECC verification command, thereby improving the reliability of memory access. Furthermore, by checking the access address, the CA interface can also be checked. When the access address is transmitted incorrectly, the CA interface can be further checked for poor wiring, signal interference, or other hardware failures.

[0022] In one exemplary embodiment, the memory control module is further configured to receive an indication signal of the ECC verification result sent by the memory.

[0023] In this embodiment, after performing ECC verification, the memory can generate an indication signal based on the ECC verification result and return the indication signal to the memory control module. The indication signal includes a first alarm signal, a second alarm signal, and a verification pass signal, which are used to indicate whether the ECC verification result is a single-bit error, a multi-bit error, or no error, respectively. The memory control module can perform data transmission control on the written data or read data according to the indication signal. For example, when the indication signal is the first alarm signal or the verification pass signal, the write data carried by the write request is transmitted to the memory, and the data read from the memory is transmitted to the sender of the read request; when the indication signal is the second alarm signal, the sender of the write request or the sender of the read / write request is reported.

[0024] In one exemplary embodiment, the memory control module may include an address translation unit and a command generation and sending unit; The address translation unit is configured to convert the address carried in the received access request into the first physical address, and output the first physical address to the ECC encoder and the command generation and sending unit; The command generation and sending unit is configured to generate the access command based on the first physical address, generate the ECC verification command based on the received first ECC code, and send the access command and the ECC verification command to the memory in sequence.

[0025] In this embodiment, the address translation unit can be connected to the read address channel and write address channel of the AXI bus, receive the physical address of the read device, convert the physical address of the device into a first physical address, and send the first physical address to the command generation and sending unit and the ECC encoder.

[0026] In this embodiment, after receiving the first physical address, the command generation and sending unit can generate an access command based on the first physical address. The access command can be a write command or a read command. The command generation and sending unit can receive the first ECC code generated by the ECC encoder and generate an ECC verification command based on the first ECC code. When sending the access command and the ECC verification command sequentially to the CA interface of the memory, the ECC verification command follows the access command immediately, which can improve the reliability of command transmission and facilitate the memory to perform ECC verification after receiving the access command and the ECC verification command. Figure 2a As shown, the ECC verification command follows the read command. In the diagram, READ represents the read command, and ECC represents the ECC verification command. READ includes BA, BG, BL, C, and AP; Figure 2b As shown, the ECC verification command follows the write command. In the figure, WRITE represents the write command, ECC represents the ECC verification command, and WRITE includes BA, BG, BL, WR_P, C, and AP. Figure 2a and Figure 2b In this context, BA represents bank address, BG represents bank group, BL represents burst length, C represents column address, AP represents autoprecharge, WR_P represents wr_partial, and DES represents Device Deselect.

[0027] In one exemplary embodiment, the memory controller is a DDR controller or a high-bandwidth memory controller; The ECC encoder is an HEC encoder, the first ECC code is an HEC code, and the first ECC code of the first physical address supports single-bit error correction and multi-bit error checking for the first physical address.

[0028] In this embodiment, the ECC encoder can be an HEC encoder that executes the HEC algorithm. The first ECC code generated is the first HEC code. HEC (Header Error Correction) is used to verify and correct errors in the header information during data transmission. The HEC verification and error correction algorithm is used to encode the first physical address and generate the first HEC code.

[0029] In this embodiment, the DDR controller is a Double Data Rate (DDR) synchronous dynamic random access memory controller, which can be used as a controller for DDR2, DDR3, DDR4, DDR5 and other memory types; the memory controller can also be a High Bandwidth Memory Controller (HBMC), which can be used as a controller for High Bandwidth Memory (HBM), and is a controller for managing 3D stacked memory.

[0030] This application also provides a memory, such as... Figure 3 As shown, it includes: peripheral circuitry and a memory cell array; The peripheral circuitry includes a command parsing unit, an ECC verification module, and an address decoding unit. The command parsing unit is configured to receive access commands and ECC verification commands sent by the memory controller, parse the access commands to obtain the second physical address, and parse the ECC verification commands to obtain the second ECC code of the second physical address. The ECC verification module is configured to perform ECC verification on the second physical address based on the second physical address and the second ECC code, return an indication signal of the ECC verification result to the memory controller, and output the physical address based on the ECC verification result. The address decoding unit is configured to generate an address selection signal based on the physical address output by the ECC verification module, and output the address selection signal to the memory cell array. The storage cell array is configured to select a corresponding storage cell according to the address selection signal, and to store or retrieve data in the selected storage cell.

[0031] In this embodiment, the address decoding unit can generate an address selection signal based on the physical address. The address decoding unit may include a row decoding circuit, a column decoding circuit, and a bank decoding circuit. The row decoding circuit can generate a row selection signal (referred to as row) based on the physical address and send it to the memory cell array. The column decoding circuit can generate a column selection signal (referred to as col) based on the physical address and send it to the memory cell array. The bank decoding circuit can generate a bank selection signal (referred to as bank) based on the physical address and send it to the memory cell array.

[0032] In this embodiment, the second physical address may be the same as or different from the first physical address, and the second ECC code may be the same as or different from the first ECC code. The first ECC code is obtained by the memory controller based on the first physical address.

[0033] In this embodiment, when the command parsing unit receives the access command sent by the memory controller through the CA interface, the received access command and / or ECC verification command may be changed due to a CA interface error. The change in the access command may include changing the first physical address carried to a second physical address, and the change in the ECC verification command may include changing the first ECC code carried to a second ECC code. When the CA interface is faulty, the first physical address may change to generate a different second physical address, and / or the first ECC code may change to generate a different second ECC code. When there is no error in the CA interface, the second physical address is the same as the first physical address, and the second ECC code is the same as the first ECC code.

[0034] In this embodiment, the ECC verification module can use the same ECC verification and error correction algorithm as the ECC encoder to perform ECC verification, realize the checking and error correction of the second physical address, and return an indication signal of the ECC verification result to the memory controller.

[0035] In one exemplary embodiment, the indication signal for the ECC verification result can be one of the following: A first alarm signal indicating that the received second physical address has a single-bit error; A second alarm signal indicating that the received second physical address has a multi-bit error; A verification pass signal indicating that the received second physical address does not contain any errors.

[0036] In this embodiment, when a single-bit error exists in the second physical address, the ECC verification module can correct the single-bit error. The corrected second physical address is the same as the first physical address, and a first alarm signal is sent to the memory controller. The physical address sent by the ECC verification module to the address decoding unit is the first physical address, which is the correct physical address.

[0037] In this embodiment, when there is a multi-bit error in the second physical address, the ECC verification module cannot correct the multi-bit error, but it can send a second alarm signal to the memory controller. The physical address sent by the ECC verification module to the address decoding unit is the second physical address, which is the physical address with the multi-bit error.

[0038] In this embodiment, when there is no error in the second physical address, the ECC verification module sends a verification pass signal to the memory controller. The physical address sent by the ECC verification module to the address decoding unit is the second physical address, which is the same as the first physical address and is a correct physical address.

[0039] In one exemplary embodiment, the memory may further include two alarm pins; the two alarm pins are configured to send the indication signal to the memory controller.

[0040] In this embodiment, by setting two alarm pins, the first alarm signal, the second alarm signal, and the verification pass signal can be distinguished. Since existing memory only has one alarm pin with a width of 1 bit, the output binary data is only 0 and 1, which cannot meet the output indication signal requirements of this embodiment. The two alarm pins can be the first alarm pin and the second alarm pin, and each pin supports 1 bit of binary data output. When the first alarm signal is output, 1 can be output on the first alarm pin and 0 can be output on the second alarm pin, that is, the first alarm signal is 10. When the second alarm signal is output, 1 can be output on the first alarm pin and 1 can be output on the second alarm pin, that is, the second alarm signal is 11. When the verification pass signal is output, 0 can be output on the first alarm pin and 0 can be output on the second alarm pin, that is, the verification pass signal is 00. These three indication signals only need to be different. The above three indication signals 10, 11, and 00 are exemplary descriptions and are not intended to limit this application. They will not be described in detail again.

[0041] In one exemplary embodiment, the ECC verification module may include: The verification unit is configured to perform ECC verification on the second physical address based on the second physical address and the second ECC code, generate the ECC verification result, and send it to the feedback unit; when a single-bit error exists, the error correction unit corrects the second physical address, and the first physical address obtained after correction is used as the output physical address; when there is no error or a multi-bit error exists, the second physical address is used as the output physical address. The error correction unit is configured to correct the second physical address to generate the first physical address, and return the first physical address to the verification unit; The feedback unit is configured to generate the indication signal based on the ECC verification result and send the indication signal to the memory controller through the two alarm pins.

[0042] In this embodiment, when the second physical address has a single-bit error or no error, the physical address sent by the verification unit to the address decoding unit is the correct access address; when the second physical address has multiple-bit errors, the physical address sent by the verification unit to the address decoding unit is the incorrect access address.

[0043] In this embodiment, the feedback unit can be connected to the memory control module through two alarm pins to send the indication signal generated by the feedback unit to the memory control module of the memory controller.

[0044] In one exemplary embodiment, the memory is a dynamic random access memory (DRAM) chip, and the ECC code is an HEC code.

[0045] In this embodiment, the dynamic random access memory (DRAM) may include DDR2, DDR3, DDR4, DDR5, or high bandwidth memory (HBM).

[0046] This application embodiment also provides a storage module, including a memory controller as described in the above embodiments and a memory as described in the above embodiments, such as... Figure 4 As shown.

[0047] In this embodiment, the memory controller and the memory can be connected through the physical layer interface (PHY). The physical layer interface (PHY) can ensure compatibility between the memory controller and the memory, and ensure that the memory controller and the memory can be connected and communicate seamlessly.

[0048] In this embodiment, when the memory controller and the memory are a DDR controller and DRAM respectively, the physical layer interface PHY can be a DDR PHY. The DDR controller, DRAM, DDR PHY, processor and interface, bus, etc., together constitute the DRAM access system. The ECC encoder can be an HEC encoder, and the ECC verification module can be an HEC verification module. Figure 5 As shown.

[0049] In this embodiment, as Figure 5The DRAM access system described above connects the processor to the AXI bus inside the DDR controller via an AXI interface. The read address channel and write address channel of the AXI bus are connected to the address translation unit of the DDR controller, while the write data channel and read data channel of the AXI bus are connected to the DDR PHY. The write data channel includes a first FIFO buffer, and the read data channel includes a second FIFO buffer. The DDR controller also includes a memory control module and an HEC encoder. The memory control module includes an address translation unit and a command generation and transmission unit. The DRAM includes peripheral circuitry, a DRAM array, two alarm pins, and a CA interface. The peripheral circuitry includes a command parsing unit, an HEC verification module, and an address decoding unit. The HEC verification module includes a verification unit, an error correction unit, and a feedback unit. The PHY connects to the DRAM array via a data bus and to the processor via the write and read data channels of the AXI bus. The write data channel includes a first FIFO buffer, and the read data channel includes a second FIFO buffer. This connection enables data transmission between the processor and the first and second FIFO buffers, as well as data transmission between the first and second FIFO buffers and the DRAM array. The DRAM array can include multiple DRAM chips. The DDR PHY connects to two alarm pins of the memory and also to the memory control module. This connection enables the memory to send indication signals to the memory control module. The DDR PHY connects to the memory's CA interface and can also connect to the command generation and sending unit of the memory control module. This connection enables the command generation and sending unit to send access commands and HEC verification commands to the command parsing unit.

[0050] In one exemplary embodiment, the storage module is a CXL storage module, and the memory controller is located in the controller of the CXL storage module.

[0051] In this embodiment, the processor can send CXL message access requests to the controller of the CXL storage module, including CXL message read requests and CXL message write requests. The CXL storage module can read data from the memory and send it to the processor according to the CXL message read request, or the CXL storage module can write the write data it carries to the memory according to the CXL message write request. The CXL storage module can be adapted to check the CXL message access address, thereby improving the reliability of CXL message read and write.

[0052] This application embodiment also provides a memory access method, including steps S100-S400, such as... Figure 6 As shown: S100: The memory controller receives an access request, obtains a first physical address, generates an access command based on the first physical address, and encodes the first physical address to generate an ECC verification command; S200: The memory controller sends the access command and the ECC verification command to the memory; S300: The memory performs ECC verification based on the second physical address carried by the received access command and the second ECC code carried by the received ECC verification command, and returns an indication signal of the ECC verification result to the memory controller; S400: The memory controller performs data transmission control according to the indication signal.

[0053] In this embodiment, steps S100 and S300 use the same ECC error correction algorithm to implement ECC encoding and ECC verification respectively. Step S200 is executed by the memory control module in the memory controller. After step S100 and before step S200, the memory control module can first set the sending timing of the access command and the ECC verification command, so that the ECC verification command follows the access command.

[0054] In this embodiment, when executing step S400, the memory control module of the memory controller can receive an indication signal. The memory control module can control the transmission of written data or read data according to the indication signal. When the indication signal is a first alarm signal or a verification pass signal, the written data can be written to the memory cell array, or the read data can be sent to the processor. When the indication signal is a second alarm signal, the memory control module can report an external processor access failure, and the processor can resend the access request.

[0055] In this embodiment, data can be written from the first FIFO buffer through the write data channel, physical layer interface, and data bus to the storage unit array; data read from the storage unit array can be temporarily stored in the second FIFO buffer through the data bus, physical layer interface, and read data channel.

[0056] In one exemplary embodiment, step S100 may include steps S110-S130: S110: Receive the access request and convert the address carried in the access request into the first physical address; S120: Encode the first physical address to generate a first ECC code; S130: Generate the access command based on the first physical address, and generate the ECC verification command based on the first ECC code.

[0057] In this embodiment, steps S110-S130 are operations performed by the memory controller. The memory controller can receive access requests via the AXI bus. The device physical address carried in the read request can be transmitted to the address translation unit via the read address channel of the AXI bus. The device physical address carried in the write request can be transmitted to the address translation unit via the write address channel of the AXI bus. The address translation unit can perform the "address conversion to the first physical address" in step S110. The address translation unit sends the first physical address to the ECC encoder and the command generation and sending unit. The ECC encoder can perform step S120 and send the generated first ECC code to the command generation and sending unit. The command generation and sending unit can perform step S130.

[0058] To illustrate steps S110 and S120 of the embodiments of this application, the following specific example describes in detail the method for generating a first HEC code using the CRC8 algorithm. This method is based on... Figure 5 The DRAM access system shown in this example uses DDR5 memory. Each channel in the DDR5 memory corresponds to a DDR controller, and each channel corresponds to multiple Ranks. Multiple Ranks will not work simultaneously.

[0059] The process of generating a first physical address from the physical address of the CXL message device and encoding the first physical address using the CRC8 algorithm to generate a first HEC code is as follows: Figure 7 As shown: The physical address of the CXL message device is 40 bits, and its bit index is [39:0]; The address translation unit converts the physical address of the CXL message device into a 40-bit first physical address. The physical address field of the DDR5 memory includes a 3-bit CID address (bit index [2:0]), a 17-bit row physical address Row (bit index [16:0]), a 2-bit Rank physical address (bit index [1:0]), an 11-bit column physical address Col (bit index [10:8] and [7:0]), a 5-bit Bank physical address (bit index [4:0]), and a 2-bit channel physical address Chn (bit index [1:0]). The address translation unit sends the 40-bit first physical address to the HEC encoder. The HEC encoder uses the CRC8 algorithm to implement HEC encoding. The CRC8 algorithm's check formula uses x... 8 +x 2 +x+1 and calculate the initial value as 0; In DDR5 memory, the column physical address Col with bit index [3:0] represents the bit width of the column address, so deleting it will not affect the HEC encoding of the first physical address. Furthermore, since each channel in DDR5 memory corresponds to a DDR controller, and each channel corresponds to multiple Ranks, and multiple Ranks do not work simultaneously, deleting the channel physical address Chn and the Rank physical address will not affect the HEC encoding of the first physical address. Therefore, the HEC encoder deletes 2 bits of the channel physical address Chn, 2 bits of the Rank physical address, and 4 bits of the column physical address Col with bit index [3:0] from the first physical address to obtain a 32-bit HEC calculation address. The 32-bit HEC calculation address includes PHY Addr Byte1, PHY Addr Byte2, PHY Addr Byte3, and PHY Addr Byte4. PHY Addr Byte1 corresponds to CID [2:0] and Bank [4:0], PHY Addr Byte2 corresponds to Row [16:9], PHY Addr Byte3 corresponds to Row [8:1], and PHY Addr Byte4... Byte4 corresponds to Row[0] and Col[10:4].

[0060] When the address information involved in CRC8 calculation is 32 bits long, single-bit error correction can be achieved. The 32-bit HEC calculation address is encoded using the CRC8 algorithm to generate the first 8-bit HEC code.

[0061] In one exemplary embodiment, step S300 may include steps S310-S320: S310: Parse the access command to obtain the second physical address, and parse the ECC verification command to obtain the second ECC code; S320: Perform ECC verification on the second physical address based on the second physical address and the second ECC code, and return an indication signal of the ECC verification result to the memory controller.

[0062] In this embodiment, the second physical address may be the same as or different from the first physical address, and the second ECC code may be the same as or different from the first ECC code.

[0063] In this embodiment, step S310 is the operation performed by the command parsing unit of the memory, and step S320 is the operation performed by the ECC verification module of the memory.

[0064] In one exemplary embodiment, step S320 may include steps S321-S322: S321: Perform the ECC verification based on the second physical address and the second ECC code, and generate the ECC verification result; S322: When a single-bit error exists in the second physical address, the second physical address is corrected, the first physical address obtained after correction is output to the address decoding unit, and a first alarm signal is sent to the memory controller. When the second physical address has a multi-bit error, the second physical address is output to the address decoding unit, and a second alarm signal is sent to the memory controller; When there is no error in the second physical address, the second physical address is output to the address decoding unit, and a verification pass signal is sent to the memory controller.

[0065] In one embodiment of this example, step S321 is executed by the verification unit. The verification process uses an ECC error correction algorithm, such as the CRC8 algorithm. When the verification result is 0, it means that the ECC verification result is that there is no error in the second physical address, that is, the second physical address is the same as the first physical address. The verification unit sends the second physical address to the address decoding unit of the memory and transmits the ECC verification result (no error) to the feedback unit. The feedback unit generates a verification pass signal, and the memory sends the verification pass signal to the memory controller through the alarm pin.

[0066] In another embodiment of this example, step S321 is executed by the verification unit. The verification process uses an ECC error correction algorithm, such as the CRC8 algorithm. When the verification result is not 0, the ECC error correction algorithm can be used to locate the error in the second physical address. When the second physical address has a single-bit error, the verification unit can send the second physical address to the error correction unit for error correction, and restore the second physical address to the first physical address. The error correction unit returns the first physical address obtained after error correction to the verification unit. The verification unit sends the first physical address to the address decoding unit of the memory and transmits the ECC verification result (single-bit error) to the feedback unit. The feedback unit generates a first alarm signal, and the memory sends the first alarm signal to the memory controller through the alarm pin.

[0067] In another embodiment of this example, step S321 is executed by the verification unit. The verification process uses an ECC error correction algorithm, such as the CRC8 algorithm. When the verification result is not 0, the ECC error correction algorithm can be used to locate the error in the second physical address. When the second physical address has a multi-bit error, the verification unit sends the second physical address to the address decoding unit of the memory and transmits the ECC verification result (multi-bit error) to the feedback unit. The feedback unit generates a second alarm signal, and the memory sends the second alarm signal to the memory controller through the alarm pin.

[0068] In this embodiment, when the ECC verification result is that there is no error or a single bit error exists, the physical address output by the verification unit to the address decoding unit is the correct access address. The address decoding unit generates row selection signal, column selection signal, and bank selection signal according to the physical address and sends them to the storage unit array. The storage unit array completes the writing or reading of data according to the row selection signal, column selection signal, and bank selection signal.

[0069] In this embodiment, when the ECC check result indicates a multi-bit error, the second physical address output by the check unit to the address decoding unit is an incorrect access address. The peripheral circuit can still generate row selection signals, column selection signals, and bank selection signals based on the second physical address and send them to the memory cell array. The memory cell array reads data based on the row selection signals, column selection signals, and bank selection signals, and can temporarily store the read data in the second FIFO buffer through the data bus, physical layer interface, and read data channel. The memory control module can report to the processor based on the received second alarm signal and re-acquire the access command.

[0070] In this embodiment, when the HEC verification method is used, the verification unit can perform HEC verification using the CRC8 algorithm based on the second physical address and the second HEC code, such as... Figure 8 As shown, the verification unit can append the second HEC code to the second physical address to form the data to be verified. The data to be verified includes PHY Addr Byte1', PHY Addr Byte2', PHY Addr Byte3', PHY Addr Byte4', and the second HEC code. PHY Addr Byte1', PHY Addr Byte2', PHY Addr Byte3', and PHY Addr Byte4' together constitute the second physical address. When the CA interface malfunctions, a transmission error may occur, causing the second physical address to... Figure 7 The 32-bit HEC calculation address may differ, meaning that PHYAddr Byte1' may differ from... Figure 7The PHY Addr Byte1 is different from the PHY Addr Byte2. Figure 7 The PHY Addr Byte2 is different from the PHY Addr Byte3. Figure 7 The PHY Addr Byte3 is different from the PHY Addr Byte4. Figure 7 If the PHYAddr Byte4 is different, or if the second HEC code is different from the first HEC code, the verification unit can use the CRC8 algorithm to verify the data to be verified. If the verification result is 0, it indicates that there is no error in the second physical address. If the verification result is not 0, it is necessary to further determine whether there is a single-bit error or a multi-bit error in the second physical address.

[0071] To illustrate the memory access method of this application embodiment, a specific example two is used below to describe in detail the memory writing method, which is based on... Figure 5 The DRAM access system execution shown includes steps WS1 to WS10, wherein WS8 includes WS8-1, WS8-2, or WS8-3: WS1: The processor sends a CXL message write request. The physical address of the write device carried by the CXL message is transmitted to the address translation unit through the write address channel of the AXI bus. The write data carried by the write request is temporarily stored in the first FIFO buffer. WS2: The address translation unit converts the physical address of the write device into the first physical address, and outputs the first physical address to the HEC encoder and the command generation and transmission unit respectively; WS3: The HEC encoder uses the CRC8 algorithm to encode the first physical address, generating an 8-bit first HEC code; WS4: The command generation and sending unit generates an access command W (write command) based on the first physical address, generates an HEC verification command based on the first HEC code, and sets the command sending timing. WS5: The command generation and sending unit sends the access command W and the HEC verification command sequentially according to the transmission sequence, and sends them to the CA interface through the DDR PHY; the command parsing unit receives the access command W and the HEC verification command sent by the CA interface; the first FIFO buffer sends the write data to the DDR PHY; WS6: The command parsing unit parses the access command W to obtain the second physical address and outputs it to the verification unit; it parses the HEC verification command to obtain the second HEC code and outputs it to the verification unit. WS7: The verification unit performs HEC verification on the second physical address based on the second physical address and the second HEC code, and uses the CRC8 algorithm to generate the HEC verification result; WS8-1: If the HEC check result indicates a single-bit error in the second physical address, the check unit sends the HEC check result to the feedback unit, which generates an indication signal—the first alarm signal 10—and outputs it to two alarm pins. The check unit sends the second physical address to the error correction unit, which corrects the second physical address and returns the corrected first physical address to the check unit. The check unit then outputs the first physical address to the address decoding unit. WS8-2: If the HEC check result indicates that there is a multi-bit error in the second physical address, the check unit sends the HEC check result to the feedback unit, the feedback unit generates an indication signal - the second alarm signal 11 and outputs it to two alarm pins, and the check unit outputs the second physical address to the address decoding unit. WS8-3: If the HEC check result indicates that there is no error in the second physical address, the check unit sends the HEC check result to the feedback unit, the feedback unit generates an indication signal - check pass signal 00 and outputs it to two alarm pins, and the check unit outputs the second physical address to the address decoding unit; WS9: The address decoding unit performs address decoding based on the first physical address or the second physical address, generates address selection signals row, col, and rank, and outputs the address selection signals to the DRAM array; the two alarm pins send indication signals to the memory control module through the DDR PHY; WS10: When the indication signal received by the memory control module is the first alarm signal 10 and the second alarm signal 11, the error can be recorded for subsequent processing. For multi-bit errors, retransmission can be performed.

[0072] To illustrate the memory access method of this application embodiment, a specific example three is used below to describe in detail the memory reading method, which is based on... Figure 5 The DRAM access system execution shown includes steps RS1 to RS10, wherein RS8 includes RS8-1, RS8-2, or RS8-3: RS1: The processor sends a CXL message read request, and the physical address of the read device carried in the CXL message is transmitted to the address translation unit through the read address channel of the AXI bus; RS2: The address translation unit converts the physical address of the reading device into the first physical address, and outputs the first physical address to the HEC encoder and the command generation and transmission unit respectively; RS3: The HEC encoder uses the CRC8 algorithm to encode the first physical address, generating an 8-bit first HEC code; RS4: The command generation and sending unit generates an access command R (read command) based on the first physical address, generates an HEC verification command based on the first HEC code, and sets the command sending timing. RS5: The command generation and sending unit sends the access command R and the HEC verification command sequentially according to the sending sequence, and sends them to the CA interface through the DDR PHY; the command parsing unit receives the access command R and the HEC verification command sent by the CA interface. RS6: The command parsing unit parses the access command R to obtain the second physical address and outputs it to the verification unit; it parses the HEC verification command to obtain the second HEC code and outputs it to the verification unit. RS7: The verification unit performs HEC verification on the second physical address based on the second physical address and the second HEC code, and uses the CRC8 algorithm to generate the HEC verification result. RS8-1: If the HEC check result indicates a single-bit error in the second physical address, the check unit sends the HEC check result to the feedback unit, which generates an indication signal—the first alarm signal 10—and outputs it to two alarm pins; the check unit sends the second physical address to the error correction unit, which corrects the second physical address and returns the corrected first physical address to the check unit, which outputs the first physical address to the address decoding unit; RS8-2: If the HEC check result indicates that there is a multi-bit error in the second physical address, the check unit sends the HEC check result to the feedback unit, the feedback unit generates an indication signal - the second alarm signal 11 and outputs it to the two alarm pins, and the check unit outputs the second physical address to the address decoding unit. RS8-3: If the HEC check result indicates that there is no error in the second physical address, the check unit sends the HEC check result to the feedback unit, the feedback unit generates an indication signal - check pass signal 00 and outputs it to two alarm pins, and the check unit outputs the second physical address to the address decoding unit. RS9: Two alarm pins send indication signals to the memory control module via the DDR PHY; the address decoding unit performs address decoding based on the first physical address or the second physical address, generates address selection signals row, col, and rank, and outputs the address selection signals to the DRAM array. The DRAM array uses the data stored at the address indicated by the address selection signal as the read data and temporarily stores it in the second FIFO temporary storage area via the data bus and the DDR PHY. RS10: When the indication signal received by the memory control module is the first alarm signal or the second alarm signal, the error can be recorded for subsequent processing. For multi-bit errors, retransmission can be performed.

[0073] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A memory controller, characterized in that, include: The memory control module is configured to generate an access command based on a received access request and send the access command to the memory, the access command carrying a first physical address; An ECC encoder is configured to encode the first physical address using an error correction algorithm capable of correcting at least a single bit error, thereby generating a first ECC code. The memory control module is further configured to generate an ECC verification command based on the first ECC code and send the ECC verification command to the memory, wherein the ECC verification command carries the first ECC code.

2. The memory controller as claimed in claim 1, characterized in that, Also includes: The memory control module is also configured to receive an indication signal of the ECC verification result sent by the memory.

3. The memory controller as described in claim 1, characterized in that, The memory control module includes an address translation unit and a command generation and sending unit; The address translation unit is configured to convert the address carried in the received access request into the first physical address, and output the first physical address to the ECC encoder and the command generation and sending unit; The command generation and sending unit is configured to generate the access command based on the first physical address, generate the ECC verification command based on the received first ECC code, and send the access command and the ECC verification command to the memory in sequence.

4. The memory controller as described in claim 1, characterized in that: The memory controller is a DDR controller or a high-bandwidth memory controller; The ECC encoder is an HEC encoder, the first ECC code is an HEC code, and the first ECC code of the first physical address supports single-bit error correction and multi-bit error checking for the first physical address.

5. A memory, characterized in that, include: Peripheral circuits and memory cell arrays; The peripheral circuitry includes a command parsing unit, an ECC verification module, and an address decoding unit. The command parsing unit is configured to receive access commands and ECC verification commands sent by the memory controller, parse the access commands to obtain the second physical address, and parse the ECC verification commands to obtain the second ECC code of the second physical address. The ECC verification module is configured to perform ECC verification on the second physical address based on the second physical address and the second ECC code, return an indication signal of the ECC verification result to the memory controller, and output the physical address based on the ECC verification result. The address decoding unit is configured to generate an address selection signal based on the physical address output by the ECC verification module, and output the address selection signal to the memory cell array. The storage cell array is configured to select a corresponding storage cell according to the address selection signal, and to store or retrieve data in the selected storage cell.

6. The memory as described in claim 5, characterized in that: The indication signal for the ECC verification result is one of the following: A first alarm signal indicating that the received second physical address has a single-bit error; A second alarm signal indicating that the received second physical address has a multi-bit error; A verification pass signal indicating that the received second physical address does not contain any errors.

7. The memory as claimed in claim 6, characterized in that: It also includes two alarm pins; The two alarm pins are configured to send the indication signal to the memory controller.

8. The memory as claimed in claim 7, characterized in that, The ECC verification module includes: The verification unit is configured to perform ECC verification on the second physical address based on the second physical address and the second ECC code, generate the ECC verification result, and send it to the feedback unit; when a single-bit error exists, the error correction unit corrects the second physical address and uses the first physical address obtained after correction as the output physical address; when there is no error or a multi-bit error exists, the second physical address is used as the output physical address. The error correction unit is configured to correct the second physical address to generate the first physical address, and return the first physical address to the verification unit; The feedback unit is configured to generate the indication signal based on the ECC verification result and send the indication signal to the memory controller through the two alarm pins.

9. The memory as claimed in claim 5, characterized in that: The memory is a dynamic random access memory (DRAM) chip, and the ECC code is an HEC code.

10. A storage module, comprising a memory controller and a memory, characterized in that: The memory controller is the memory controller as described in any one of claims 1-4; The memory is the memory described in any one of claims 5-9.

11. The storage module as described in claim 10, characterized in that: The storage module is a CXL storage module, and the memory controller is located in the controller of the CXL storage module.

12. A memory access method, characterized in that, include: The memory controller receives an access request, obtains a first physical address, generates an access command based on the first physical address, and encodes the first physical address to generate an ECC verification command. The memory controller sends the access command and the ECC verification command to the memory; The memory performs ECC verification based on the second physical address carried by the received access command and the second ECC code carried by the received ECC verification command, and returns an indication signal of the ECC verification result to the memory controller. The memory controller performs data transmission control according to the indication signal.

13. The memory access method as described in claim 12, characterized in that, The memory controller receives an access request, obtains a first physical address, generates an access command based on the first physical address, and encodes the first physical address to generate an ECC verification command, including: Receive the access request and convert the address carried in the access request into the first physical address; The first physical address is encoded to generate the first ECC code; The access command is generated based on the first physical address, and the ECC verification command is generated based on the first ECC code.

14. The memory access method as described in claim 13, characterized in that, The memory performs ECC verification based on the second physical address carried in the received access command and the second ECC code carried in the received ECC verification command, and returns an indication signal of the ECC verification result to the memory controller, including: The access command is parsed to obtain the second physical address, and the ECC verification command is parsed to obtain the second ECC code; The second physical address is subjected to ECC verification based on the second physical address and the second ECC code, and an indication signal of the ECC verification result is returned to the memory controller.

15. The memory access method as described in claim 14, characterized in that, The step of performing ECC verification on the second physical address based on the second physical address and the second ECC code, and returning an indication signal indicating the ECC verification result to the memory controller, includes: The ECC verification is performed based on the second physical address and the second ECC code to generate the ECC verification result. When a single-bit error exists in the second physical address, the second physical address is corrected, the first physical address obtained after correction is output to the address decoding unit, and a first alarm signal is sent to the memory controller. When the second physical address has a multi-bit error, the second physical address is output to the address decoding unit, and a second alarm signal is sent to the memory controller; When there is no error in the second physical address, the second physical address is output to the address decoding unit, and a verification pass signal is sent to the memory controller.

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