A configurable NAND flash controller

By introducing a dynamic hierarchical FTL module and a phased state machine driving mechanism into the NAND Flash controller, and combining hot and sequential feature extraction, online hierarchical writing and dynamic path selection are realized. This solves the problems of high random write latency, write amplification effect and high garbage collection pressure in the existing technology, and improves the performance stability of the system and the versatility of the controller.

CN122363609APending Publication Date: 2026-07-10HEFEI ZHONGKE MICROELECTRONICS INNOVATION CENT CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HEFEI ZHONGKE MICROELECTRONICS INNOVATION CENT CO LTD
Filing Date
2026-03-27
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

Existing NAND Flash controllers lack online tiered writing and dynamic path selection mechanisms in mixed SLC/TLC storage scenarios, resulting in high random write latency, significant write amplification effect, increased garbage collection pressure, and insufficient performance stability under load fluctuations.

Method used

A configurable NAND Flash controller is provided. By extracting heat and sequence characteristics at the PS end and combining them with a dynamic hierarchical FTL module to make hierarchical decisions, it dynamically selects the SLC or TLC storage path. At the PL end, a staged state machine is used to drive the NAND Flash operation process. High-speed data conversion is achieved by utilizing FPGA resources. AXI-Lite-mapped configuration register group and status register group are set to realize parameter configuration and status monitoring.

Benefits of technology

Reduce random write latency, mitigate write amplification, reduce garbage collection pressure, improve write stability and sustained performance under fluctuating load scenarios, and enhance controller versatility and system observability.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122363609A_ABST
    Figure CN122363609A_ABST
Patent Text Reader

Abstract

The application discloses a configurable NAND Flash controller and relates to the field of NAND Flash control. The controller comprises a PS control module and a PL logic implementation controller module. The PS control module communicates with the PL logic implementation controller module through an AXI bus, and the PL logic implementation controller module is connected with a NAND Flash. The PS control module comprises a host computer communication module, a dynamic layered FTL module and a NAND Flash channel controller module. The PL logic implementation module comprises an AXI-Lite interface module, an AXI-Stream interface module, a clock module, an ECC module, an instruction generation and data buffer processing module and a multi-path NAND Flash channel controller module. The controller is used for data read-write control and online layered writing in a mixed SLC / TLC scene, so that the random write performance is improved.
Need to check novelty before this filing date? Find Prior Art