An artificial intelligence agent hardware security mode switching apparatus

Abstract

This invention discloses a hardware-triggered security mode switching device and method for artificial intelligence agents, belonging to the fields of G06F21 / 71 and G11C17 / 14. Addressing the shortcomings of existing technologies that rely on software / main control chips, this invention employs an independent hardware module design, including a non-electrically erasable storage structure (such as mask ROM, OTP) for storing a security rule set, a hardware instruction monitoring unit for physically intercepting and parsing instruction streams, a hardware anomaly detection unit for comparing security rules, a hardware security mode triggering unit for generating trigger signals, and a physically isolated security mode execution interface for transmitting signals. The device is completely independent of the agent's main control chip and any externally loadable and modifiable software, ensuring that security mode switching can still be performed even if the main control chip fails or is attacked. This solution effectively prevents the execution of harmful commands sent from data centers, provides hardware-level tamper-proof security protection, 100% resists malicious instruction tampering, and significantly improves the security of artificial intelligence agents.

Description

Technical Field

[0001] This invention relates to the technology in the fields of G06F21 / 71 and G11C17 / 14, and in particular to a hardware security control module for an artificial intelligence agent based on a non-electrically erasable and rewritable memory structure, used to prevent the execution of various harmful instructions and ensure that the agent switches to a safe mode state by hardware triggering after receiving a harmful instruction. Terminology Explanation The "non-electrically rewritable storage structure" described in this invention includes all storage media such as mask ROM and OTP that cannot be erased or modified by electrical signals after leaving the factory. These storage media have their storage security rules and parameters fixed by a specific process before leaving the factory, and once fixed, they cannot be modified by any software or electrical signals. Background Technology

[0002] Currently, the safety control of artificial intelligence agents (such as humanoid robots and industrial robots) mainly relies on the main control chip and software-level protection mechanisms, which have the following key shortcomings: 1. Software tamperability: Existing security control schemes are usually based on software algorithms, which can be reverse-engineered, modified, or bypassed by malicious attackers, and cannot provide true physical-level security protection. 2. Risk of main control chip failure: When the main control chip fails due to malfunction or attack, the entire security control system will fail, and the security behavior of the intelligent agent under extreme conditions cannot be guaranteed. 3. Reversibility of storage media: Traditional memory (such as EEPROM, Flash) can be erased, written or modified during operation, and the security rule set and parameters may be maliciously tampered with. 4. Command streams are easily intercepted: Existing command stream monitoring solutions are mostly implemented through software, lacking physical isolation and direct interception capabilities at the hardware level, and cannot effectively prevent the execution of malicious commands. Summary of the Invention

[0003] This invention aims to address the shortcomings of existing technologies that rely on software / main control chips, and provides a hardware-level security protection mechanism to ensure that the switching of intelligent agent security modes is not affected by software or externally loadable programs. Purpose of the invention: To provide a hardware-triggered security mode switching device and method for artificial intelligence agents, which achieves physical interception of instruction streams, unmodifiable storage of security rules, and triggering execution of security modes through an independent hardware module, ensuring that security mode switching can still be performed even if the main control chip fails or is attacked. Technical Solution: This invention provides a hardware-triggered artificial intelligence agent safety mode switching device and method, the core of which is to use an independent hardware module to achieve the following functions: 1. Hardware secure storage module: It adopts a non-electrically erasable storage structure (such as mask ROM or OTP), and the storage behavior constraint rule set and security mode parameters are fixed before leaving the factory to ensure that these rules and parameters cannot be modified by software or external signals during operation. 2. Hardware instruction monitoring unit: It adopts customized ASIC / FPGA hardware logic circuits to physically intercept and parse the execution instruction stream of the intelligent agent. The interception and parsing process is independent of the main control chip of the intelligent agent, without the participation of any external loadable or modifiable software. 3. Hardware anomaly detection unit: It adopts hardware comparison logic circuit and generates anomaly detection signal based on the hardware comparison result of the execution instruction stream and the behavioral constraint rule set. The anomaly detection process does not require the participation of the main control chip. 4. Hardware security mode triggering unit: generates a security mode triggering signal in response to an anomaly detection signal. 5. Safe mode execution interface: It adopts a physically isolated hardware interface (such as PCIe / USB-C) and transmits the safe mode trigger signal to the execution control unit of the intelligent agent through a hardware communication path independent of the main control chip. Beneficial effects: This invention achieves the following key advantages through a hardware-level security protection mechanism: • 100% protection against malicious command tampering: The security rule set and parameters are permanently stored using a non-electrically rewritable storage structure, which cannot be modified by software or external signals. • Resistance to main control failure: All security mode switching processes are completely independent of the main control chip. Even if the main control chip fails or is attacked, the security mode switching can still be performed. • Real-time security detection: The hardware instruction monitoring unit and anomaly detection unit directly process the instruction stream, without relying on the software processing of the main control chip, resulting in faster detection speed. • Hardware-level physical isolation: The safe mode execution interface adopts a physical isolation design to ensure that the trigger signal transmission path is not controlled by the main control chip. • High reliability: Independent power supply and clock source design improve system stability and reliability, avoiding safety function failures due to power fluctuations. Attached Figure Description

[0004] Figure 1: Block diagram of the device Figure 1 shows the overall structure of the device of the present invention, including the following key components: • Hardware secure storage module (1): It adopts a non-electrically erasable storage structure, such as mask ROM or OTP, to solidify storage security rules and parameters. • Hardware instruction monitoring unit (2): A hardware logic circuit implemented using ASIC or FPGA, used to physically intercept and parse the execution instruction stream. • Hardware anomaly detection unit (3): A hardware comparison logic circuit implemented with FPGA, used to detect harmful instructions in the execution instruction stream. • Hardware security mode trigger unit (4): used to generate security mode trigger signal. • Safe Mode Execution Interface (5): Uses PCIe or USB-C interface to achieve physical isolation communication with the main control chip. • Independent power supply module (6): Provides a stable 5V±0.5V power supply, which is completely isolated from the main control chip power system. • Independent clock source (7): Provides a 16MHz ± 1% clock signal to ensure that the device is not affected by the main control chip clock. Figure 2: Method Flowchart Figure 2 illustrates the specific flow of the method of the present invention, including the following key steps: • Step 201: Solidify storage security rules and parameters to an electrically erasable and rewritable storage structure. • Step 202: The hardware instruction monitoring unit physically intercepts and parses the execution instruction stream. • Step 203: The hardware anomaly detection unit performs a hardware comparison between the instruction stream and the security rules. • Step 204: Generate a safe mode trigger signal when a hazard command is detected. • Step 205: Transmit the trigger signal to the execution control unit through the physical isolation interface. Figure 3: Circuit diagram of storage module Figure 3 illustrates the specific implementation of the non-electrically erasable and non-writable memory structure in this invention: • The left side is the mask ROM structure (301): the data is solidified and stored through photolithography, including regular storage area and parameter storage area, and the data cannot be modified after it is written. • The right side is the OTP structure (302): It achieves one-time writing through anti-fuse programming. After programming, the fuse blows and locks the data, and the data cannot be modified irreversibly. • The middle part is the control circuit (303): including read-only control during operation, one-time write control during the factory process, and permanent lock control after solidification, to ensure that there are no erase / write / modification operations during operation, which meets the security requirements of being tamper-proof. Detailed Implementation

[0005] Example 1: Humanoid Robot Safety Mode Switching Device In this embodiment, the device is an independent hardware module physically separated from the humanoid robot's main control board. It adopts an independent power supply (5V±0.5V) and an independent clock source (16MHz±1%) design to ensure that its operation is not affected by the main control chip's power supply or clock. The hardware secure storage module employs mask ROM technology and has a capacity of 1MB. It is used to permanently store the set of behavioral constraint rules and safety mode parameters for the humanoid robot. These rules include arm movement restrictions, vertical standing posture parameters, etc. Once permanently stored, they cannot be modified by any electrical signals or software. The hardware instruction monitoring unit uses a customized ASIC circuit, which is electrically connected to the humanoid robot's instruction flow bus. It directly intercepts and parses the instruction flow through dedicated hardware logic, without relying on the main control chip's software processing. The hardware anomaly detection unit uses a hardware comparison logic circuit implemented with an FPGA to compare the parsed instruction stream with the behavioral constraint rule set in the mask ROM in real time to detect whether there are harmful instructions. When a hazard command is detected, the hardware safety mode triggering unit generates a safety mode trigger signal and transmits the trigger signal to the humanoid robot's execution control unit through a physically isolated PCIe interface, causing it to enter safety mode: slowly lowering its arms to a vertical position and standing still with its legs upright. Example 2: Industrial Robot Safety Mode Switching Device In this embodiment, the device uses OTP memory technology with a capacity of 512KB. Before leaving the factory, the safety mode parameters (such as the home return instruction set) of the industrial robot are written to it once using a dedicated programming device. After OTP programming, irreversible solidification is achieved through a fuse locking mechanism. The hardware instruction monitoring unit uses ASIC circuits to monitor the execution instruction flow bus of the industrial robot and detect whether there are harmful instructions (such as motion instructions that exceed the safe range). The hardware anomaly detection unit uses a hardware comparison logic circuit implemented with FPGA to compare the instruction stream with the security rules stored in OTP and generate anomaly detection signals. When a hazard command is detected, the hardware safety mode trigger unit generates a safety mode trigger signal and transmits the signal to the industrial robot's execution control unit via the USB-C interface, causing it to enter safety mode: slowly stop the current action and slowly return to its original position. Example 3: Multi-scenario Application Expansion The hardware security control device of the present invention can be extended to various artificial intelligence agent scenarios, including: • Service robots: Safety mode includes stopping all actions and remaining stationary. • Autonomous driving system: Safety modes include switching to safe driving mode, reducing vehicle speed, and maintaining lane position. • Medical AI system: Safety mode includes switching to conservative treatment mode to avoid high-risk operations. In all embodiments, the hardware modules of the device employ independent power supply and clock source design to ensure that their operation is unaffected by the power supply or clock of the main control chip. The safe mode execution interface adopts a physically isolated design to ensure that the trigger signal transmission path is not controlled by the main control chip.

Claims

1. A hardware-triggered artificial intelligence agent security mode switching device, characterized in that, The device is an independent hardware module physically separated from the main control board of the intelligent agent, and it adopts an independent power supply and independent clock source design; the device includes: The hardware secure storage module is a non-electrically erasable and rewritable storage structure (such as mask ROM, OTP), and is configured with a set of storage behavior constraint rules and at least one preset security mode parameters that are factory-fixed. The hardware instruction monitoring unit is a hardware logic circuit (e.g., a customized ASIC / FPGA) electrically connected to the execution instruction flow bus of the intelligent agent. It is configured to physically intercept and parse the execution instruction flow of the intelligent agent, and the interception and parsing process is independent of the main control chip of the intelligent agent, without the participation of any external loadable or modifiable software. The hardware anomaly detection unit is electrically connected to the hardware instruction monitoring unit and is a hardware comparison logic circuit. It is configured to generate an anomaly detection signal based on the hardware comparison result between the execution instruction stream and the behavior constraint rule set, and the anomaly detection process is completed without the participation of the main control chip. A hardware security mode triggering unit is electrically connected to the hardware anomaly detection unit and is configured to generate a security mode triggering signal in response to the anomaly detection signal. The safe mode execution interface is a hardware interface (e.g., PCIe / USB-C) that is physically isolated from the main control chip. It is electrically connected to the hardware safe mode trigger unit and is configured to transmit the safe mode trigger signal and the corresponding safe mode parameters to the execution control unit of the intelligent agent through a hardware communication path independent of the main control chip. The generation, transmission, and retrieval of the security mode trigger signal are completely independent of the main control chip of the intelligent agent and any externally loadable and modifiable software running on it, ensuring that the security mode switching can still be performed when the main control chip fails or is attacked.

2. A hardware-triggered method for switching the security mode of an artificial intelligence agent, applied in the artificial intelligence agent security mode switching device as described in claim 1, characterized in that it includes the following steps:

1. The behavioral constraint rule set and at least one preset security mode parameter are factory-fixed and stored in the hardware security storage module of the device's non-electrically erasable storage structure (e.g., mask ROM, OTP); 2. Through the hardware logic circuit (e.g., customized ASIC / FPGA) hardware instruction monitoring unit of the device, the execution instruction stream on the intelligent agent execution instruction stream bus is physically intercepted and parsed. The interception and parsing process is independent of the main control chip of the intelligent agent and does not involve any external loadable or modifiable software.

3. The hardware anomaly detection unit of the device performs a hardware comparison between the execution instruction stream and the behavior constraint rule set, and generates an anomaly detection signal based on the comparison result. The anomaly detection process does not require the participation of the main control chip.

4. The hardware security mode triggering unit of the device generates a security mode triggering signal in response to the anomaly detection signal; 5. Through the physical isolation hardware interface (e.g., PCIe / USB-C) of the device, the security mode execution interface and independent hardware communication path are used to transmit the security mode trigger signal and the corresponding security mode parameters to the execution control unit of the intelligent agent, so that the intelligent agent switches to the preset security mode; in, The entire execution process of steps 2)-5) is completely independent of the main control chip of the agent and any externally loadable and modifiable software running on it, ensuring that the agent's security mode switching can still be performed when the main control chip fails or is attacked.

3. A hardware security control device for artificial intelligence agents, characterized in that, The device is an independent hardware module physically separated from the main control board of the intelligent agent, and it adopts an independent power supply and independent clock source design, including: The hardware secure storage unit is a non-electrically erasable and non-writable storage structure (such as mask ROM, OTP), with fixed storage behavior constraints and preset security response parameters; The hardware instruction monitoring unit is a hardware logic circuit (such as a customized ASIC / FPGA) that is electrically connected to the execution instruction flow bus of the intelligent agent. It physically monitors the execution instruction flow that passes through it. The monitoring process is independent of the main control chip of the intelligent agent and does not involve any external loadable or modifiable software. The hardware anomaly detection unit, electrically connected to the hardware instruction monitoring unit, is a hardware comparison logic circuit configured to generate anomaly detection signals based on the hardware comparison results between the execution instruction stream and the behavior constraint rule set. A hardware security mode triggering unit is electrically connected to the hardware anomaly detection unit and is configured to generate a security mode triggering signal in response to the anomaly detection signal. The safe mode execution interface is a hardware interface (e.g., PCIe / USB-C) that is physically isolated from the main control chip. It is electrically connected to the hardware safe mode trigger unit and is configured to transmit the safe mode trigger signal to the execution control unit of the intelligent agent through a hardware communication path independent of the main control chip. The generation and transmission of the security mode trigger signal are completely independent of the main control chip of the intelligent agent and any externally loadable and modifiable software running on it.

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