Phase-locked loop based multi-motor global clock synchronization system and method

Abstract

This invention belongs to the field of motor synchronous control, and particularly relates to a multi-motor global clock synchronization system and method based on a phase-locked loop (PLL). The system includes a clock generation module and N motor control channels. The clock generation module generates a global reference clock signal in a preset frequency band. Each channel includes a phase detection module, a trigger phase adjustment module, a PID calculation module, and a drive module. During operation, the phase detection module detects the phase difference between the trigger feedback signal of its channel and the global reference clock signal and outputs the deviation. The trigger phase adjustment module adjusts the phase of the trigger signal according to the deviation. When the phase difference is less than a preset locking threshold, it outputs a calibration trigger signal locked to the reference edge of the global reference clock signal. The PID calculation module is triggered only when the locking edge arrives to perform proportional-integral-derivative (PI) calculations and generate motor control quantities. The drive module drives the motor accordingly, thereby eliminating synchronization errors caused by phase mismatch at the trigger edge.

Description

Technical Field

[0001] This invention belongs to the field of motor synchronization control, and particularly relates to a multi-motor global clock synchronization system and method based on phase-locked loop. Background Technology

[0002] In multi-motor cooperative control systems, achieving precise synchronous operation of multiple motors requires that the PID calculation modules of each motor control channel can start calculations and update control quantities simultaneously. In existing solutions, even if the microcontroller sets the same control cycle for each motor, the trigger signals for each channel essentially originate from different timer frequency division links or software interrupt services. These trigger sources lack a unified global clock reference. Affected by crystal oscillator frequency drift, interrupt nesting delays, and task scheduling jitter, there will inevitably be random phase deviations between the rising edges of triggers from different channels, with these deviations fluctuating randomly on the order of microseconds to milliseconds. When the PID calculation modules of multiple motors start calculations and update control quantities at different times, even if the position commands are exactly the same, the actual drive timing of each motor cannot remain synchronized, resulting in accumulated mechanical errors. This multi-channel trigger edge "lock-up" problem cannot be completely eliminated simply by increasing the processor's clock frequency or introducing a real-time operating system, because the software execution mechanism inherently lacks the ability to align multiple hardware trigger edges at the nanosecond level. Therefore, in a multi-motor control system, how to force the trigger start-up edges of the PID calculation modules of each channel to be locked to the same reference clock edge from the random phase relationship that originally belonged to different clock domains, thereby eliminating the random jitter of the control cycle caused by the phase deviation of the trigger edge, and compressing the timing error of the multi-motor control cycle from the millisecond level to the nanosecond level, has become a key technical problem that urgently needs to be solved in this field.

[0003] To address the aforementioned issues, various multi-motor synchronous control schemes have been proposed by those skilled in the art in recent years. For example, patent CN1170157A discloses a method and apparatus for manipulating a drive system. The drive system includes at least two drive groups with multiple drive devices regulated by drive regulators. The drive regulators of one drive group are synchronized via a drive bus using local synchronization clock pulses. These local synchronization clock pulses are synchronized with the global synchronization clock pulses via a drive data network connected to the drive control device, and the synchronization of the entire device's drive devices is achieved through a global signal. This scheme achieves synchronization of the drive devices through the coordination of local and global synchronization clocks. However, it relies on the drive data network to transmit synchronization clock pulses, making it difficult to eliminate delays and jitter along the transmission path. The accuracy of synchronizing the local and global synchronization clocks is limited by the real-time performance of the communication network. In high-precision applications below the microsecond level, the residual phase deviation between the trigger edges of each drive device remains significant.

[0004] For example, patent application CN115912999A discloses a multi-motor synchronous drive control system and method, including a DSP module, an FPGA module, a synchronization processing circuit, and a multi-motor load. The DSP module processes the position and current data of each motor to obtain the voltage control quantity of each motor and sends it to the FPGA module. The FPGA module generates the position and current data of each motor based on the digital signals from the position and current sensors and sends it to the DSP module, converting the voltage control quantity into a PWM wave signal. The synchronization processing circuit generates a motor drive signal based on the PWM wave signal and sends it to the multi-motor load. This scheme solves the cumulative error problem caused by the system clock asynchrony by using a dual-processor system of DSP and FPGA. However, since the data processing is performed by independent dual processors, each processor operates in an independent clock domain. The data interaction between the DSP and FPGA still has a cross-clock domain synchronization delay, and the start time of the PID calculation of each motor control channel cannot guarantee strict edge-level alignment.

[0005] Furthermore, in the field of industrial motion control, real-time Ethernet technologies such as EtherCAT use distributed clocks (DC) to synchronize clocks between network devices, allowing each device to share the same system time. DC provides synchronization accuracy better than 1 microsecond. However, the distributed clock mechanism synchronizes the local clock counters of each network node, rather than the PID trigger edges of each motor control channel. The time between the node's local clock and the PID calculation start edge still requires a software interrupt service or hardware timer comparison and matching step. The delay jitter introduced by this step is usually on the order of tens of nanoseconds to several microseconds, which is difficult to meet the sub-microsecond requirements of multi-motor synchronous control.

[0006] In summary, how to force the starting edge of the PID calculation of multiple motors from the random phase relationship belonging to different clock domains to the same reference clock edge, so as to eliminate the timing jitter of the control cycle caused by the phase deviation of the trigger edge, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention proposes a multi-motor global clock synchronization system and method based on a phase-locked loop (PLL). The system includes a clock generation module and N motor control channels. The clock generation module generates a global reference clock signal within a preset frequency band. Each channel includes a phase detection module, a trigger phase adjustment module, a PID calculation module, and a drive module. During operation, the phase detection module detects the phase difference between the trigger feedback signal of its channel and the global reference clock signal and outputs the deviation. The trigger phase adjustment module adjusts the phase of the trigger signal according to the deviation in the direction of decreasing the phase difference. When the phase difference is less than a preset locking threshold, it outputs a calibration trigger signal locked to the reference edge of the global reference clock signal. The PID calculation module is triggered only when the locking edge arrives to perform proportional-integral-derivative (PID) calculations and generate motor control quantities. The drive module drives the motor accordingly. All channels use the same global reference clock signal as the phase-locked reference, forcing the start edges of each PID calculation to be aligned with the same reference edge. The timing deviation of the multi-motor control cycle does not exceed a preset synchronization accuracy threshold, thereby fundamentally eliminating synchronization errors caused by trigger edge phase mismatch.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] A multi-motor global clock synchronization system based on a phase-locked loop includes:

[0010] The clock generation module is configured to generate a global reference clock signal in a preset frequency band;

[0011] N motor control channels, each channel controls one motor, and each channel includes:

[0012] The phase detection module receives the global reference clock signal at its first input terminal and a trigger feedback signal representing the current phase of the trigger signal of this channel at its second input terminal. It is configured to detect the phase difference between the trigger feedback signal and the global reference clock signal and output a deviation amount proportional to the phase difference.

[0013] The trigger phase adjustment module is configured to adjust the phase of the trigger signal of this channel in the direction of reducing the phase difference according to the deviation amount, and output a calibration trigger signal when the phase difference is reduced to within a preset locking threshold. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal.

[0014] The PID calculation module is configured to be triggered only when the locking edge of the calibration trigger signal arrives to perform proportional-integral-derivative operations and output motor control quantities.

[0015] The drive module is configured to drive the corresponding motor according to the motor control quantity; wherein, the trigger phase adjustment module of all channels uses the global reference clock signal as a common phase-locked reference, so that the operation start edge of each PID calculation module is aligned to the same reference edge of the global reference clock signal.

[0016] Specifically, the output deviation amount, which is proportional to the phase difference, includes:

[0017] The time interval between the edge of the trigger feedback signal and the reference edge of the global reference clock signal is measured, and a digital quantization value that is linearly proportional to the time interval is output; wherein, the digital quantization value is equal to the time interval divided by the period of the global reference clock signal, and the unit resolution of the digital quantization value is one clock cycle of the global reference clock signal;

[0018] The digital quantization value calculated in the current control cycle is compared with the historical digital quantization value in the previous control cycle to obtain the phase deviation change.

[0019] The proportional adjustment component is obtained by multiplying the digital quantization value by a preset proportional coefficient, and the integral adjustment component is obtained by multiplying the phase deviation change by a preset integral coefficient. The proportional adjustment component and the integral adjustment component are then superimposed to generate the deviation.

[0020] Specifically, the values ​​of the preset proportional coefficient and the preset integral coefficient satisfy the following conditions: the product of the preset proportional coefficient and the digital quantization value of the current control cycle constitutes a proportional adjustment component, and the product of the preset integral coefficient and the phase deviation change of the current control cycle constitutes an integral adjustment component; the phase adjustment step size generated by the phase adjustment module driven by the deviation is equal to the sum of the proportional adjustment component and the integral adjustment component; wherein, the value of the preset proportional coefficient is such that when the digital quantization value is a first value, the single phase adjustment step size is not greater than a first preset step size threshold; the value of the preset integral coefficient is such that when the phase deviation change is a second value, the single phase adjustment step size is not greater than a second preset step size threshold; and when the digital quantization value decreases from the first value of the current control cycle to the second value of the next control cycle, the corresponding phase adjustment step size decreases from the first step size value to the second step size value; when the digital quantization value continues to decrease to a third value and the third value is less than a preset convergence judgment threshold, the phase difference is determined to have converged to within the preset locking threshold, and a locking state is established.

[0021] Specifically, the trigger phase adjustment module includes a dynamic parameter adjustment unit, which is configured as follows:

[0022] Within M consecutive control cycles, the digital quantization value of the current control cycle is compared with the historical digital quantization value of the previous control cycle to obtain the phase deviation change in the current control cycle.

[0023] When the first, second, and third conditions are met simultaneously, it is determined that the closed-loop regulation is in an oscillation state. The preset proportional coefficient of the next control cycle is updated to the first attenuation proportional coefficient, and the preset integral coefficient of the next control cycle is updated to the first attenuation integral coefficient. The first condition is that the absolute value of the digital quantization value is greater than the absolute value of the historical digital quantization value. The second condition is that the absolute value of the phase deviation change is greater than the preset divergence judgment threshold. The third condition is that the phase deviation change of the current control cycle has the opposite sign to the phase deviation change of the previous control cycle.

[0024] Specifically, the dynamic parameter adjustment unit is also configured as follows:

[0025] When both the fourth and fifth conditions are met, the closed-loop regulation is determined to be in an overdamped convergence state, and the preset integral coefficient of the next control cycle is updated to the first enhanced integral coefficient. The fourth condition is that the absolute value of the digital quantization value is less than the absolute value of the historical digital quantization value, and the fifth condition is that the absolute value of the phase deviation change is less than the preset under-adjustment judgment threshold.

[0026] Wherein, the first attenuation ratio coefficient is less than the preset ratio coefficient, the first attenuation integral coefficient is less than the preset integral coefficient, the first enhancement integral coefficient is greater than the preset integral coefficient, and the preset divergence judgment threshold is greater than the preset undertuning judgment threshold.

[0027] Specifically, the trigger phase adjustment module further includes a drift compensation unit, which is configured as follows:

[0028] After the locked state is established, the current sampled value of the digital quantization value of this channel is obtained every preset drift detection cycle;

[0029] Compare the absolute value of the current sampled value with a preset drift warning threshold;

[0030] When the absolute value of the current sampled value is greater than the preset drift warning threshold and less than the preset lock threshold, it is determined that the lock edge of the trigger signal of this channel has a phase drift relative to the reference edge of the global reference clock signal, and a drift compensation operation is triggered.

[0031] Specifically, the drift compensation operation is as follows: based on the sign and amplitude of the current sampled value, a phase compensation step is generated, and the phase of the trigger signal of this channel is adjusted in steps along the direction of decreasing the absolute value of the current sampled value until the absolute value of the current sampled value falls back below the preset drift warning threshold; wherein, the preset drift warning threshold is less than the preset locking threshold, the preset drift detection period is greater than the control period, and the phase compensation step is less than the maximum phase adjustment step size of the trigger phase adjustment module before the locking state is established.

[0032] Specifically, the PID calculation module includes an edge discrimination unit, which is configured as follows:

[0033] The edge of the calibration trigger signal is detected. When the calibration trigger signal changes from the first level state to the second level state, a filter timing window with a preset filter duration is triggered.

[0034] Within the filtering timing window, the global reference clock signal is used as the sampling clock to sample the level state of the calibration trigger signal multiple times to obtain multiple sampled level values;

[0035] The plurality of sampled level values ​​are compared one by one with the second level state, and the number of sampled level values ​​that match the second level state is counted and used as a stable count value.

[0036] Specifically, the edge discrimination unit is also configured as follows:

[0037] The stable count value is compared with a preset stable count threshold. When the stable count value is greater than or equal to the preset stable count threshold, the current edge is determined to be a true locked edge. A trigger enable signal is generated and sent to the PID calculation module to trigger the execution of proportional-integral-derivative (PID) calculation.

[0038] When the stable count value is less than the preset stable count threshold, the current edge is determined to be an interference glitch, the current edge is discarded, and the trigger enable signal is not generated; wherein, the preset filtering duration is K times the period of the global reference clock signal, the preset stable count threshold is less than or equal to K, and K is a positive integer.

[0039] Specifically, the PID calculation module also includes a trigger enable management unit, which is configured as follows:

[0040] After the power-on reset signal is released, the PID trigger enable flag of this channel is set to the first logic state. The first logic state indicates that the PID calculation module is prohibited from responding to any edge of the calibration trigger signal.

[0041] Within each control cycle, the digital quantization value of the current control cycle output by the phase detection module is received, and the absolute value of the digital quantization value is compared with the preset locking threshold.

[0042] When the absolute value of the digital quantization value is less than the preset locking threshold, the PID trigger enable flag is updated from the first logic state to the second logic state. The second logic state indicates that the PID calculation module is allowed to respond to the locking edge of the calibration trigger signal.

[0043] When the absolute value of the digital quantization value is greater than or equal to the preset locking threshold, the PID trigger enable flag is kept in the first logic state, and a preset safety control value is output to the drive module. The preset safety control value is a fixed value stored in the register in advance, and the fixed value makes the corresponding motor output zero torque.

[0044] Specifically, the phase detection module further includes a path delay calibration unit, which is configured as follows:

[0045] During the system initialization phase and when the trigger signals of each channel are not enabled, a calibration pulse signal is injected into the starting point of the trigger feedback signal transmission path of this channel.

[0046] Using the global reference clock signal as the timing reference, the number of clock cycles that the calibration pulse signal takes from the injection time to the second input terminal of the phase detection module is measured and used as the path delay count value of this channel.

[0047] Write the path delay count value of this channel into the path delay compensation register of this channel;

[0048] After the system enters the normal operation phase, in each control cycle, the path delay count value in the path delay compensation register of this channel is read, and the digital quantization value is updated to: the difference obtained by subtracting the path delay count value from the original measurement count value, wherein the original measurement count value is the count value obtained by counting the time interval between the edge of the trigger feedback signal and the reference edge of the global reference clock signal with the period of the global reference clock signal as the quantization unit.

[0049] A multi-motor global clock synchronization method based on phase-locked loops includes:

[0050] Generate a global reference clock signal in a preset frequency band;

[0051] For each motor control channel, execute:

[0052] Receive a trigger feedback signal that represents the current phase of the channel trigger signal;

[0053] The trigger feedback signal and the global reference clock signal are phase-detected to determine the phase difference between them, and a deviation amount proportional to the phase difference is output.

[0054] Based on the deviation, the phase of the channel trigger signal is adjusted in the direction of reducing the phase difference. When the phase difference is less than a preset locking threshold, a calibration trigger signal is output. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal.

[0055] The proportional-integral-derivative (PID) operation is triggered only when the locking edge of the calibration trigger signal arrives, generating a motor control quantity.

[0056] The corresponding motor is driven according to the motor control quantity; wherein, the phase adjustment of the trigger signal of all channels is locked with the same global reference clock signal, so that the starting edge of each proportional-integral-derivative operation is forcibly aligned with the same reference edge, and the timing deviation of the multi-channel motor control cycle is not greater than the preset synchronization accuracy threshold.

[0057] A multi-motor global clock synchronization method based on phase-locked loops includes:

[0058] Generate a global reference clock signal in a preset frequency band;

[0059] For each motor control channel, execute:

[0060] Receive a trigger feedback signal that represents the current phase of the channel trigger signal;

[0061] The trigger feedback signal and the global reference clock signal are phase-detected to determine the phase difference between them, and a deviation amount proportional to the phase difference is output.

[0062] Based on the deviation, the phase of the channel trigger signal is adjusted in the direction of reducing the phase difference. When the phase difference is less than a preset locking threshold, a calibration trigger signal is output. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal.

[0063] The proportional-integral-derivative (PID) operation is triggered only when the locking edge of the calibration trigger signal arrives, generating a motor control quantity.

[0064] The corresponding motor is driven according to the motor control quantity; wherein, the phase adjustment of the trigger signal of all channels is locked with the same global reference clock signal, so that the starting edge of each proportional-integral-derivative operation is forcibly aligned with the same reference edge, and the timing deviation of the multi-channel motor control cycle is not greater than the preset synchronization accuracy threshold.

[0065] Compared with the prior art, the beneficial effects of the present invention are:

[0066] This invention generates a global reference clock signal by setting a unified clock generation module, and configures a phase comparison module and a trigger phase adjustment module in each motor control channel to form a closed-loop phase-locked circuit. This ensures that the phase of the trigger signals of each channel no longer drifts independently, but is forcibly locked to the same reference clock edge. The phase comparison module detects the phase difference between the trigger feedback signal and the global reference clock signal in real time, and the trigger phase adjustment module continuously adjusts in the direction of reducing the phase difference until the phase difference converges within a preset locking threshold, thereby outputting a calibration trigger signal with strictly aligned edges. The PID calculation module uses only the locked edge of this calibration trigger signal as the operation start condition, fundamentally eliminating the random jitter of the trigger edge caused by software scheduling or independent timer frequency division. After the trigger start edges of all channels are forcibly aligned to the same reference edge, the start time of multi-channel PID calculation is synchronized at the nanosecond level, the control quantity update time is consistent, the synchronization of the motor drive signal output by the drive module is greatly improved, and the timing deviation of the multi-channel motor control cycle is compressed to within a preset synchronization accuracy threshold, thereby eliminating the mechanical synchronization error caused by trigger edge phase mismatch. Attached Figure Description

[0067] Figure 1 This is a block diagram of the multi-motor global clock synchronization system based on the phase-locked loop of Embodiment 1 of the present invention;

[0068] Figure 2 This is a flowchart illustrating the process of triggering the enable management unit in Embodiment 2 of the present invention.

[0069] Figure 3 This is a flowchart of the multi-motor global clock synchronization method based on phase-locked loop in Embodiment 3 of the present invention. Detailed Implementation

[0070] Example 1

[0071] Please see Figure 1 The present invention provides an embodiment of a multi-motor global clock synchronization system based on a phase-locked loop, comprising the following steps:

[0072] The clock generation module is configured to generate a global reference clock signal in a preset frequency band;

[0073] In this embodiment, a TCXO-5070-100MHz high-precision temperature-compensated crystal oscillator is selected as the core clock source. Its frequency stability is better than ±0.5ppm, temperature coefficient is ±0.5ppm / ℃, and operating temperature is -40℃ to +85℃, meeting the requirements of harsh industrial environments. The clock frequency can be flexibly configured in 1MHz steps within the FPGA's internal MMCM in the range of 10MHz to 100MHz. When the synchronization accuracy requirement is at the 10ns level, frequencies of 50MHz and above are preferred to obtain higher phase quantization resolution. Through the built-in 8-channel SN65LVDS108 differential buffer and LVDS differential transmission lines with equal-length impedance matching, the characteristic impedance is 50Ω and the length error is ±5mm, the same reference clock is synchronously distributed to each channel, ensuring that the transmission path delay difference of each channel is ≤1 reference clock cycle. At the same time, the built-in two-stage RC low-pass filter with a cutoff frequency of 1MHz, AMS1117-3.3 linear regulator noise suppression, and 0.5mm aluminum EMI shielding structure make the peak-to-peak jitter of the output clock cycle <50ps. The basis for this jitter index is that a periodic jitter of 50ps corresponds to a phase noise of less than 0.01 reference clock cycles, which has a negligible impact on phase locking accuracy, thus providing a stable and reliable reference for each channel. Taking 50MHz as an example, a clock cycle of 20ns can meet a synchronization resolution of 10ns, and a 10ns cycle at 100MHz can provide a finer quantization resolution for nanosecond-level synchronization. A differential line length error of ±5mm corresponds to a delay difference of about 25ps, which is much smaller than 1 reference clock cycle, ensuring the consistency of the clock arrival time of each channel.

[0074] N motor control channels, each channel controls one motor, and each channel includes:

[0075] The phase detection module receives the global reference clock signal at its first input terminal and a trigger feedback signal representing the current phase of the trigger signal of this channel at its second input terminal. It is configured to detect the phase difference between the trigger feedback signal and the global reference clock signal and output a deviation amount proportional to the phase difference. In this embodiment, the trigger feedback signal is directly taken from the output terminal of the trigger phase adjustment module of this channel, and fed back to the phase detection module after being buffered by the IBUF primitive in the FPGA at level 1. The feedback path delay is fixed and included in the path delay calibration range.

[0076] The phase adjustment module is triggered and configured as follows:

[0077] In each control cycle, the phase difference is compared with a preset locking threshold;

[0078] When the phase difference is greater than or equal to the preset locking threshold, the trigger phase adjustment module maintains the phase adjustment state and continues to adjust the phase of the trigger signal of this channel in steps according to the deviation of the current control cycle in the direction of reducing the absolute value of the phase difference. The phase difference still exists between the edge of the output calibration trigger signal and the reference edge of the global reference clock signal. The PID calculation module is in the disabled trigger state and does not respond to the edge of the calibration trigger signal.

[0079] When the phase difference is less than the preset locking threshold, the trigger phase adjustment module switches from the phase adjustment state to the locking state, stops the phase step adjustment, and outputs a calibration trigger signal. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal. The PID calculation module is in the trigger-enabled state and responds to the locking edge of the calibration trigger signal to perform proportional-integral-derivative (PID) operations. The trigger phase adjustment module compares and judges the phase difference once in each control cycle and determines whether to maintain the state or switch the state in the next control cycle based on the comparison result.

[0080] In this embodiment, phase adjustment employs a two-stage structure of coarse and fine adjustment: coarse adjustment is achieved through frequency division using an internal FPGA counter, with a resolution of one reference clock cycle, enabling wide-range and rapid phase adjustment to meet the lock-up establishment speed requirements; fine adjustment is implemented using the IDELAYE2 primitive within the Xilinx Artix-7 FPGA, with a resolution of 78 picoseconds. This primitive is a standard hardware resource for Xilinx 7 series FPGAs, providing fine phase adjustment capabilities without additional hardware costs. The preset lock-up threshold is configured via a 16-bit register, ranging from 0.5 to 10 reference clock cycles, with a default value of 2 reference clock cycles. This setting is based on the fact that when the phase difference is less than 2 clock cycles, the deviation at the PID calculation start time has less than 0.1% impact on the motor synchronization accuracy, meeting the synchronization accuracy requirements of most industrial applications.

[0081] The PID calculation module is configured to be triggered only when the locking edge of the calibration trigger signal arrives to perform proportional-integral-derivative (PID) operations and output motor control quantities. In this embodiment, the PID calculation module is implemented using pure hardware logic, employing a 16-bit Q12 fixed-point arithmetic format, with a fixed operation cycle of 18 50MHz global reference clock cycles (360ns), and no software scheduling delay. The proportional coefficient, integral coefficient, and derivative coefficient are stored in three independent 16-bit registers, which can be configured online via the AXI-Lite bus. In this embodiment, the 18-clock-cycle operation cycle is set based on the following: the PID operation includes a 3-stage pipelined multiplier and a 2-stage pipelined adder. Each multiplier consumes 4 clock cycles, and each adder consumes 2 clock cycles, for a total pipeline delay of 3×4+2×2=16 clock cycles. An additional 2 clock cycles are added for result latching time, totaling 18 clock cycles. The pure hardware logic implementation is based on the principle of eliminating delay jitter caused by software interrupts and task scheduling, ensuring strict consistency of PID operation time across all channels.

[0082] The drive module is configured to drive the corresponding motor according to the motor control input. All channel trigger phase adjustment modules use the global reference clock signal as a common phase-locked reference, ensuring that the start-up edges of each PID calculation module are aligned to the same reference edge of the global reference clock signal. This limits the timing deviation between multiple motor control cycles to within a preset synchronization accuracy threshold. In this embodiment, the preset synchronization accuracy threshold is configured via a 16-bit register, ranging from 0.5 to 2 reference clock cycles, with a default value of 1 reference clock cycle. This configuration range is based on the following: the lower limit of 0.5 clock cycles represents the smallest timing deviation achievable by the FPGA's internal logic under equal-length clock path routing and edge alignment constraints, for example, 10 nanoseconds at a 50MHz clock; the upper limit of 2 clock cycles corresponds to 40 nanoseconds, which is the upper limit for synchronization accuracy requirements in most industrial multi-motor collaborative control applications. The default value of 1 clock cycle is 20 nanoseconds at a 50MHz reference clock, and the resulting motor speed synchronization error is less than 0.01%, meeting the requirements for high-precision multi-motor collaborative control. Through the above register configuration, the system can flexibly adjust the synchronization accuracy threshold according to actual application requirements, achieving a balance between the minimum deviation achievable by the hardware and the synchronization accuracy required by the application.

[0083] Example 2

[0084] It should be further noted that the phase detection module in this embodiment also includes a path delay calibration unit, which is configured as follows:

[0085] During the system initialization phase and when the trigger signals of each channel are not enabled, a calibration pulse signal is injected into the starting point of the trigger feedback signal transmission path of this channel.

[0086] Using the global reference clock signal as the timing reference, the number of clock cycles that the calibration pulse signal takes from the injection time to the second input terminal of the phase detection module is measured and used as the path delay count value of this channel.

[0087] Write the path delay count value of this channel into the path delay compensation register of this channel;

[0088] After the system enters the normal operation phase, in each control cycle, the path delay count value in the path delay compensation register of this channel is read, and the digital quantization value is updated to: the difference obtained by subtracting the path delay count value from the original measurement count value, wherein the original measurement count value is the count value obtained by counting the time interval between the edge of the trigger feedback signal and the reference edge of the global reference clock signal with the period of the global reference clock signal as the quantization unit.

[0089] In this embodiment, the calibration pulse signal is a positive pulse with a width of one global reference clock cycle. The injection time is strictly synchronized with the rising edge of the global reference clock signal, with a pulse rise time ≤ 1ns and a fall time ≤ 1ns. The path delay measurement uses a rising edge-triggered 16-bit binary adder counter. When the calibration pulse signal is injected, the counter is synchronously cleared and starts counting. When the calibration pulse signal reaches the second input terminal of the phase detector module, the counter synchronously stops counting. The final count value of the counter is the path delay count value. The path delay compensation register is a 16-bit read-only register. Its value remains unchanged during normal system operation and can only be updated when the system is reinitialized. The digital quantization value update uses a 16-bit signed integer subtraction operation. The result retains the sign bit and only takes the absolute value when outputting the phase difference amplitude to ensure that the phase adjustment direction information is not lost. The calibration process is automatically executed after the system is powered on without manual intervention. After calibration is completed, a high-level valid calibration completion flag is generated, which is retained until the system is powered off. The calibration pulse signal width is set to 1 clock cycle because this width ensures reliable identification by the edge detection circuit without interfering with subsequent circuits. The value of the 16-bit counter is based on the fact that the maximum measurable path delay is 65536 clock cycles, which corresponds to 1.3ms at a 50MHz clock, much larger than the maximum delay of actual PCB routing and FPGA internal logic (<1μs).

[0090] It should be further explained that the injection switching mechanism and arrival time detection logic of the calibration pulse signal in this embodiment are limited to:

[0091] The starting point of the trigger feedback signal transmission path is defined as the calibration pulse signal output terminal of the trigger phase adjustment module. This terminal is the same physical port as the trigger signal output terminal during normal operation. It is implemented using an internal LUT in the FPGA through a 2-to-1 data selector (MUX), with a switching delay of less than 1ns. During the calibration phase, the multiplexer switches to the calibration pulse signal input terminal, and during the normal operation phase, it automatically switches to the trigger signal input terminal. The detection of the arrival time of the calibration pulse signal is implemented by a dedicated edge detection circuit inside the phase detection module. This circuit is only enabled during the path delay calibration phase and is automatically disabled during the normal operation phase. The edge detection circuit adopts a two-stage synchronous flip-flop structure. Both the first and second stage flip-flops use the FPGA's internal FDCE primitive. The first stage flip-flop samples the input signal at the rising edge of the global reference clock, and the second stage flip-flop samples the output of the first stage flip-flop. When the output of the second stage is low and the output of the first stage is high, it is determined that the rising edge of the calibration pulse signal has arrived, and a high-level counter stop signal with a width of one global reference clock cycle is immediately generated. The two-stage synchronous flip-flop structure is designed to reduce the probability of metastability to 10. -12 The following specifications meet industrial-grade reliability requirements.

[0092] It should be further noted that the channel isolation and metastability handling mechanism for path delay calibration in this embodiment is limited to:

[0093] Path delay calibration is performed serially from channel number 0 to N-1, calibrating only one channel at a time. The calibration pulse signal is injected only into the currently calibrated channel, and the multiplexer outputs of other channels are driven at a fixed low level to avoid crosstalk of the calibration pulse signals. The setup time of the two-stage synchronous flip-flops is ≥2ns, and the hold time is ≥1ns, both meeting the requirements for input setup / hold time in the Xilinx Artix-7 series FPGA device datasheet (DS181). If the time difference between the arrival time of the calibration pulse signal and the rising edge of the global reference clock is less than the setup time, the counter stop signal is delayed until the next rising edge of the global reference clock, and the measurement result is automatically incremented by 1, ensuring that the measurement error does not exceed one clock cycle. The serial calibration setting is based on the principle of avoiding mutual interference between multi-channel calibration pulse signals and improving calibration accuracy.

[0094] As a specific example, in this embodiment, taking a global reference clock frequency of 50MHz and a period of 20 nanoseconds as an example, the calibration pulse width is 20 nanoseconds, injected at the 0th rising edge; the time from injection to arrival at the phase detector module input is measured to be 60 nanoseconds for channel 1, corresponding to a path delay count value of 3; channel 2 measures 80 nanoseconds, corresponding to a path delay count value of 4; count values ​​3 and 4 are written to the 16-bit path delay compensation register of the corresponding channel, respectively. During normal operation, if the original measured count value of channel 1 in a certain control cycle is 8, the updated digital quantization value is 8 minus 3 equals 5, corresponding to an actual phase difference of 100 nanoseconds; if the original measured count value of channel 2 in the same control cycle is 9, the updated digital quantization value is 9 minus 4 equals 5, also corresponding to an actual phase difference of 100 nanoseconds. This method eliminates the inherent path deviations of each channel caused by differences in PCB wiring length, different internal logic delays of FPGA, and different transmission delays of IO interface through serial calibration, edge synchronization detection, and path delay compensation register. It ensures that the phase measurement reference of each channel is completely consistent, the calibration accuracy reaches one global reference clock cycle, and the calibration error is less than 20 nanoseconds.

[0095] It should be further explained that the deviation amount output in this embodiment, which is proportional to the phase difference, includes:

[0096] The time interval between the edge of the trigger feedback signal and the reference edge of the global reference clock signal is measured, and a digital quantization value that is linearly proportional to the time interval is output; wherein, the digital quantization value is equal to the time interval divided by the period of the global reference clock signal, and the unit resolution of the digital quantization value is one clock cycle of the global reference clock signal.

[0097] The digital quantization value calculated in the current control cycle is compared with the historical digital quantization value in the previous control cycle to obtain the phase deviation change.

[0098] The proportional adjustment component is obtained by multiplying the digital quantization value by a preset proportional coefficient, and the integral adjustment component is obtained by multiplying the phase deviation change by a preset integral coefficient. The proportional adjustment component and the integral adjustment component are then superimposed to generate the deviation.

[0099] It should be further explained that the calculation method for the digital quantization value and the synthesis logic for the deviation in this embodiment are limited to:

[0100] The time interval measurement uses the rising edge counting method, with the rising edge of the global reference clock signal as the counting reference and the rising edge of the trigger feedback signal as the stopping reference. The counting result is directly used as the original measurement count value. The phase deviation change is equal to the digital quantization value of the current control cycle minus the digital quantization value of the previous control cycle. The result retains the sign to indicate the direction of the phase deviation change; a positive value indicates an increase in phase deviation, and a negative value indicates a decrease in phase deviation. Both the proportional and integral adjustment components use 16-bit Q12 fixed-point arithmetic, retaining 12 decimal places. The calculation result is rounded to the nearest integer and used as the final deviation. The sign of the deviation indicates the direction of phase adjustment; a positive value indicates that the trigger signal phase is lagging and needs to be adjusted forward, while a negative value indicates that the trigger signal phase is leading and needs to be adjusted backward. The historical digital quantization value of the previous control cycle is stored in a 16-bit read / write register, implemented using the FPGA's internal FDCE primitive, and is automatically updated at the end of each control cycle. The Q12 fixed-point format is set based on the fact that it can meet the speed requirements of 16-bit operations while ensuring sufficient accuracy (0.000244); the rising edge counting method is set based on the fact that it is simple to implement and the counting error does not exceed one clock cycle.

[0101] It should be further noted that the format definition and historical value initialization rules for fixed-point arithmetic in this embodiment are limited to:

[0102] The 16-bit fixed-point number uses the Q12 format, with the high 4 bits representing the integer part and the low 12 bits representing the fractional part. The 4 bits of the integer part are set based on the following: the largest integer that can be represented is 15, corresponding to a maximum phase difference of 15 reference clock cycles, covering the maximum initial phase difference allowed by the system of 10 clock cycles with a 50% margin. Preset proportional and integral coefficients are stored in dedicated registers in Q12 format. Each motor control channel maintains an independent historical digital quantization value register. This register is independently initialized when the trigger signal of this channel is enabled. The initialization value is the digital quantization value measured in the first control cycle after the trigger signal of this channel is enabled. This ensures that the first adjustment of each channel starts from its own actual initial phase difference, with the integral adjustment component initially set to zero, ensuring that the phase locking process of each channel is independent and does not interfere with each other. At the end of each control cycle, the digital quantization value of the current control cycle is written to the historical digital quantization value register, overwriting the value of the previous cycle. The rounding operation adopts the "round to even" rule, which means that when the decimal part is exactly equal to 0.5, the nearest even integer is taken. This rule can make the expected value of rounding error zero, avoid the cumulative deviation of long-term calculation, and ensure the long-term stability of fixed-point number calculation.

[0103] It should be further explained that the overflow handling and phase direction preservation mechanism for fixed-point arithmetic in this embodiment are limited to:

[0104] The multiplication operation uses a 32-bit signed multiplier to multiply two 16-bit Q12 format operands, resulting in a 32-bit Q24 format intermediate product. To convert the Q24 format back to Q12 format, the 32-bit product result needs to be arithmetically right-shifted by 12 bits. The arithmetic right shift ensures the correct extension of the sign bit of the signed number, and the shifted result remains in 16-bit Q12 format, stored in the lower 16 bits of the 32-bit register. After the shift, it is checked whether the 16-bit Q12 result exceeds the representation range of a 16-bit signed integer, i.e., whether it is less than -32768 or greater than +32767. If it exceeds the range, saturation processing is performed: if the result is greater than +32767, it is forced to be output as +32767; if the result is less than -32768, it is forced to be output as -32768. If it does not exceed the range, the lower 16 bits after the arithmetic right shift are directly output as the final result. The saturation processing in this embodiment is performed after the arithmetic right shift, which can avoid sign reversal or data truncation errors caused by excessively large multiplication results, and ensure the stability and directional correctness of fixed-point arithmetic under extreme conditions.

[0105] After subtracting the path delay count from the digital quantization value, the sign bit is retained. This sign bit is only used for the final calculation of the absolute value of the phase difference, and the phase adjustment direction is determined solely by the sign bit. A positive sign bit indicates that the trigger signal phase lags behind the global reference clock edge and needs to be adjusted forward; a negative sign bit indicates that the trigger signal phase leads and needs to be adjusted backward. This phase direction retention mechanism ensures that the lead and lag direction information is not lost during subsequent absolute value calculations, guaranteeing the correctness of the phase adjustment direction.

[0106] As a specific example, in this embodiment, the global reference clock signal frequency is 50MHz and the clock period is 20ns. If the measured time interval between the rising edge of the trigger feedback signal and the rising edge of the global reference clock is 120ns within a certain control cycle, then the original measured count value is the quotient of this time interval divided by the clock period, i.e., 120 ÷ 20 = 6, corresponding to a digital quantization value of 6. The digital quantization value of the previous control cycle after path delay compensation is 8, and this value is stored in the historical digital quantization value register. Subtracting the historical digital quantization value of 8 from the digital quantization value of the previous control cycle from the current control cycle's digital quantization value of 6 yields a phase deviation change of -2, indicating that the phase deviation has decreased by 2 clock cycles compared to the previous control cycle.

[0107] In this example, the preset proportional coefficient is set to 0.5, and the preset integral coefficient is set to 0.2. The preset proportional and integral coefficients are chosen based on the following: a preset proportional coefficient of 0.5 ensures that, under the condition of maximum permissible initial phase difference, the single proportional adjustment step size does not exceed the first preset step size threshold; a preset integral coefficient of 0.2 ensures that, under the condition of maximum permissible phase deviation rate of change, the single integral adjustment step size does not exceed the second preset step size threshold. Based on these coefficients, the proportional adjustment component is the current digital quantization value multiplied by the preset proportional coefficient, i.e., 6 × 0.5 = 3.0; the integral adjustment component is the phase deviation change multiplied by the preset integral coefficient, i.e., -2 × 0.2 = -0.4. Adding the proportional and integral adjustment components together yields a deviation of 3.0 + (-0.4) = 2.6, which is rounded to the nearest integer of 3. This deviation is positive, indicating that the trigger signal phase lags and needs to be adjusted forward by 3 clock cycles, corresponding to a physical adjustment of 3 × 20ns = 60ns.

[0108] It should be further explained that the preset proportional coefficient and the preset integral coefficient in this embodiment satisfy the following conditions: the product of the preset proportional coefficient and the digital quantization value of the current control cycle constitutes the proportional adjustment component, and the product of the preset integral coefficient and the phase deviation change of the current control cycle constitutes the integral adjustment component; the phase adjustment step size generated by the phase adjustment module driven by the deviation is equal to the sum of the proportional adjustment component and the integral adjustment component; wherein, the value of the preset proportional coefficient is such that when the digital quantization value is a first value, the single phase adjustment step size is not greater than a first preset step size threshold; the value of the preset integral coefficient is such that when the phase deviation change is a second value, the single phase adjustment step size is not greater than a second preset step size threshold; and when the digital quantization value decreases from the first value of the current control cycle to the second value of the next control cycle, the corresponding phase adjustment step size decreases from the first step size value to the second step size value; when the digital quantization value continues to decrease to a third value and the third value is less than a preset convergence judgment threshold, the phase difference is determined to have converged to within the preset locking threshold, and a locking state is established.

[0109] It should be further explained that the value constraints of the preset coefficients and the locking state determination logic in this embodiment are limited to:

[0110] The first value is the maximum initial phase difference allowed by the system, which is a preset configurable parameter. Its value is much smaller than the control cycle. The specific value can be determined through simulation or physical experiment calibration based on the inertia, synchronization accuracy requirements, and convergence speed requirements of the controlled motor system. Under a typical configuration of a 50MHz global reference clock and a 1ms control cycle, the control cycle corresponds to 50,000 reference clock cycles. The first value is set to 10 reference clock cycles, corresponding to 1 / 5000 of the control cycle. This value can cover the initial phase deviation that may occur in most actual operating conditions, and also ensure that the phase locking process is completed within a finite number of control cycles.

[0111] The first preset step size threshold is the maximum single proportional adjustment step size set to avoid proportional adjustment overshoot, and its value is 1 / 5 of the first value. In a typical configuration with a 50MHz reference clock and a first value of 10 clock cycles, the first preset step size threshold is set to 2 clock cycles. The design basis for this threshold is that when the single proportional adjustment step size does not exceed 1 / 5 of the current phase deviation, the adjustment overshoot can be controlled within 20%, effectively avoiding system oscillations caused by excessive step size and ensuring the stability of closed-loop regulation.

[0112] The second value is the maximum allowable rate of change of phase deviation, which is half the value of the first value. In a typical configuration with a 50MHz reference clock and the first value being 10 clock cycles, the second value is set to 5 clock cycles. This value is designed based on the fact that the rate of change of phase deviation reflects the speed of change of the phase difference between adjacent control cycles. Constraining its upper limit to half of the first value ensures a fast adjustment response while preventing excessive accumulation of integral control components due to an excessively large rate of change, thus avoiding adjustment lag or overshoot caused by integral saturation.

[0113] The second preset step size threshold is the maximum single integral adjustment step size set to avoid oscillations caused by integral adjustment. Its value is half of the first preset step size threshold. In a typical configuration with a 50MHz reference clock and a first preset step size threshold of two clock cycles, the second preset step size threshold is set to one clock cycle. The design basis for this threshold is that the integral adjustment component is used to eliminate steady-state error, but its response speed should be lower than that of the proportional adjustment component. Constraining the upper limit of the integral adjustment step size to half of the upper limit of the proportional adjustment step size can prevent excessive integral action from causing low-frequency oscillations, ensuring the stability and convergence smoothness of the adjustment process.

[0114] Based on the above parameter constraints, the maximum permissible value of the preset proportional coefficient is determined by dividing the first preset step size threshold by the first value, i.e., 2 ÷ 10 = 0.2; the maximum permissible value of the preset integral coefficient is determined by dividing the second preset step size threshold by the second value, i.e., 1 ÷ 5 = 0.2. In practical applications, the specific values ​​of the preset proportional coefficient and the preset integral coefficient can be further optimized within the above maximum permissible range, taking into account the characteristics of the controlled object.

[0115] A preset convergence threshold, which is less than a preset locking threshold, is used to determine whether the phase difference has been essentially eliminated. When the absolute value of the digital quantization value is less than the preset convergence threshold for multiple consecutive control cycles, the phase difference is determined to have converged to within the preset locking threshold, and a locking state is established, with the locking state flag set to an active level. After the locking state is established, the phase adjustment module is triggered to switch from the phase adjustment state to the locked state, stopping large-step phase adjustment. Subsequent adjustments are made only through micro-adjustment mode with small-step compensation, and the phase adjustment step size is automatically limited to no more than 0.5 clock cycles to maintain phase stability. When the absolute value of the digital quantization value in any control cycle is greater than or equal to the preset locking threshold, it is immediately determined to be unlocked, the locking state flag is cleared, and the system re-enters the phase adjustment state.

[0116] It should be further explained that the execution logic of the phase adjustment step size and the locking state confirmation mechanism in this embodiment are limited as follows:

[0117] The phase adjustment step size is based on the global reference clock cycle as the smallest unit. The deviation is rounded to the nearest integer to obtain the actual number of clock cycles adjusted. Forward adjustment means advancing the rising edge of the trigger signal by the corresponding number of clock cycles, while backward adjustment means delaying the rising edge of the trigger signal by the corresponding number of clock cycles.

[0118] The establishment of a locked state requires that the absolute value of the digital quantization value for five consecutive control cycles be less than a preset convergence threshold to avoid false locking caused by single noise interference. The basis for setting the lock confirmation for five consecutive control cycles is that, under the assumption that random noise follows a normal distribution, the probability that the phase difference of five consecutive independent sampling cycles is less than the threshold is greater than 99.99%, which can effectively eliminate the interference of random noise on the lock state judgment.

[0119] Once the lockout is established, if the absolute value of the digital quantization value in any control cycle is greater than or equal to the preset lockout threshold, it is immediately determined as a lost lockout, the lockout flag is cleared, and the system re-enters the phase adjustment state. The response delay for the lost lockout determination is no more than one control cycle, ensuring that the system can quickly respond to phase anomalies and switch to a safe state in a timely manner.

[0120] It should be further explained that the fine-tuning mechanism of the locked state and the unlock recovery logic in this embodiment are limited to:

[0121] After the locked state is established, the phase adjustment module does not completely stop working, but enters a fine-tuning mode. Step adjustment is only performed when the absolute value of the digital quantization value is greater than the fine-tuning trigger threshold, and the adjustment step size is fixed at the fine-tuning step size value. In this embodiment, the fine-tuning trigger threshold is set to 0.2 clock cycles, and the fine-tuning step size is set to 0.1 clock cycles. The basis for setting the fine-tuning trigger threshold is as follows: taking a 50MHz global reference clock as an example, 0.2 clock cycles corresponds to a 4ns phase deviation, while the fine-tuning phase resolution used in this system is 78ps. 4ns is approximately 50 times 78ps. This ratio can effectively distinguish between the real minute phase drift caused by factors such as temperature drift and device aging and the measurement fluctuations caused by quantization noise, avoiding frequent triggering of unnecessary fine-tuning operations under noise interference. The basis for setting the fine-tuning step size in this embodiment is that 0.1 clock cycles can effectively compensate for the aforementioned identifiable minute phase drift, and because the step size is small enough, it will not cause system oscillation, ensuring phase stability in the locked state.

[0122] After a lock-up failure, the system automatically re-enters phase adjustment mode, clears the historical digital quantization value register, and restarts the phase locking process. When the number of lock-up failures exceeds a preset lock-up failure threshold within a unit of time, the system reports a hardware fault flag. In this embodiment, the preset lock-up failure threshold is set to 10 times / minute. This threshold is set based on the following: Under normal operating conditions, crystal oscillator frequency drift and power supply voltage fluctuations are slow changes, and system lock-up failures are low-probability events, usually far below 1 time / minute. If the number of lock-up failures reaches 10 times / minute within a unit of time, it indicates that there may be hardware-level faults in the system, such as clock source failure, power supply abnormality, or strong external electromagnetic interference. It is necessary to promptly notify the host system through fault flag reporting for troubleshooting and processing.

[0123] As a specific example, the setting of relevant parameters and the phase locking process in this embodiment are as follows:

[0124] The control cycle is set to 1ms. The global reference clock frequency is set to 50MHz, and the clock cycle is 20ns. The preset lock threshold is set to 2 clock cycles, corresponding to a phase deviation of 40ns; the preset convergence judgment threshold is set to 1 clock cycle, corresponding to 20ns; and the preset synchronization accuracy threshold is set to 1 clock cycle, corresponding to a timing deviation of 20ns.

[0125] Regarding the phase adjustment parameters, the first value is set to 10 clock cycles, corresponding to 200 ns, and its value is 1 / 5000 of the control cycle. The basis for setting this first value is that it represents the maximum allowable initial phase difference in the system design, and its value must be much smaller than the control cycle to ensure that the phase locking process is completed within a finite number of control cycles. The first preset step size threshold is set to 2 clock cycles, corresponding to 40 ns, and its value is 1 / 5 of the first value. Based on this first preset step size threshold, the maximum allowable value of the preset proportional coefficient is calculated by dividing the first preset step size threshold by the first value, i.e., 2 ÷ 10 = 0.2. This constraint ensures that under the condition of maximum initial phase difference, the initial phase adjustment will not cause overshoot or oscillation due to an excessively large step size.

[0126] The second value is set to 5 clock cycles, corresponding to 100 ns, and is half the value of the first value, representing the maximum allowable rate of change of phase deviation. The second preset step size threshold is set to 1 clock cycle, corresponding to 20 ns, and is half the value of the first preset step size threshold. Based on this second preset step size threshold, the maximum allowable value of the preset integral coefficient is calculated by dividing the second preset step size threshold by the second value, i.e., 1 ÷ 5 = 0.2. This constraint ensures that the integral adjustment component will not cause overshoot under the condition of most drastic phase deviation changes.

[0127] During the lock establishment process, if the current control cycle's digital quantization value is 10, the proportional adjustment component is 10 × 0.2 = 2, and the single phase adjustment step size is 2 clock cycles. In the next control cycle, the digital quantization value decreases to 5, so the proportional adjustment component is 5 × 0.2 = 1, and the single phase adjustment step size is reduced to 1 clock cycle. When the digital quantization value continues to decrease to 0.8 clock cycles, this value is less than the preset convergence threshold by 1 clock cycle. It is determined that the phase difference has converged to within the preset lock threshold, the lock state is established, and the lock state flag is set to valid.

[0128] It should be further noted that the phase adjustment module in this embodiment includes a dynamic parameter adjustment unit, which is configured as follows:

[0129] Within M consecutive control cycles, the digital quantization value of the current control cycle is compared with the historical digital quantization value of the previous control cycle to obtain the phase deviation change in the current control cycle.

[0130] When the first, second, and third conditions are met simultaneously, it is determined that the closed-loop regulation is in an oscillation state. The preset proportional coefficient of the next control cycle is updated to the first attenuation proportional coefficient, and the preset integral coefficient of the next control cycle is updated to the first attenuation integral coefficient. The first condition is that the absolute value of the digital quantization value is greater than the absolute value of the historical digital quantization value. The second condition is that the absolute value of the phase deviation change is greater than the preset divergence judgment threshold. The third condition is that the phase deviation change of the current control cycle has the opposite sign to the phase deviation change of the previous control cycle.

[0131] When both the fourth and fifth conditions are met, the closed-loop regulation is determined to be in an overdamped convergence state, and the preset integral coefficient of the next control cycle is updated to the first enhanced integral coefficient. The fourth condition is that the absolute value of the digital quantization value is less than the absolute value of the historical digital quantization value, and the fifth condition is that the absolute value of the phase deviation change is less than the preset under-adjustment judgment threshold.

[0132] Wherein, the first attenuation ratio coefficient is less than the preset ratio coefficient, the first attenuation integral coefficient is less than the preset integral coefficient, the first enhancement integral coefficient is greater than the preset integral coefficient, and the preset divergence judgment threshold is greater than the preset undertuning judgment threshold.

[0133] It should be further explained that the state determination logic and parameter update rules for dynamic parameter adjustment in this embodiment are limited to:

[0134] The number of consecutive detection periods M is set to 3. Based on statistical principles, this value can exclude misjudgments caused by single - time random fluctuations at a 95% confidence level. After each control period ends, the dynamic parameter adjustment unit makes a state determination based on the current digital quantization value e(k), the historical digital quantization value e(k - 1), and the phase deviation change Δe(k). The determination of the normal convergence state must satisfy two conditions simultaneously in each of three consecutive control periods: |e(k)| < |e(k - 1)|, that is, the amplitude strictly decreases; and THR_under < |Δe(k)| < THR_div, that is, the absolute value of the phase deviation change is between the preset under - adjustment judgment threshold THR_under and the preset divergence judgment threshold THR_div. When the above conditions are met in three consecutive control periods, it is determined that the closed - loop regulation has restored from the oscillation state or the over - damped convergence state to the normal convergence state, and the proportional coefficient is automatically restored to the initial preset value Kp and the integral coefficient is restored to the initial preset value Ki before the start of the next control period. The first attenuation proportional coefficient Kp_att = Kp×0.5, the first attenuation integral coefficient Ki_att = Ki×0.5, and the first enhancement integral coefficient Ki_enh = Ki×1.5. The values of 0.5 - fold attenuation and 1.5 - fold enhancement can maintain the system stability margin while effectively suppressing oscillations or accelerating convergence. The parameter update and restoration operations are both executed after the end of the current control period and before the start of the next control period, and are only executed once within the same control period; the phase adjustment step size of the current period is always calculated using the coefficients before the update, and the variables e(k) and Δe(k) are written into the corresponding historical registers at the end of this period to ensure the continuity and timing certainty of the adjustment process.

[0135] It should be further noted that the determination criteria and parameter restoration mechanism for the continuous conditions in this embodiment are defined as:

[0136] The dynamic parameter adjustment unit uses each control cycle as the basic judgment unit and realizes reliable identification of the closed-loop state through a continuous satisfaction counting mechanism. After each control cycle ends, the dynamic parameter adjustment unit performs the following steps: First, it performs variable acquisition and calculation. It reads the digital quantization value of the current control cycle, denoted as e(k), reads the historical digital quantization value stored in the previous control cycle, denoted as e(k - 1), calculates the phase deviation change amount of the current control cycle Δe(k) = e(k) - e(k - 1), and reads the phase deviation change amount Δe(k - 1) stored in the previous control cycle. Both e(k) and e(k - 1) are signed numbers. A positive value indicates that the trigger signal phase lags behind the reference edge of the global reference clock signal, and a negative value indicates that the phase is ahead. Then, it respectively checks the determination conditions for the oscillation state and the overdamped convergence state: The oscillation state must simultaneously satisfy three sub-conditions. The first condition is |e(k)| > |e(k - 1)|, that is, the amplitude increases. The second condition is |Δe(k)| > THR_div, where THR_div is a preset divergence judgment threshold, that is, the change rate diverges. The third condition is that Δe(k) and Δe(k - 1) have different signs and Δe(k - 1) ≠ 0, that is, the sign of the phase deviation change amount alternates in consecutive control cycles; The overdamped convergence state must simultaneously satisfy two sub-conditions. The fourth condition is |e(k)| < |e(k - 1)|, that is, the amplitude decreases. The fifth condition is |Δe(k)| < THR_under, where THR_under is a preset undershoot judgment threshold, that is, the change rate is undershoot. The dynamic parameter adjustment unit internally maintains two independent continuous satisfaction counters, namely the oscillation continuous satisfaction counter C_osc and the overdamped continuous satisfaction counter C_over: When the current cycle simultaneously satisfies the first condition, the second condition, and the third condition, C_osc is incremented by 1, otherwise C_osc is cleared; When the current cycle simultaneously satisfies the fourth condition and the fifth condition, C_over is incremented by 1, otherwise C_over is cleared. When C_osc reaches 3, it is determined that the closed-loop adjustment enters the oscillation state. Before the start of the next control cycle, the proportional coefficient Kp is updated to the first attenuation proportional coefficient Kp_att, the integral coefficient Ki is updated to the first attenuation integral coefficient Ki_att, and C_osc is cleared; When C_over reaches 3, it is determined that the closed-loop adjustment enters the overdamped convergence state. Before the start of the next control cycle, the integral coefficient Ki is updated to the first enhanced integral coefficient Ki_enh, the proportional coefficient Kp remains unchanged, and C_over is cleared. After entering the oscillation state, if the first condition, the second condition, and the third condition are no longer simultaneously satisfied for three consecutive control cycles, it is determined that the oscillation state is解除. Before the start of the next control cycle, the proportional coefficient is restored to the initial preset value Kp, and the integral coefficient is restored to the initial preset value Ki; After entering the overdamped convergence state, if the fourth condition and the fifth condition are no longer simultaneously satisfied for three consecutive control cycles, it is determined that the overdamped convergence state is解除. Before the start of the next control cycle, the integral coefficient is restored to the initial preset value Ki.Parameter update and recovery operations are performed after the end of the control cycle and before the start of the next control cycle, and are performed only once within the same control cycle. When calculating the phase adjustment step size within the current control cycle, the coefficients before the update are always used for calculation; at the end of each control cycle, the current e(k) is written to the historical digital quantization value register as e(k-1) for the next cycle, and the current Δe(k) is written to the historical phase deviation change register as Δe(k-1) for the next cycle, ensuring the continuity and stability of the adjustment process.

[0137] It should be further explained that the comprehensive determination logic for the oscillation state and the parameter smoothing transition mechanism in this embodiment are limited to:

[0138] The determination of an oscillation state requires the simultaneous fulfillment of a first condition, a second condition, and a third condition. The first condition is that the absolute value of the digital quantization value is greater than the absolute value of the historical digital quantization value, i.e., the amplitude is increasing. The second condition is that the absolute value of the phase deviation change is greater than a preset divergence judgment threshold. The third condition is that the phase deviation change in the current control cycle has the opposite sign to the phase deviation change in the previous control cycle, i.e., the phase difference oscillates between leading and lagging. All three conditions are indispensable. When the sign of the phase deviation change alternates but the first condition is not met, i.e., the amplitude is not increasing, it is determined to be a normal overshoot during convergence rather than an oscillation, and parameter decay is not triggered. When both the first and second conditions are met but the alternating sign condition is not met, i.e., the amplitude is increasing but the sign is not alternating, it is determined to be a divergence state rather than an oscillation state, and parameter decay is also not triggered.

[0139] As a specific example, in this embodiment, the number of continuous detection cycles M is set to 3 control cycles. The preset proportional coefficient is set to 0.2, and the preset integral coefficient is set to 0.1. These values ​​are determined through simulation or experimental calibration based on the inertia and response bandwidth requirements of the controlled motor system, so that under the maximum allowable initial phase difference, the single phase adjustment step size does not exceed the first preset step size threshold, and the phase locking process does not produce overshoot. The first attenuation proportional coefficient is 0.5 times the preset proportional coefficient, i.e., 0.1; the first attenuation integral coefficient is 0.5 times the preset integral coefficient, i.e., 0.05; and the first enhancement integral coefficient is 1.5 times the preset integral coefficient, i.e., 0.15. The preset divergence judgment threshold is set to 3 clock cycles (corresponding to 60ns), and the preset undershoot judgment threshold is set to 0.5 clock cycles (corresponding to 10ns). The preset divergence judgment threshold is greater than the preset undershoot judgment threshold.

[0140] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 2, 3, and 4 respectively, and the phase deviation changes are +1, +1, and +1 respectively, satisfying the condition of increasing amplitude but no alternating sign, then it is determined to be a divergent state rather than an oscillating state, and parameter decay is not triggered.

[0141] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 2, -3, and 4 respectively, and the phase deviation changes are -5, +7, and -7 respectively, and simultaneously satisfy the conditions of increasing absolute values ​​of digital quantization values, absolute values ​​of phase deviation changes greater than the preset divergence judgment threshold of 3, and alternating signs, then the closed-loop regulation is determined to be in an oscillation state. In the next control cycle, the proportional coefficient will be updated to the first attenuation proportional coefficient of 0.1, and the integral coefficient will be updated to the first attenuation integral coefficient of 0.05.

[0142] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 4, 3.5, and 3.2 respectively, and the phase deviation changes are -0.4, -0.3, and -0.3 respectively, all satisfying the condition that the absolute values ​​of the digital quantization values ​​decrease and the absolute values ​​of the phase deviation changes are less than the preset under-adjustment judgment threshold of 0.5, then the closed-loop regulation is determined to be in an overdamped convergence state, and the integral coefficient will be updated to the first enhanced integral coefficient of 0.15 in the next control cycle.

[0143] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 3.2, 2.7, and 2.1 respectively, and the phase deviation changes are -0.5, -0.6, and -0.6 respectively, all satisfying the condition that the absolute values ​​of the digital quantization values ​​decrease and the absolute values ​​of the phase deviation changes are within the preset under-adjustment judgment threshold of 0.5 and the preset divergence judgment threshold of 3, then it is determined that the closed-loop adjustment has recovered to the normal convergence state, and the proportional coefficient and the integral coefficient are restored to their respective preset values, namely 0.2 and 0.1.

[0144] It should be further noted that the phase adjustment module in this embodiment also includes a drift compensation unit, which is configured as follows:

[0145] After the locked state is established, the current sampled value of the digital quantization value of this channel is obtained every preset drift detection cycle;

[0146] Compare the absolute value of the current sampled value with a preset drift warning threshold;

[0147] When the absolute value of the current sampled value is greater than the preset drift warning threshold and less than the preset lock threshold, it is determined that the lock edge of the trigger signal of this channel has a phase drift relative to the reference edge of the global reference clock signal, and a drift compensation operation is triggered.

[0148] It should be further explained that the detection period and early warning judgment logic for phase drift in this embodiment are limited as follows:

[0149] The preset drift detection period is an integer multiple of the control period and is much larger than the control period. Its value can be set according to the system drift characteristics, for example, it can be set to 100 control periods or 1000 control periods. The basis for this setting is that the temperature drift of the crystal oscillator and the phase drift caused by component aging are both slow changes. With a control period of 1ms, 100 control periods correspond to a detection interval of 100ms, which is sufficient to capture the cumulative trend of phase drift, while avoiding the impact on the normal control timing of the system due to excessive detection.

[0150] The preset drift warning threshold is less than the preset lock threshold, and its value is set to 1 / 2 of the preset lock threshold. The reason for setting this value is that setting the warning threshold at half the lock threshold can trigger the compensation operation in advance before the phase drift amount accumulates to a critical range that is sufficient to cause a loss of lock, thereby effectively preventing accidental loss of lock due to phase drift exceeding the limit.

[0151] To avoid false triggering caused by single electromagnetic interference or instantaneous measurement noise, phase drift determination adopts a continuous multiple confirmation mechanism: only when the absolute value of three consecutive drift detection sampling values ​​is greater than the preset drift warning threshold, it is determined that the locking edge of the trigger signal of this channel has drifted relative to the reference edge of the global reference clock signal, and a drift compensation operation is triggered; if the absolute value of any of the three consecutive sampling values ​​is less than or equal to the preset drift warning threshold, it is not determined to be a phase drift, and the current locking state remains unchanged.

[0152] The drift detection function is enabled only when the lock status flag is at a valid level; when the lock status flag is cleared, the drift detection function is immediately suspended to avoid performing invalid drift detection operations in the unlocked state.

[0153] It should be further noted that, in this embodiment, the definition of the drift sampling time and the detection pause mechanism are limited to:

[0154] The current sampled value for each drift detection is taken from the digital quantization value calculated in the last control cycle within the corresponding drift detection cycle, and the sampling time is the end time of that control cycle.

[0155] The drift detection cycle is timed by an independent 16-bit binary adder counter, which operates on a rising edge triggering mode. When the lock status flag is set to an active level, the counter is synchronously cleared and immediately starts counting. When the count value accumulates to the value corresponding to the preset drift detection cycle, a drift sampling operation is triggered. After sampling is completed, the counter is automatically cleared and the next round of counting begins, thus forming a periodic drift detection cycle.

[0156] If the lock status flag is cleared during the counting process of the drift detection cycle, the counter is immediately cleared and stops counting until the lock status is re-established and the lock status flag is set to an active level again, at which point the counter restarts counting from zero. The sampled value obtained from each sample is stored in a dedicated 16-bit drift sampling register and is automatically updated after each sample. The use of an independent counter for drift detection cycle timing is based on the principle that it ensures the detection cycle is unaffected by changes in the state of other logic modules in the system, thus ensuring the accuracy and independence of the drift detection time base.

[0157] It should be further explained that the multi-channel independent drift compensation and phase shift implementation mechanism in this embodiment is limited to:

[0158] Each motor control channel is configured with an independent MMCM primitive within the Xilinx Artix-7 FPGA to implement independent phase offset of the trigger signal for that channel. The phase offset resolution is no less than 0.1 clock cycles, and the offset range covers -0.5 clock cycles to +0.5 clock cycles, corresponding to a phase angle range of -180 degrees to +180 degrees. Drift compensation operations only modify the phase offset value of the channel currently experiencing phase drift and do not affect the normal phase state of other channels. The phase offset value is written to the configuration register of the corresponding MMCM via the AXI-Lite bus, and the completion delay of the write operation is no more than 10 global reference clock cycles. The basis for using independent MMCM configuration for each channel to achieve phase offset settings is: it can achieve high-precision, wide-range independent phase adjustment, and the phase adjustment operations between channels are completely decoupled, ensuring the independence and reliability of the multi-channel system.

[0159] As a specific example, in this embodiment, the control cycle is set to 1ms, and the preset drift detection cycle is set to 100 control cycles, meaning phase drift detection is performed once every 100ms. The preset lock threshold is set to 2 clock cycles, corresponding to 40ns; the preset drift warning threshold is set to 1 clock cycle, corresponding to 20ns. This warning threshold is half of the preset lock threshold, aiming to trigger compensation in advance before the phase drift accumulates to the lock threshold, thereby effectively avoiding loss of lock due to drift exceeding the limit. The number of consecutive samples used for drift determination is set to 3. If the digital quantization values ​​obtained from 3 consecutive drift detections are 1.2, 1.3, and 1.1, respectively, and their absolute values ​​are all greater than the preset drift warning threshold 1 and less than the preset lock threshold 2, then it is determined that the trigger signal of this channel has experienced phase drift, triggering the drift compensation operation. If a certain sample value is 1.2, but the subsequent two sample values ​​are 0.8 and 0.9, since not all 3 consecutive sample values ​​meet the determination condition, it is not determined to be phase drift, and the system continues to perform normal periodic detection. The configuration of this embodiment can effectively detect slow phase drift caused by factors such as crystal oscillator temperature drift, power supply voltage fluctuation and long-term aging of components. At the same time, through a continuous multiple confirmation mechanism, it can reliably distinguish between instantaneous electromagnetic interference and real phase drift, avoiding false triggering of compensation operations.

[0160] It should be further explained that the drift compensation operation in this embodiment is as follows: based on the sign and amplitude of the current sampled value, a phase compensation step is generated, and the phase of the trigger signal of this channel is adjusted in steps along the direction of decreasing the absolute value of the current sampled value until the absolute value of the current sampled value falls back below the preset drift warning threshold; wherein, the preset drift warning threshold is less than the preset locking threshold, the preset drift detection period is greater than the control period, and the phase compensation step is less than the maximum phase adjustment step size of the trigger phase adjustment module before the locking state is established.

[0161] It should be further noted that the step adjustment method and termination condition for drift compensation in this embodiment are limited to:

[0162] After the lockout state is established, the drift compensation unit acquires the current digital quantization value of the current channel as the drift sample value, denoted as e_comp(n), at the end of each drift detection cycle, with a preset drift detection period T_drift (T_drift is much larger than the control cycle), and reads the drift sample value e_comp(n-1) from the previous drift detection cycle. The drift compensation operation follows the following fixed-step, successive approximation adjustment logic: the phase compensation step Δφ_comp is a preset fixed value, which is no more than 0.2 reference clock cycles to ensure the smoothness of the compensation process and avoid phase abrupt changes or re-lockout caused by excessive single compensation. Each drift compensation operation performs only one step adjustment, that is, adjusting the phase Δφ_comp of the trigger signal of this channel in the direction of decreasing |e_comp(n)|. The direction of adjustment is determined by the sign of e_comp(n), that is, a positive value of e_comp(n) indicates that the phase of the trigger signal of this channel is lagging behind the reference edge of the global reference clock signal, and needs to be adjusted forward; a negative value of e_comp(n) indicates that the phase is leading, and needs to be adjusted backward. After a single adjustment is completed, the next adjustment is not performed immediately, but waits for the next drift detection cycle T_drift to arrive before resampling and judging again, thus leaving sufficient phase stabilization observation time between two adjacent compensation operations. The drift compensation completion judgment adopts a two-confirmation mechanism: when the absolute values ​​of the drift sampling values ​​|e_comp(n)| and |e_comp(n-1)| of two consecutive drift detection cycles are both less than the preset drift warning threshold THR_warn, it is determined that the phase drift of the trigger signal of this channel has been effectively compensated to within the warning threshold, the drift compensation operation is completed, compensation stops and returns to the normal periodic drift detection state. The setting of confirming compensation completion for two consecutive cycles is based on the fact that it can effectively eliminate premature termination of compensation caused by single sampling errors or instantaneous disturbances, ensuring reliable convergence of drift compensation. Throughout the entire drift compensation process, the lock status flag of this channel remains at 1, the PID calculation module responds normally to the lock edge of the calibration trigger signal and performs proportional-integral-derivative operations, and the update of motor control inputs and drive signal output are unaffected, achieving parallel and uninterrupted operation of drift compensation and normal motor control.

[0163] It should be further explained that the implementation method of the phase compensation step size and the state maintenance of the compensation process in this embodiment are limited to:

[0164] During drift compensation, fine-grained phase adjustment of less than one reference clock cycle is uniformly implemented through the phase offset function of the FPGA's internal MMCM, with a phase offset resolution of no less than 0.1 reference clock cycles. The configurable phase compensation step is denoted as Δφ_comp, which is preset to a fixed value via a register, with a configuration range of 0.1 to 0.5 reference clock cycles and a step size of 0.1 reference clock cycles to adapt to the drift characteristics of different systems. Each drift compensation operation performs only one phase adjustment with a step of Δφ_comp, and the adjustment direction is determined by the sign of the current drift sample value e_comp(n). Since the delay time from writing to physical effect of the MMCM phase offset configuration is approximately 1.5 control cycles, to ensure complete stability of the phase adjustment and avoid missampling during the transition phase, it is stipulated that at least 2 control cycles must be waited after each phase adjustment before performing the next drift sampling and judgment, thus reserving a safety margin of 0.5 control cycles. Throughout the drift compensation process, the trigger phase adjustment module remains locked, the locked state flag remains active, and the PID calculation module responds normally to the locking edge of the calibration trigger signal and performs calculations, thus achieving uninterrupted parallel operation of drift compensation and motor synchronous control.

[0165] It should be further explained that the overshoot suppression and compensation upper limit mechanism for drift compensation in this embodiment is limited as follows:

[0166] During drift compensation, the phase compensation step of a single drift compensation is denoted as Δφ_comp, which is a preset fixed value. In this embodiment, Δφ_comp = 0.2 reference clock cycles, and this value is selected within the preset configurable range of 0.1 to 0.5 reference clock cycles. The system also sets a maximum allowable adjustment constraint value of Δφ_max = 0.5 reference clock cycles for a single drift compensation. This constraint is the safe upper limit of the value of Δφ_comp. The basis for setting it is: when Δφ_comp ≤ 0.5 reference clock cycles, under the most unfavorable operating condition (i.e., |e_comp(n)| is exactly near the preset drift warning threshold THR_warn and the adjustment direction is towards the preset locking threshold THR_lock), the phase change caused by a single compensation operation will not cause |e_comp(n)| to jump from within THR_warn to above THR_lock, thereby effectively avoiding accidental loss of lock due to overshoot in a single compensation operation. In this embodiment, the preset locking threshold THR_lock = 2 reference clock cycles, the preset drift warning threshold THR_warn = 1 reference clock cycle, and the selected Δφ_comp = 0.2 satisfies the constraint requirement that Δφ_comp ≤ Δφ_max, and leaves a safety margin.

[0167] Each drift compensation operation performs only one phase adjustment with a step size of Δφ_comp. The adjustment direction is determined by the sign of the drift sample value e_comp(n) obtained in the current drift detection cycle: when e_comp(n)>0, it indicates that the phase of the trigger signal of this channel lags behind the reference edge of the global reference clock signal, and the phase of the trigger signal Δφ_comp is adjusted forward; when e_comp(n)<0, it indicates that the phase is ahead, and the phase of the trigger signal Δφ_comp is adjusted backward. If, after 10 consecutive drift compensation operations, the absolute value of the sample value |e_comp(n)| in the most recent 10 consecutive drift detection cycles still has not fallen below THR_warn, it indicates that the total cumulative phase compensation has reached 10×Δφ_comp=2 reference clock cycles, and the phase drift has not been effectively suppressed. Based on this, it is determined that the phase drift speed is abnormal, which may be caused by hardware-level faults such as crystal oscillator failure or drastic changes in ambient temperature. The system reports a drift over-limit fault flag and requests manual intervention.

[0168] Throughout the drift compensation process, the system continuously monitors the absolute value of the digital quantization value e(k) of the current control cycle: once it detects that |e(k)|>THR_lock, it immediately determines that the phase drift of the trigger signal of this channel has exceeded the lock tolerance range, forcibly terminates the currently executing drift compensation operation, and triggers the lock-out recovery process, switching the trigger phase adjustment module from the locked state back to the phase adjustment state, and re-establishing the phase lock.

[0169] The determination of drift compensation completion adopts a two-confirmation mechanism: when the absolute values ​​of the sampled values ​​|e_comp(n)| and |e_comp(n-1)| in two consecutive drift detection cycles are both less than THR_warn, it is determined that the phase drift of the trigger signal of this channel has been effectively compensated to within the warning threshold, the drift compensation operation is completed, compensation stops and the system returns to normal periodic drift detection state.

[0170] As a specific example, assume that the sampled value e_comp(n) obtained in a certain drift detection is +1.2 reference clock cycles. Since |e_comp(n)| > THR_warn = 1 and < THR_lock = 2, drift compensation is triggered. Because e_comp(n) is positive, the phase of the trigger signal is adjusted forward by Δφ_comp = 0.2 reference clock cycles. Wait for the next drift detection period T_drift and then perform the second sampling. The sampled value drops to +1.0. Since |e_comp(n + 1)| = 1.0 is still not less than THR_warn, continue to adjust forward by 0.2 reference clock cycles. Wait for another T_drift and then perform the third sampling. The sampled value drops to +0.8, and |e_comp(n + 2)| = 0.8 < THR_warn; continue to wait for another T_drift and then perform the fourth sampling. The sampled value is +0.6, and |e_comp(n + 3)| = 0.6 < THR_warn. At this time, the absolute values of the sampled values +0.8 and +0.6 in two consecutive drift detection periods are both less than THR_warn, meeting the condition for completing drift compensation, and the compensation operation is stopped. This compensation mechanism can control the residual deviation of phase drift within the order of magnitude of Δφ_comp in the long term, ensuring that the synchronization accuracy of the system during long-term operation is not less than 2 nanoseconds under a 100 MHz global reference clock.

[0171] It should be further noted that the PID calculation module in this embodiment includes an edge discrimination unit, and the edge discrimination unit is configured to:

[0172] Detect the edge of the calibration trigger signal. When it detects that the calibration trigger signal jumps from the first level state to the second level state, trigger and start a filtering timing window with a preset filtering duration;

[0173] Within the filtering timing window, use the global reference clock signal as the sampling clock to sample the level state of the calibration trigger signal multiple times to obtain multiple sampled level values;

[0174] Compare each of the multiple sampled level values with the second level state, and count the number of sampled level values that match the second level state among the multiple sampled level values as the stable count value;

[0175] Compare the stable count value with a preset stable count threshold. When the stable count value is greater than or equal to the preset stable count threshold, determine that the current edge is a true lock edge, generate a trigger enable signal, and send the trigger enable signal to the PID calculation module to trigger the execution of proportional-integral-derivative operation;

[0176] When the stable count value is less than the preset stable count threshold, the current edge is determined to be an interference glitch, the current edge is discarded, and the trigger enable signal is not generated; wherein, the preset filtering duration is K times the period of the global reference clock signal, the preset stable count threshold is less than or equal to K, K is a positive integer, and in this embodiment, the value is 4.

[0177] It should be further explained that the filtering window setting and sampling statistics logic for edge detection in this embodiment are limited to:

[0178] The first level state is low, and the second level state is high. Edge detection is rising edge detection. Sampling is performed at the rising edge of each global reference clock within the filtering timing window, resulting in K sampled level values. The stable count value is calculated using a real-time accumulation method, updating the stable count value immediately after each sampling. The final stable count value is output when the filtering timing window ends. The filtering timing window is implemented by a 4-bit binary adder counter, synchronously cleared, and triggered by a rising edge. The counter starts counting from 0 and ends when it counts to K. The basis for K=4 is: according to the statistical characteristics of electromagnetic interference in industrial environments, 99% of interference pulse widths are less than three 50MHz clock cycles (60ns), and a filtering window of 4 cycles can effectively filter out the vast majority of interference.

[0179] It should be further explained that the metastability suppression and window activation logic for edge detection in this embodiment is limited to:

[0180] Edge detection employs a two-stage synchronous flip-flop structure. Both the first and second stages utilize the FPGA's internal FDCE primitive. The first stage flip-flop samples the calibration trigger signal at the rising edge of the global reference clock, while the second stage flip-flop samples the output of the first stage. When the output of the second stage flip-flop is low and the output of the first stage flip-flop is high, a rising edge is detected, and a filtering timing window is immediately initiated. Once the filtering timing window is started, no new edge detection requests are responded to until the window ends, preventing multiple triggers within the same window. The sampling operation is strictly performed at the rising edge of the global reference clock signal to ensure synchronization of the sampling time. The MTBF (Mean Time Between Failures) of the metastability suppression circuit is greater than 10. 9 The system operates for hours, meeting industrial-grade reliability requirements. The reason for not responding to new edges after the window starts is to prevent the same interference pulse from generating multiple trigger signals.

[0181] It should be further explained that the nesting processing of the filtering window and the effective edge priority mechanism in this embodiment are limited to:

[0182] If a new edge transition (including rising and falling edges) is detected within the filtering timing window, the transition is ignored, and sampling and statistics for the current window continue. If the stable count value reaches the threshold after the filtering window ends, a trigger enable signal is generated. If the threshold is not reached, the edge detection state is immediately restored. Only one trigger enable signal is generated within the same control cycle. Even if multiple valid edges are detected, only the first one is responded to, ensuring that the PID calculation is executed only once per control cycle. The basis for responding to only the first edge within the same control cycle is to ensure the periodicity of PID calculation and avoid control chaos caused by repeated calculations.

[0183] As a specific example, in this embodiment, the global reference clock signal frequency is 50MHz and the period is 20ns; K is set to 4, and the preset filtering duration is 4 clock cycles, i.e., 80ns; when the calibration trigger signal is detected to transition from low level to high level, the filtering timing window is immediately started, the 4-bit counter is cleared and starts counting; the calibration trigger signal is sampled at the 1st, 2nd, 3rd, and 4th rising edges of the global reference clock within the filtering window, resulting in 4 sampled level values; if the 4 sampled level values ​​are high, high, high, and low in sequence, a stable count value of 3 is obtained; if the 4 sampled level values ​​are high, low, high, and high in sequence, a stable count value of 3 is obtained; this filtering method can effectively filter out narrow pulse interference with a duration of less than 3 clock cycles (60ns), improving the anti-interference capability of edge detection.

[0184] It should be further explained that the criteria for determining the effective edge and the logic for generating the trigger enable signal in this embodiment are limited to:

[0185] The preset stable counting threshold is set to three-quarters of the filter timing window length K, rounded up, where K is the filter timing window length in units of the global reference clock cycle, and is set to 4. This threshold setting can ensure the filtering of narrow pulse interference with a duration of less than 3 clock cycles while controlling the detection response delay of the effective edge to within 1 clock cycle, thereby balancing anti-interference capability and edge detection response speed.

[0186] The trigger enable signal is a positive pulse with a width exactly equal to one global reference clock cycle. This pulse is generated on the rising edge of the first global reference clock after the end of the filtered timing window, ensuring that the trigger enable signal is strictly synchronized with the global reference clock.

[0187] When an edge is identified as an interference glitch and discarded because its stable count value is less than the preset stable count threshold, the edge identification unit immediately resets and returns to the edge detection state, waiting for the next possible edge to arrive.

[0188] Within a control cycle, the edge discrimination unit generates a trigger enable signal at most once. Once the trigger enable signal is generated, the edge discrimination unit will not respond to any edge of the calibration trigger signal for the remainder of the current control cycle to avoid repeated triggering of PID calculations. This mechanism is implemented through a 1-bit control cycle flag: the flag is cleared at the beginning of the control cycle, set to 1 after the trigger enable signal is generated, and prevents the generation of new trigger enable signals when the flag is 1. The flag is automatically cleared at the end of the control cycle.

[0189] It should be further explained that the synchronization mechanism and repeated trigger suppression logic of the trigger enable signal in this embodiment are limited to:

[0190] The trigger enable signal is fully synchronized with the global reference clock signal, with both its rising and falling edges aligned with the rising edge of the global reference clock. The mechanism of generating only one trigger enable signal within the same control cycle is implemented using a 1-bit control cycle flag, constructed using the FDCE primitive within the FPGA. At the start of the control cycle, this flag is synchronously cleared to zero; when the edge detection unit determines that the current edge is a valid lock edge and generates the trigger enable signal, the flag is immediately set to logic 1. When the flag is logic 1, the edge detection unit no longer generates a new trigger enable signal, thus avoiding repeated triggering of PID calculations within the same control cycle. At the end of the control cycle, the flag is automatically cleared to zero, and the edge detection unit resumes its edge detection function, preparing to respond to valid edges in the next control cycle.

[0191] The trigger enable signal is directly connected to the hardware trigger input of the PID calculation module, ensuring that the delay time from the activation of the trigger enable signal to the start of PID calculation is no greater than one global reference clock cycle. The basis for adopting hardware triggering is that hardware triggering can guarantee the absolute accuracy of the trigger timing, completely avoiding the uncertainty caused by software interrupt response delay and operating system task scheduling jitter, thereby ensuring strict synchronization of the start edge of multi-channel PID calculation.

[0192] It should be further noted that the timeout protection and exception handling mechanism for PID calculation in this embodiment is limited to:

[0193] The PID calculation module incorporates an 8-bit binary adder counter that is synchronously reset to zero. A rising-edge triggered timeout counter starts counting when the enable signal is active. If the PID calculation is not completed when the preset timeout threshold (100 clock cycles) is reached, the calculation is forcibly terminated, and the valid control value of the previous control cycle is output. Simultaneously, the system reports a PID calculation timeout fault. This mechanism prevents system crashes caused by hardware failures. The 100-clock-cycle timeout threshold is based on the fact that the normal execution time of a PID calculation is 18 clock cycles; the 100-cycle threshold provides sufficient margin to effectively distinguish between normal operation and hardware failure.

[0194] As a specific example, in this embodiment, K=4, and the preset stable counting threshold is set to 3. If the stable count value is 3 or 4, the current edge is determined to be a true locked edge, and a trigger enable signal with a width of 20ns is generated on the first rising edge of the global reference clock after the end of the filtering window to trigger the PID operation. If the stable count value is 2 or 1, the current edge is determined to be an interference glitch, the edge is discarded, and no trigger enable signal is generated. For example, if an interference pulse with a duration of 40ns occurs, and only the first two of the four samples within the filtering window are high-level, the stable count value is 2, which is less than the threshold of 3, so it is determined to be an interference glitch and the PID operation is not triggered. This setting can filter out electromagnetic interference pulses with a duration of less than 60ns commonly seen in industrial environments while ensuring response speed, preventing the PID operation from being falsely triggered.

[0195] Further explanation is needed; please refer to [link / reference]. Figure 2 In this embodiment, the PID calculation module further includes a trigger enable management unit, which is configured as follows:

[0196] After the power-on reset signal is released, the PID trigger enable flag of this channel is set to the first logic state. The first logic state indicates that the PID calculation module is prohibited from responding to any edge of the calibration trigger signal.

[0197] Within each control cycle, the digital quantization value of the current control cycle output by the phase detection module is received, and the absolute value of the digital quantization value is compared with the preset locking threshold.

[0198] When the absolute value of the digital quantization value is less than the preset locking threshold, the PID trigger enable flag is updated from the first logic state to the second logic state. The second logic state indicates that the PID calculation module is allowed to respond to the locking edge of the calibration trigger signal.

[0199] When the absolute value of the digital quantization value is greater than or equal to the preset locking threshold, the PID trigger enable flag is kept in the first logic state, and a preset safety control value is output to the drive module. The preset safety control value is a fixed value stored in the register in advance, and the fixed value makes the corresponding motor output zero torque.

[0200] It should be further noted that the PID trigger enable state transition logic and safety control quantity settings in this embodiment are limited to:

[0201] The first logic state is logic 0, and the second logic state is logic 1. The PID trigger enable flag is updated only at the beginning of each control cycle and remains updated until the next control cycle. The preset safety control value is a 16-bit unsigned integer with a value of 0, corresponding to a zero-voltage or zero-duty-cycle PWM signal output by the drive module, causing the motor to output zero torque. When the PID trigger enable flag switches from the second logic state back to the first logic state, the preset safety control value is immediately output to the drive module to ensure the motor stops quickly. The state of the PID trigger enable flag can be read via the AXI-Lite bus for the host computer to monitor the system status. The basis for updating the flag at the beginning of the control cycle is to ensure the synchronization of state transitions and avoid control anomalies caused by state transitions in the middle of the control cycle.

[0202] It should be further noted that the definition of the comparison time and the output mechanism of the safety control quantity in this embodiment are limited as follows:

[0203] The start time of each control cycle is defined as a preset rising edge of the global reference clock signal, which is strictly aligned with the end time of the previous control cycle. When this preset rising edge arrives, the trigger enable management unit receives the digital quantization value calculated and latched by the phase detector module in the previous control cycle, and compares the absolute value of the digital quantization value with a preset lock threshold. The comparison result directly determines the state of the PID trigger enable flag in the current control cycle: if the absolute value of the digital quantization value is less than the preset lock threshold, the PID trigger enable flag is set to logic 1, indicating that the PID calculation module is allowed to respond to the lock edge of the calibration trigger signal; if the absolute value of the digital quantization value is greater than or equal to the preset lock threshold, the PID trigger enable flag is held or set to logic 0, indicating that the PID calculation module is prohibited from responding to any edge.

[0204] When the PID trigger enable flag is logic 0, the input signal of the drive module is forcibly switched to a preset safety control value through a 2-to-1 data selector, completely ignoring the motor control value output by the PID calculation module. This 2-to-1 data selector is implemented using the lookup table resources within the FPGA, with a signal transmission delay of less than 1 nanosecond, ensuring real-time safety switching. The preset safety control value is a fixed value pre-stored in a register. This value causes the drive module to output a zero-duty-cycle pulse-width modulated signal or a zero-voltage analog signal, thereby causing the corresponding motor to output zero torque. When the PID trigger enable flag is logic 1, the 2-to-1 data selector switches the input of the drive module to the motor control value output by the PID calculation module, and the motor operates according to normal control commands.

[0205] In this embodiment, the safety control output has the highest priority and is unaffected by any other control signals or status flags. The core basis for this priority setting is to ensure that under any abnormal circumstances, including system power-on unlocking, phase loss during operation, or false triggering due to external interference, the motor can be forcibly switched to a safe state, thereby effectively preventing motor runaway and protecting equipment and personnel safety. The highest priority is achieved through hardware-level signal forced selection, requiring no software intervention, further improving the reliability and real-time performance of the safety response.

[0206] As a specific example, in this embodiment, the preset locking threshold is set to 2 clock cycles, corresponding to a phase deviation of 40ns. After the power-on reset signal is released, the PID trigger enable flag is initialized to logic 0, disabling the PID calculation module from responding to any calibration trigger signal edge. The input of the drive module is forcibly switched to the preset safety control quantity through a 2-to-1 data selector, causing the corresponding motor to output zero torque.

[0207] At the beginning of a certain control cycle, i.e. at the preset rising edge of the global reference clock signal, the trigger enable management unit receives the digital quantization value 1.5 calculated and latched by the phase detector module in the previous control cycle. Its absolute value is less than the preset locking threshold 2. The trigger enable management unit updates the PID trigger enable flag to logic 1, allowing the PID calculation module to respond to the locking edge of the calibration trigger signal. The input of the drive module is switched to the motor control quantity output by the PID calculation module, and the motor enters the normal controlled operation state.

[0208] At the beginning of the next control cycle, the digital quantization value received by the trigger enable management unit becomes 2.5, and its absolute value is greater than or equal to the preset lockout threshold of 2. The trigger enable management unit keeps the PID trigger enable flag bit at logic 0, prohibits the PID calculation module from responding to any edge, and the input of the drive module is forcibly switched to the preset safety control quantity by the 2-to-1 data selector, so that the motor outputs zero torque.

[0209] If, during normal operation, external electromagnetic interference causes the digital quantization value to momentarily jump to 3, and its absolute value exceeds the preset locking threshold, the PID trigger enable flag is cleared at the beginning of the current control cycle. The input to the drive module is immediately forced to switch to the preset safety control quantity, and the motor stops controlled operation. Once the external interference is eliminated, the absolute value of the digital quantization value falls back below the preset locking threshold, and the phase locking condition is met, the PID trigger enable flag is reset to logic 1, and the motor returns to normal controlled operation. This mechanism ensures that when the phase is not locked or is lost during operation, the motor remains in a safe zero-torque state, preventing any abnormal movement and ensuring system safety.

[0210] It should be further explained that the drive module in this embodiment includes a drive signal generation unit and a synchronous output control unit; it should be further explained that the drive signal generation unit in this embodiment is configured to: receive the motor control quantity output by the PID calculation module, and convert the motor control quantity into a drive signal required to drive the corresponding motor, wherein the drive signal is a pulse width modulation signal or a voltage analog signal;

[0211] It should be further noted that the conversion logic and parameter settings of the drive signal in this embodiment are limited to:

[0212] The motor control input is a 16-bit unsigned integer, ranging from 0 to 65535. The carrier frequency of the pulse width modulation (PWM) signal is preset to 20kHz, with a resolution of 16 bits and a duty cycle range of 0% to 100%, where 0 corresponds to a 0% duty cycle and 65535 corresponds to a 100% duty cycle. The voltage analog signal is generated by a 16-bit digital-to-analog converter (DAC) of model AD5689, with an output range of 0V to 10V, where 0 corresponds to 0V and 65535 corresponds to 10V. The conversion uses a linear mapping relationship, with no nonlinear correction during the conversion process, ensuring a strict linear correspondence between the control input and the drive signal. The drive signal generation unit is implemented using pure hardware logic, and the conversion delay from the motor control input to the PWM signal output is no greater than one global reference clock cycle. The 20kHz carrier frequency is chosen because it is above the range of human hearing, which avoids noise from the motor. The 16-bit resolution is chosen because it allows for a duty cycle adjustment accuracy of 0.0015%, meeting the requirements of high-precision motor control.

[0213] It should be further noted that the PWM signal generation logic and dead time setting in this embodiment are limited to:

[0214] The pulse width modulation (PWM) signal is generated using a center-aligned method, with a triangular wave as the carrier. For three-phase motor drives, the drive signal generation unit outputs three-phase, six-channel complementary symmetrical PWM signals. The dead time is preset to 2 microseconds and is inserted at the switching moment of the complementary PWM signal to prevent shoot-through between the upper and lower bridge arms. The dead time can be configured via a register, ranging from 0 to 10 microseconds with a step size of 0.1 microseconds. The polarity of the PWM signal can be configured via a register to be active high or active low to adapt to different power drive chips. The 2-microsecond dead time is based on the fact that the typical IGBT turn-off delay time is 1.5 microseconds, leaving a 0.5-microsecond margin to effectively prevent shoot-through between the upper and lower bridge arms.

[0215] It should be further noted that the synchronous update and anomaly protection mechanism of the PWM signal in this embodiment is limited to:

[0216] The PWM signal duty cycle register is updated only at the trough of each PWM cycle to avoid glitches in the PWM waveform. The drive signal generation unit has built-in overcurrent, overvoltage, and overheat detection interfaces. When an abnormal signal is detected, all PWM signals are immediately set to low level, cutting off the motor drive power supply. The abnormal state is reported to the ARM processor through the register. The reason for updating the duty cycle at the trough is to avoid narrow pulses in the PWM waveform and improve the quality of the drive signal.

[0217] As a specific example, in this embodiment, the motor control quantity is 32768, corresponding to a 50% duty cycle or a 5V voltage analog signal; the carrier frequency of the pulse width modulation signal is 20kHz, the period is 50μs, and the duty cycle adjustment step size corresponding to the 16-bit resolution is approximately 0.0015%, which can achieve precise adjustment of the motor speed; the voltage analog signal is generated by the 16-bit DAC chip AD5689, with an output accuracy of ±1LSB, corresponding to a voltage error of approximately 0.15mV, which can meet the requirements of high-precision motor drive; the drive signal generation unit is implemented using the FPGA internal hardware PWM module, with a conversion delay of no more than one global reference clock cycle (20ns); for three-phase permanent magnet synchronous motor drive, the drive signal generation unit also includes a space vector pulse width modulation (SVPWM) module, which can convert the motor control quantity into a three-phase six-channel PWM signal.

[0218] It should be further explained that the synchronous output control unit in this embodiment is configured to: latch the multiple drive signals generated by the drive signal generation unit using the global reference clock signal as the timing reference; and after all the drive signals of all channels have been updated, synchronously output each drive signal to each motor at a preset edge of the same global reference clock signal; wherein, the preset edge maintains a fixed phase relationship with the operation start edge of each PID calculation module, so that the delay time from the completion of PID calculation to the output of drive signal is consistent across all channels.

[0219] It should be further explained that the synchronous latching and output logic of the drive signal in this embodiment is limited to:

[0220] The latching operation is triggered by the rising edge of the global reference clock signal, and the drive signals of all channels are latched simultaneously on the same latching edge. The preset edge is the rising edge of the global reference clock signal, and the phase difference between it and the PID calculation start edge is fixed at N global reference clock cycles, where N is the number of clock cycles corresponding to the maximum execution time of the PID calculation plus 2 clock cycles. The synchronous output control unit has a built-in N-bit binary adder counter, which is synchronously cleared and triggered by the rising edge. When the PID calculation start edge arrives, the counter is cleared and starts counting. When the count reaches N, a latching signal is generated, and the drive signals of all channels are latched and output simultaneously. The latching signal is a positive pulse with a width of 1 global reference clock cycle, and the latches of all channels respond simultaneously. The basis for N = maximum PID execution time + 2 clock cycles is that the maximum execution time of the PID calculation is 18 clock cycles, and adding a margin of 2 cycles ensures that the drive signals of all channels have been updated.

[0221] It should be further noted that the fixed delay mechanism and latch structure for synchronous output in this embodiment are limited to:

[0222] The synchronous output control unit does not rely on the completion flag of the drive signal update for each channel, but instead uses a fixed delay to ensure that the drive signals of all channels have been updated. The value of N is the number of clock cycles corresponding to the maximum execution time of the PID calculation plus 2, reserving a margin of 1 clock cycle. All channel drive signal latches use the same type of FDCE primitive, and the clock path length of each latch is ensured to be consistent during placement and routing, further reducing output deviation between channels. The latch outputs are directly connected to the FPGA's I / O pins, which use the same drive strength (8mA) and slew rate (fast) configuration. The basis for equal-length clock path routing is to control the clock deviation of each channel's latches within 100ps, further improving synchronization accuracy.

[0223] It should be further explained that the global triggering and channel-independent enabling mechanism for synchronous output in this embodiment is limited to:

[0224] The synchronous output control unit generates a global latch signal, which is simultaneously responded to by the latches of all channels. Each channel is configured with an independent 1-bit output enable register. When the output enable bit of a channel is 0, the drive signal of that channel is forced to a safe state (low level). The global latch signal and the output enable signal are logically ANDed and then output to the IO pin to ensure the unity of independent channel control and global synchronization. The basis for independent channel enabling is to enable the independent start and stop of a single motor without affecting the synchronous operation of other motors.

[0225] As a specific example, in this embodiment, the maximum execution time of the PID calculation is 180ns, corresponding to 9 global reference clock cycles (20ns / cycle), so N is set to 10; the PID calculation starts at the 0th rising edge of the global reference clock, the counter starts counting from 0, and when it counts to 10, a latch signal is generated at the 10th rising edge of the global reference clock; the drive signals of all channels are latched and output to each motor at the 10th rising edge; this mechanism ensures that the delay time from the completion of the PID calculation to the output of the drive signal for each channel is 200ns, and the delay difference between channels is no more than 1 global reference clock cycle (20ns), further improving the synchronization accuracy of multi-channel motor drive signals; for an 8-channel motor control system, this synchronization output mechanism can control the output time deviation of the 8 drive signals to within 20ns, which is far better than the millisecond-level deviation of the traditional software synchronization method.

[0226] This application employs a high-precision temperature-compensated crystal oscillator combined with two-stage RC low-pass filtering, linear regulated power supply noise suppression, and an aluminum electromagnetic shielding structure to generate a low-jitter global reference clock. This clock is then synchronously distributed to each channel via LVDS differential transmission lines with equal-length impedance matching, ensuring minimal difference in transmission path delay between channels and laying a stable and reliable timing foundation for high-precision phase locking. Furthermore, by integrating a path delay calibration unit into the phase detection module, and using a serial calibration method combined with Grubbs' criterion outlier removal, two-stage synchronous trigger metastability suppression, and a fixed-delay feedback path design, precise timing can be achieved. It accurately measures and compensates for inherent path deviations in each channel caused by PCB routing differences, FPGA internal logic delays, and I / O interface transmission delays, significantly improving the calibration accuracy of the phase measurement benchmark and eliminating systematic errors in multi-channel phase measurements at their source. By employing a two-stage phase adjustment structure of coarse and fine adjustment in the triggered phase adjustment module, combined with a three-condition oscillation comprehensive judgment logic based on amplitude increment, deviation change rate, and alternating sign changes, and a linear gradual parameter update mechanism, it ensures rapid adjustment speed under large phase deviations while effectively suppressing oscillations and overdamping phenomena during the adjustment process, significantly reducing the time required for phase measurement. The system features a short phase lock-in time and employs an independent drift compensation unit to provide micro-step compensation for long-term slow phase drift caused by crystal oscillator temperature drift, power supply voltage fluctuations, and component aging, ensuring high synchronization accuracy during long-term system operation. By integrating a two-stage synchronous trigger with a sliding window filter edge discrimination unit and a graded safety protection trigger enable management unit into the PID calculation module, it effectively filters out most narrow-pulse electromagnetic interference in industrial environments, preventing PID calculation mis-triggering. Furthermore, through a graded safety mechanism of first-stage zero-torque free stop and second-stage emergency stop, along with hysteresis recovery logic, it quickly switches the motor to a safe state in the event of phase lock-in, avoiding equipment damage and personnel injury, significantly improving the system's anti-interference capability and operational safety. By adopting a global synchronous latch output mechanism based on a fixed-delay counter in the drive module, combined with equal-length clock path wiring and unified IO configuration, it ensures that the drive signals of all channels are output synchronously at the same global reference clock edge, greatly reducing the output timing deviation of multi-motor drive signals. Ultimately, it achieves highly consistent timing of multi-motor control cycles and extremely high speed synchronization accuracy, fully meeting the stringent requirements of industrial-grade high-precision multi-motor collaborative control systems.

[0227] Example 3

[0228] As a specific example, in this embodiment, the preset frequency band of the global reference clock signal is set to 100MHz, and the clock period is 10 nanoseconds; the preset locking threshold is set to 2 clock cycles, corresponding to a phase deviation of 20 nanoseconds; the preset synchronization accuracy threshold is set to 1 clock cycle, corresponding to a timing deviation of 10 nanoseconds; the control cycle is set to 1,000,000 clock cycles, corresponding to 10 milliseconds; the preset convergence judgment threshold is set to 1 clock cycle, corresponding to 10 nanoseconds; the preset locking state confirmation cycle number is set to 5 consecutive control cycles; and the preset hysteresis width is set to 0.5 clock cycles, corresponding to 5 nanoseconds. In this embodiment, the global reference clock frequency is set to 100MHz based on the following: a 10ns clock cycle provides a finer phase quantization resolution than a 50MHz clock (20ns cycle), meeting the requirement of 10ns-level synchronization accuracy. Furthermore, the 100MHz frequency is within the MMCM operating range of the Xilinx Artix-7 FPGA, eliminating the need for an additional PLL frequency multiplier circuit. The control cycle is set to 1000 clock cycles (10 microseconds) based on the following: this cycle is much larger than the 18 clock cycles for PID calculation and the 20 clock cycles for drive signal output, leaving sufficient timing margin. At the same time, the 10 microsecond control frequency (100kHz) can meet the bandwidth requirements of the servo motor current loop.

[0229] To further illustrate the implementation logic of this embodiment, a specific complete example is given below to explain the entire process. This example is only to illustrate the feasibility at the computational level and does not represent actual values. The specific values ​​can be determined by those skilled in the art through simulation experiments or physical experiments. The specific implementation process is as follows:

[0230] I. System power-on reset and initialization phase, specifically:

[0231] After the system powers on, a high-level active global reset signal lasts for 10 global reference clock cycles (100 nanoseconds). After the reset signal is released, the clock generation module starts up and enters a stable state. It should be further noted that the startup and stabilization logic of the clock generation module in this embodiment is limited as follows: after the TCXO-5070-100MHz temperature-compensated crystal oscillator powers on, it undergoes a 10-millisecond warm-up and stabilization time, achieving an output frequency stability of ±0.5ppm; the FPGA's internal MMCM primitive performs frequency multiplication / division processing on the TCXO output clock; after the lock indicator light illuminates, the clock generation module outputs a stable 100MHz global reference clock signal. This signal is transmitted through an internal 8-channel SN65LVDS108 differential output buffer, and synchronously distributed to the first input terminal of the phase detection module of the 8 motor control channels via LVDS differential transmission lines with equal-length impedance matching (50Ω characteristic impedance, length error ±5mm). The difference in the transmission path delay of the reference clock received by each channel is ≤1 clock cycle (10 nanoseconds).

[0232] In this embodiment, the control cycle is set to 1000 reference clock cycles, corresponding to 10 microseconds; the preset lock threshold THR_lock is set to 2 reference clock cycles, corresponding to 20 nanoseconds; the preset drift warning threshold THR_warn is set to 1 reference clock cycle, corresponding to 10 nanoseconds; the preset convergence judgment threshold is set to 1 reference clock cycle, corresponding to 10 nanoseconds; the preset synchronization accuracy threshold is set to 1 reference clock cycle, corresponding to 10 nanoseconds; and the preset drift detection cycle is set to 1000 control cycles, corresponding to 10 seconds.

[0233] At this time, the trigger signals of each channel are in an disabled state. On the first rising edge of the global reference clock after the reset release, the trigger enable management unit initializes the PID trigger enable flag of each channel to a logic low level '0', disabling the PID calculation module from responding to any edge trigger. At the same time, it forces the input of each channel drive module to switch to the preset safety control quantity register and outputs the preset safety control quantity 0x0000. This value is a fixed value pre-stored in the 16-bit read-only register of each channel. The corresponding drive module outputs a PWM signal with zero duty cycle, so that each motor outputs zero torque and remains stationary.

[0234] II. The path delay calibration phase, specifically:

[0235] With all channel trigger signals disabled and the global calibration completion flag set to '0', the path delay calibration unit sequentially performs path delay measurements from channel number 0 to 7, calibrating only one channel at a time. The multiplexers for other channels remain low-level grounded to avoid crosstalk from calibration pulse signals. It should be further noted that the single-channel path delay measurement procedure in this embodiment is limited to:

[0236] Calibration pulse signal injection: On the first rising edge of the global reference clock after the calibration start signal of the current calibration channel is valid, the path delay calibration unit injects a calibration pulse signal with a width of 1 global reference clock cycle (10 nanoseconds) into the starting point of the transmission path of the trigger feedback signal of this channel. The rising edge of the pulse is strictly synchronized with the rising edge of the global reference clock signal, and the pulse rising edge time is ≤1ns and the falling edge time is ≤1ns.

[0237] Delay Measurement: The 16-bit synchronous adder counter is synchronously cleared to zero and starts counting when the calibration pulse signal is injected. The counter increments by 1 on each rising edge of the global reference clock. After the calibration pulse signal is transmitted through the PCB traces, the FPGA internal IBUF primitives and the IO interface, it reaches the second input of the phase detection module. After the dedicated two-stage synchronous flip-flop structure inside the phase detection module detects the rising edge of the calibration pulse signal, it immediately generates a counter stop signal with a width of 1 clock cycle. The counter stops counting synchronously, and the final count value is the original value of the path delay for this measurement.

[0238] Multiple measurements and data processing: The above measurement process is repeated 16 times for each channel, and 16 calibration pulse signals are continuously injected to obtain 16 raw measurement values; outliers are removed from the 16 measurement values ​​using the Grubbs criterion, with a significance level set at 0.05; after removing outliers, the arithmetic mean and variance of the remaining valid measurement values ​​are calculated.

[0239] Result determination and storage: If the number of valid measurements is ≥10 and the variance is ≤2 clock cycles, the arithmetic mean is rounded to the nearest integer and written to the 16-bit path delay compensation register of this channel; if the number of valid measurements is <10 or the variance is >2 clock cycles, the measurement is determined to be unreliable and 16 measurements are re-executed; if 3 consecutive measurements are unreliable, a calibration fault flag for this channel is reported and the system stops the calibration process.

[0240] It should be further explained that the specific execution logic of the Grubbs criterion in this embodiment is limited as follows: calculate the arithmetic mean and standard deviation of 16 measurements; calculate the Grubbs statistic for each measurement, which is equal to the absolute value of the difference between the measurement and the arithmetic mean divided by the standard deviation; compare the largest Grubbs statistic with the critical value of 2.443 corresponding to a significance level of 0.05 and a sample size of 16; if the largest Grubbs statistic is greater than 2.443, then the outlier is removed, and the above process is repeated for the remaining 15 values ​​until there are no outliers. In this embodiment, the critical value of 2.443 in the Grubbs criterion is set based on the statistical distribution critical value when the significance level is 0.05 and the sample size is 16. This value is calculated through the critical value table of the Grubbs test or the inverse cumulative distribution function, and its physical meaning is: when the measurement data follows a normal distribution, the probability that a single measurement value deviates from the mean by more than this critical value is less than 5%. Using a significance level of 0.05 can effectively identify outliers while avoiding excessive rejection of normal data, and a sample size of 16 balances measurement accuracy with calibration time overhead, thereby ensuring the statistical reliability of path delay measurement.

[0241] As a specific example, in this embodiment, taking the first channel as an example, the original count values ​​of the 16 measurements are 5, 5, 6, 5, 5, 5, 6, 5, 5, 5, 5, 6, 5, 5, 5, 5 clock cycles respectively; the calculated arithmetic mean is 5.1875, and the standard deviation is 0.4031; the maximum Grubbs statistic is (6-5.1875) / 0.4031=2.015, which is less than the critical value of 2.443, and there are no outliers; the arithmetic mean is rounded to 5 and written into the path delay compensation register of the first channel, corresponding to a physical delay time of 50 nanoseconds.

[0242] Taking the second channel as an example, the original count values ​​of the 16 measurements are 4, 4, 5, 4, 4, 4, 4, 5, 4, 4, 4, 5, 4, 4, 4, 4, 5, 4, 4 clock cycles respectively; the calculated arithmetic mean is 4.1875, and the standard deviation is 0.4031; the maximum Grubbs statistic is (5-4.1875) / 0.4031=2.015, which is less than the critical value of 2.443, and there are no outliers; the arithmetic mean is rounded to 4 and written into the path delay compensation register of the second channel, corresponding to a physical delay time of 40 nanoseconds.

[0243] After all the path delay count values ​​for the 8 channels have been written, the path delay calibration unit generates a high-level active global calibration completion flag, and the system automatically enters the normal operation phase, with the trigger signals for each channel being enabled sequentially.

[0244] III. Phase Adjustment and Lock-in Establishment Phase, specifically:

[0245] After path delay calibration is completed, the trigger signals for each channel are enabled sequentially according to their channel numbers, triggering the phase adjustment module to enter the phase adjustment state. It should be further noted that the fixed timing of each control cycle in this embodiment is limited as follows:

[0246] Clock cycle 0: Control cycle begins, trigger enable management unit updates PID trigger enable flag bit according to digital quantization value of previous control cycle;

[0247] Clock cycles 1-10: The phase detection module completes the reading of the original measurement count value, path delay compensation, and digital quantization value calculation;

[0248] Clock cycles 11-20: Trigger the phase adjustment module to complete phase difference comparison, deviation calculation and phase adjustment operations;

[0249] Clock cycles 21-30: The dynamic parameter adjustment unit completes status determination and parameter update;

[0250] 999970 clock cycles remaining: The system is waiting for the next control cycle to begin.

[0251] Within each control cycle, the phase detection module performs the following operations: using the rising edge of the global reference clock signal as the counting reference and the rising edge of the trigger feedback signal as the stop reference, it measures the time interval between the two using the rising edge counting method to obtain the original measured count value; it reads the path delay count value in the path delay compensation register of this channel, subtracts the path delay count value from the original measured count value to obtain the compensated digital quantization value, and retains the sign bit of the result to characterize the phase lead / lag relationship.

[0252] Taking channel 1 as an example, in the first control cycle after the trigger signal is enabled (denoted as control cycle 0), the original measurement count is 25, and the path delay count is 5. Therefore, the digital quantization value is 25 - 5 = +20, corresponding to a physical phase deviation of 200 nanoseconds. This means that the rising edge of the trigger feedback signal for channel 1 lags behind the rising edge of the global reference clock signal by 200 nanoseconds. In the same control cycle, the original measurement count for channel 2 is 24, and the path delay count is 4. Therefore, the digital quantization value is 24 - 4 = +20, also corresponding to a physical phase deviation of 200 nanoseconds. After path delay compensation, the phase measurement reference for each channel is unified.

[0253] After the digital quantization value is calculated, the phase adjustment module is triggered to compare the absolute value of the digital quantization value with the preset lock threshold 2 in the 15th clock cycle of each control cycle. Taking channel 1 as an example, the digital quantization value in control cycle 0 is +20. Since the absolute value 20 is greater than the preset lock threshold 2, the phase adjustment module maintains the phase adjustment state and adjusts the phase of the trigger signal of this channel in steps according to the deviation in the direction of decreasing the absolute value of the phase difference.

[0254] The preset proportional coefficient is 0.5 (0x0800 in Q12 format), and the preset integral coefficient is 0.125 (0x0200 in Q12 format). The proportional adjustment component is the digital quantization value multiplied by the proportional coefficient, and the integral adjustment component is the phase deviation change multiplied by the integral coefficient. The deviation is the sum of the proportional and integral adjustment components, rounded to the nearest integer, which is the phase adjustment step size. It should be further noted that the initialization logic for the historical digital quantization value in this embodiment is limited to: in the first control cycle after the trigger signal of this channel is enabled, the historical digital quantization value register is initialized to the digital quantization value of the current control cycle. Therefore, during the first adjustment, the phase deviation change is 0, and the integral adjustment component is 0.

[0255] In control cycle 0, the historical digital quantization value of channel 1 is initialized to +20, and the phase deviation change is 20-20=0; the proportional adjustment component is 20×0.5=10, and the integral adjustment component is 0×0.125=0; the deviation is 10+0=10, rounded to 10 step units, indicating that the trigger signal phase needs to be adjusted forward by 10 clock cycles (100 nanoseconds). The phase adjustment is implemented using a two-stage structure of coarse adjustment and fine adjustment. The coarse adjustment is achieved through frequency division using the FPGA's internal counter, with a resolution of 1 clock cycle; the fine adjustment is achieved through the IDELAYE2 primitive inside the XilinxArtix-7 FPGA, with a resolution of 78ps. This adjustment is a coarse adjustment, advancing the rising edge of the trigger signal by 10 clock cycles.

[0256] The adjustment process is repeated in each control cycle, specifically as follows:

[0257] First control cycle: The digital quantization value decreases from +20 to +10. The historical digital quantization value is +20. The phase deviation change is 10-20=-10. The proportional adjustment component is 10×0.5=5, and the integral adjustment component is -10×0.125=-1.25. The deviation is 5-1.25=3.75, rounded to 4 step units, and adjusted forward 4 clock cycles.

[0258] Second control cycle: The digital quantization value drops to +6, the historical digital quantization value is +10, the phase deviation change is 6-10=-4; the proportional adjustment component is 6×0.5=3, the integral adjustment component is -4×0.125=-0.5; the deviation is 3-0.5=2.5, rounded to 3 step units, and adjusted forward 3 clock cycles.

[0259] Third control cycle: The digital quantization value drops to +3, the historical digital quantization value is +6, the phase deviation change is 3-6=-3; the proportional adjustment component is 3×0.5=1.5, the integral adjustment component is -3×0.125=-0.375; the deviation is 1.5-0.375=1.125, rounded to 1 step unit, and adjusted forward by 1 clock cycle.

[0260] Fourth control cycle: The digital quantization value drops to +1, the historical digital quantization value is +3, the phase deviation change is 1-3=-2; the proportional adjustment component is 1×0.5=0.5, the integral adjustment component is -2×0.125=-0.25; the deviation is 0.5-0.25=0.25, rounded to 0 step units, and phase adjustment is not performed.

[0261] It should be further explained that the update logic of the PID trigger enable flag in this embodiment is limited as follows: in the 0th clock cycle of each control cycle, the trigger enable management unit reads the digital quantization value of the previous control cycle and compares its absolute value with the preset locking threshold 2; if it is less than 2, the PID trigger enable flag is updated to logic high level '1'; if it is greater than or equal to 2, it is kept at logic low level '0'.

[0262] In the 0th clock cycle of the 5th control cycle, the trigger enable management unit reads the digital quantization value of the 4th control cycle +1. Its absolute value of 1 is less than the preset lockout threshold 2. Therefore, the PID trigger enable flag is updated from logic low level '0' to logic high level '1', allowing the PID calculation module to respond to the lockout edge of the calibration trigger signal.

[0263] When the absolute value of the digital quantization value for five consecutive control cycles is less than the preset convergence threshold by one clock cycle, the lock status flag is valid, and the lock establishment is officially completed. In this example, the digital quantization values ​​for control cycles 4 to 8 are +1, +0.8, +0.9, +0.7, and +0.8, respectively, all less than 1. Therefore, in the last clock cycle of the 8th control cycle, the lock status flag is '1'. The total time from initial adjustment to lock establishment is 8 control cycles, corresponding to 80 milliseconds. If a channel fails to lock within 50 consecutive control cycles (500 milliseconds), the system reports a lock timeout fault.

[0264] IV. The dynamic parameter adjustment stage, specifically:

[0265] During the phase-locking establishment process, the dynamic parameter adjustment unit performs state determination in the 25th clock cycle of each control cycle, using M=3 consecutive control cycles as the detection window. The preset divergence judgment threshold is set to 3 clock cycles (30 nanoseconds), and the preset underadjustment judgment threshold is set to 0.5 clock cycles (5 nanoseconds). It should be further noted that the state determination logic of the dynamic parameter adjustment in this embodiment is limited to:

[0266] The oscillation state is determined as follows: three conditions are met simultaneously for three consecutive control cycles: ① The absolute value of the digital quantization value is greater than the absolute value of the historical digital quantization value (amplitude increases); ② The absolute value of the phase deviation change is greater than the preset divergence judgment threshold 3; ③ The sign of the phase deviation change changes alternately. All three conditions are indispensable.

[0267] The overdamped convergence state is determined as follows: two conditions are met simultaneously for three consecutive control cycles: ① The absolute value of the digital quantization value is less than the absolute value of the historical digital quantization value (amplitude decreases); ② The absolute value of the phase deviation change is less than the preset under-adjustment judgment threshold of 0.5 clock cycles.

[0268] The parameter update rules are as follows: when the system is determined to be in an oscillation state, the proportional coefficient and integral coefficient gradually change linearly to 0.5 times the initial value within 3 control cycles; when the system is determined to be in an overdamped convergence state, the integral coefficient gradually changes linearly to 1.5 times the initial value within 3 control cycles; when the system returns to a normal convergence state, the parameters gradually change back to the initial value within 3 control cycles.

[0269] As a specific example, in this embodiment:

[0270] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 5, 6, and 7 respectively, and the phase deviation changes are +1, +1, and +1 respectively, with no alternation of signs, the oscillation state determination condition is not met, and the state is determined to be divergent, thus parameter adjustment is not triggered.

[0271] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 2, -3, and 4 respectively, and the phase deviation changes are -5, +7, and -7 respectively, satisfying the conditions of increasing amplitude, an absolute value of phase deviation change greater than 3, and alternating signs, then it is determined to be an oscillation state. The linear gradual change process of the parameters is as follows: In the first control cycle, the proportional coefficient becomes 0.5 - 0.0833 = 0.4167, and the integral coefficient becomes 0.125 - 0.0208 = 0.1042; in the second control cycle, the proportional coefficient becomes 0.3333, and the integral coefficient becomes 0.0833; in the third control cycle, the proportional coefficient becomes 0.25, and the integral coefficient becomes 0.0625.

[0272] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 8, 6, and 5 respectively, and the phase deviation changes are -2, -1, and -1 respectively, and the absolute value of the phase deviation change is greater than 0.5, the overdamped convergence state judgment condition is not met.

[0273] If, within three consecutive control cycles, the absolute values ​​of the digital quantization values ​​are 4, 3.5, and 3.2 respectively, and the phase deviation changes are -0.3, -0.4, and -0.3 respectively, satisfying the conditions of decreasing amplitude and an absolute value of phase deviation change less than 0.5, it is determined to be an overdamped convergence state. The linear gradual change process of the integral coefficient is as follows: in the first control cycle, it becomes 0.125 + 0.0208 = 0.1458; in the second control cycle, it becomes 0.1667; and in the third control cycle, it becomes 0.1875.

[0274] When the absolute values ​​of the digital quantization values ​​are 3.2, 2.7, and 2.1 respectively over three consecutive control cycles, and the phase deviation changes are -0.5, -0.6, and -0.6 respectively, satisfying the condition that the amplitude decreases and the absolute value of the phase deviation change is between 0.5 and 3, it is determined to be a normal convergence state. The parameters gradually return to the initial values ​​of 0.5 and 0.125 linearly over the three control cycles.

[0275] V. Synchronization phase after locking, specifically:

[0276] After the lock is established, the calibration trigger signals of all eight motor control channels are locked to the rising edge of the same global reference clock signal, and the start edge of the operation of each PID calculation module is forcibly aligned with the same reference edge. The PID calculation module is implemented with pure hardware logic, using a 16-bit Q12 fixed-point arithmetic format, with a fixed operation period of 18 100MHz global reference clock cycles (180 nanoseconds), and no software scheduling delay.

[0277] The 10-bit counter built into the synchronous output control unit is set to N=20. This value is based on the maximum execution time of PID, which is 18 clock cycles plus a margin of 2 cycles, to ensure that the drive signals of all channels have been updated. It should be further noted that the synchronous output control logic in this embodiment is limited as follows: when the PID calculation start edge arrives, the counter is synchronously cleared and starts counting; when the count reaches 20, a global latch signal with a width of 1 clock cycle is generated at the rising edge of the 20th global reference clock; the drive signal latches of all channels (using the FPGA's internal FDCE primitive) simultaneously latch their respective drive signals at the rising edge of this latch signal; the output of the latches is updated to the FPGA's IO pins at the next clock edge of the latch signal.

[0278] The delay time from the completion of the PID calculation to the output of the drive signal is 200 nanoseconds (20 clock cycles × 10 nanoseconds) across all channels, and the delay difference between channels is no greater than one global reference clock cycle (10 nanoseconds). The drive signal generation unit converts the 16-bit motor control quantity output by the PID calculation module into a pulse width modulation signal with a 20kHz carrier frequency. It is generated using a center-aligned method, with a triangular wave carrier, a duty cycle resolution of 16 bits, and a duty cycle adjustment step size of approximately 0.0015%.

[0279] Taking a certain control cycle as an example, the motor control quantity of the first channel is 32768, corresponding to a PWM signal with a 50% duty cycle; the motor control quantity of the second channel is 16384, corresponding to a PWM signal with a 25% duty cycle; the output timing deviation of the two PWM signals is no more than 10 nanoseconds, ensuring that the speed synchronization error of the two motors is controlled within 0.01%, meeting the preset synchronization accuracy requirements.

[0280] VI. Phase drift compensation stage, specifically:

[0281] After the lockout is established, the drift compensation unit acquires the current sampled value of the digital quantization value of this channel every preset drift detection cycle, i.e., 1000 control cycles (10 milliseconds × 1000 = 10 seconds). It should be further noted that the drift detection and compensation logic in this embodiment is limited to:

[0282] Drift detection is specifically performed as follows: when the lock status flag is set to '1', the 16-bit drift detection counter is synchronously cleared and starts counting; when the count reaches 1000 control cycles, a sampling is triggered, and the sampled value is the digital quantization value calculated in the current control cycle; if the absolute value of three consecutive sampled values ​​is greater than the preset drift warning threshold 1 and less than the preset lock threshold 2, a phase drift is determined to have occurred, and a drift compensation operation is triggered.

[0283] Drift compensation is specifically as follows: the phase compensation step is fixed at 0.2 clock cycles (2 nanoseconds), which is implemented through the phase offset function of the MMCM primitive inside the FPGA. The phase offset resolution is not less than 0.1 clock cycles. Each compensation operation only performs one step adjustment. The phase offset value is written to the configuration register of the MMCM through the AXI-Lite bus, and the write delay is not greater than 10 clock cycles. After the adjustment is completed, wait for 2 control cycles for the phase adjustment to take effect before the next sampling judgment is performed.

[0284] The compensation is terminated when the absolute value of two consecutive sampled values ​​is less than the preset drift warning threshold 1. The drift compensation is then determined to be complete and the compensation operation is stopped.

[0285] As a specific example, in this embodiment, after the lock is established, the first channel:

[0286] 1000th control cycle: Sample value is +1.2, absolute value is greater than 1;

[0287] 2000th control cycle: Sample value is +1.3, absolute value is greater than 1;

[0288] 3000th control cycle: Sample value is +1.4, absolute value is greater than 1;

[0289] If three consecutive sampled values ​​meet the drift detection criteria, a drift compensation operation is triggered. The positive sign of the sampled value indicates a phase lag in the trigger signal, which is adjusted forward by 0.2 clock cycles each time.

[0290] After the 3000th control cycle ends: the first compensation is performed, and the MMCM phase offset value increases by 0.2 clock cycles;

[0291] 4000th control cycle: Sample value is +1.0, absolute value is equal to 1;

[0292] After the 4000th control cycle ends: the second compensation is performed, and the MMCM phase offset value is increased by 0.2 clock cycles;

[0293] 5000th control cycle: Sample value is +0.8, absolute value is less than 1;

[0294] 6000th control cycle: Sample value is +0.7, absolute value is less than 1;

[0295] If two consecutive sampled values ​​are both less than the preset drift warning threshold of 1, the drift compensation is deemed complete, and the compensation operation is stopped. The entire drift compensation process is completed within 40 seconds, during which the lockout status flag remains at '1', the PID calculation is executed normally, and the motor operation is unaffected.

[0296] VII. Anti-interference and security protection phase, specifically:

[0297] During system operation, if external electromagnetic interference causes glitches in the calibration trigger signal, the edge discrimination unit immediately activates the anti-interference mechanism. It should be further noted that the edge discrimination logic in this embodiment is limited to:

[0298] Edge detection employs a two-stage synchronous flip-flop structure. Both the first and second stage flip-flops utilize the FPGA's internal FDCE primitive, sampling and calibrating the trigger signal at the rising edge of each global reference clock.

[0299] When the second stage output is low and the first stage output is high, it is determined that a rising edge has arrived, and a filter timing window with a duration of K=4 clock cycles (40 nanoseconds) is immediately started.

[0300] The calibration trigger signal is sampled at the 1st, 2nd, 3rd and 4th rising edges of the global reference clock within the filtering window, and the number of high-level samplings is counted as a stable count value.

[0301] If the stable count value is greater than or equal to the preset stable count threshold of 3, it is determined to be a true locking edge, and a trigger enable signal with a width of 1 clock cycle is generated at the first rising edge of the global reference clock after the window ends; if the stable count value is less than 3, it is determined to be an interference glitch, the edge is discarded, and no trigger enable signal is generated.

[0302] Taking a certain interference event as an example, the edge discrimination unit detects an interference pulse with a duration of 20 nanoseconds and starts the filtering timing window. If the four sampling results within the window are high, low, low, low in sequence, and the stable count value is 1, which is less than the threshold of 3, it is judged as an interference glitch, and no trigger enable signal is generated, and the PID calculation is not executed. If the four sampling results are high, low, high, high in sequence, and the stable count value is 3, which is greater than or equal to the threshold of 3, it is judged as a true locked edge, and a trigger enable signal is generated to trigger the PID calculation.

[0303] If the interference intensity is large enough to cause the digital quantization value to jump instantaneously, for example, the digital quantization value of the first channel jumps from +1 in the locked state to +5, the trigger enable management unit detects that the absolute value of the digital quantization value 5 is greater than or equal to the preset lockout threshold 2 in the 0th clock cycle of the current control cycle. It immediately updates the PID trigger enable flag from logic high level '1' to logic low level '0', and in the same clock cycle, it forcibly switches the input of the drive module to the preset safety control quantity 0x0000, so that the motor output of the first channel stops running with zero torque.

[0304] It should be further noted that the security protection classification and recovery logic in this embodiment are limited to:

[0305] Level 1 safety status: The absolute value of the digital quantization value is ≥2 and <5, the output torque is zero and the vehicle stops freely, and the PID trigger enable flag is '0';

[0306] Level 2 safety status: The absolute value of the digital quantization value is ≥5. The output braking torque quickly brakes and triggers an emergency stop signal, directly cutting off the IGBT drive power supply. Manual reset is required to restore the system.

[0307] Level 1 safety recovery mechanism: The absolute value of the digital quantization value must be less than the recovery threshold (lock threshold - hysteresis width = 2 - 0.5 = 1.5) for 3 consecutive control cycles before the PID trigger enable flag can be restored to '1', avoiding frequent switching at the threshold boundary.

[0308] In this example, the digital quantization value jumps to +5, entering a level two safety state, triggering an emergency stop signal. The motor brakes rapidly and the drive power is cut off. After the interference is eliminated, the digital quantization value gradually drops back to +1.4, and remains below 1.5 for three consecutive control cycles. After manual reset by the operator, the system re-enters phase adjustment state. Once phase lock is re-established, the motor resumes normal operation. This safety protection mechanism has a response time of no more than one control cycle, or 10 milliseconds, and can complete the safety state switch before abnormal motor movement occurs, ensuring the safety of equipment and personnel.

[0309] Example 4

[0310] Please see Figure 3 Another embodiment of the present invention provides a multi-motor global clock synchronization method based on a phase-locked loop, comprising:

[0311] S1. Generate a global reference clock signal in a preset frequency band;

[0312] S2. For each motor control channel, execute:

[0313] S21. Receive a trigger feedback signal that represents the current phase of the channel trigger signal;

[0314] S22. Perform phase detection between the trigger feedback signal and the global reference clock signal, detect the phase difference between the two, and output a deviation amount that is proportional to the phase difference;

[0315] S23. In each control cycle, the phase difference is compared with the preset locking threshold;

[0316] When the phase difference is greater than or equal to the preset locking threshold, the trigger phase adjustment module maintains the phase adjustment state and continues to adjust the phase of the trigger signal of this channel in steps according to the deviation of the current control cycle in the direction of reducing the absolute value of the phase difference. The phase difference still exists between the edge of the output calibration trigger signal and the reference edge of the global reference clock signal. The PID calculation module is in the disabled trigger state and does not respond to the edge of the calibration trigger signal.

[0317] When the phase difference is less than the preset locking threshold, the trigger phase adjustment module switches from the phase adjustment state to the locking state, stops the phase step adjustment, and outputs a calibration trigger signal. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal. The PID calculation module is in the trigger-enabled state and responds to the locking edge of the calibration trigger signal to perform proportional-integral-derivative (PID) operations. The trigger phase adjustment module compares and judges the phase difference once in each control cycle and determines whether to maintain the state or switch the state in the next control cycle based on the comparison result.

[0318] S24. Only when the locking edge of the calibration trigger signal arrives is the proportional-integral-derivative operation triggered to generate the motor control quantity.

[0319] S3. Drive the corresponding motor according to the motor control quantity; wherein, the phase adjustment of the trigger signal of all channels is locked with the same global reference clock signal, so that the starting edge of each proportional-integral-derivative operation is forcibly aligned with the same reference edge, and the timing deviation of the multi-channel motor control cycle is not greater than the preset synchronization accuracy threshold.

[0320] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the claims. All of these variations are within the protection scope of the present invention.

Claims

1. A multi-motor global clock synchronization system based on a phase-locked loop, characterized in that, include: The clock generation module is configured to generate a global reference clock signal in a preset frequency band; N motor control channels, each channel controls one motor, and each channel includes: The phase detection module receives the global reference clock signal at its first input terminal and a trigger feedback signal representing the current phase of the trigger signal of this channel at its second input terminal. It is configured to detect the phase difference between the trigger feedback signal and the global reference clock signal and output a deviation amount proportional to the phase difference. The trigger phase adjustment module is configured to adjust the phase of the trigger signal of this channel in the direction of reducing the phase difference according to the deviation amount, and output a calibration trigger signal when the phase difference is reduced to within a preset locking threshold. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal. The PID calculation module is configured to be triggered only when the locking edge of the calibration trigger signal arrives to perform proportional-integral-derivative operations and output motor control quantities. The drive module is configured to drive the corresponding motor according to the motor control quantity; wherein, the trigger phase adjustment module of all channels uses the global reference clock signal as a common phase-locked reference, so that the operation start edge of each PID calculation module is aligned to the same reference edge of the global reference clock signal, thereby limiting the timing deviation between the control cycles of multiple motors to within a preset synchronization accuracy threshold.

2. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 1, characterized in that, The output deviation is proportional to the phase difference, including: The time interval between the edge of the trigger feedback signal and the reference edge of the global reference clock signal is measured, and a digital quantization value that is linearly proportional to the time interval is output; wherein, the digital quantization value is equal to the time interval divided by the period of the global reference clock signal, and the unit resolution of the digital quantization value is one clock cycle of the global reference clock signal; The digital quantization value calculated in the current control cycle is compared with the historical digital quantization value in the previous control cycle to obtain the phase deviation change. The proportional adjustment component is obtained by multiplying the digital quantization value by a preset proportional coefficient, and the integral adjustment component is obtained by multiplying the phase deviation change by a preset integral coefficient. The proportional adjustment component and the integral adjustment component are then superimposed to generate the deviation.

3. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 2, characterized in that, The preset proportional coefficient and the preset integral coefficient satisfy the following conditions: the product of the preset proportional coefficient and the digital quantization value of the current control cycle constitutes a proportional adjustment component, and the product of the preset integral coefficient and the phase deviation change of the current control cycle constitutes an integral adjustment component; the phase adjustment step size generated by the phase adjustment module driven by the deviation is equal to the sum of the proportional adjustment component and the integral adjustment component; wherein, the value of the preset proportional coefficient is such that when the digital quantization value is a first value, the single phase adjustment step size is not greater than a first preset step size threshold; the value of the preset integral coefficient is such that when the phase deviation change is a second value, the single phase adjustment step size is not greater than a second preset step size threshold; and when the digital quantization value decreases from the first value of the current control cycle to the second value of the next control cycle, the corresponding phase adjustment step size decreases from the first step size value to the second step size value; when the digital quantization value continues to decrease to a third value and the third value is less than a preset convergence judgment threshold, the phase difference is determined to have converged to within the preset locking threshold, and a locking state is established.

4. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 3, characterized in that, The trigger phase adjustment module includes a dynamic parameter adjustment unit, which is configured to: Within M consecutive control cycles, the digital quantization value of the current control cycle is compared with the historical digital quantization value of the previous control cycle to obtain the phase deviation change in the current control cycle. When the first, second, and third conditions are met simultaneously, it is determined that the closed-loop regulation is in an oscillation state. The preset proportional coefficient of the next control cycle is updated to the first attenuation proportional coefficient, and the preset integral coefficient of the next control cycle is updated to the first attenuation integral coefficient. The first condition is that the absolute value of the digital quantization value is greater than the absolute value of the historical digital quantization value. The second condition is that the absolute value of the phase deviation change is greater than the preset divergence judgment threshold. The third condition is that the phase deviation change of the current control cycle has the opposite sign to the phase deviation change of the previous control cycle.

5. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 4, characterized in that, The dynamic parameter adjustment unit is further configured to: When both the fourth and fifth conditions are met, the closed-loop regulation is determined to be in an overdamped convergence state, and the preset integral coefficient of the next control cycle is updated to the first enhanced integral coefficient. The fourth condition is that the absolute value of the digital quantization value is less than the absolute value of the historical digital quantization value, and the fifth condition is that the absolute value of the phase deviation change is less than the preset under-adjustment judgment threshold. Wherein, the first attenuation ratio coefficient is less than the preset ratio coefficient, the first attenuation integral coefficient is less than the preset integral coefficient, the first enhancement integral coefficient is greater than the preset integral coefficient, and the preset divergence judgment threshold is greater than the preset undertuning judgment threshold.

6. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 5, characterized in that, The trigger phase adjustment module further includes a drift compensation unit, which is configured as follows: After the locked state is established, the current sampled value of the digital quantization value of this channel is obtained every preset drift detection cycle; Compare the absolute value of the current sampled value with a preset drift warning threshold; When the absolute value of the current sampled value is greater than the preset drift warning threshold and less than the preset lock threshold, it is determined that the lock edge of the trigger signal of this channel has a phase drift relative to the reference edge of the global reference clock signal, and a drift compensation operation is triggered.

7. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 6, characterized in that, The drift compensation operation is as follows: based on the sign and amplitude of the current sampled value, a phase compensation step is generated, and the phase of the trigger signal of this channel is adjusted in steps along the direction of decreasing the absolute value of the current sampled value until the absolute value of the current sampled value falls back below the preset drift warning threshold; wherein, the preset drift warning threshold is less than the preset locking threshold, the preset drift detection period is greater than the control period, and the phase compensation step is less than the maximum phase adjustment step size of the trigger phase adjustment module before the locking state is established.

8. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 7, characterized in that, The PID calculation module includes an edge discrimination unit, which is configured as follows: The edge of the calibration trigger signal is detected. When the calibration trigger signal changes from the first level state to the second level state, a filter timing window with a preset filter duration is triggered. Within the filtering timing window, the global reference clock signal is used as the sampling clock to sample the level state of the calibration trigger signal multiple times to obtain multiple sampled level values; The plurality of sampled level values ​​are compared one by one with the second level state, and the number of sampled level values ​​that match the second level state is counted and used as a stable count value.

9. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 8, characterized in that, The edge discrimination unit is further configured to: The stable count value is compared with a preset stable count threshold. When the stable count value is greater than or equal to the preset stable count threshold, the current edge is determined to be a true locked edge. A trigger enable signal is generated and sent to the PID calculation module to trigger the execution of proportional-integral-derivative (PID) calculation. When the stable count value is less than the preset stable count threshold, the current edge is determined to be an interference glitch, the current edge is discarded, and the trigger enable signal is not generated; wherein, the preset filtering duration is K times the period of the global reference clock signal, the preset stable count threshold is less than or equal to K, and K is a positive integer.

10. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 9, characterized in that, The PID calculation module further includes a trigger enable management unit, which is configured as follows: After the power-on reset signal is released, the PID trigger enable flag of this channel is set to the first logic state. The first logic state indicates that the PID calculation module is prohibited from responding to any edge of the calibration trigger signal. Within each control cycle, the digital quantization value of the current control cycle output by the phase detection module is received, and the absolute value of the digital quantization value is compared with the preset locking threshold.

11. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 10, characterized in that, The trigger enable management unit is also configured to: When the absolute value of the digital quantization value is less than the preset locking threshold, the PID trigger enable flag is updated from the first logic state to the second logic state. The second logic state indicates that the PID calculation module is allowed to respond to the locking edge of the calibration trigger signal. When the absolute value of the digital quantization value is greater than or equal to the preset locking threshold, the PID trigger enable flag is kept in the first logic state, and a preset safety control value is output to the drive module. The preset safety control value is a fixed value stored in the register in advance, and the fixed value makes the corresponding motor output zero torque.

12. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 11, characterized in that, The phase detection module further includes a path delay calibration unit, which is configured to: During the system initialization phase and when the trigger signals of each channel are not enabled, a calibration pulse signal is injected into the starting point of the trigger feedback signal transmission path of this channel. Using the global reference clock signal as the timing reference, the number of clock cycles that the calibration pulse signal takes from the injection time to the second input terminal of the phase detection module is measured and used as the path delay count value of this channel.

13. The multi-motor global clock synchronization system based on a phase-locked loop as described in claim 12, characterized in that, The path delay calibration unit is also configured to: Write the path delay count value of this channel into the path delay compensation register of this channel; After the system enters the normal operation phase, in each control cycle, the path delay count value in the path delay compensation register of this channel is read, and the digital quantization value is updated to: the difference obtained by subtracting the path delay count value from the original measurement count value, wherein the original measurement count value is the count value obtained by counting the time interval between the edge of the trigger feedback signal and the reference edge of the global reference clock signal with the period of the global reference clock signal as the quantization unit.

14. A multi-motor global clock synchronization method based on a phase-locked loop, implemented based on any one of claims 1-13, characterized in that, include: Generate a global reference clock signal in a preset frequency band; For each motor control channel, execute: Receive a trigger feedback signal that represents the current phase of the channel trigger signal; The trigger feedback signal and the global reference clock signal are phase-detected to determine the phase difference between them, and a deviation amount proportional to the phase difference is output. Based on the deviation, the phase of the channel trigger signal is adjusted in the direction of reducing the phase difference. When the phase difference is less than a preset locking threshold, a calibration trigger signal is output. The calibration trigger signal has a locking edge that is locked to the reference edge of the global reference clock signal. The proportional-integral-derivative (PID) operation is triggered only when the locking edge of the calibration trigger signal arrives, generating a motor control quantity. The corresponding motor is driven according to the motor control quantity; wherein, the phase adjustment of the trigger signal of all channels is locked with the same global reference clock signal, so that the starting edge of each proportional-integral-derivative operation is forcibly aligned with the same reference edge, and the timing deviation of the multi-channel motor control cycle is not greater than the preset synchronization accuracy threshold.

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