High energy efficiency multi-mode clock data recovery circuit
By designing a high-efficiency multi-mode clock data recovery circuit, the problem that existing clock data recovery circuits are difficult to adapt to different data rates and power consumption optimizations is solved, achieving improved energy efficiency and enhanced flexibility in low-noise scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2026-04-13
- Publication Date
- 2026-07-10
AI Technical Summary
Existing clock data recovery circuits are difficult to dynamically adapt to different data rates, have poor flexibility, and cannot optimize power consumption in low-noise scenarios, resulting in low energy efficiency.
Design a high-efficiency multi-mode clock data recovery circuit, including a multi-mode sampling module, a deserialization module, a multi-mode phase detection control module, a phase interpolation module, a parallel data output module, and a CDR mode control module. The multi-mode sampling module dynamically adapts to different rate modes, and the multi-mode phase detection control module reduces the system's requirements on the PLL.
It improves the energy efficiency ratio in low-noise scenarios, enhances the system's flexibility and noise tolerance, and enables high-bandwidth applications.
Smart Images
Figure CN122371967A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a high-efficiency multi-mode clock data recovery circuit. Background Technology
[0002] With the widespread adoption of wireless communication devices and smart wireless terminals, and the rise of technologies such as artificial intelligence and big data, high-speed serial links (SerDes), as a key technology in high-speed data transmission, significantly impact the overall performance of computing systems. During high-speed data transmission, noise can cause delays or amplitude distortion. Therefore, at the receiving end, data relocation, or clock data recovery, is necessary. The clock data recovery circuit is a critical module in the SerDes system, and its performance largely determines key indicators such as the bit error rate.
[0003] Currently, clock data recovery circuits are typically designed for a single communication standard or a fixed data rate. While this can meet the basic requirements of specific scenarios, it is difficult to dynamically adapt to different data rates, resulting in poor flexibility. At the same time, under fixed bandwidth, traditional clock data recovery circuits cannot dynamically adjust power consumption according to channel conditions (such as jitter and noise), causing them to operate at high power consumption even in low-noise scenarios, making it difficult to optimize energy efficiency. Summary of the Invention
[0004] The purpose of this invention is to provide a high-efficiency multi-mode clock data recovery circuit to solve the problems in the background art.
[0005] To solve the above-mentioned technical problems, the present invention provides a high-efficiency multi-mode clock data recovery circuit, including: a multi-mode sampling module, a deserialization module, a multi-mode phase detection control module, a phase interpolation module, a parallel data output module, and a CDR mode control module; The multimode sampling module is connected to the phase interpolation module and the deserialization module, and is used to sample the differential signal from the equalizer output and generate a signal, which is a data signal and an edge signal, or a data signal and an error signal. The deserialization module is connected to the multi-mode sampling module, the parallel data output module, and the multi-mode phase detection control module. It reduces the speed of the signal output by the multi-mode sampling module and outputs it to the subsequent digital circuits to compensate for the speed difference between analog circuits operating at higher frequencies and digital circuits operating at lower frequencies. The multi-mode phase detection control module is connected to the deserialization module and the phase interpolation module. It performs phase detection based on the input signal and generates a control word for adjusting the output clock phase of the phase interpolation module. The phase interpolation module is connected to the multi-mode phase detection control module and the multi-mode sampling module, and is used to adjust the phase of the PLL output clock to generate the sampling clock of the multi-mode sampling module, and to sample the data and edges of the input signal respectively. The parallel data output module is connected to the deserialization module and is used to output the final parallel output data of the physical layer, as well as a clock signal with the same frequency as the parallel output data. The CDR mode control module is connected to the multi-mode sampling module, the deserialization module, the multi-mode phase detection control module, the phase interpolation module, and the parallel data output module, and is used to control and select the working mode of the clock data recovery circuit.
[0006] In one embodiment, the multi-mode sampling module includes a first sampling module, a second sampling module, a third sampling module, and a fourth sampling module; The first sampling module samples the input data using the first clock signal CK0, the second sampling module samples the input data using the second clock signal CK90, the third sampling module samples the input data using the third clock signal CK180, and the fourth sampling module samples the input data using the fourth clock signal CK270.
[0007] In one embodiment, the operating modes of the multi-mode sampling module include full-rate mode, half-rate mode, and 1 / 4-rate mode; In the full-rate mode, the first sampling module and the third sampling module operate normally. The first sampling module outputs a data signal, and the third sampling module outputs an edge signal. The first sampling module includes a sampler 1 and a decision unit 1. The input of sampler 1 is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The input of decision unit 1 is connected to the output of sampler 1, and decision unit 1 outputs the sampling result pre_data at the intermediate moment of the data. The third sampling module includes a sampler 3 and a decision unit 3. The input of sampler 3 is connected to the differential signal output by the equalizer and the third clock signal CK180 output by the phase interpolation module. The input of decision unit 3 is connected to the output of sampler 3, and decision unit 3 outputs the sampling result pre_edge at the edge of the data. In the half-rate mode, the first, second, third, and fourth sampling modules operate normally. The first and third sampling modules output data signals, while the second and fourth sampling modules output edge signals. The first sampling module includes a sampler and a decision unit. The input of sampler is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The input of decision unit is connected to the output of sampler, and decision unit outputs the sampling result pre_data1 at the intermediate moment of the data. The second sampling module includes a sampler and a decision unit. The input of sampler is connected to the differential signal output by the equalizer and the second clock signal CK90 output by the phase interpolation module. The input of Decision 2 is connected to the output of Sampler 2, and Decision 2 outputs the sampling result pre_edge1 of the data edge; The third sampling module includes Sampler 3 and Decision 3. The input of Sampler 3 is connected to the differential signal output by the equalizer and the third clock signal CK180 output by the phase interpolation module. The input of Decision 3 is connected to the output of Sampler 3, and Decision 3 outputs the sampling result pre_data2 of the data midpoint; The fourth sampling module includes Sampler 4 and Decision 4. The input of Sampler 4 is connected to the differential signal output by the equalizer and the fourth clock signal CK270 output by the phase interpolation module. The input of Decision 4 is connected to the output of Sampler 4, and Decision 4 outputs the sampling result pre_edge2 of the data edge; In the 1 / 4 rate mode, the first, second, third, and fourth sampling modules operate normally, and all of them output data signals and error signals for phase detection. The first sampling module includes sampler one, threshold decision group one, and threshold decision group five. The input of sampler one is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The inputs of threshold decision group one and threshold decision group five are connected to the output of sampler one and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group one output data signal pre_data1, with threshold decision group five output error signal pre_error1 for phase detection; The second sampling module includes sampler two, threshold decision group two, and threshold decision group six. The input of sampler two is connected to the differential signal output from the equalizer and the second clock signal CK90 output from the phase interpolation module. The inputs of threshold decision group two and threshold decision group six are connected to the output of sampler two and the negative reference signal V. REF - and the positive reference signal V REF+, with threshold decision group two output data signal pre_data2, with threshold decision group six output error signal pre_error2 for phase detection; The third sampling module includes sampler three, threshold decision group three, and threshold decision group seven. The input of sampler three is connected to the differential signal output from the equalizer and the third clock signal CK180 output from the phase interpolation module. The inputs of threshold decision group three and threshold decision group seven are connected to the output of sampler three and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group three output data signal pre_data3, with threshold decision group seven output error signal pre_error3 for phase detection; The fourth sampling module includes sampler four, threshold decision group four, and threshold decision group eight. The input of sampler four is connected to the differential signal output from the equalizer and the fourth clock signal CK270 output from the phase interpolation module. The inputs of threshold decision group four and threshold decision group eight are connected to the output of sampler four and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group four output data signal pre_data4, with threshold decision group four output error signal pre_error4 used for phase detection.
[0008] In one implementation, each threshold decision group has the same structure, including a first threshold decision group and a second threshold decision group. The input terminals of both threshold decision groups are connected to differential input data and positive and negative reference signals VREF+ and VREF-. The first threshold decision group compares the input data with the difference between the positive and negative reference signals VREF+ and VREF- to obtain buffered decision data 1. The second threshold decision group compares the input data with the difference between the negative and positive reference signals VREF- and VREF+ to obtain buffered decision data 2. When the decision result of the previous bit of the input data is 1, threshold decision group one, threshold decision group two, threshold decision group three, and threshold decision group four select buffered decision data 1 as the final decision result; when the decision result of the previous bit of the input data is 0, buffered decision data 2 is selected as the final decision result. Threshold decision group one, threshold decision group two, threshold decision group three, and threshold decision group four implement the function of a predictive decision feedback equalizer. Conversely, when the decision result of the previous bit of the input data is 1, the gated buffer decision data 2 of threshold decision group five, threshold decision group six, threshold decision group seven and threshold decision group eight is used as the final output result; when the decision result of the previous bit of the input data is 0, the gated buffer decision data 1 is used as the final output result.
[0009] In one embodiment, the multimode phase detection control module includes a phase detection module and a phase control module; the input terminal of the phase detection module is connected to the output terminal of the deserialization module, the output terminal of the phase detection module is connected to the input terminal of the phase control module, and the output terminal of the phase control module is connected to the input terminal of the phase interpolation module.
[0010] In one embodiment, the phase detection module includes: The delay unit, connected to the deserialization module, is used to delay the input data signal, edge signal, and error signal; A lead / lag decision unit is connected to the deserialization module and the delay unit to determine the lead / lag state of the input signal. A phase integrator, connected to the bit lead / lag decision unit, is used to accumulate the result of the bit lead / lag decision unit.
[0011] In one embodiment, the phase control module includes: Most of the voting units are connected to the phase detection module and are used to perform voting filtering on the phase detection control word to determine the effective phase adjustment direction and avoid misadjustment caused by transient noise interference. The phase controller, connected to the majority voter and the phase interpolation module, drives the phase interpolator to adjust the phase delay of the sampling clock according to the filtered phase detection control word.
[0012] In one implementation, the CDR mode control module outputs control signals for full-rate mode, half-rate mode, and 1 / 4-rate mode respectively, based on the mode selection signal input from the external SPI.
[0013] This invention provides a high-efficiency multi-mode clock data recovery circuit. Through the multi-mode sampling module, it can dynamically adapt to different rate modes, improve the energy efficiency ratio in low-noise scenarios, enhance flexibility, and realize high-bandwidth applications. Through the multi-mode phase detection control module, it can effectively reduce the system's requirements for PLL and improve noise tolerance. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the clock data recovery circuit in an embodiment of the present invention; Figure 2 This is a schematic diagram of the full-rate mode sampling module in an embodiment of the present invention; Figure 3 This is a schematic diagram of the half-rate mode sampling module in an embodiment of the present invention; Figure 4 This is a schematic diagram of the 1 / 4 rate mode sampling module in an embodiment of the present invention; Figure 5This is a schematic diagram of the phase detection control module in an embodiment of the present invention. Detailed Implementation
[0015] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the high-efficiency multi-mode clock data recovery circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0016] This invention provides a high-efficiency multi-mode clock data recovery circuit, the architecture of which is as follows: Figure 1 As shown, it includes: The multimode sampling module, connected to the phase interpolation module and the deserialization module, is used to sample the differential signals INP and INN from the output of the equalizer to generate the data signal pre_data and the edge signal pre_edge (error signal pre_error). The deserialization module, connected to the multi-mode sampling module, the parallel data output module, and the multi-mode phase detection control module, is used to reduce the data signal pre_data and the edge signal pre_edge (error signal pre_error) output by the multi-mode sampling module to the data signal data and the edge signal edge (error signal error), and then output them to the subsequent digital circuits (parallel data output module and multi-mode phase detection control module), thereby compensating for the speed difference between analog circuits operating at higher frequencies and digital circuits operating at lower frequencies. The multi-mode phase detection control module is connected to the deserialization module and the phase interpolation module. It performs phase detection based on the input data signal (data) and the edge signal (error signal), thereby generating a control word PI_code for adjusting the output clock phase of the phase interpolation module.
[0017] The phase interpolation module, connected to the multi-mode phase detection control module and the multi-mode sampling module, is used to adjust the phase of the PLL output clock and generate the sampling clocks CK0 / 180 and CK90 / 270 of the multi-mode sampling module, which sample the data and edges of the input signal, respectively. The parallel data output module, connected to the deserialization module, is used to output the final parallel output data dataout of the physical layer, as well as the clock signal phy_clk with the same frequency as the parallel output data; The CDR mode control module is connected to the multi-mode sampling module, deserialization module, multi-mode phase detection control module, phase interpolation module, and parallel data output module, and is used to control and select the operating mode of the clock data recovery circuit.
[0018] like Figure 1As shown, the multi-mode sampling module includes a first sampling module (sampling module 1), a second sampling module (sampling module 2), a third sampling module (sampling module 3), and a fourth sampling module (sampling module 4). The first sampling module samples the input data using the first clock signal CK0, the second sampling module samples the input data using the second clock signal CK90, the third sampling module samples the input data using the third clock signal CK180, and the fourth sampling module samples the input data using the fourth clock signal CK270.
[0019] The multi-mode sampling module operates in three modes: full-rate mode, half-rate mode, and 1 / 4-rate mode. In full-rate mode, such as... Figure 2 As shown, only the first and third sampling modules in the multi-mode sampling module are working normally. More specifically, the first sampling module includes sampler 1 and decision unit 1. The input of sampler 1 is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The input of decision unit 1 is connected to the output of sampler 1, and decision unit 1 outputs the sampling result pre_data of the intermediate time of the data. The third sampling module includes sampler 3 and decision unit 3. The input of sampler 3 is connected to the differential signal output by the equalizer and the third clock signal CK180 output by the phase interpolation module. The input of decision unit 3 is connected to the output of sampler 3, and decision unit 3 outputs the sampling result pre_edge of the data edge.
[0020] In half-rate mode, such as Figure 3As shown, the first, second, third, and fourth sampling modules in the multi-mode sampling module operate normally. More specifically, the first sampling module includes sampler 1 and decision unit 1. The input of sampler 1 is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The input of decision unit 1 is connected to the output of sampler 1, and decision unit 1 outputs the sampling result pre_data1 at the intermediate time of the data. The second sampling module includes sampler 2 and decision unit 2. The input of sampler 2 is connected to the differential signal output by the equalizer and the second clock signal CK90 output by the phase interpolation module. The input of decision unit 2 is connected to the output of sampler 2, and decision unit 2 outputs the sampling result pre_data1 at the intermediate time of the data. The first sampling module outputs the sampling result pre_edge1 of the data edge; the second sampling module includes sampler 3 and decision unit 3. The input of sampler 3 is connected to the differential signal output by the equalizer and the third clock signal CK180 output by the phase interpolation module. The input of decision unit 3 is connected to the output of sampler 3. Decision unit 3 outputs the sampling result pre_data2 of the data midpoint; the third sampling module includes sampler 4 and decision unit 4. The input of sampler 4 is connected to the differential signal output by the equalizer and the fourth clock signal CK270 output by the phase interpolation module. The input of decision unit 4 is connected to the output of sampler 4. Decision unit 4 outputs the sampling result pre_edge2 of the data edge.
[0021] In 1 / 4 rate mode, such as Figure 4 As shown, the first, second, third, and fourth sampling modules in the multi-mode sampling module are operating normally. More specifically, the first sampling module includes sampler 1, threshold decision group 1, and threshold decision group 5. The input of sampler 1 is connected to the differential signal output from the equalizer and the first clock signal CK0 output from the phase interpolation module. The inputs of threshold decision group 1 and threshold decision group 5 are connected to the output of sampler 1 and the negative reference signal V. REF - and the positive reference signal V REF +, Threshold decision group 1 outputs data signal pre_data1, threshold decision group 5 outputs error signal pre_error1 for phase detection; The second sampling module includes sampler 2, threshold decision group 2, and threshold decision group 6. The input of sampler 2 is connected to the differential signal output from the equalizer and the second clock signal CK90 output from the phase interpolation module. The inputs of threshold decision group 2 and threshold decision group 6 are connected to the output of sampler 2 and the negative reference signal V. REF - and the positive reference signal V REF +, Threshold decision group 2 outputs data signal pre_data2, threshold decision group 6 outputs error signal pre_error2 for phase detection; The third sampling module includes sampler 3, threshold decision group 3, and threshold decision group 7. The input of sampler 3 is connected to the differential signal output from the equalizer and the third clock signal CK180 output from the phase interpolation module. The inputs of threshold decision group 3 and threshold decision group 7 are connected to the output of sampler 3 and the negative reference signal V. REF - and the positive reference signal V REF +, Threshold decision group 3 outputs data signal pre_data3, threshold decision group 7 outputs error signal pre_error3 for phase detection; The fourth sampling module includes sampler 4, threshold decision group 4, and threshold decision group 8. The input of sampler 4 is connected to the differential signal output from the equalizer and the fourth clock signal CK270 output from the phase interpolation module. The inputs of threshold decision group 4 and threshold decision group 8 are connected to the output of sampler 4 and the negative reference signal V. REF - and the positive reference signal V REF +, Threshold decision group 4 outputs data signal pre_data4, threshold decision group 8 outputs error signal pre_error4 for phase detection.
[0022] Each threshold decision group has the same structure, including a first threshold decision unit and a second threshold decision unit. The input terminals of both threshold decision units are connected to differential input data and positive and negative reference signals V. REF + and V REF - The first threshold decision unit compares the input data with the positive reference signal V. REF + and negative reference signal V REF The difference between - is compared to obtain buffered decision data 1. The second threshold decision unit compares the input data with the negative reference signal V. REF - and the positive reference signal V REF The difference between the input data and the buffer decision data is compared to obtain buffer decision data 2. When the decision result of the previous input data is 1, threshold decision group 1, threshold decision group 2, threshold decision group 3, and threshold decision group 4 select buffer decision data 1 as the final decision result; when the decision result of the previous input data is 0, buffer decision data 2 is selected as the final decision result. Threshold decision group 1, threshold decision group 2, threshold decision group 3, and threshold decision group 4 implement the function of predictive DFE (Decision Feedback Equalizer); conversely, when the decision result of the previous input data is 1, threshold decision group 5, threshold decision group 6, threshold decision group 7, and threshold decision group 8 select buffer decision data 2 as the final output result; when the decision result of the previous input data is 0, buffer decision data 1 is selected as the final output result.
[0023] The threshold decision unit in 1 / 4 rate mode shares a single decision unit structure with the decision units in full rate and half rate modes. Specifically, the first threshold decision unit in threshold decision unit groups 1, 2, 3, and 4 corresponds to decision unit 1, decision unit 2, decision unit 3, and decision unit 4 in full rate and half rate modes, respectively. In full rate and half rate modes, the CDR mode control module controls the positive reference signal V. REF + and negative reference signal V REF - When they are equal, the threshold of the threshold decision controller is zero, which is equivalent to making a decision on the differential input data.
[0024] like Figure 5 As shown, the multimode phase detection and control module includes a phase detection module and a phase control module. The input of the phase detection module is connected to the output of the deserialization module, the output of the phase detection module is connected to the input of the phase control module, and the output of the phase control module is connected to the input of the phase interpolation module.
[0025] The phase detection module includes a delay unit, a bit lead / lag decision unit, and a phase integrator. The delay unit is connected to the output of the deserialization module. In full-rate mode, the delay unit outputs the first data signal `data` and the first edge signal `edge` from the deserialization module to generate the delayed first data signal `data_d1` and the delayed first edge signal `edge_d1`. In half-rate mode, the delay unit outputs the first data signal `data1`, the second data signal `data2`, the first edge signal `edge1`, and the second edge signal `edge2` to generate the delayed first data signal `data1_d1`, the second data signal `data2_d1`, the first edge signal `edge1_d1`, and the second edge signal `edge2_d1`. In 1 / 4-rate mode, the delay unit outputs... The first data signal data1, the second data signal data2, the third data signal data3, the fourth data signal data4, the first error signal error1, the second error signal error2, the third error signal error3, and the fourth error signal error4 are used to generate the delayed first data signal data1_d1, the second data signal data2_d1, the third data signal data3_d1, the fourth data signal data4_d1, the first error signal error1_d1, the second error signal error2_d1, the third error signal error3_d1, and the fourth error signal error4_d1.
[0026] The bit-lead / lag decision unit is connected to the outputs of the deserialization module and the delay unit. In full-rate mode, the bit-lead / lag decision unit receives the first data signal `data` and the first edge signal `edge` output from the deserialization module and executes the Bang-Bang two-point phase detection algorithm. In half-rate mode, the bit-lead / lag decision unit receives the first data signal `data1`, the second data signal `data2`, the first edge signal `edge1`, and the second edge signal `edge2` output from the deserialization module, as well as the first data signal `data1_d1`, the second data signal `data2_d1`, the first edge signal `edge1_d1`, and the first edge signal `edge2_d1` output from the delay unit and executes the Bang-Bang three-point phase detection algorithm. In 1 / 4-rate mode, the bit-lead / lag decision unit receives the first data signal `data1`, the second data signal `data2`, the first edge signal `edge1`, and the second edge signal `edge2` output from the deserialization module and executes the Bang-Bang three-point phase detection algorithm. The data signals data1, data2, data3, data4, error1, error2, error3, and error4, and the delay outputs data1_d1, data2_d1, data3_d1, data4_d1, error1_d1, error2_d1, error3_d1, and error4_d1, are used to execute the Mueller-muller four-point phase detection algorithm.
[0027] The Bang-Bang two-point phase detection algorithm is based on the principle of binary phase detection. It performs an XOR operation on the single-point data signal (data) and the single-point edge signal (edge_d1), and generates a bit lead / lag indicator signal based on the result. When the current edge sample value leads the ideal edge sample value, the first logic state bit lead / lag indicator signal is output; when the current edge sample value lags the ideal edge sample value, the second logic state bit lead / lag indicator signal is output.
[0028] The Bang-Bang three-point phase detection algorithm is based on the principle of symmetrical window phase detection. It performs an AND operation on the single-point data signal data1 and the two-point edge signals edge1 (single-point edge signal edge1 and single-point edge signal edge1_d1), and an AND operation on the single-point data signal data2 and the two-point edge signals edge2 (single-point edge signal edge2 and single-point edge signal edge2_d1). Based on the operation results, it generates bit lead / lag indicator signals. When the current edge sample value leads the ideal edge sample value, it outputs the bit lead / lag indicator signal of the first logic state; when the current edge sample value lags the ideal edge sample value, it outputs the bit lead / lag indicator signal of the second logic state.
[0029] The Mueller-muller four-point phase detection algorithm is based on the minimum mean square error detection principle. It performs an AND operation on two-point data signals data1 (single-point data signal data1 and single-point data signal data1_d1) and two-point error signals error1 (single-point error signal error1 and single-point error signal error1_d1), an AND operation on two-point data signals data2 (single-point data signal data2 and single-point data signal data2_d1) and two-point error signals error2 (single-point error signal error2 and single-point error signal error2_d1), an AND operation on two-point data signals data3 (single-point data signal data3 and single-point data signal data3_d1) and two-point error signals error3 (single-point error signal error3 and single-point error signal error3_d1), and an AND operation on two-point data signals data4 (single-point data signal data4 and single-point data signal data4_d1) and two-point error signals error4 (single-point error signal error4 and single-point error signal error4_d1). When the current edge sample value leads the ideal edge sample value, the bit lead / lag indicator signal of the first logic state is output; when the current edge sample value lags the ideal edge sample value, the bit lead / lag indicator signal of the second logic state is output.
[0030] The phase integrator is connected to the bit lead / lag decision unit. Each clock cycle, the phase integrator receives bit lead / lag indication signals p0, p1, p2, ..., p in parallel. k-1 The k-way bit lead / lag indicator signals are summed with a sign, where the bit lead / lag indicator signal in the first logic state represents a positive weight and the bit lead / lag indicator signal in the second logic state represents a negative weight, to obtain the net phase error accumulation value PI_ctrl for the current clock cycle.
[0031] The phase control module includes a majority voter and a phase controller. The majority voter is connected to the phase integrator. Each clock cycle, the majority voter receives the accumulated net phase error from the phase integrator, iterates it against the historical accumulated value stored in the previous internal register, truncates the low-order bits below the effective precision threshold, and retains the required phase control word PI_acc. The phase controller receives the phase control word PI_acc from the majority voter, and performs binary-hot code compilation based on the phase control word and combinational logic circuitry to generate the control signal PI_code for the phase adjustment step size.
[0032] like Figure 1 As shown, the CDR mode control module outputs control signals for full-rate mode, half-rate mode, and 1 / 4-rate mode respectively based on the mode selection signal input from the external SPI.
[0033] In full-rate mode, only one phase interpolation module is enabled, outputting two-phase clocks CK0 and CK180. In the multi-mode sampling module, sampling module 1 and sampling module 3 are enabled. In decision group 1 and decision group 3, only the first threshold decision unit is enabled, and the reference signal V... REF + and negative reference signal V REF - Equal, CK0 samples the data at the middle moment, and CK180 samples the data at the edge. At this time, the phase detection module works in the Bang-Bang two-point phase detection mode.
[0034] In half-rate mode, both phase interpolation modules are enabled, outputting a four-phase clock CK0 / 90 / 180 / 270. All four sampling modules in the multi-mode sampling module are enabled. Only the first threshold-based decision maker in decision maker group 1, 2, 3, and 4 is enabled, and the reference signal V... REF + and negative reference signal V REF - Equal, CK0 / 180 samples the data at the middle time, CK90 / 270 samples the data at the edge, at this time the phase detection module works in Bang-Bang three-point phase detection mode.
[0035] In 1 / 4 rate mode, both phase interpolation modules are enabled, outputting a four-phase clock CK0 / 90 / 180 / 270. All four sampling modules in the multi-mode sampling module are enabled. All decision devices in threshold decision device groups 1, 2, 3, 4, 5, 6, 7, and 8 are enabled. The reference signal V... REF + and negative reference signal V REF - The four-phase clocks CK0 / 90 / 180 / 270 sample the data at the midpoint of the time. At this time, the phase detection module works in the Mueller-muller four-point phase detection mode.
[0036] Full-rate mode is suitable for low-speed applications, half-rate mode is suitable for medium- and high-speed applications, and 1 / 4-rate mode is suitable for ultra-high-speed applications.
[0037] Based on the above technical means, the high-efficiency multi-mode clock data recovery circuit provided by the present invention can dynamically adapt to different rate modes through the multi-mode sampling module, improve the energy efficiency ratio in low-noise scenarios, improve flexibility, and realize high-bandwidth applications; the multi-mode phase detection control module can effectively reduce the system's requirements for PLL and improve noise tolerance.
[0038] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A high-efficiency multi-mode clock data recovery circuit, characterized in that, include: Multimode sampling module, deserialization module, multimode phase detection control module, phase interpolation module, parallel data output module, CDR mode control module; The multimode sampling module is connected to the phase interpolation module and the deserialization module, and is used to sample the differential signal from the equalizer output and generate a signal, which is a data signal and an edge signal, or a data signal and an error signal. The deserialization module is connected to the multi-mode sampling module, the parallel data output module, and the multi-mode phase detection control module. It reduces the speed of the signal output by the multi-mode sampling module and outputs it to the subsequent digital circuits to compensate for the speed difference between analog circuits operating at higher frequencies and digital circuits operating at lower frequencies. The multi-mode phase detection control module is connected to the deserialization module and the phase interpolation module. It performs phase detection based on the input signal and generates a control word for adjusting the output clock phase of the phase interpolation module. The phase interpolation module is connected to the multi-mode phase detection control module and the multi-mode sampling module, and is used to adjust the phase of the PLL output clock to generate the sampling clock of the multi-mode sampling module, and to sample the data and edges of the input signal respectively. The parallel data output module is connected to the deserialization module and is used to output the final parallel output data of the physical layer, as well as a clock signal with the same frequency as the parallel output data. The CDR mode control module is connected to the multi-mode sampling module, the deserialization module, the multi-mode phase detection control module, the phase interpolation module, and the parallel data output module, and is used to control and select the working mode of the clock data recovery circuit.
2. The high-efficiency multi-mode clock data recovery circuit as described in claim 1, characterized in that, The multi-mode sampling module includes a first sampling module, a second sampling module, a third sampling module, and a fourth sampling module; The first sampling module samples the input data using the first clock signal CK0, the second sampling module samples the input data using the second clock signal CK90, the third sampling module samples the input data using the third clock signal CK180, and the fourth sampling module samples the input data using the fourth clock signal CK270.
3. The high-efficiency multi-mode clock data recovery circuit as described in claim 2, characterized in that, The multi-mode sampling module has three operating modes: full-rate mode, half-rate mode, and 1 / 4-rate mode. In the full-rate mode, the first sampling module and the third sampling module operate normally. The first sampling module outputs a data signal, and the third sampling module outputs an edge signal. The first sampling module includes a sampler 1 and a decision unit 1. The input of sampler 1 is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The input of decision unit 1 is connected to the output of sampler 1, and decision unit 1 outputs the sampling result pre_data at the intermediate moment of the data. The third sampling module includes a sampler 3 and a decision unit 3. The input of sampler 3 is connected to the differential signal output by the equalizer and the third clock signal CK180 output by the phase interpolation module. The input of decision unit 3 is connected to the output of sampler 3, and decision unit 3 outputs the sampling result pre_edge at the edge of the data. In the half-rate mode, the first, second, third, and fourth sampling modules operate normally. The first and third sampling modules output data signals, while the second and fourth sampling modules output edge signals. The first sampling module includes a sampler and a decision unit. The input of sampler is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The input of decision unit is connected to the output of sampler, and decision unit outputs the sampling result pre_data1 at the intermediate moment of the data. The second sampling module includes a sampler and a decision unit. The input of sampler is connected to the differential signal output by the equalizer and the second clock signal CK90 output by the phase interpolation module. The input of Decision 2 is connected to the output of Sampler 2, and Decision 2 outputs the sampling result pre_edge1 of the data edge; The third sampling module includes Sampler 3 and Decision 3. The input of Sampler 3 is connected to the differential signal output by the equalizer and the third clock signal CK180 output by the phase interpolation module. The input of Decision 3 is connected to the output of Sampler 3, and Decision 3 outputs the sampling result pre_data2 of the data midpoint; The fourth sampling module includes Sampler 4 and Decision 4. The input of Sampler 4 is connected to the differential signal output by the equalizer and the fourth clock signal CK270 output by the phase interpolation module. The input of Decision 4 is connected to the output of Sampler 4, and Decision 4 outputs the sampling result pre_edge2 of the data edge; In the 1 / 4 rate mode, the first, second, third, and fourth sampling modules operate normally, and all of them output data signals and error signals for phase detection. The first sampling module includes sampler one, threshold decision group one, and threshold decision group five. The input of sampler one is connected to the differential signal output by the equalizer and the first clock signal CK0 output by the phase interpolation module. The inputs of threshold decision group one and threshold decision group five are connected to the output of sampler one and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group one output data signal pre_data1, with threshold decision group five output error signal pre_error1 for phase detection; The second sampling module includes sampler two, threshold decision group two, and threshold decision group six. The input of sampler two is connected to the differential signal output from the equalizer and the second clock signal CK90 output from the phase interpolation module. The inputs of threshold decision group two and threshold decision group six are connected to the output of sampler two and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group two output data signal pre_data2, with threshold decision group six output error signal pre_error2 for phase detection; The third sampling module includes sampler three, threshold decision group three, and threshold decision group seven. The input of sampler three is connected to the differential signal output from the equalizer and the third clock signal CK180 output from the phase interpolation module. The inputs of threshold decision group three and threshold decision group seven are connected to the output of sampler three and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group three output data signal pre_data3, with threshold decision group seven output error signal pre_error3 for phase detection; The fourth sampling module includes sampler four, threshold decision group four, and threshold decision group eight. The input of sampler four is connected to the differential signal output from the equalizer and the fourth clock signal CK270 output from the phase interpolation module. The inputs of threshold decision group four and threshold decision group eight are connected to the output of sampler four and the negative reference signal V. REF - and the positive reference signal V REF +, with threshold decision group four output data signal pre_data4, with threshold decision group four output error signal pre_error4 used for phase detection.
4. The high-efficiency multi-mode clock data recovery circuit as described in claim 3, characterized in that, Each threshold decision group has the same structure, including a first threshold decision group and a second threshold decision group. The input terminals of both threshold decision groups are connected to differential input data and positive and negative reference signals VREF+ and VREF-. The first threshold decision group compares the input data with the difference between the positive and negative reference signals VREF+ and VREF- to obtain buffered decision data 1. The second threshold decision group compares the input data with the difference between the negative and positive reference signals VREF- and VREF+ to obtain buffered decision data 2. When the decision result of the previous bit of the input data is 1, threshold decision group one, threshold decision group two, threshold decision group three, and threshold decision group four select buffered decision data 1 as the final decision result; when the decision result of the previous bit of the input data is 0, buffered decision data 2 is selected as the final decision result. Threshold decision group one, threshold decision group two, threshold decision group three, and threshold decision group four implement the function of a predictive decision feedback equalizer. Conversely, when the decision result of the previous bit of the input data is 1, the gated buffer decision data 2 of threshold decision group five, threshold decision group six, threshold decision group seven and threshold decision group eight is used as the final output result; when the decision result of the previous bit of the input data is 0, the gated buffer decision data 1 is used as the final output result.
5. The high-efficiency multi-mode clock data recovery circuit as described in claim 1, characterized in that, The multi-mode phase detection and control module includes a phase detection module and a phase control module; the input terminal of the phase detection module is connected to the output terminal of the deserialization module, the output terminal of the phase detection module is connected to the input terminal of the phase control module, and the output terminal of the phase control module is connected to the input terminal of the phase interpolation module.
6. The high-efficiency multi-mode clock data recovery circuit as described in claim 5, characterized in that, The phase detection module includes: The delay unit, connected to the deserialization module, is used to delay the input data signal, edge signal, and error signal; A lead / lag decision unit is connected to the deserialization module and the delay unit to determine the lead / lag state of the input signal. A phase integrator, connected to the bit lead / lag decision unit, is used to accumulate the result of the bit lead / lag decision unit.
7. The high-efficiency multi-mode clock data recovery circuit as described in claim 5, characterized in that, The phase control module includes: Most of the voting units are connected to the phase detection module and are used to perform voting filtering on the phase detection control word to determine the effective phase adjustment direction and avoid misadjustment caused by transient noise interference. The phase controller, connected to the majority voter and the phase interpolation module, drives the phase interpolator to adjust the phase delay of the sampling clock according to the filtered phase detection control word.
8. The high-efficiency multi-mode clock data recovery circuit as described in claim 1, characterized in that, The CDR mode control module outputs control signals for full-rate mode, half-rate mode, and 1 / 4-rate mode respectively, based on the mode selection signal input from the external SPI.