Method of controlling the preparation of gate metallization

Abstract

This invention provides a method for fabricating a control gate metallization. The method includes: providing a substrate; forming a control gate structure based on an initial control gate layer and a conductive extension layer; forming an isolation sidewall on the inner wall of the control gate structure; forming a word line structure within the space enclosed by the isolation sidewall; performing back etching on the word line structure and the control gate structure so that their top height is lower than the top of the isolation sidewall; and forming a metal silicide layer on top of the word line structure and the control gate structure. This invention utilizes the conductive extension layer to increase the effective conductive surface area at the top of the control gate, thereby enabling the formation of metal silicide and reducing gate resistance. Simultaneously, the height difference created by the back etching process allows the protruding isolation sidewall to act as a physical barrier, effectively preventing bridging short circuits during metallization and improving device operating speed and production yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for preparing control gate metallization. Background Technology

[0002] As semiconductor manufacturing processes advance, the feature size of integrated circuit devices continues to shrink. In flash memory devices, the physical dimensions of active regions such as the gate, source, and drain of transistors are also miniaturized. While this reduction in size significantly increases storage density, it also brings a significant side effect: a sharp increase in the equivalent series resistance of interconnecting components. This increased resistance directly leads to increased resistive-capacitive delay, severely limiting the read and write speeds of the circuit and affecting the overall performance of the device.

[0003] In existing high-performance flash memory technologies, such as devices employing a mirrored gate structure, the main components include a floating gate (FG), a control gate (CG) located above the floating gate, and adjacent word lines (WL). In traditional fabrication processes, to achieve high-density array layouts, the control gate (CG) is typically buried deep beneath a hard mask layer or tightly surrounded by sidewall structures. This structural feature results in a barrier layer (such as oxides or nitrides) hindering the contact between metal atoms and the polysilicon of the control gate during subsequent self-aligned salicide processes, making it impossible to form a low-resistivity salicide layer on top of the control gate.

[0004] Due to the lack of a metal silicide layer, the control gate retains a high polysilicon bulk resistance, leading to decreased device drive capability and signal transmission delay. Furthermore, existing processes often struggle to precisely control the isolation height between the control gate and word lines when attempting to expose the control gate for metallization. This can easily cause unexpected electrical short circuits between the word lines and the control gate during metallization, thereby reducing yield.

[0005] Therefore, the industry urgently needs an optimized device structure and fabrication method that can effectively metallize the control gate and reduce its contact resistance while ensuring reliable isolation. Summary of the Invention

[0006] This application primarily addresses the technical problems in the prior art where, as the size of semiconductor devices shrinks, the control gate resistance increases and becomes difficult to metallize, and short circuits easily occur with word lines during the metallization process.

[0007] To address the aforementioned technical problems, this invention provides a method for preparing a controlled gate metallization, comprising the following steps:

[0008] Step 1: Provide a substrate, and form a stacked structure including an initial control gate layer on the substrate; form a conductive extension layer electrically connected to the initial control gate layer, such that the initial control gate layer and the conductive extension layer together constitute a control gate structure;

[0009] Step 2: Form an isolation sidewall on the inner sidewall of the control fence structure;

[0010] Step 3: Form a letter-line structure within the space enclosed by the isolation sidewalls;

[0011] Step 4: Perform a back etching process on the word line structure and the control gate structure so that the top height of the word line structure and the control gate structure is lower than the top height of the isolation sidewall;

[0012] Step 5: Form a metal silicide layer on the top surface of the word line structure and the control gate structure.

[0013] Preferably, in step one, the step of forming a stacked structure including an initial control gate layer includes: forming a pad layer, a floating gate material layer, an inter-electrode dielectric layer, the initial control gate layer, and a hard mask layer sequentially from bottom to top on a substrate; thereafter, opening the hard mask layer to form an opening, thereby exposing the sidewalls of the initial control gate layer, and forming a conductive extension layer on the sidewalls of the opening and establishing an electrical connection with the initial control gate layer.

[0014] Preferably, in step one, the step of forming the conductive extension layer includes: forming a composite functional layer in the opening, the composite functional layer including a first material layer and a second material layer; performing planarization and etching processes on the first material layer and the second material layer to remove the first material layer and the second material layer at the bottom of the opening; wherein the first material layer retained on the sidewall serves as the conductive extension layer, and the second material layer retained on the surface of the first material layer serves as a protective layer.

[0015] Preferably, in step one, both the first material layer and the initial control gate layer are doped polysilicon, and the second material layer is an oxide; the protective layer is used to protect the vertical portion of the control gate structure in step two.

[0016] Preferably, in step two, the step of forming the isolation sidewall includes: depositing a sidewall material layer; performing anisotropic etching on the sidewall material layer to remove the bottom sidewall material layer, and continuing to etch the stacked structure at the bottom of the opening until the padding layer is exposed, thereby forming the isolation groove and the isolation sidewall.

[0017] Preferably, in step three, the step of forming the character line structure includes: depositing a character line material layer in the space; performing chemical mechanical planarization on the character line material layer, and the character line structure formed by filling it presents a T-shaped structure that is wider at the top and narrower at the bottom.

[0018] Preferably, step three further includes forming a protective cap layer on top of the T-shaped character line structure, wherein the method for forming the protective cap layer is selected from any of the following: forming an oxide layer on top of the character line structure by oxidizing; depositing a dielectric material after etching the top of the character line structure; or depositing a dielectric material after excessively grinding the character line structure.

[0019] Preferably, in step four, before performing the back etching process, the process further includes removing the hard mask layer that may exist in step one, and using the word line structure and the control gate structure as a mask to self-align and etch the underlying film layer to define the memory cell structure.

[0020] Preferably, after defining the memory cell structure and before forming the metal silicide layer in step five, the method further includes: forming an outer wall on the exposed sidewall of the memory cell structure; the outer wall covers the sidewall of the floating gate material layer, the inter-electrode dielectric layer and the control gate structure in the memory cell structure, and is used to protect the sidewall from being silicided during the metallization process.

[0021] Preferably, in step five, the step of forming the metal silicide layer includes: depositing a metal layer that covers the exposed top of the word line structure and the control gate structure; and performing an annealing process to react the metal layer with the silicon material to achieve simultaneous metallization of the word line and the control gate.

[0022] As described above, the method for preparing the control gate metallization of the present invention has the following beneficial effects:

[0023] This application creates a composite control gate structure by building a conductive extension layer on top of the initial control gate layer. This structure allows the control gate to still provide sufficient top area for metal silicide formation even in extremely small devices, significantly reducing the bulk resistance and contact resistance of the control gate and improving the device's access speed. Simultaneously, this application utilizes an etch-back process to precisely control the height of the word line and control gate, ensuring it is below the top of the dielectric isolation sidewall. This height difference, combined with the protruding dielectric sidewall, forms a physical isolation barrier, effectively preventing lateral bridging short circuits between the word line and control gate during self-aligned metal silicide processes, greatly improving the process window and device yield. Furthermore, this process flow achieves simultaneous metallization of the control gate, word line, and source / drain regions, offering strong process compatibility and simplifying manufacturing steps. Attached Figure Description

[0024] Figure 1 The diagram shows a flow chart of the method for fabricating control gate metallization provided in an embodiment of the present invention.

[0025] Figure 2The diagram shows a cross-sectional view of the device after a multilayer structure is formed on the substrate in an embodiment of the present invention.

[0026] Figure 3 The diagram shows a cross-sectional view of the device after the hard mask layer is opened to form an opening in an embodiment of the present invention.

[0027] Figure 4 The diagram shows a cross-sectional view of the device after the composite functional layer is deposited inside the opening in an embodiment of the present invention.

[0028] Figure 5 The diagram shows a cross-sectional view of the device after planarization of the composite functional layer in an embodiment of the present invention.

[0029] Figure 6 The diagram shows a cross-sectional view of the device after etching to form a conductive extension layer and a protective layer in an embodiment of the present invention.

[0030] Figure 7 The diagram shows a cross-sectional view of the device after the isolation sidewall and isolation groove are formed in an embodiment of the present invention.

[0031] Figure 8 The diagram shown is a cross-sectional view of the device after the word line structure is formed in an embodiment of the present invention.

[0032] Figure 9 The diagram shows a cross-sectional view of the device after a protective cap layer is formed on top of the word line structure in an embodiment of the present invention.

[0033] Figure 10 The diagram shows a cross-sectional view of the device after the hard mask layer is removed, the memory cell structure is defined, and the outer wall is formed in an embodiment of the present invention.

[0034] Figure 11 The diagram shows a cross-sectional view of the device after back etching of the word line structure and control gate structure in an embodiment of the present invention.

[0035] Figure 12 The diagram shown is a cross-sectional view of the device after the metal silicide layer has been formed in an embodiment of the present invention. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] This application provides a method for preparing a control gate metallization. Figure 1This is a schematic flowchart of the control gate metallization fabrication method provided in the embodiments of this application. Figure 1 As shown, the method includes:

[0038] Step 1: Provide a substrate 101, and form a stacked structure including an initial control gate layer 105 on the substrate 101; form a conductive extension layer 107 electrically connected to the initial control gate layer 105, such that the initial control gate layer 105 and the conductive extension layer 107 together constitute a control gate structure.

[0039] The substrate 101 may include a bulk semiconductor substrate, such as a bulk silicon substrate, a doped silicon substrate, a bulk germanium substrate, etc. In some embodiments, the substrate 101 may also include a semiconductor insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor material of the substrate 101 may also include silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof. Various implantation regions, such as P-type well regions or N-type well regions, may be formed on the substrate 101. By constructing a conductive extension layer 107 on the substrate 101 based on the initial control gate layer 105, the volume and effective conductive surface area of ​​the control gate can be expanded in the vertical direction, thereby providing a structural basis for subsequent resistance reduction using the vertical space without increasing the device planar footprint.

[0040] In some embodiments, the step of forming a stacked structure including the initial control gate layer 105 includes: as follows Figure 2 As shown, a liner layer 102, a floating gate material layer 103, an inter-electrode dielectric layer 104, an initial control gate layer 105, and a hard mask layer 106 are sequentially formed from bottom to top on a substrate 101; thereafter, as... Figure 3 As shown, an opening is formed in the hard mask layer 106, exposing the sidewalls of the initial control gate layer 105. A conductive extension layer 107 is formed on the sidewalls of the opening and establishes an electrical connection with the initial control gate layer 105. The pad layer 102 may include silicon oxide, which may be formed by thermal oxidation, such as dry oxidation or wet oxidation, or by chemical vapor deposition (CVD) processes, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The floating gate material layer 103 and the initial control gate layer 105 may be composed of conductive materials, including but not limited to polysilicon, doped polysilicon, amorphous silicon, metal, or conductive metal nitride.

[0041] In some embodiments, polycrystalline silicon is deposited using an LPCVD process, and impurity ions such as phosphorus, arsenic, or boron are incorporated through in-situ doping or ion implantation to adjust conductivity. The inter-electrode dielectric layer 104 can employ a multilayer dielectric structure, such as an oxide-nitride-oxide (ONO) structure, or a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), or combinations thereof. The hard mask layer 106 may include silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, or combinations thereof, with a thickness sufficient to withstand subsequent chemical mechanical polishing (CMP) processes. The formation of openings can be achieved by defining patterns using photolithography and then using anisotropic dry etching processes, such as reactive ion etching (RIE), through the hard mask layer 106. The exposure of the sidewalls of the initial control gate layer 105 is key to achieving a low-resistance ohmic contact with the subsequently formed conductive extension layer 107, ensuring that the two work electrically as a whole.

[0042] In some embodiments, the step of forming the conductive extension layer 107 includes: as follows Figure 4 As shown, a composite functional layer is formed within the opening. This composite functional layer includes a first material layer (which will subsequently form a conductive extension layer 107) and a second material layer (which will subsequently form a protective layer 108). The first and second material layers are planarized and etched to remove the first and second material layers at the bottom of the opening, thus exposing the initial control gate layer 105, forming a layer as shown. Figure 6 The structure shown is as follows: a first material layer retained on the sidewall serves as a conductive extension layer 107, and a second material layer retained on the surface of the first material layer serves as a protective layer 108. The deposition of the composite functional layer can employ a conformal deposition process, such as LPCVD or ALD, to ensure thickness uniformity on the opening sidewalls. The planarization of the first and second material layers can be performed using a CMP process, stopping at the top surface of the hard mask layer 106, forming a structure as shown. Figure 5 The structure is shown. Subsequent etching can employ a high aspect ratio dry etching process, utilizing a time-controlled mode or an endpoint detection mode to remove material from the bottom of the opening while retaining material on the sidewalls. This self-aligned process avoids additional photolithography steps, reducing the risk of failure due to photolithographic alignment errors.

[0043] In some embodiments, both the first material layer (conductive extension layer 107) and the initial control gate layer 105 are doped polysilicon, and the second material layer (protective layer 108) is an oxide. The protective layer 108 is used to protect the vertical portion of the control gate structure in step two. The first material layer may be made of the same polysilicon material as the initial control gate layer 105 and subjected to the same type of heavy doping to avoid forming a barrier at the interface. The second material layer may be tetraethoxysilane (TEOS)-based silicon oxide, high-temperature oxide (HTO), or other dielectric materials with a high etch selectivity to polysilicon. During the subsequent etching process to form the isolation sidewalls, the protective layer 108 acts as an etch barrier layer, preventing the first material layer, which serves as the conductive extension layer, from being damaged laterally or longitudinally, maintaining the geometric integrity of its upper end, and ensuring the consistency of the memory cells.

[0044] Step 2: An isolation sidewall 109 is formed on the inner wall of the control gate structure. The formation of the isolation sidewall 109 establishes reliable dielectric isolation between the control gate and the word lines to be filled subsequently, preventing breakdown and leakage current under high-voltage operation.

[0045] In some embodiments, such as Figure 7 As shown, the steps for forming the isolation sidewall 109 include: depositing a sidewall material layer; performing anisotropic etching on the sidewall material layer to remove the bottom sidewall material layer, and continuing to etch the stacked structure at the bottom of the opening until the pad layer 102 is exposed (or the substrate 101 is exposed through the pad layer), thereby forming the isolation trench and the isolation sidewall 109, while also reducing the height of the conductive extension layer 107. The sidewall material layer may include silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), or combinations thereof, and the formation method may include LPCVD, PECVD, or ALD. The anisotropic etching step typically uses fluorine-containing gases (such as CF4, CHF3, CH2F2, C4F8, etc.) or chlorine-containing gases (such as Cl2), combined with oxygen, nitrogen, or argon. This step not only removes the bottom sidewall material, but also continues to etch downwards through the inter-electrode dielectric layer 104 and the floating gate material layer 103, using the sidewall and the upper hard mask as a mask. This continuous self-aligned etching process simultaneously defines the width of the floating gate and the channel area, eliminating alignment errors between the floating gate and word lines, and between the floating gate and the control gate.

[0046] Step 3: Form a word line structure 111 within the space enclosed by the isolation sidewall 109. The word line structure 111 serves as the selection gate for the memory cell.

[0047] In some embodiments, such as Figure 8As shown, the steps for forming the word line structure 111 include: depositing a word line material layer in the space; chemically and mechanically planarizing the word line material layer, resulting in a T-shaped structure 111 that is wider at the top and narrower at the bottom. Before depositing the word line material layer, a word line dielectric layer 110 (tunneling oxide layer) is typically formed on the exposed substrate 101 surface (channel region) and the floating gate sidewalls. This layer can be high-quality silicon oxide grown by thermal oxidation. The word line material layer can include polysilicon, or in some advanced nodes, it can include a metal gate material such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), etc.

[0048] In some embodiments, such as Figure 9 As shown, the method also includes forming a protective cap layer 112 on top of the T-shaped word line structure 111. The method for forming the protective cap layer 112 is selected from any of the following: forming an oxide layer on top of the word line structure by oxidizing it; depositing a dielectric material after etching the top of the word line structure; or depositing a dielectric material after excessive polishing of the word line structure. If oxidation is used, wet oxidation or in-situ steam generation (ISSG) processes can be employed. If etching followed by backfilling is used, high-density plasma CVD (HDP-CVD) or flow-through CVD (FCVD) can be used to fill the silicon oxide, followed by CMP planarization. If excessive polishing is used, the upper surface of the word line material layer is polished to form a depression, which is then filled with dielectric material by CVD and the excess is removed by CMP. The protective cap layer 112 can be made of silicon oxide or silicon oxynitride, and its function is to act as a hard mask to protect the word line material from corrosion or damage and maintain the word line height during the subsequent removal of the hard mask layer 106 (typically silicon nitride, removed using hot phosphoric acid).

[0049] Step 4: Perform a back etching process on the word line structure 111 and the control gate structure, so that the top height of the word line structure 111 and the control gate structure (including 105 and 107) is lower than the top height of the isolation sidewall 109. For example... Figure 11 As shown, this etching process effectively adjusts the relative height difference between the conductive structure and the dielectric isolation structure. At this point, the isolation sidewall 109 protrudes vertically, forming a physical barrier similar to a "fence." This height difference design effectively blocks the lateral diffusion path during subsequent metal silicide growth, prevents electrical short circuits between the word line and the control gate, and improves the process window.

[0050] In some embodiments, prior to the etch-back process, the method further includes removing the hard mask layer 106 that may be present in step one, and using the word line structure 111 and the control gate structure as a mask, self-aligning and etching the underlying film layer to define the memory cell structure. For example... Figure 10As shown, the hard mask layer 106 is removed. The hard mask layer 106 can be removed using a wet etchant with high selectivity for oxides and polysilicon, such as hot phosphoric acid. Subsequent self-aligned etching is typically anisotropic dry etching, using word lines and control gates as hard masks to remove floating gate layers and inter-electrode dielectric layers outside the active region or in the bit line direction, thereby achieving isolation of individual memory cells in the bit line direction.

[0051] In some embodiments, after defining the memory cell structure and before forming the metal silicide layer 114 in step five, the method further includes: Figure 10 As shown, an outer wall 113 is formed on the exposed sidewalls of the memory cell structure. The outer wall 113 covers the sidewalls of the floating gate material layer 103, the inter-electrode dielectric layer 104, and the control gate structure (105, 107) in the memory cell structure, and is used to protect the sidewalls from silicide formation during metallization. The outer wall 113 may include an oxide, silicon nitride, or silicon oxide-silicon nitride composite layer. The outer wall 113 is formed by an omnidirectional deposition and etch-back process. This outer wall 113 not only seals the sidewalls of the floating gate and the inter-electrode dielectric layer, preventing the diffusion of metal atoms that may lead to leakage paths, but also prevents short circuits between the floating gate and the control gate or between the floating gate and the word line caused by sidewall silicide formation, ensuring that metal silicide is only generated on the predetermined top surface.

[0052] Step 5: Form a metal silicide layer 114 on the top surface of the word line structure 111 and the control gate structure. For example... Figure 12 As shown, metal silicide formation transforms a high-resistivity semiconductor surface into a low-resistivity metal-semiconductor compound surface, significantly reducing the sheet resistance of the polysilicon gate.

[0053] In some embodiments, the step of forming the metal silicide layer 114 includes: depositing a metal layer covering the exposed tops of the word line structure 111 and the control gate structure (105, 107); and performing an annealing process to react the metal layer with silicon material to simultaneously metallize the word line and the control gate. The metal layer may include cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), tungsten (W), erbium (Er), ytterbium (Yb), palladium (Pd), or alloys thereof (e.g., nickel-platinum alloys, titanium-tantalum alloys, etc.). Deposition may be performed using physical vapor deposition (PVD), such as DC sputtering or RF sputtering. The annealing process typically includes a one-step or two-step rapid thermal annealing (RTA) process. In the first annealing step, the metal reacts with the contacting silicon to form a metal-rich silicide; subsequently, unreacted metal (e.g., metal deposited on the outer wall 113 and the protruding isolation sidewall 109) is removed; finally, a second annealing step at a higher temperature is performed to convert the metal-rich silicide into a low-resistivity monosilicide or disilicide phase (e.g., NiSi, CoSi2, TiSi2). Due to the specific control gate structure of this application and the word line structure 111 after removing the protective cap layer 112, the metal layer can make sufficient contact with the top of both gates, especially the conductive extension layer 107 of the control gate provides additional top contact area. Through the physical isolation of the protruding isolation sidewall 109, the low-resistivity processing of the dual gates is safely and reliably achieved in the same metallization process. It is worth noting that during the metal layer deposition and annealing steps, since the source and drain regions (not shown in the figure) in the substrate 101 located on both sides of the memory cell structure are also exposed, the metal layer also covers the surfaces of the source and drain regions. Therefore, the aforementioned annealing process causes the metal layer to react with the single-crystal silicon in the source and drain regions. Simultaneously, while forming the word line structure 111 and the metal silicide layer 114 on top of the control gate structure, metal silicide layers are also formed on the surfaces of the source and drain regions. This simultaneous metallization process eliminates the need for additional photolithography masking steps. The metal silicides on the surfaces of the source and drain regions significantly reduce the contact resistance between the subsequently formed contact plugs and the active regions, further improving the overall drive current and access speed of the device.

[0054] This application also provides a semiconductor device fabricated using the control gate metallization method described above. This semiconductor device can be an embedded non-volatile memory, a standalone flash memory, an electrically erasable programmable read-only memory, etc. Structurally, the device is characterized by a control gate structure comprising an initial control gate layer 105 and a conductive extension layer 107, and a word line structure 111, both of which are topped with a metal silicide layer 114, and are separated by a dielectric isolation sidewall 109 higher than the silicide surface. This structural design, while meeting the requirements of high-density integration at miniaturized process nodes, significantly reduces gate resistance and improves the device's read speed, erase / write efficiency, and reliability.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating controlled gate metallization, characterized in that, At least including: Step 1: Provide a substrate, and form a stacked structure including an initial control gate layer on the substrate; form a conductive extension layer electrically connected to the initial control gate layer, such that the initial control gate layer and the conductive extension layer together constitute a control gate structure; Step 2: Form an isolation sidewall on the inner sidewall of the control fence structure; Step 3: Form a letter-line structure within the space enclosed by the isolation sidewalls; Step 4: Perform a back etching process on the word line structure and the control gate structure so that the top height of the word line structure and the control gate structure is lower than the top height of the isolation sidewall; Step 5: Form a metal silicide layer on the top surface of the word line structure and the control gate structure.

2. The method for fabricating control gate metallization according to claim 1, characterized in that: In step one, the step of forming a stacked structure including an initial control gate layer includes: forming a pad layer, a floating gate material layer, an inter-electrode dielectric layer, the initial control gate layer, and a hard mask layer sequentially from bottom to top on a substrate; thereafter, opening the hard mask layer to form an opening, thereby exposing the sidewalls of the initial control gate layer, and forming a conductive extension layer on the sidewalls of the opening and establishing an electrical connection with the initial control gate layer.

3. The method for fabricating control gate metallization according to claim 2, characterized in that: In step one, the step of forming the conductive extension layer includes: forming a composite functional layer in the opening, the composite functional layer including a first material layer and a second material layer; performing planarization and etching processes on the first material layer and the second material layer to remove the first material layer and the second material layer at the bottom of the opening; wherein the first material layer retained on the sidewall serves as the conductive extension layer, and the second material layer retained on the surface of the first material layer serves as a protective layer.

4. The method for fabricating control gate metallization according to claim 3, characterized in that: In step one, both the first material layer and the initial control gate layer are doped polysilicon, and the second material layer is an oxide; the protective layer is used to protect the vertical portion of the control gate structure in step two.

5. The method for fabricating control gate metallization according to claim 2, characterized in that: In step two, the step of forming the isolation sidewall includes: depositing a sidewall material layer; performing anisotropic etching on the sidewall material layer to remove the bottom sidewall material layer, and continuing to etch the stacked structure at the bottom of the opening until the padding layer is exposed, thereby forming the isolation groove and the isolation sidewall.

6. The method for fabricating control gate metallization according to claim 1, characterized in that: In step three, the step of forming the character line structure includes: depositing a character line material layer in the space; performing chemical mechanical planarization on the character line material layer, and the resulting character line structure exhibiting a T-shaped structure that is wider at the top and narrower at the bottom.

7. The method for fabricating control gate metallization according to claim 6, characterized in that: Step three also includes the step of forming a protective cap layer on top of the T-shaped character line structure, wherein the method for forming the protective cap layer is selected from any of the following: forming an oxide layer on top of the character line structure; Dielectric material is deposited after etching the top of the letter line structure; After excessive grinding of the character line structure, a medium material is deposited.

8. The method for fabricating control gate metallization according to claim 1, characterized in that: In step four, before performing the etch-back process, the process also includes removing any hard mask layer that may have been present in step one, and using the word line structure and the control gate structure as a mask, self-aligning the underlying film layer to define the memory cell structure.

9. The method for fabricating control gate metallization according to claim 8, characterized in that: After defining the memory cell structure and before forming the metal silicide layer in step five, the method further includes: forming an outer wall on the exposed sidewall of the memory cell structure; the outer wall covers the sidewall of the floating gate material layer, the inter-electrode dielectric layer and the control gate structure in the memory cell structure, and is used to protect the sidewall from being silicided during the metallization process.

10. The method for fabricating control gate metallization according to claim 1, characterized in that: In step five, the step of forming the metal silicide layer includes: depositing a metal layer that covers the exposed top of the word line structure and the control gate structure; and performing an annealing process to react the metal layer with the silicon material to achieve simultaneous metallization of the word line and the control gate.

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