Wafer defect detection method, device, medium and equipment
By mapping wafer images to the polar coordinate domain and constructing a detection model with radial-angular feature extraction layers, the problems of accuracy and model complexity in wafer defect detection are solved, achieving efficient wafer defect detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NORTHEASTERN UNIV CHINA
- Filing Date
- 2026-06-15
- Publication Date
- 2026-07-14
AI Technical Summary
Existing wafer defect detection methods suffer from insufficient accuracy and complex model network structures.
By mapping wafer images to the polar coordinate domain, a detection model containing radial-angular feature extraction layers is constructed to jointly model local texture information and cross-regional nonlocal dependencies. Feature extraction and fusion are then performed using a pre-trained target detection model to achieve chip-level and wafer-level defect detection.
It improves the accuracy and robustness of defect detection, simplifies the model architecture, and reduces training and deployment costs.
Smart Images
Figure CN122391234A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of wafer inspection technology, and in particular to a wafer defect detection method, apparatus, medium and equipment. Background Technology
[0002] Wafer chips are the critical carriers in semiconductor manufacturing, and their manufacturing quality directly affects the electrical performance, power consumption, and long-term reliability of integrated circuits. Wafer fabrication typically involves multiple complex processes, including oxidation, photolithography, etching, ion implantation, thin film deposition, and chemical mechanical polishing. Problems such as particle contamination, scratches, pattern breakage, and residue accumulation at any stage can create different types of defects on the wafer surface, potentially leading to chip failure or even complete wafer scrap. Therefore, automated defect detection and classification of each die on the wafer before product shipment is crucial for ensuring yield and process stability.
[0003] Existing detection approaches can be broadly categorized into two types: one is traditional image processing methods, represented by image enhancement, threshold segmentation, and geometric feature analysis; the other is automatic recognition methods based on machine learning and deep learning models.
[0004] Traditional image processing methods often employ a rule-based process combining grayscale conversion, filtering and noise reduction, thresholding, edge detection, and morphological operations to extract and identify defective regions. While these methods are straightforward and computationally efficient, they are highly dependent on human experience and are sensitive to factors such as lighting, contrast, noise levels, and the regularity of wafer surface patterns. When the texture structure is complex or there are significant variations in process conditions between batches, false positives and false negatives are prone to occur, and their generalization ability is limited.
[0005] Existing automatic identification methods, namely deep learning methods based on deep neural networks, typically treat the wafer as a regular two-dimensional image and use local convolution operations to extract features from a fixed local window in a Cartesian coordinate system. Essentially, they apply spatially local, parameter-shared linear operators to the local neighborhood. For spatially far-distance correlated defect patterns that are coupled across radial regions, such as large-scale annular defects, banded defects spanning multiple rings, and process anomaly patterns involving multiple regions, several layers of stacked local convolutions are needed to establish long-distance dependencies. This significantly increases the network depth and parameter scale, resulting in a complex model network architecture and high training and deployment costs.
[0006] Therefore, there is an urgent need for a wafer defect detection method to solve the problems of inaccurate wafer defect detection and complex model network structure in existing technologies. Summary of the Invention
[0007] In view of this, this application provides a wafer defect detection method, apparatus, medium and equipment, the main purpose of which is to solve the problems of inaccurate wafer defect detection and complex network structure of existing models.
[0008] To address the above problems, this application provides a wafer defect detection method, comprising: The original wafer image of the wafer to be tested is processed to obtain a polar coordinate image; The polar coordinate image is divided into annular regions to obtain the radial and angular positions corresponding to each annular region; Using the radial-angular feature extraction layers of each target in the pre-trained target detection model, feature extraction is performed on the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, based on the radial and angular positions corresponding to each annular region, to obtain intermediate features that contain the features of each annular region corresponding to each radial-angular feature extraction layer of the target. The intermediate features are fused using the target feature fusion layer in the pre-trained target detection model to obtain the fused target features. Based on the target defect detection layer in the pre-trained target detection model, chip-level defect detection and wafer-level defect detection are performed on the target features to obtain target detection results.
[0009] Optionally, the original wafer image of the wafer to be tested is processed to obtain a polar coordinate image, specifically including: The original wafer image of the wafer to be tested is preprocessed to obtain the preprocessed wafer image. The preprocessed wafer image is subjected to coordinate transformation to obtain a polar coordinate image.
[0010] Optionally, before performing feature extraction, the method further includes: The polar coordinate image is mapped to initial features using the feature mapping formula.
[0011] Optionally, each of the target radial-angular feature extraction layers includes a local linear transformation operator and a radial-angular nonlocal operator; When performing intermediate feature extraction, the radial-angular feature extraction layer for any target specifically includes: Based on the radial and angular positions corresponding to each annular region, the local linear transformation operator is used to extract local features at the current radial and angular positions from the initial features or the intermediate features output by the previous target radial-angular feature extraction layer, thereby obtaining the first feature containing the local features of each annular region. Based on the radial and angular positions corresponding to each annular region, the radial-angular nonlocal operator is used to extract cross-regional features at the current radial and angular positions using the initial features or the intermediate features output by the previous target radial-angular feature extraction layer, thereby obtaining a second feature containing global features of each annular region. The first feature and the second feature are concatenated to obtain the concatenated feature. The splicing features are subjected to nonlinear activation processing to obtain the intermediate features.
[0012] Optionally, the target defect detection layer in the pre-trained target detection model performs chip-level defect detection and wafer-level defect detection on the target features to obtain target detection results, specifically including: Based on the target features, wafer-level defect detection is performed using the target wafer-level defect detection module in the target defect detection layer to obtain wafer-level defect detection results. Based on the target features, chip-level defect detection is performed using the target chip-level defect detection module in the target defect detection layer to obtain chip-level defect detection results. The target detection result is obtained based on the wafer-level defect detection result and the chip-level defect detection result.
[0013] Optionally, the step of performing chip-level defect detection based on target features using the target chip-level defect detection module in the target defect detection layer to obtain chip-level defect detection results specifically includes: Based on the pooling layer in the target chip-level defect detection module, pooling is performed on the regions corresponding to each chip unit in the target features to obtain the chip-level features corresponding to each chip unit. Based on the characteristics of each chip, the defect probability of each chip unit having defects is calculated by using the target classifier in the target chip-level defect detection module. Based on the defect probability of each chip unit and a predetermined probability threshold, chip units with a defect probability greater than the probability threshold are identified as target chip units with defects.
[0014] Optionally, the method further includes: pre-determining the probability threshold corresponding to each annular region, specifically including: Based on the background fluctuation level and the baseline probability threshold corresponding to each annular zone, the probability threshold corresponding to each annular zone is determined. The step of determining chip units with defect probabilities greater than a predetermined probability threshold as target chip units with defects, based on the defect probability of each chip unit and a predetermined probability threshold, specifically includes: Based on the defect probability of each chip unit and the probability threshold corresponding to the annular region to which each chip unit belongs, chip units with a defect probability greater than the probability threshold are identified as target chip units with defects.
[0015] To address the above problems, this application provides a wafer defect detection device, comprising: The processing module is used to process the original wafer image of the wafer to be tested to obtain a polar coordinate image; The segmentation module is used to divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region. The extraction module is used to extract features from the radial-angular feature extraction layers of each target in the pre-trained target detection model, based on the radial and angular positions corresponding to each annular region, and to extract features from the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, to obtain intermediate features corresponding to each radial-angular feature extraction layer of the target that contain the features of each annular region. The fusion module is used to perform feature fusion on the intermediate features using the target feature fusion layer in the pre-trained target detection model to obtain the fused target features. The detection module is used to perform chip-level defect detection and wafer-level defect detection on the target features based on the target defect detection layer in the pre-trained target detection model, and obtain the target detection results.
[0016] To address the aforementioned problems, this application provides a storage medium storing a computer program that, when executed by a processor, implements the steps of any of the aforementioned wafer defect detection methods.
[0017] To address the aforementioned problems, this application provides an electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program in the memory, implements the steps of any of the aforementioned wafer defect detection methods.
[0018] The wafer defect detection method, apparatus, medium, and device in this application, by mapping wafer images to the polar coordinate domain, enable a more natural expression of the radial structural features and angular distribution features of the wafer, which is beneficial to improving the model's utilization of the wafer's geometric prior information. By constructing a detection model that includes radial-angular feature extraction layers, the joint modeling of local texture information and cross-regional nonlocal dependencies is achieved. Therefore, it has stronger feature expression capabilities and higher detection robustness in the detection of annular anomalies, edge band anomalies, repetitive anomalies, and other complex distribution patterns, enabling accurate wafer defect detection. Furthermore, the model architecture is simple, and the training and deployment costs are low.
[0019] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description
[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a flowchart of a wafer defect detection method according to an embodiment of this application; Figure 2 This is a structural block diagram of a wafer defect detection device according to another embodiment of this application; Figure 3 This is a structural block diagram of an electronic device according to another embodiment of this application. Detailed Implementation
[0021] Various embodiments and features of this application are described herein with reference to the accompanying drawings.
[0022] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.
[0023] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.
[0024] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.
[0025] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.
[0026] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.
[0027] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as a representative basis for teaching those skilled in the art to use this application in a variety of substantially any suitable detailed structures.
[0028] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.
[0029] This application provides a wafer defect detection method, such as... Figure 1 As shown, it includes the following steps: Step S101: Process the original wafer image of the wafer to be tested to obtain a polar coordinate image; Step S102: Divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region; Step S103: Using the radial-angular feature extraction layers of each target in the pre-trained target detection model, feature extraction is performed on the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, based on the radial and angular positions corresponding to each annular region, to obtain intermediate features corresponding to each target radial-angular feature extraction layer that contain the features of each annular region. Step S104: Use the target feature fusion layer in the pre-trained target detection model to perform feature fusion on each of the intermediate features to obtain the fused target features; Step S105: Based on the target defect detection layer in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the target features to obtain the target detection result.
[0030] The wafer defect detection method in this embodiment maps the wafer image to the polar coordinate domain, enabling a more natural expression of the wafer's radial structural features and angular distribution features. This improves the model's utilization of prior geometric information about the wafer. By constructing a detection model that includes radial-angular feature extraction layers, it achieves joint modeling of local texture information and cross-regional nonlocal dependencies. Therefore, it has stronger feature representation capabilities and higher detection robustness in detecting annular anomalies, edge band anomalies, repetitive anomalies, and other complex distribution patterns. It can accurately detect wafer defects, and the model architecture is simple with low training and deployment costs.
[0031] Another embodiment of this application provides a wafer defect detection method, including the following steps: Step S201: Image acquisition is performed on the wafer object to be tested to obtain the original wafer image; In this step, an industrial camera or a line scan camera can be used to image the wafer under test to obtain the original wafer image. The original wafer image can be a grayscale image or a color image; it can be a single-frame image or a multi-frame stitched image. This application does not strictly limit the image source; as long as the acquired image can reflect the grayscale distribution, texture features, or structural anomalies of the wafer surface, edges, and chip area, it can be used as input to this method.
[0032] Step S202: Perform image preprocessing on the original wafer image of the wafer to be tested to obtain the preprocessed wafer image; In this step, image preprocessing includes any one or more of the following: grayscale normalization, edge-preserving denoising, and standardization. Specifically, the original wafer image can be subjected to grayscale normalization, edge-preserving denoising, and standardization sequentially to obtain the preprocessed wafer image.
[0033] In the specific implementation process of this step, the preprocessing procedure is as follows: Step S202-1, grayscale normalization processing; To reduce brightness differences between different batches of images caused by variations in exposure conditions, light intensity, or imaging equipment parameters, grayscale normalization is performed on the original wafer images to obtain normalized images. Its expression is:
[0034] in, and These represent the minimum and maximum gray values in the original image, respectively. This is a small constant set to prevent the denominator from being zero. This step ensures that different images maintain consistency across the grayscale, thereby improving the stability of subsequent processing.
[0035] Step S202-2, edge preservation and noise reduction processing; To suppress random noise, local bright spots, and imaging disturbances, while preserving defect boundaries and texture structure information as much as possible, an edge-preserving denoising method is preferred for normalized images. The image is then processed. Preferably, a bilateral filtering method can be used to obtain a denoised image. Its expression is:
[0036] in, Indicates the current pixel position. Indicated by The center's neighborhood window, Represents the spatial domain smoothing parameter. This represents the grayscale smoothing parameter. This is the normalization factor. Using this type of edge-preserving filtering method helps to remove noise while retaining local edge features relevant to defect detection.
[0037] Step S202-3, standardization process; To improve the consistency of input data distribution during network training and inference, the denoised images are preferred. (Right now The wafer image is then standardized to obtain the final preprocessed image. Its expression is:
[0038] in, and Representing images respectively The mean and standard deviation. equal .
[0039] After this processing, the image data is more suitable for input into subsequent neural network structures for feature learning.
[0040] Step S203: Perform coordinate transformation processing on the preprocessed wafer image to obtain a polar coordinate image; In the specific implementation process of this step, the orientation of the preprocessed wafer image can be corrected based on a predetermined reference mark to obtain a corrected wafer image; and coordinate transformation processing can be performed on the corrected wafer image to obtain the polar coordinate image.
[0041] The process of correcting the orientation of the preprocessed wafer image based on a predetermined reference marker to obtain a corrected wafer image specifically includes: performing wafer outer contour detection on the preprocessed wafer image to determine the position and size of the wafer object to be tested in the preprocessed wafer image; determining a rotation compensation angle between the predetermined reference marker and a predetermined reference direction based on the predetermined reference marker; and rotating the preprocessed wafer image based on the rotation compensation angle to obtain the corrected wafer image.
[0042] In other words, this step, in its specific implementation, includes the following steps: Step S203-1, wafer outer contour inspection; Preprocessed images The outer contour of the wafer is extracted, and the wafer center is determined by methods such as circle detection, edge fitting, or Hough transform. and wafer radius This allows us to obtain the position and size of the wafer object under test within the preprocessed wafer image. The center and radius parameters serve as the fundamental geometric parameters for subsequent polar coordinate mapping.
[0043] Step S203-2, notch or alignment mark direction detection; To standardize wafer rotation direction, the position of notches or alignment marks is detected in the wafer edge region, and the current wafer orientation angle is determined based on their orientation. For any pixel Its polar angle relative to the center of the wafer can be expressed as:
[0044] In practice, the angular position of the gap or mark can be determined through edge continuity analysis, template matching, local gray-scale abrupt change detection, or other directional identification methods.
[0045] Step S203-3 Attitude correction; In this step, the compensation angle between the reference mark and the predetermined reference direction can be determined based on the predetermined reference mark.
[0046] That is, the standard reference direction angle is set as The required rotation compensation angle for the wafer image for:
[0047] Finally, based on the rotation compensation angle, the preprocessed wafer image is geometrically rotated to obtain the orientation-corrected wafer image. Its expression is:
[0048] in, Indicates the rotation angle is A two-dimensional rotation matrix. After attitude correction, different wafer images maintain consistency in the angular reference, which is beneficial for subsequent polar coordinate unfolding and unified feature modeling.
[0049] Step S203-4, polar coordinate mapping; The polar coordinate image is obtained by performing coordinate transformation on the corrected wafer image; that is, by transforming the corrected wafer image... The Cartesian coordinate representation is converted to a polar coordinate representation consistent with the wafer geometry.
[0050] That is, the image after pose correction. According to the wafer center and wafer radius Mapping to the polar coordinate domain yields a polar coordinate image. Its expression is:
[0051] in, Represents the normalized radial coordinates. This represents angular coordinates. Through this mapping, features in the wafer image that were originally attached to the circular boundary and radial hierarchy can be expressed in a more regular form in the polar coordinate domain.
[0052] Step S204: Divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region; In this step, to further highlight the radial layering characteristics of the wafer, the normalized radial region is... Divided into Annular band Specifically, it is expressed as:
[0053] The annular banding helps organize the features of different radius regions of the wafer into a hierarchical representation, facilitating subsequent explicit modeling of the correlation between different radial regions. Preferably, the annular bands can be divided with equal width, or non-equal width banding can be used based on process experience, edge anomaly distribution patterns, or image resolution.
[0054] Step S205: Map the polar coordinate image to initial features using the feature mapping formula; In this step, after completing the polar coordinate mapping and annular zone division, the polar coordinate image and its corresponding positional encoding information are mapped to the initial input features of the network. The feature mapping formula is:
[0055] in, Indicates initial features; Represents the input embedding mapping; This indicates splicing by channel; Represents a polar coordinate image; Represents the normalized radial coordinates. Represents angular coordinates.
[0056] Step S206: Using the radial-angular feature extraction layers of each target in the pre-trained target detection model, feature extraction is performed on the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, based on the radial and angular positions corresponding to each annular region, to obtain intermediate features corresponding to each target radial-angular feature extraction layer that contain the features of each annular region. In this step, the target detection model includes several cascaded radial-angular feature extraction layers; each radial-angular feature extraction layer includes a local linear transformation operator and a radial-angular nonlocal operator. When performing intermediate feature extraction in the arbitrary target radial-angular feature extraction layer, the specific steps include: based on the radial and angular positions corresponding to each annular region, using the initial features or the intermediate features output by the previous target radial-angular feature extraction layer, performing local feature extraction on the current radial and angular positions using a local linear transformation operator to obtain a first feature containing the local features of each annular region. Based on the radial and angular positions corresponding to each annular region, the initial features or the intermediate features output by the previous target radial-angular feature extraction layer are used to perform cross-region feature extraction on the current radial and angular positions using radial-angular nonlocal operators, thereby obtaining a second feature that contains global features of each annular region. The first feature and the second feature are concatenated to obtain the concatenated feature; the concatenated feature is then subjected to nonlinear activation processing to obtain the intermediate feature. .
[0057] That is, let's assume For the first The output features of the target radial-angular feature extraction layer, then the first... Target radial-angular feature extraction layer output features It can be represented as:
[0058] in, This represents a local linear transformation operator, obtained through model training, used to transform the th... The layer performs a local linear transformation to extract local features at the current location; This represents the radial-angular nonlocal operator, obtained through model training, used to analyze the first... The layer performs global feature extraction across locations; This represents the first feature extracted; This represents the extracted second feature; This represents a nonlinear activation function. By combining local transformation terms with nonlocal operator terms, both the detailed representation of local defects and the modeling of global distribution patterns can be considered simultaneously.
[0059] Step S207: Use the target feature fusion layer in the pre-trained target detection model to perform feature fusion on each of the intermediate features to obtain the fused target features; In the specific implementation process, this step can utilize the target feature fusion layer to combine the intermediate features output by multiple radial-angular feature extraction layers. By stacking the layers, the final deep features are obtained, which are the fused target features. .
[0060] In the specific implementation of this step, let the intermediate features output by the radial-angular feature extraction layers of each target be as follows: First, feature alignment mapping is used. Each intermediate feature is mapped to a uniform spatial size and channel dimension to obtain aligned features. Its expression is:
[0061] in, It represents any one or a combination of upsampling, downsampling, linear mapping, and convolutional mapping. Then, the aligned features are concatenated along the channel dimension to obtain the fused feature, the expression of which is:
[0062] Finally, the fused features are subjected to linear transformation and nonlinear activation processing using the target feature fusion layer to obtain the fused target features, the expression of which is:
[0063] in, Indicates a channel splicing operation; and This represents the trainable parameters in the target feature fusion layer. This represents a non-linear activation function. By fusing intermediate features from different levels, both shallow local texture details and deep cross-region semantic information can be preserved simultaneously, thereby improving the accuracy of subsequent wafer-level and chip-level defect detection.
[0064] Step S208: Based on the target features, perform wafer-level defect detection using the target wafer-level defect detection module in the target defect detection layer to obtain wafer-level defect detection results; Step S208-1: Based on the pooling layer in the target wafer-level defect detection module, the target features are analyzed. Pooling is performed to obtain wafer-level features. ;
[0065] Step S208-2: Based on wafer-level features, the target normalization exponential function Softmax / function in the target wafer-level defect detection module is used to calculate the probability that the wafer object under test belongs to different defect types, thus obtaining the classification probability vector. This allows us to obtain wafer-level defect detection results.
[0066]
[0067] in, and The parameters for the wafer-level classifier are obtained through model training. The wafer-level output can be used to identify overall distribution patterns such as ring-shaped anomalies, edge anomalies, local cluster anomalies, and random anomalies, thereby providing auxiliary basis for process tracking, fault location, and quality analysis.
[0068] Step S209: Based on the target features, perform chip-level defect detection using the target chip-level defect detection module in the target defect detection layer to obtain chip-level defect detection results; In its implementation, this step specifically includes the following steps: Step S209-1: Based on the pooling layer in the target chip-level defect detection module, analyze the regions corresponding to each chip unit in the target features. Pooling is performed separately to obtain the chip-level features corresponding to each chip unit. ; That is, the first The region of each chip in the polar coordinate domain or its corresponding mapped domain is: Then, by analyzing deep features / target features By performing pooling within this region, the first [unit / item] can be obtained. Features of a chip Its expression is:
[0069] in, This indicates pooling processing, preferably average pooling, max pooling, or attention pooling. In this way, spatially distributed features can be compressed into decision feature vectors corresponding to individual chip units, thereby obtaining chip-level features corresponding to each chip unit. .
[0070] Step S209-2: Based on chip-level features, use the target classifier Sigmoid in the target chip-level defect detection module to calculate the defect probability of each chip unit. ; That is, based on the chip-level features of the i-th chip unit. Calculate the first number using a classifier Predicted probability of a chip being defective Its expression is:
[0071] in, and These are the classifier parameters, obtained through model training.
[0072] Step S209-3: Based on the defect probability of each chip unit and a predetermined probability threshold, determine the chip unit with a defect probability greater than the probability threshold as the target chip unit with a defect.
[0073] In this step, the preset judgment threshold is used. This yields the final chip-level determination result:
[0074] in, Indicates the first One chip was identified as a defective chip. Indicates the first The chip was determined to be a normal chip.
[0075] Step S210: Obtain the target detection result based on the wafer-level defect detection result and the chip-level defect detection result.
[0076] The method in this embodiment converts the original wafer image into a polar coordinate image and combines it with annular region segmentation to accurately locate the radial and angular positions of each region. This makes the defect features more regular in polar coordinates, laying the foundation for subsequent feature extraction and effectively improving defect localization accuracy. Secondly, the model employs a targeted radial-angular feature extraction layer, extracting features step-by-step for each annular region. This eliminates the need for complex general feature extraction structures, simplifying the model architecture while focusing on key defect features, reducing redundant computation, and lowering model inference complexity. Furthermore, the target feature fusion layer integrates intermediate features from each layer, fully preserving defect details in each annular region and avoiding feature loss, further improving the accuracy of detection results. Finally, the target defect detection layer simultaneously achieves chip-level and wafer-level defect detection, eliminating the need to build multiple additional detection branches, simplifying the model structure, and simultaneously achieving accurate identification of defects at different levels. This balances detection comprehensiveness and accuracy. The overall solution significantly improves the accuracy and efficiency of wafer defect detection while ensuring the model is simple and easy to deploy.
[0077] In this embodiment, to make chip-level defect detection more reasonable and accurate, and to improve the robustness of the detection results, corresponding probability thresholds can be dynamically determined for different annular regions. That is, before performing chip-level defect detection, the probability thresholds corresponding to each annular region are pre-determined. Specifically, this includes determining the probability thresholds for each annular region based on the background fluctuation level or uncertainty corresponding to each annular region and the baseline probability threshold. Its expression is:
[0078] in, As the baseline threshold, For the first The background fluctuation statistics or uncertainty estimates corresponding to each annular zone This is the adjustment coefficient.
[0079] Therefore, based on the defect probability of each chip unit and a predetermined probability threshold, chip units with a defect probability greater than the probability threshold are determined as target chip units with defects. Specifically, when executing step S209-3, it includes: based on the defect probability of each chip unit and the probability threshold corresponding to the annular region to which each chip unit belongs, determining chip units with a defect probability greater than the probability threshold as target chip units with defects.
[0080] In this embodiment, in order to improve the accuracy of chip-level defect detection results, after completing step S209 and obtaining the defect detection results of each chip unit, several defect clusters can be determined based on each target chip unit, and defect cluster scores can be calculated. Valid defect clusters are then selected based on the scores of each defect cluster, and finally, the target chip units in the valid defect clusters are determined as chip units with defects.
[0081] In other words, consistency analysis can be performed on defect clusters formed by spatially adjacent defective chips. Let the defect cluster be... Then its cluster score can be defined as:
[0082] When the size of a defect cluster and its cluster score simultaneously meet the preset conditions, the cluster can be identified as a valid defect cluster, thereby confirming that each chip unit in the valid defect cluster has a defect. This can reduce the impact of isolated noise or occasional false detections on the overall output results.
[0083] The method in this embodiment converts the original wafer image into a polar coordinate image and combines it with annular region segmentation to accurately locate the radial and angular positions of each region. This makes the defect features more regular in polar coordinates, laying the foundation for subsequent feature extraction and effectively improving defect localization accuracy. Secondly, the model employs a targeted radial-angular feature extraction layer, extracting features step-by-step for each annular region. This eliminates the need for complex general feature extraction structures, simplifying the model architecture while focusing on key defect features, reducing redundant computation, and lowering model inference complexity. Furthermore, the target feature fusion layer integrates intermediate features from each layer, fully preserving defect details in each annular region and avoiding feature loss, further improving the accuracy of detection results. Finally, the target defect detection layer simultaneously achieves chip-level and wafer-level defect detection, eliminating the need to build multiple additional detection branches, simplifying the model structure, and simultaneously achieving accurate identification of defects at different levels. This balances detection comprehensiveness and accuracy. The overall solution significantly improves the accuracy and efficiency of wafer defect detection while ensuring the model is simple and easy to deploy.
[0084] In this embodiment, the target detection model can be pre-trained. The specific model training process is as follows: Step 1: Acquire images of several sample wafers; Step 2: Process the wafer images of each sample to obtain the processed polar coordinate images of the samples; Step 3: Divide the polar coordinate image of the sample into annular regions to obtain the radial and angular positions of the sample corresponding to each annular region; Step 4: Using each initial radial-angular feature extraction layer in the initial detection model, based on the radial and angular positions corresponding to each annular region, extract features from the initial features of the sample corresponding to the polar coordinate image of the sample, or the intermediate features of the sample output by the previous initial radial-angular feature extraction layer, to obtain intermediate features of the sample that contain the features of each annular region corresponding to each initial radial-angular feature extraction layer. Step 5: Use the initial feature fusion layer in the initial detection model to perform feature fusion on the intermediate features of each sample to obtain the fused target features of the sample; Step 6: Based on the initial defect detection layer in the initial detection model, perform chip-level defect detection and wafer-level defect detection on the target features of the sample to obtain the initial detection results; Step 7: Based on the initial detection results, calculate the initial loss, determine whether the initial loss meets the predetermined training stopping condition, and if the predetermined training stopping condition is not met, adjust the parameters in each initial radial-angular feature extraction layer, initial feature fusion layer and initial defect detection layer in the initial detection model to obtain the current detection model, and return to step 4 until the calculated current loss meets the predetermined training stopping condition, and use the current detection model as the target detection model.
[0085] In this step, parameter optimization specifically involves optimizing the local linear transformation operators in each initial radial-angular feature extraction layer, the radial-angular nonlocal operators in each initial radial-angular feature extraction layer, the parameters in the initial feature fusion layer, and the parameters in the normalized exponential function Softmax / function in the initial defect detection layer. The parameters in the Softmax function of the normalized exponential function in the initial defect detection layer. Classifier parameters in the initial defect detection layer and classifier parameters Adjustments and optimizations will be made.
[0086] In this embodiment, the specific process for calculating the loss is as follows: Assume there is a total The chip sample, the first The true label of each chip sample is The predicted probability is The chip-level loss function can then be expressed as a weighted binary cross-entropy function, as follows:
[0087] in, This represents the weight of defective samples, used to alleviate the problem of sample class imbalance.
[0088] Simultaneously setting up wafer-level auxiliary output branches can further introduce wafer-level auxiliary losses. Assume there are a total... There are 10 wafer samples, with 10 categories. , No. The one-hot label for each wafer sample is: The predicted probability is Then the wafer-level auxiliary loss can be expressed as:
[0089] Therefore, the total loss function can be expressed as:
[0090] in, This is a weighting coefficient. When wafer-level auxiliary output is not required, it can be set as follows: .
[0091] After model training is complete, the trained parameters can be embedded into the inference model and deployed on industrial control computers, GPU servers, edge computing devices, or other inspection terminals. During online inspection, steps S201 to S210 are executed sequentially to complete defect detection and result output for the wafer image under test.
[0092] Another embodiment of this application provides a wafer defect detection device, such as... Figure 2 As shown, it includes: Processing module 11 is used to process the original wafer image of the wafer to be tested to obtain a polar coordinate image; The segmentation module 12 is used to divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region. Extraction module 13 is used to extract features from the initial features corresponding to the polar coordinate image or the intermediate features output by the previous target radial-angular feature extraction layer in the target detection model obtained by pre-training, based on the radial and angular positions corresponding to each annular region, to obtain intermediate features corresponding to each target radial-angular feature extraction layer and containing the features of each annular region. The fusion module 14 is used to perform feature fusion on the intermediate features using the target feature fusion layer in the pre-trained target detection model to obtain the fused target features; The detection module 15 is used to perform chip-level defect detection and wafer-level defect detection on the target features based on the target defect detection layer in the pre-trained target detection model, and obtain the target detection result.
[0093] In this embodiment, the processing module is specifically used to: perform image preprocessing on the original wafer image of the wafer to be tested to obtain a preprocessed wafer image; and perform coordinate transformation processing on the preprocessed wafer image to obtain a polar coordinate image.
[0094] In this embodiment, the wafer defect detection device further includes a mapping module, which is used to map the polar coordinate image into initial features using a feature mapping formula.
[0095] In this embodiment, each of the target radial-angular feature extraction layers includes a local linear transformation operator and a radial-angular nonlocal operator. The extraction module is used to: extract local features from the initial feature or the intermediate feature output by the previous target radial-angular feature extraction layer using the local linear transformation operator in the corresponding target radial-angular feature extraction layer, based on the radial and angular positions corresponding to each annular region, to obtain a first feature containing local features of each annular region; extract cross-regional features from the initial feature or the intermediate feature output by the previous target radial-angular feature extraction layer using the radial-angular nonlocal operator in the corresponding target radial-angular feature extraction layer, based on the radial and angular positions corresponding to each annular region, to obtain a second feature containing global features of each annular region; concatenate the first feature and the second feature to obtain a concatenated feature; and perform nonlinear activation processing on the concatenated feature to obtain the intermediate feature.
[0096] In this embodiment, the detection module is specifically used for: performing wafer-level defect detection using the target wafer-level defect detection module in the target defect detection layer based on target features, and obtaining wafer-level defect detection results; performing chip-level defect detection using the target chip-level defect detection module in the target defect detection layer based on target features, and obtaining chip-level defect detection results; and obtaining the target detection result based on the wafer-level defect detection results and the chip-level defect detection results.
[0097] In this embodiment, the detection module is specifically used to: perform pooling processing on the regions corresponding to each chip unit in the target features based on the pooling layer in the target chip-level defect detection module, to obtain chip-level features corresponding to each chip unit; calculate the defect probability of each chip unit having a defect based on each chip-level feature using the target classifier in the target chip-level defect detection module; and determine the chip units with a defect probability greater than the probability threshold as target chip units with defects based on the defect probability of each chip unit and a predetermined probability threshold.
[0098] In this embodiment, the wafer defect detection device further includes: a determination module, which is used to: pre-determine the probability threshold corresponding to each annular region, specifically: determine the probability threshold corresponding to each annular region based on the background fluctuation level and the baseline probability threshold corresponding to each annular region; and the detection module, specifically used to: determine the chip unit with a defect probability greater than the probability threshold as the target chip unit with a defect based on the defect probability of each chip unit and the probability threshold corresponding to the annular region to which each chip unit belongs.
[0099] In this embodiment, by mapping the wafer image to the polar coordinate domain, the radial structural features and angular distribution features of the wafer are expressed more naturally, which is beneficial to improving the model's utilization of the wafer's geometric prior information. By constructing a detection model that includes radial-angular feature extraction layers, the joint modeling of local texture information and cross-regional nonlocal dependencies is realized. Therefore, it has stronger feature expression capabilities and higher detection robustness in the detection of annular anomalies, edge band anomalies, repetitive anomalies, and other complex distribution patterns. It can accurately detect wafer defects, and the model architecture is simple with low training and deployment costs.
[0100] Another embodiment of this application provides a storage medium storing a computer program, which, when executed by a processor, implements the following method steps: Step 1: Process the original wafer image of the wafer to be tested to obtain a polar coordinate image; Step 2: Divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region; Step 3: Using the radial-angular feature extraction layers of each target in the pre-trained target detection model, based on the radial and angular positions corresponding to each annular region, feature extraction is performed on the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, to obtain intermediate features corresponding to each target radial-angular feature extraction layer that contain the features of each annular region. Step 4: Use the target feature fusion layer in the pre-trained target detection model to fuse the intermediate features and obtain the fused target features; Step 5: Based on the target defect detection layer in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the target features to obtain the target detection results.
[0101] The specific implementation process of the above method steps can be found in the embodiments of the above arbitrary wafer defect detection method, which will not be repeated here.
[0102] In this application, by mapping the wafer image to the polar coordinate domain, the radial structural features and angular distribution features of the wafer are expressed more naturally, which is beneficial to improving the model's utilization of the wafer's geometric prior information. By constructing a detection model that includes radial-angular feature extraction layers, the joint modeling of local texture information and cross-regional nonlocal dependencies is realized. Therefore, in the detection of annular anomalies, edge band anomalies, repetitive anomalies and other complex distribution patterns, it has stronger feature expression capabilities and higher detection robustness, and can accurately detect wafer defects. Moreover, the model architecture is simple, and the training and deployment costs are low.
[0103] Another embodiment of this application provides an electronic device, such as... Figure 3 As shown, it includes at least a memory 1 and a processor 2. The memory 1 stores a computer program, and the processor 2 performs the following method steps when executing the computer program in the memory 1: Step 1: Process the original wafer image of the wafer to be tested to obtain a polar coordinate image; Step 2: Divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region; Step 3: Using the radial-angular feature extraction layers of each target in the pre-trained target detection model, based on the radial and angular positions corresponding to each annular region, feature extraction is performed on the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, to obtain intermediate features corresponding to each target radial-angular feature extraction layer that contain the features of each annular region. Step 4: Use the target feature fusion layer in the pre-trained target detection model to fuse the intermediate features and obtain the fused target features; Step 5: Based on the target defect detection layer in the pre-trained target detection model, perform chip-level defect detection and wafer-level defect detection on the target features to obtain the target detection results.
[0104] The specific implementation process of the above method steps can be found in the embodiments of the above arbitrary wafer defect detection method, which will not be repeated here.
[0105] In this application, by mapping the wafer image to the polar coordinate domain, the radial structural features and angular distribution features of the wafer are expressed more naturally, which is beneficial to improving the model's utilization of the wafer's geometric prior information. By constructing a detection model that includes radial-angular feature extraction layers, the joint modeling of local texture information and cross-regional nonlocal dependencies is realized. Therefore, in the detection of annular anomalies, edge band anomalies, repetitive anomalies and other complex distribution patterns, it has stronger feature expression capabilities and higher detection robustness, and can accurately detect wafer defects. Moreover, the model architecture is simple, and the training and deployment costs are low.
[0106] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. Those skilled in the art can make various modifications or equivalent substitutions to this application within the scope and nature of this application, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.
Claims
1. A method for detecting wafer defects, characterized in that, include: The original wafer image of the wafer to be tested is processed to obtain a polar coordinate image; The polar coordinate image is divided into annular regions to obtain the radial and angular positions corresponding to each annular region; Using the radial-angular feature extraction layers of each target in the pre-trained target detection model, feature extraction is performed on the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, based on the radial and angular positions corresponding to each annular region, to obtain intermediate features that contain the features of each annular region corresponding to each radial-angular feature extraction layer of the target. The intermediate features are fused using the target feature fusion layer in the pre-trained target detection model to obtain the fused target features. Based on the target defect detection layer in the pre-trained target detection model, chip-level defect detection and wafer-level defect detection are performed on the target features to obtain target detection results.
2. The method as described in claim 1, characterized in that, The process of processing the original wafer image of the wafer to be tested to obtain a polar coordinate image specifically includes: The original wafer image of the wafer to be tested is preprocessed to obtain the preprocessed wafer image. The preprocessed wafer image is subjected to coordinate transformation to obtain a polar coordinate image.
3. The method as described in claim 1, characterized in that, Before performing feature extraction, the method further includes: The polar coordinate image is mapped to initial features using the feature mapping formula.
4. The method as described in claim 1, characterized in that, Each of the target radial-angular feature extraction layers includes a local linear transformation operator and a radial-angular nonlocal operator; When performing intermediate feature extraction, the radial-angular feature extraction layer for any target specifically includes: Based on the radial and angular positions corresponding to each annular region, the local linear transformation operator is used to extract local features at the current radial and angular positions from the initial features or the intermediate features output by the previous target radial-angular feature extraction layer, thereby obtaining the first feature containing the local features of each annular region. Based on the radial and angular positions corresponding to each annular region, the radial-angular nonlocal operator is used to extract cross-regional features at the current radial and angular positions using the initial features or the intermediate features output by the previous target radial-angular feature extraction layer, thereby obtaining a second feature containing global features of each annular region. The first feature and the second feature are concatenated to obtain the concatenated feature. The splicing features are subjected to nonlinear activation processing to obtain the intermediate features.
5. The method as described in claim 1, characterized in that, The target defect detection layer in the pre-trained target detection model performs chip-level defect detection and wafer-level defect detection on the target features to obtain target detection results, specifically including: Based on the target features, wafer-level defect detection is performed using the target wafer-level defect detection module in the target defect detection layer to obtain wafer-level defect detection results. Based on the target features, chip-level defect detection is performed using the target chip-level defect detection module in the target defect detection layer to obtain chip-level defect detection results. The target detection result is obtained based on the wafer-level defect detection result and the chip-level defect detection result.
6. The method as described in claim 5, characterized in that, The process of performing chip-level defect detection based on target features using the target chip-level defect detection module in the target defect detection layer to obtain chip-level defect detection results specifically includes: Based on the pooling layer in the target chip-level defect detection module, pooling is performed on the regions corresponding to each chip unit in the target features to obtain the chip-level features corresponding to each chip unit. Based on the characteristics of each chip, the defect probability of each chip unit having defects is calculated by using the target classifier in the target chip-level defect detection module. Based on the defect probability of each chip unit and a predetermined probability threshold, chip units with a defect probability greater than the probability threshold are identified as target chip units with defects.
7. The method as described in claim 6, characterized in that, The method further includes: pre-determining the probability threshold corresponding to each annular region, specifically including: Based on the background fluctuation level and the baseline probability threshold corresponding to each annular zone, the probability threshold corresponding to each annular zone is determined. The step of determining chip units with defect probabilities greater than a predetermined probability threshold as target chip units with defects, based on the defect probability of each chip unit and a predetermined probability threshold, specifically includes: Based on the defect probability of each chip unit and the probability threshold corresponding to the annular region to which each chip unit belongs, chip units with a defect probability greater than the probability threshold are identified as target chip units with defects.
8. A wafer defect detection device, characterized in that, include: The processing module is used to process the original wafer image of the wafer to be tested to obtain a polar coordinate image; The segmentation module is used to divide the polar coordinate image into annular regions to obtain the radial and angular positions corresponding to each annular region. The extraction module is used to extract features from the radial-angular feature extraction layers of each target in the pre-trained target detection model, based on the radial and angular positions corresponding to each annular region, and to extract features from the initial features corresponding to the polar coordinate image or the intermediate features output by the previous radial-angular feature extraction layer, to obtain intermediate features corresponding to each radial-angular feature extraction layer of the target that contain the features of each annular region. The fusion module is used to perform feature fusion on the intermediate features using the target feature fusion layer in the pre-trained target detection model to obtain the fused target features. The detection module is used to perform chip-level defect detection and wafer-level defect detection on the target features based on the target defect detection layer in the pre-trained target detection model, and obtain the target detection results.
9. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the wafer defect detection method according to any one of claims 1-7.
10. An electronic device, characterized in that, It includes at least a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program in the memory, implements the steps of the wafer defect detection method according to any one of claims 1-7.