State control circuit and control method thereof

Abstract

The application discloses a state control circuit and a control method thereof, and relates to the technical field of electronic information. The state control circuit comprises a controller, a state machine connected with the controller, a conversion circuit, a first conversion circuit and a second conversion circuit. The state machine is used for providing state codes to the conversion circuit under the control of the controller and storing the state codes returned by the conversion circuit into a state register of the state machine. The first conversion circuit sets the state codes to preset states between two states. Since the preset states jump by one bit relative to the two states, the metastable state phenomenon during state switching can be eliminated. The second conversion circuit converts the state codes of the state machine into a predetermined format. Since the state codes in the predetermined format jump by one bit during state switching, the metastable state phenomenon during state switching can be eliminated.

Description

Technical Field

[0001] This application relates to the field of electronic information technology, and in particular to state control circuits and control methods thereof. Background Technology

[0002] In the design of digital circuit state machines, some encoding schemes have the following drawbacks: during state transitions, multiple bits of adjacent states may flip simultaneously, which can easily cause asynchronous flipping timing of the state register, leading to circuit race conditions and metastability issues, and consequently causing data read / write errors or loss. Furthermore, they consume a lot of resources, making them unsuitable for high-speed digital circuit scenarios, and their overall security and flexibility are insufficient, failing to meet the requirements for high-precision and high-reliability timing control. Summary of the Invention

[0003] This application provides a state control circuit and a control method thereof to at least solve the metastability problem in related technologies.

[0004] This application provides a state control circuit, including: a controller; a state machine connected to the controller, used to provide a state code to a transition circuit under the control of the controller, and store the state code returned by the transition circuit in the state register of the state machine; and the aforementioned transition circuit, including at least one of a first transition circuit and a second transition circuit; wherein, the first transition circuit is connected to the state machine and the controller, used to, under the control of the controller, first switch the state code provided by the state machine from a first state to a preset state and return it to the state machine, and then switch the state code from the preset state to a second state and return it to the state machine, wherein the state code of the preset state undergoes a one-bit transition relative to both the state code of the first state and the state code of the second state; the second transition circuit is connected to the state machine and the controller, used to, under the control of the controller, convert the state code of the first state or the second state provided by the state machine into a predetermined format, and return the state code of the predetermined format to the state machine, wherein the state code of the predetermined format undergoes a one-bit transition when switching from the first state to the second state.

[0005] This application also provides a control method for the aforementioned state control circuit. The control method includes: a state machine, under the control of a controller, provides a state code to a transition circuit, the transition circuit including at least one of a first transition circuit and a second transition circuit; the first transition circuit, under the control of the controller, switches the state code provided by the state machine from a first state to a preset state and returns it to the state machine, then switches the state code from the preset state to a second state and returns it to the state machine, wherein the state code of the preset state undergoes a one-bit transition relative to both the state code of the first state and the state code of the second state; or, the second transition circuit, under the control of the controller, converts the state code of the first state or the second state provided by the state machine into a predetermined format and returns the predetermined format state code to the state machine, wherein the predetermined format state code undergoes a one-bit transition when switching from the first state to the second state; and the state machine, under the control of the controller, stores the state code returned by the transition circuit in the state register of the state machine.

[0006] According to embodiments of this application, at least one of a first transition circuit and a second transition circuit is provided in the state control circuit. Each of the first and second transition circuits can eliminate transition conflicts (i.e., metastability) during state machine transitions between adjacent states using different mechanisms under the control of the controller. Specifically, the first transition circuit sets the state code to a preset state between two states. Since the preset state undergoes a one-bit transition relative to both states, the metastability during state transitions can be eliminated. The second transition circuit converts the state code of the state machine into a predetermined format. Since the predetermined format state code undergoes a one-bit transition during state transitions, the metastability during state transitions can also be eliminated. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of state machine state transitions in related technologies.

[0009] Figure 2 This is a schematic diagram of the state control circuit according to an embodiment of this application.

[0010] Figure 3 This is a schematic diagram of a state control circuit based on a first switching circuit according to an embodiment of this application.

[0011] Figure 4 This is a schematic diagram of a state control scheme based on a first switching circuit according to an embodiment of this application.

[0012] Figure 5 This is a schematic diagram of the status register in an embodiment of this application.

[0013] Figure 6 This is a schematic diagram of a signal synchronization circuit according to an embodiment of this application.

[0014] Figure 7 This is a schematic diagram of the delay sub-circuit of an embodiment of this application.

[0015] Figure 8 This is a schematic diagram of the switching sub-circuit of an embodiment of this application.

[0016] Figure 9 This is a schematic diagram of a state control circuit based on the second switching circuit according to an embodiment of this application.

[0017] Figure 10 This is a schematic diagram of a state control scheme based on a second switching circuit according to an embodiment of this application.

[0018] Figure 11 This is a schematic diagram of a state control circuit according to an embodiment of this application.

[0019] Figure 12 This is a schematic diagram of the status register in an embodiment of this application.

[0020] Figure 13 This is a schematic diagram of a status register according to an embodiment of this application.

[0021] Figure 14 This is a schematic diagram of the second conversion circuit according to an embodiment of this application.

[0022] Figure 15 This is a schematic diagram of a state control circuit according to another embodiment of this application.

[0023] Figure 16 This is a schematic diagram of a state control scheme based on a mode selection circuit according to an embodiment of this application.

[0024] Figure 17 This is a schematic diagram of loading a configuration file for a digital circuit according to an embodiment of this application.

[0025] Figure 18 This is a schematic diagram of a state control circuit according to another embodiment of this application.

[0026] Figure 19 This is a schematic diagram of a switching sub-circuit based on the third scheme in an embodiment of this application.

[0027] Figure 20 This is a schematic diagram of the second conversion circuit based on the third scheme in an embodiment of this application.

[0028] Figure 21 This is a schematic diagram of a digital circuit according to an embodiment of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0030] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] In the field of digital circuit design, state machines belong to sequential logic circuits and are composed of flip-flops, combinational logic, and other circuits. They complete the system's function by relying on state transitions and digital logic outputs. State machines are commonly used in programmable logic devices such as FPGAs (Field-Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices). When designing a state machine, each state needs to be encoded. State encoding methods typically include binary encoding, one-hot encoding, and Gray code. The expected function of the system is achieved through state transitions. One-hot encoding is a commonly used state encoding method. Its core principle is to use a t-bit state register to encode t states. It has a simple structure, is suitable for medium-scale and combinational logic circuits, and is widely used in the design of conventional sequential logic systems.

[0032] One-hot encoding is a single-bit valid encoding. It uses a t-bit state register to encode t states. Only one bit of each state is valid. Taking 5 states as an example, the encoding of each state is shown in Table 1.

[0033] Table 1

[0034]

[0035] This encoding method is suitable for combinational logic circuits and medium-scale circuits, but its disadvantage is that it requires a significant amount of combinational logic resources. There is a two-bit difference between adjacent states; that is, two adjacent bits in the one-hot encoded state register differ. For example, during the transition from state 1 to state 2, two bits will differ: bit '1' in state 1 will jump to bit '0', and bit '0' in state 1 will jump to bit '1'. The same situation exists for other adjacent state transitions. Because one-hot encoding carries the risk of asynchronous flipping of the two registers, it can lead to circuit races and hazards, resulting in metastability and causing errors or even data loss during read / write operations. Therefore, the one-hot encoding design for state machines in related technologies is unsuitable for high-speed digital circuit scenarios, exhibiting poor overall security and flexibility.

[0036] like Figure 1 As shown, the state machine set up in the FPGA can encode p states using a state register. After the FPGA is powered on and reset, the state machine enters state 1, and the state code stored in the state machine is state 1 (000…0001). When the FPGA completes data reading, service processing, and other operations, and the first trigger signal is valid, the state machine is controlled to enter state 2 (000…0010). Similarly, when the (p-1)th trigger signal is valid, the state machine is controlled to enter state p (100…0000). During the transition between every two adjacent states, the FPGA processes the relevant service, and when the corresponding trigger signal is valid, the state machine enters the next state, until it returns to state 1, and then the state transition cycle repeats. When the state machine uses one-hot encoding to encode the FPGA states, the state code stored in the state machine has two different bits when transitioning from the first state (e.g., state 1) to the second state (e.g., state 2). When the state machine is connected to a high-speed clock, metastability of the signal may occur.

[0037] In some related technologies, the fractional part measurement circuit applied to high-resolution time-to-digital converters includes one-hot code decoding logic, employing differential delay line technology, two-stage sampling to eliminate metastability and glitches, one-hot code generation technology, and one-hot code decoding technology. The overall circuit of this scheme uses a two-layer sampling circuit. The second-layer signal sampling circuit delays the sampling of the output of the first-layer signal sampling circuit by a phase difference, thereby avoiding metastability and glitches from the trigger output. This scheme avoids metastability through delayed sampling; however, two-stage sampling only reduces the probability of metastability, but cannot completely eliminate it.

[0038] In some related technologies, the conversion method from one-hot code to sequential binary code includes: obtaining the code to be processed; initializing the code to be processed as one-hot code; using the logical OR value of the j-th bit of the one-hot code corresponding to the i-th bit in the sequential binary code as the value of the i-th bit according to a preset conversion formula; and sequentially determining the values ​​of all i to obtain the sequential binary code. This scheme uses an OR gate conversion circuit to convert one-hot code to sequential binary code. Since the binary code involves multiple bits, metastability cannot be avoided, and it may even translate the unstable signals of the metastability into erroneous data.

[0039] Figure 2 This is a schematic diagram of the state control circuit according to an embodiment of this application.

[0040] like Figure 2 As shown, the state control circuit includes a controller 1, a state machine 2, and a transition circuit 3. The transition circuit 3 includes at least one of a first transition circuit 31 and a second transition circuit 32.

[0041] State machine 2 is connected to controller 1 and is used to provide state codes to conversion circuit 3 under the control of controller 1, and to store the state codes returned by conversion circuit 3 into the state register of state machine 2.

[0042] The first conversion circuit 31 is connected to the state machine 2 and the controller 1. Under the control of the controller 1, it first switches the state code provided by the state machine 2 from the first state to the preset state and returns it to the state machine 2. Then, it switches the state code from the preset state to the second state and returns it to the state machine 2. The state code of the preset state undergoes a one-bit change relative to the state code of the first state and the state code of the second state.

[0043] The second conversion circuit 32 is connected to the state machine 2 and the controller 1. Under the control of the controller 1, it converts the state code of the first state or the state code of the second state provided by the state machine 2 into a predetermined format and returns the state code of the predetermined format to the state machine 2. The predetermined format state code undergoes a bit transition when switching from the first state to the second state.

[0044] State machine 2 can be a digital circuit state machine, belonging to sequential logic circuits. It can rely on the clock signal of controller 1 as its operating cycle, and use the state register of state machine 2 to store the current working state of the circuit system. It can also switch between different states according to preset rules. The first state stored in state machine 2 can be the current working state of the circuit system, and the second state received and stored by state machine 2 can be the next working state that the circuit system will be in.

[0045] When a state machine uses one-hot encoding, the state code of the state machine switches directly from the first state to the second state, which involves two different bits. The state register of the state machine needs to make two-bit transitions, which can lead to metastability due to asynchronous transitions.

[0046] The controller 1 can control the first conversion circuit 31 to switch the state code of the first state provided by the state machine 2 to the state code of the preset state and return it to the state machine 2. The preset state and the first state have one different bit, so the state register of the state machine 2 only needs to perform one bit change; then switch the state code of the preset state to the state code of the second state and return it to the state machine 2. The second state and the preset state have one different bit, so the state register of the state machine 2 only needs to perform one bit change. This can effectively eliminate metastability and is suitable for the case where the state machine 2 is connected to an external high-speed clock.

[0047] The controller 1 can also control the second conversion circuit 32 to convert the state code of the first state provided by the state machine 2 into a state code of the first state in a predetermined format and return it to the state machine 2. The controller 1 can also convert the state code of the second state provided by the state machine 2 into a state code of the second state in a predetermined format and return it to the state machine 2. The state code of the predetermined format of the state machine 2 switches from the first state to the second state. The state code of the first state in a predetermined format and the state code of the second state in a predetermined format have one different bit, which can effectively eliminate metastability.

[0048] According to embodiments of this application, at least one of a first transition circuit and a second transition circuit is provided in the state control circuit. Each of the first and second transition circuits can eliminate transition conflicts (i.e., metastability) during state machine transitions between adjacent states using different mechanisms under the control of the controller. Specifically, the first transition circuit sets the state code to a preset state between two states. Since the preset state undergoes a one-bit transition relative to both states, the metastability during state transitions can be eliminated. The second transition circuit converts the state code of the state machine into a predetermined format. Since the predetermined format state code undergoes a one-bit transition during state transitions, the metastability during state transitions can also be eliminated.

[0049] Figure 3 This is a schematic diagram of a state control circuit based on a first switching circuit according to an embodiment of this application.

[0050] like Figure 3 As shown, the first conversion circuit 31 includes a delay sub-circuit 311 and a switching sub-circuit 312.

[0051] The delay sub-circuit 311 receives control signals and trigger signals from controller 1, delays the trigger signals according to the control signals, and obtains a transition signal. The switching sub-circuit 312 is connected to the delay sub-circuit 311 and the state machine 2, and receives the state code of the first state from the state machine 2. Under the control of the trigger signal from controller 1, it switches the received state code from the first state to a preset state and returns the state code of the preset state to the state machine 2. Under the control of the transition signal from the delay sub-circuit 311, it switches the state code from the preset state to the second state and returns the state code of the second state to the state machine 2. In the preset state, all bits of the state code are zero.

[0052] According to an embodiment of this application, a preset state of all '0's is added to the state code. During the state machine operation, during the transition from the first state to the second state, after the circuit system has completed relevant data read / write, signal processing, and other operations, the controller generates a trigger signal. Upon receiving the trigger signal, the first transition circuit controls the first state to jump to the all '0's state, then generates a transition signal to the second state, and then controls the transition from the all '0's state to the second state. During the transition from the first state to the all '0's state and from the all '0's state to the second state, only one bit differs, preventing signal race conditions.

[0053] Figure 4 This is a schematic diagram of a state control scheme based on a first switching circuit according to an embodiment of this application.

[0054] like Figure 4 As shown, a state machine can use a state register to encode p states.

[0055] The preset state for the state machine's state encoding can be state 0, where all bits of the state encoding for state 0 are 0. After the digital circuit is powered on and reset, the state machine enters state 1, and the state encoding stored in the state machine is state 1.

[0056] Combination Figure 3In the sub-process of state 1, the digital circuit performs data reading and service processing operations. When the digital circuit completes these operations, the controller issues the first trigger signal. Under the control of the first trigger signal, the switching sub-circuit 312 switches the state code provided by the state machine from state 1 to state 0 and returns it to the state machine. The delay sub-circuit 311 delays the first trigger signal to generate the first transition signal. Under the control of the first transition signal, the switching sub-circuit 312 switches the state code from state 0 to state 2 and returns it to the state machine. In the sub-process of state 2, the digital circuit performs data reading and service processing operations. When the digital circuit completes these operations, the controller issues the second trigger signal. Under the control of the second trigger signal, the switching sub-circuit 312 switches the state code provided by the state machine from state 2 to state 0 and returns it to the state machine. The delay sub-circuit 311 delays the second trigger signal to generate the second transition signal. Under the control of the second transition signal, the switching sub-circuit 312 switches the state code from state 0 to state 3 and returns it to the state machine. This process continues in a similar manner from state 3 to state p. In the sub-process of state p, the digital circuit performs data reading, service processing, and other operations. When the digital circuit completes these operations, the controller issues the p-th trigger signal. Under the control of the p-th trigger signal, the switching sub-circuit 312 switches the state code provided by the state machine from state p to state 0 and returns it to the state machine. The delay sub-circuit 311 delays the p-th trigger signal to generate the p-th transition signal. Under the control of the p-th transition signal, the switching sub-circuit 312 switches the state code from state 0 to state 1 and returns it to the state machine. This completes one business processing cycle of the state machine, and the state machine jumps back to the initial state 1. The state machine then continuously loops to start the next business processing cycle until the digital circuit terminates the operation of the state machine.

[0057] When the state machine uses one-hot encoding to encode the state of the digital circuit, the first transition circuit, under the control of the trigger signal, switches the state code provided by the state machine from the first state (e.g., state 1) to the preset state (e.g., state 0), with one different bit; then, under the control of the transition signal, it switches the state code from the preset state (e.g., state 0) to the second state transition (e.g., state 2) and returns it to the state machine, with one different bit. This can effectively eliminate metastability and is suitable for situations where the state machine is connected to an external high-speed clock.

[0058] like Figure 3As shown, controller 1, state machine 2, and first transition circuit 31 can be mounted on a digital circuit, such as a field-programmable gate array (FPGA). The FPGA can also include a data processing module 4 and a cryptographic module 5. Controller 1 can transmit data to data processing module 4, which in turn transmits the data to cryptographic module 5. Cryptographic module 5 encrypts the data and then transmits it back to data processing module 4. In one example, the data processing module can receive data transmitted from the host computer to controller 1 via the data bus and read the status code in status register 21 to obtain the state of state machine 2. It then processes the data according to different states. For example, in the subprocess of state 1, the FPGA performs a data reading operation; in the subprocess of state 2, the FPGA performs a key reading operation; in the subprocess of state 3, the FPGA sends the data and key to the cryptographic machine; in the subprocess of state 4, it waits for the cryptographic machine to complete the data encryption; in the subprocess of state 5, the FPGA returns the encrypted data to controller 1 via the data bus, and controller 1 then transmits the data back to the host computer. In one example, controller 1 can be an MCU (Microcontroller Unit). The MCU, FPGA, and cryptographic machine constitute the main components of the hardware device, which can interact with the host computer to implement data encryption / decryption functions. The hardware device can be a PCIe (Peripheral Component Interconnect Express) board. The host computer can be the application software on the host side.

[0059] In one example, the digital circuit can be a programmable logic device such as an FPGA or CPLD. During the transition from state 0 to state 1, since the FPGA system has already processed the relevant data and services, there will be no data loss or read / write anomalies caused by metastability. Similarly, during the transition from state 0 to state 2, if the state machine has service processing, there will be no data processing anomalies caused by metastability.

[0060] In one example, the delay sub-circuit 311 delays the trigger signal to generate a transition signal, and the delay duration can be 1 to p clock cycles.

[0061] According to an embodiment of this application, by adding state 0 as a preset state, during the operation of the state machine, the first transition circuit can control the transition from the first state to state 0, and then control the transition from state 0 to the second state. During the transitions from the first state to state 0 and from state 0 to the second state, only one bit differs, thus preventing signal race conditions and effectively solving the metastability problem inherent in state machines using one-hot codes.

[0062] The control logic of the state control scheme based on the first conversion circuit is simple and does not occupy additional storage space.

[0063] like Figure 3 As shown, according to an embodiment of this application, the state machine 2 includes a state register 21 and a signal synchronization circuit 22. The state register 21 is connected to the switching sub-circuit 312 and the controller 1, and is used to store the state code returned by the switching sub-circuit 312 under the control of a clock signal from the controller 1, and to provide the stored state code to the switching sub-circuit 312. The signal synchronization circuit 22 is connected to the delay sub-circuit 311, the switching sub-circuit 312, and the controller 1, and is used to receive a clock signal, a control signal, and a trigger signal from the controller 1, and under the control of the clock signal, to provide the control signal and the trigger signal to the delay sub-circuit 311, and to provide the trigger signal to the switching sub-circuit 312.

[0064] In one example, controller 1 can be connected to state machine 2 via multiple external pins, transmitting clock signals, reset signals, control signals, and trigger signals. The clock and reset signals can also be input to a first transition circuit to synchronize the clock between the state machine and the first transition circuit.

[0065] The signal synchronization circuit 22 can convert the asynchronous control signal and trigger signal output from the controller 1 into a synchronous signal. It samples the clock signal once at the rising edge, converts it into a clock-synchronized control signal and trigger signal, and inputs the clock-synchronized control signal and trigger signal to the delay sub-circuit 311 of the first conversion circuit 31, and inputs the clock-synchronized trigger signal to the switching sub-circuit 312 of the first conversion circuit 31.

[0066] The status register 21 can store the value of each bit of the status code of the state machine 2, and output the status code of the first state of the state machine 2 to the switching sub-circuit 312 of the first conversion circuit 31, receive and store the status code of the preset state from the switching sub-circuit 312, and receive and store the status code of the second state from the switching sub-circuit 312.

[0067] According to an embodiment of this application, the clock signal is derived from the master clock frequency of the digital circuit.

[0068] According to the embodiments of this application, the state machine stores state codes through a state register and a signal synchronization circuit, thereby maintaining the state information within a clock cycle. Under the control of the clock synchronization control signal and the trigger signal, the stored state codes can be provided to the switching sub-circuit, which can avoid faults such as false jumps, abnormal jumps, and state jams caused by timing misalignment, and greatly improve the accuracy and stability of state switching.

[0069] According to an embodiment of this application, the status code is an N-bit code.

[0070] Figure 5 This is a schematic diagram of the status register in an embodiment of this application.

[0071] like Figure 5 As shown, in one example, N=5, and the state code is 5 bits. The state register currently stores the 5-bit state code of the first state {One_hot_state[0], One_hot_state[1], One_hot_state[2], One_hot_state[3], One_hot_state[4]}. The state register receives the 5-bit state code of the next state from the switching sub-circuit {One_hot_next_state[0], One_hot_next_state[1], One_hot_next_state[2], One_hot_next_state[3], One_hot_next_state[4]}. The 5-bit state code of the next state from the switching sub-circuit received by the state register can be the 5-bit state code of the preset state or the 5-bit state code of the second state.

[0072] In one example, the status register may include five status register flip-flops 211 and one status register NOT gate 212.

[0073] The nth output of the status register, i.e., the output Q1 of the nth status register flip-flop 211, outputs the nth bit of the 5-bit status code for the first state. For example, the first output of the status register, i.e., the output Q1 of the first status register flip-flop 211, outputs the first bit of the 5-bit status code for the first state. The fifth output of the status register, i.e., the output Q1 of the fifth status register flip-flop 211, outputs the fifth bit of the 5-bit status code for the first state.

[0074] The nth input of the status register, i.e., input D1 of the nth status register flip-flop 211, receives the nth bit of the 5-bit status code of the preset state from the switching sub-circuit, and also receives the nth bit of the 5-bit status code of the second state from the switching sub-circuit. The clock input clk of the five status register flip-flops 211 receives the clock signal CLK from the controller. The clear input R of the five status register flip-flops 211 receives the reset signal RSTn from the controller through the status register NOT gate 212.

[0075] According to embodiments of this application, both the control signal and the trigger signal are N signals.

[0076] Figure 6 This is a schematic diagram of a signal synchronization circuit according to an embodiment of this application.

[0077] In one example, there are 5 control signals and 5 trigger signals.

[0078] like Figure 6 As shown, the signal synchronization circuit may include five trigger signal synchronization flip-flops 221, five control signal synchronization flip-flops 222, and one signal synchronization NOT gate 223. The trigger signal synchronization flip-flops 221 may be 1-bit D flip-flops with a clear input, and the control signal synchronization flip-flops 222 may be 4-bit D flip-flops with a clear input.

[0079] The asynchronous control signals {Cnt_1'[3..0], Cnt_2'[3..0], Cnt_3'[3..0], Cnt_4'[3..0], Cnt_5'[3..0]} and asynchronous trigger signals {trig_sig_1', trig_sig_2', trig_sig_3', trig_sig_4', trig_sig_5'} output by the controller are not aligned with the edges of the clock signal CLK. The asynchronous control signals and asynchronous trigger signals are converted into synchronous control signals {Cnt_1', trig_sig_2', trig_sig_3', trig_sig_4', trig_sig_5'}. [3..0], Cnt_2[3..0], Cnt_3[3..0], Cnt_4[3..0], Cnt_5[3..0]} and synchronized trigger signals {trig_sig_1, trig_sig_2, trig_sig_3, trig_sig_4, trig_sig_5} are used to input the synchronized control signal and synchronized trigger signal to the delay sub-circuit of the first conversion circuit, and input the clock synchronized trigger signal to the switching sub-circuit of the first conversion circuit, so as to realize the clock synchronization between the state machine and the first conversion circuit. For example, the signal synchronization circuit can obtain the synchronized control signal and synchronized trigger signal after sampling once at the rising edge of the clock signal CLK.

[0080] The input D2 of the nth trigger signal synchronous flip-flop 221 receives the asynchronous nth trigger signal from the controller, and the output Q2 of the nth trigger signal synchronous flip-flop 221 outputs the synchronous nth trigger signal to the first conversion circuit. The clock input clk of the 5-trigger signal synchronous flip-flop 221 receives the clock signal CLK from the controller. The clear input R of the 5-trigger signal synchronous flip-flop 221 receives the reset signal RSTn from the controller through the signal synchronization NOT gate 223.

[0081] The input terminal D3[3..0] of the nth control signal synchronous flip-flop 222 receives the asynchronous nth control signal from the controller, and the output terminal Q3[3..0] of the nth control signal synchronous flip-flop 222 outputs the synchronous nth control signal to the first conversion circuit. The clock terminal clk of the five control signal synchronous flip-flops 222 receives the clock signal CLK from the controller. The clear terminal R of the five control signal synchronous flip-flops 222 receives the reset signal RSTn from the controller through the signal synchronization NOT gate 223.

[0082] According to an embodiment of this application, the delay sub-circuit includes N timers, wherein: the clock terminal of the nth timer is connected to the controller for receiving a clock signal from the controller; the first input terminal of the nth timer is connected to the signal synchronization circuit for receiving the nth of N trigger signals; the second input terminal of the nth timer is connected to the signal synchronization circuit for receiving the nth of N control signals; and the output terminal of the nth timer is connected to the transition signal terminal of the nth control unit for outputting the nth of N transition signals.

[0083] Figure 7 This is a schematic diagram of the delay sub-circuit of an embodiment of this application.

[0084] like Figure 7 As shown, the delay sub-circuit includes five timers 3111. The output transition signal of the delay sub-circuit can be represented as {jmp_sig_1, jmp_sig_2, jmp_sig_3, jmp_sig_4, jmp_sig_5}.

[0085] The clock input of the nth timer 3111 is connected to the controller to receive the clock signal CLK from the controller. The first input D3 of the nth timer 3111 is connected to the signal synchronization circuit to receive the nth of N trigger signals. The second input C[3..0] of the nth timer 3111 is connected to the signal synchronization circuit to receive the nth of N control signals. The output Q3 of the nth timer 3111 is connected to the transition signal input of the nth control unit to output the nth of N transition signals.

[0086] In one example, the nth timer 3111 can output the value of the nth trigger signal received at its first input D3 after a delay of 1 to 15 clock cycles, based on the specific input value of the nth control signal received at its second input C[3..0]. For example, when the first control signal is 0001, the second input C[3..0] of the first timer 3111 is "0001", with a delay of 1 clock cycle. When the first trigger signal is '1', the state machine transitions from state 1 to state 0; simultaneously, the first timer 3111 outputs the first trigger signal after a delay of 1 clock cycle, i.e., the first transition signal is '1'. For example, when the first control signal is 1111, the second input terminal C[3..0] of the first timer 3111 is "1111", indicating that the first trigger signal is delayed by 15 clock cycles.

[0087] The five timers 3111 allow users to set the delay period for each state subprocess according to the actual business processing of the state machine. That is, during the transition from state 0 to the next state, if the state machine does not need to process business, a shorter delay period (such as 1 clock cycle) can be set; when the state machine needs to process other business, a longer delay period (such as 10 to 15 clock cycles) can be set to give the state machine enough time to complete the business before transitioning to the next state.

[0088] According to embodiments of this application, the extension time corresponding to the control signal can be set as needed, reserving buffer time to avoid action failures and logic misjudgments caused by insufficient timing, thereby enhancing overall operational stability. Configuring the extension duration corresponding to the control signal as needed also allows for flexible adaptation to various working sequences and application scenarios, enabling timing adjustments without hardware modifications and simplifying debugging and maintenance.

[0089] According to an embodiment of this application, the switching sub-circuit includes N control units, wherein the input terminal of the nth control unit is connected to the nth output terminal of the status register, and is used to receive the nth bit of the N-bit status code from the status register; the output terminal of the nth control unit is connected to the (n+1)th input terminal of the status register, and is used to output the (n+1)th bit of the N-bit status code to the status register, where n=1, 2, …, N, and when n=N, n+1=0; the trigger signal terminal of the nth control unit is connected to the signal synchronization circuit, and is used to receive the nth trigger signal; the transition signal terminal of the nth control unit is connected to the delay sub-circuit, and is used to receive the nth transition signal; the nth control unit is used to convert the nth bit of the status code into zero and provide it to the (n+1)th input terminal of the status register under the control of the nth trigger signal; and to restore the nth bit of the status code to 1 and provide it to the (n+1)th input terminal of the status register under the control of the nth transition signal.

[0090] Figure 8 This is a schematic diagram of the switching sub-circuit of an embodiment of this application.

[0091] like Figure 8 As shown, the switching sub-circuit includes five control units 3121.

[0092] For example, the input terminal of the first control unit 3121 is connected to the first output terminal of the status register, and is used to receive the first bit of the 5-bit status code of the first state from the status register. The output terminal of the first control unit 3121 is connected to the second input terminal of the status register, and is used to output 0 of the 5-bit status code of the preset state and the second bit of the 5-bit status code of the second state to the status register.

[0093] The trigger signal terminal of the first control unit 3121 is connected to the signal synchronization circuit to receive the first trigger signal for synchronization; the transition signal terminal of the first control unit 3121 is connected to the delay sub-circuit to receive the first transition signal; under the control of the first trigger signal, the first control unit 3121 converts the first bit of the 5-bit status code of the first state to zero to form the first bit of the 5-bit status code of the preset state, and provides the first bit of the 5-bit status code of the preset state to the second input terminal of the status register; under the control of the first transition signal, the second bit of the 5-bit status code of the preset state is restored to 1 to form the second bit of the 5-bit status code of the second state, and provides the second bit of the 5-bit status code of the second state to the second input terminal of the status register.

[0094] According to an embodiment of this application, the switching sub-circuit, under the control of a trigger signal, first converts the 5-bit state code of the first state received from the state register into state 0, and then, under the control of a transition signal, converts state 0 into the 5-bit state code of the second state. The input and output of the switching sub-circuit are transmitted bit by bit according to a preset misalignment rule. This bit-by-bit processing circuit logic simplifies the design of the back-end decoding, recognition, and execution circuits, reducing hardware complexity.

[0095] According to an embodiment of this application, the control unit includes: a first OR gate, the first input of which is used to receive an inverted signal of a reset signal from a controller, and the second input of which serves as a trigger signal terminal of the control unit; a first flip-flop, the reset terminal of which is connected to the output of the first OR gate, the input of which serves as an input terminal of the control unit, and the clock terminal of which is used to receive a clock signal from the controller; and a second OR gate, the first input of which is connected to the output of the first flip-flop, the second input of which serves as a switching signal terminal of the control unit, and the output of which serves as an output terminal of the control unit.

[0096] like Figure 8 As shown, the control unit 3121 includes a first OR gate OR_1, a first flip-flop D_FF, and a second OR gate OR_2. The first flip-flop D_FF can be a 1-bit D flip-flop with a clear input.

[0097] The first input of the first OR gate OR_1 can receive the inverted reset signal from the controller via the reset NOT gate 3122. The second input of the first OR gate OR_1 serves as the trigger signal terminal of the control unit 3121. The reset terminal R0 of the first flip-flop D_FF is connected to the output of the first OR gate OR_1. The input D4 of the first flip-flop D_FF serves as the input of the control unit 3121. The clock terminal clk of the first flip-flop D_FF is used to receive the clock signal CLK from the controller. The first input of the second OR gate OR_2 is connected to the output Q4 of the first flip-flop D_FF. The second input of the second OR gate OR_2 serves as the switching signal terminal of the control unit 3121. The output of the second OR gate OR_2 serves as the output of the control unit 3121.

[0098] The reset input R0 of the first flip-flop D_FF is also the clear input of the D flip-flop. When the reset input R0 of the first flip-flop D_FF is valid (R0='1'), the output Q4 of the first flip-flop D_FF is '0'; when the reset input R0 of the first flip-flop D_FF is invalid (R0='0'), when the clock signal CLK is valid (i.e., when the rising edge or falling edge of the clock signal CLK arrives), the value of the output Q4 of the first flip-flop D_FF is equal to the value of the input D4 of the first flip-flop D_FF, that is, Q4=D4.

[0099] According to the embodiments of this application, a trigger signal is received through a first OR gate, and a transition signal is received through a second OR gate, enabling the first flip-flop to switch the working mode. Under the control of the trigger signal, the value of the bit corresponding to the state code is first cleared to zero. After a delay, under the control of the transition signal, the value of the bit corresponding to the state code is output normally. Two independent target signals are output in different working stages, which can reduce wiring area, reduce power consumption and hardware cost, and at the same time, the circuit is highly versatile and easy to integrate.

[0100] The following combination Figure 8 Explain in detail the process of switching sub-circuit control state machine state transitions.

[0101] When the digital circuit is powered on and reset, the reset signal RSTn is '0'. After passing through the reset NOT gate 3122, it becomes '1', causing the first OR gate OR_1 in the five control units 3121 to output '1'. Therefore, the reset terminal R0 of the first flip-flop D_FF in the five control units 3121 is '1', which makes the output terminal Q4 of the first flip-flop D_FF in the five control units 3121 '0'. At this time, since the transition signal is invalid (low level), the status code outputs the invalid state "00000".

[0102] When the digital circuit ends the reset state, the controller controls the state machine to enter state 1. At this time, the reset signal RSTn is '1', which becomes '0' after passing through the reset NOT gate 3122. The 5-bit state code of state 1 is "00001". After completing data read / write, signal processing and other related operations in state 1, the controller controls the first trigger signal to change from an invalid state (low level) to an valid state (high level), that is, the first trigger signal trig_sig_1 is '1'. At this time, the first OR gate OR_1 of the first control unit 3121 outputs '1', making the reset terminal R0 of the first flip-flop D_FF of the first control unit 3121... The value is '1', making the output Q4 of the first flip-flop D_FF of the first control unit 3121 '0'. At the same time, in the subprocess of state 1, other trigger signals are invalid (low level), causing the first OR gate OR_1 of other control units 3121 to output '0', and the reset terminal R0 of the first flip-flop D_FF of other control units 3121 to be '0', which is an invalid state. Therefore, when the clock signal CLK is valid, the output Q4 of the first flip-flop D_FF of other control units 3121 is equal to the value of the input D4 of the first flip-flop D_FF of other control units 3121, and the output Q4 of the first flip-flop D_FF of other control units 3121 all output '0'. Thus, the state machine jumps from state 1 to state 0.

[0103] Simultaneously, after a delay of at least one clock cycle, the first timer 3111 changes the first transition signal from an invalid state (low level) to an valid state (high level), i.e., the first transition signal jmp_sig_1 becomes '1', causing the second OR gate OR_2 of the first control unit 3121 to output '1', thus making the second bit of the 5-bit state code '1'. At this time, since the other transition signals are invalid (low level), and the output Q of the first flip-flop D_FF of the other control unit 3121 is '0', the second OR gate OR_2 of the other control unit 3121 outputs '0'. Therefore, the combined value of the 5 state code bits is "00010", which is the 5-bit state code of the next state (state 2). The 5-bit state code of state 2 is fed back to the input of the state machine's state register. The data processing module can obtain the change of state machine state by reading the 5-bit state code of state 2, i.e., the transition from state 0 to state 2.

[0104] The transition steps from state 2 to state 0, from state 0 to state 3, from state 3 to state 0, from state 0 to state 4, from state 4 to state 0, and from state 0 to state 5 are similar to the analysis above and will not be repeated here.

[0105] In the subprocess of state 5, the state code for state 5 is "10000", corresponding to the input D4 of the first flip-flop D_FF in the five control units 3121. When the fifth trigger signal is '1', the process jumps from state 5 to state 0. Simultaneously, after a delay of at least one clock cycle, the fifth transition signal becomes '1', and the process jumps back from state 0 to state 1. This completes one cycle of the state machine, after which the state machine can start the next business processing process.

[0106] According to an embodiment of this application, the second conversion circuit includes: an encoding conversion sub-circuit connected to the state machine, used to convert an N-bit state code from the state machine into an M-bit Gray code, where M and N are both integers greater than 1. M ≥ N; Temporary storage sub-circuit, connected to the encoding conversion sub-circuit, is used to store M-bit Gray code; Output sub-circuit, connected to the temporary storage sub-circuit and the state machine, is used to output the M-bit Gray code stored in the temporary storage sub-circuit to the state machine.

[0107] In one example, N=8, M=3.

[0108] Figure 9 This is a schematic diagram of a state control circuit based on the second switching circuit according to an embodiment of this application.

[0109] like Figure 9As shown, in one example, N=8, M=3, and the predetermined format is 3-bit Gray code. The second conversion circuit 32 includes an encoding conversion sub-circuit 321, a temporary storage sub-circuit 322, and an output sub-circuit 323. The encoding conversion sub-circuit 321 is connected to the state machine 2, and the temporary storage sub-circuit 322 is connected to the encoding conversion sub-circuit 321. The output sub-circuit 323 is connected to both the temporary storage sub-circuit 322 and the state machine 2.

[0110] The encoding conversion sub-circuit 321 converts the 8-bit state code from the first state of state machine 2 into a 3-bit Gray code state code for the first state. The temporary storage sub-circuit 322 stores the 3-bit Gray code state code for the first state. The output sub-circuit 323 outputs the 3-bit Gray code state code for the first state stored by the temporary storage sub-circuit 322 to state machine 2.

[0111] During the operation of state machine 2, the state code corresponding to each state is converted into the corresponding Gray code state code. Since adjacent states in the Gray code state code differ by only 1 bit, there will be no signal race hazards.

[0112] Figure 10 This is a schematic diagram of a state control scheme based on a second switching circuit according to an embodiment of this application.

[0113] like Figure 10 As shown, based on the state code of the input one-hot code, the corresponding Gray code state code is output. When N=8, the corresponding transformation of the state code is shown in Table 2.

[0114] Table 2

[0115]

[0116] According to an embodiment of this application, the state coding scheme based on the second conversion circuit converts the one-hot code of the state machine into the corresponding Gray code state coding. Since adjacent states of the Gray code differ by only one bit, there will be no race conditions between signals, thus eliminating the risk of metastability.

[0117] like Figure 9 As shown, according to an embodiment of this application, the state machine 2 includes a state register 21 and a state transition circuit 23. The state register 21 is connected to the controller 1 and the second transition circuit 32, and is used to store an M-bit Gray code provided by the second transition circuit 32 according to a clock signal provided by the controller 1. The state transition circuit 23 is connected to the controller 1 and the second transition circuit 32, and is used to receive a clock signal and N trigger signals from the controller 1, and provide the N trigger signals as an N-bit state code to the second transition circuit 32 according to the clock signal.

[0118] Figure 11This is a schematic diagram of a state control circuit according to an embodiment of this application.

[0119] The state machine and second transition circuit can be set on a Field Programmable Gate Array (FPGA). The controller can be a microprocessor, which can be located inside the FPGA, or it can be an onboard microcontroller, which can be located outside the FPGA. Figure 11 As shown. The state machine can also be configured with a digital processing module. A cryptographic module can be configured externally to the FPGA. The cryptographic module can be connected to the controller and the state machine for data encryption / decryption.

[0120] like Figure 11 As shown, the controller can connect to the state machine via clock signal pins, reset signal pins, and trigger signal pins, inputting the clock signal, reset signal, and preset frequency to the second conversion circuit. The controller can input the clock signal, reset signal, and N trigger signals to the state machine. The state machine can input the number of bits N of the state code into the second conversion circuit. The second conversion circuit can return a 3-bit Gray code to the state machine. The controller can also connect to a data processing module via a data bus, and the data processing module can connect to a cryptographic module. The hardware device consisting of the controller, FPGA, and cryptographic module can also interact with a host computer to implement data encryption / decryption functions.

[0121] Figure 12 This is a schematic diagram of the status register in an embodiment of this application.

[0122] like Figure 12 As shown, in one example, N=8 and M=3. The state transition circuit includes eight state transition flip-flops 231 and a state transition OR gate 232. The state transition flip-flops 231 can be 1-bit D flip-flops with a reset input. The eight trigger signals received by the state register can be represented as {trig_sig_1', trig_sig_2', trig_sig_3', trig_sig_4', trig_sig_5', trig_sig_6', trig_sig_7', trig_sig_8'}.

[0123] The output Q6 of the first state transition trigger 231 outputs the first bit of the 8-bit state code of the state machine's one-hot code, and the reset terminal R6 of the first state transition trigger 231 is grounded. The input D6 of the last seven state transition triggers 231 receives the first seven trigger signals from the controller. The output Q6 of the last seven state transition triggers 231 outputs the last seven bits of the state code of the state machine. The reset terminal R6 of the last seven state transition triggers 231 receives the inverted signal of the reset signal RSTn through a state transition NOT gate 233. The first input of the state transition OR gate 232 receives the inverted signal of the reset signal RSTn through the state transition NOT gate 233, the second input of the state transition OR gate 232 receives the eighth trigger signal from the controller, and the output of the state transition OR gate 232 is connected to the input D6 of the first state transition trigger 231.

[0124] After the digital circuit is reset, it enters state 1. Since the reset signal RSTn is '0' during the digital circuit reset, it becomes '1' after passing through the state transition NOT gate 233. This causes the state transition OR gate 232 to output '1', which is then input to the input terminal D6 of the first state transition flip-flop 231. Because the reset terminal R6 of the first state transition flip-flop 231 is grounded, it is in an invalid state. Therefore, the output terminal Q6 of the first state transition flip-flop 231 is '1', meaning the first bit of the 8-bit state code of the state machine is '1'. At the same time, the '1' output of the state transition NOT gate 233 is output to the reset terminal R6 of the next 7 state transition flip-flops 231. Therefore, the output terminal Q6 of the next 7 state transition flip-flops 231 all output '0'. At this time, the 8-bit state code of the output state machine is "00000001", representing state 1.

[0125] After the digital circuit resets and the first trigger signal is '1', it indicates a transition from state 1 to state 2. At this time, the output terminal Q6 of the second state transition trigger 231 outputs '1', meaning the second bit of the 8-bit state code of the state machine is '1'. In addition, since the last 7 trigger signals are all '0', the output terminal Q6 of the first and last 6 state transition triggers 231 all output '0'. At this time, the 8-bit state code of the output state machine is "00000010", representing state 2.

[0126] Similarly, when the 2nd to 7th trigger signals are valid in sequence, the current state jumps to the next state, and the 8-bit state code of the one-hot code of the next state is output.

[0127] When the 8th trigger signal is valid, the output terminal Q6 of the 1st state transition trigger 231 outputs '1', and the output terminal Q6 of the next 7 state transition triggers 231 all output '0'. At this time, the 8-bit state code of the output state machine's one-hot code is "00000001", representing state 1, indicating that the state machine has jumped back from state 8 to state 1.

[0128] Figure 13 This is a schematic diagram of a status register according to an embodiment of this application.

[0129] like Figure 13 As shown, the status register includes an 8-bit register 213 and an 8-bit counter 214.

[0130] The input terminal D[7..0] of the 8-bit register 213 receives the padded 8-bit Gray code Gray_code[7..0] from the second conversion circuit, and the output terminal Q[7..0] of the 8-bit register 213 outputs the 8-bit Gray code Gray_code_out[7..0] of the next state, used to obtain the state code of the next state of the state machine. The input terminal C[7..0] of the 8-bit counter 214 receives the 8-bit state code One_hot_code[7..0] of the one-hot code of the state machine, and the output terminal D[7..0] of the 8-bit counter 214 outputs the number of bits N of the 8-bit state code of the one-hot code of the state machine. For example, in the embodiment, the 8-bit state code of the one-hot code of the state machine is 8 bits, so the value of the number of bits output by the 8-bit counter 214 is N="00001000", and N is input to the second conversion circuit.

[0131] According to an embodiment of this application, the second conversion circuit further includes: a judgment sub-circuit, connected to the controller, for receiving a clock signal from the controller, and outputting an enable signal at the output terminal of the judgment sub-circuit in response to the clock signal frequency being higher than a preset frequency, and outputting a disable signal at the output terminal of the judgment sub-circuit in response to the clock signal frequency being lower than the preset frequency; an allocation sub-circuit, connected to the judgment sub-circuit and the temporary storage sub-circuit, for enabling the temporary storage sub-circuit in response to receiving the enable signal from the judgment sub-circuit, and disabling the temporary storage sub-circuit in response to receiving the disable signal from the judgment sub-circuit; and an output sub-circuit, also connected to the judgment sub-circuit, for outputting the M-bit Gray code stored in the temporary storage sub-circuit to the state machine in response to receiving the enable signal from the judgment sub-circuit, and returning the N-bit state code received from the state machine to the state machine in response to receiving the disable signal.

[0132] Figure 14 This is a schematic diagram of the second conversion circuit according to an embodiment of this application.

[0133] like Figure 9 and Figure 14As shown, the second conversion circuit also includes a judgment sub-circuit 324 and an allocation sub-circuit 325. The judgment sub-circuit 324 is connected to the controller 1, and the allocation sub-circuit 325 is connected to the judgment sub-circuit 324 and the temporary storage sub-circuit 322. The output sub-circuit 323 is connected to the judgment sub-circuit 324.

[0134] When the clock signal frequency is higher than the preset frequency, the output of the judgment sub-circuit 324 outputs an enable signal, enabling the allocation sub-circuit 325, which in turn enables the temporary storage sub-circuit 322. The output of the judgment sub-circuit 324 also outputs an enable signal, enabling the output sub-circuit 323, which then outputs the M-bit Gray code stored in the temporary storage sub-circuit to the state machine. When the clock signal frequency is lower than the preset frequency, the output of the judgment sub-circuit 324 outputs a disable signal, disabling the allocation sub-circuit 325, which in turn disables the temporary storage sub-circuit 322. The output of the judgment sub-circuit 324 also outputs a disable signal, disabling the output sub-circuit 323, which then returns the N-bit state code received from the state machine to the state machine.

[0135] In one example, such as Figure 14 As shown, the judgment sub-circuit 324 may include a comparator CMP. Port 1 of the comparator CMP receives the clock signal CLK from the controller, and port 2 of the comparator CMP receives a preset frequency. The preset frequency can be 50MHz, and the clock signal originates from the main clock frequency of the digital circuit. When the frequency of the clock signal CLK is greater than 50MHz, the digital circuit is determined to be a high-speed digital circuit, requiring state machine encoding conversion. When the frequency of the clock signal CLK is less than 50MHz, the digital circuit is determined to be a low-speed digital circuit.

[0136] The output of the decision sub-circuit 324 outputs an enable signal, enabling the allocation sub-circuit 325. The allocation sub-circuit 325 can allocate a temporary storage area to store the Gray code state code. For example, the decision sub-circuit 324 can read the number of bits N of the current state machine's one-hot code state code, and then generate the number of bits M of the Gray code based on the value of N. The 8-bit state code received from the state machine's one-hot code needs to be encoded using 3 bits of Gray code; then, the allocation sub-circuit 325 allocates an M-bit register as a temporary storage area based on the value of M. Additionally, the output of the decision sub-circuit 324 outputs a disable signal, disabling the allocation sub-circuit 325 and preventing the allocation of a temporary storage area.

[0137] According to the embodiments of this application, temporary storage areas are dynamically allocated based on clock frequency. In high-speed digital circuits, temporary storage areas are dynamically allocated on demand, which can improve system adaptability. In low-speed digital circuits, temporary storage areas are not allocated, but only when business needs are met. When idle, they do not occupy space, further improving system adaptability.

[0138] In one example, such as Figure 14 As shown, the sub-circuit 325 may include a first buffer Tri_1, a log function unit 3251, and an integer unit 3252.

[0139] The enable terminal en of the first buffer Tri_1 can be connected to the output terminal of the judgment sub-circuit 324 through the second NOT gate NOT_2. The input terminal of the first buffer Tri_1 is used to receive the number of bits N in the 8-bit state code from the state machine, and obtain the number of bits 3 of the Gray code through the log function unit 3251 and the rounding unit 3252.

[0140] The output of the decision sub-circuit 324 outputs a low-level enable signal, which becomes high after passing through the second NOT gate NOT_2, enabling the distribution sub-circuit 325. The enable terminal en of the first buffer Tri_1 receives a high level, turning on Tri_1. N is then output through Tri_1 to the log function unit 3251 for calculation. Then, the integer part is rounded up by the rounding function 3252 to obtain M. Calculate M according to the following formula (1).

[0141] (1);

[0142] in, This indicates rounding up. For example, when N=5, Rounding up 2.32 gives When N=8, Rounding up 3 gives .

[0143] According to an embodiment of this application, the encoding conversion sub-circuit includes M third OR gates, at least one bit of the N-bit state code output by the state machine is provided to the corresponding input of the corresponding third OR gate, and the output of the M third OR gates is used to output M-bit Gray code.

[0144] In one example, N=8 and M=3. The 8-bit state code of the one-hot code output by the state machine is represented as {One_hot_code[0], One_hot_code[1], One_hot_code[2], One_hot_code[3], One_hot_code[4], One_hot_code[5], One_hot_code[6], One_hot_code[7]}. The 3-bit Gray code state code is represented as {Gray_code[0], Gray_code[1], Gray_code[2]}. The supplementary state code of the 3-bit Gray code is represented as {Gray_code[3], Gray_code[4], Gray_code[5], Gray_code[6], Gray_code[7]}.

[0145] like Figure 14 As shown, the encoding conversion sub-circuit 321 includes three third OR gates (OR_3). At least one bit of the 8-bit state code output by the state machine is provided to the corresponding input of the corresponding third OR gate (OR_3). The outputs of the three third OR gates (OR_3) are used to output a 3-bit Gray code. For example, the first bit of the 8-bit state code output by the state machine is not connected to the third OR gate (OR_3). The third bit of the 8-bit state code output by the state machine is connected to the second input of the first third OR gate (OR_3) and the first input of the second third OR gate (OR_3). The 8-bit state code output by the state machine can be logically connected to output a 3-bit Gray code.

[0146] According to the embodiments of this application, a combinational logic circuit is constructed using M third OR gates. Through logical AND operations, the N-bit state code is converted according to rules, and the M-bit Gray code is accurately output. The simplified combinational logic circuit can improve the response speed.

[0147] According to an embodiment of this application, the temporary storage sub-circuit includes: a fourth OR gate, the first input of which is connected to the output of the judgment sub-circuit, and the second input of which is used to receive the inverted signal of the reset signal from the controller; M second flip-flops, the reset terminals of which are connected to the output of the fourth OR gate, the clock terminals of which are connected to the controller to receive the clock signal, the input terminals of which are connected to the M outputs of the encoding conversion sub-circuit to receive the M-bit Gray code, and the outputs of which serve as the outputs of the temporary storage sub-circuit.

[0148] like Figure 14 As shown, the temporary storage sub-circuit 322 includes a fourth OR gate OR_4 and three second flip-flops DFF.

[0149] The first input of the fourth OR gate OR_4 is connected to the output of the judgment sub-circuit 324. The second input of the fourth OR gate OR_4 can receive the inverted signal of the reset signal RSTn from the controller through the first NOT gate NOT_1. The reset terminals R0 of the three second flip-flops DFF are connected to the output of the fourth OR gate OR_4. The clock terminals clk of the three second flip-flops DFF are connected to the controller to receive the clock signal CLK. The input terminals D5 of the three second flip-flops DFF are connected to the three output terminals of the encoding conversion sub-circuit 321 to receive the 3-bit Gray code. The output terminal Q5 of the three second flip-flops DFF serves as the output of the temporary storage sub-circuit 322.

[0150] According to the embodiments of this application, by coordinating the enable signal at the output of the judgment sub-circuit and the system clock signal, the M-bit Gray code from the encoding conversion sub-circuit is delayed, which can ensure that the M-bit Gray code from the encoding conversion sub-circuit is stably output at a specified time.

[0151] According to an embodiment of this application, the output sub-circuit includes: M second buffers, the enable terminals of the M second buffers are connected to the output terminals of the judgment sub-circuit, and the input terminals of the M second buffers are used to receive M bits from the N-bit state code from the state machine; M fourth OR gates, the first input terminals of the M fourth OR gates are respectively connected to the M output terminals of the temporary storage sub-circuit, the second input terminals of the M fourth OR gates are respectively connected to the output terminals of the M second buffers, and the output terminals of the M fourth OR gates serve as the M first output terminals of the output sub-circuit; and K AND gates, the first input terminals of the K AND gates are used to receive K bits from the N-bit state code from the state machine, the second input terminals of the K AND gates are connected to the output terminals of the judgment sub-circuit, and the output terminals of the K AND gates serve as the K second output terminals of the output sub-circuit, where K+M=N, and K is an integer greater than 1.

[0152] According to embodiments of this application, by coordinating the enable signal at the output of the judgment sub-circuit, it receives M bits of Gray code from the temporary storage sub-circuit, or receives M bits from the N-bit state code received from the state machine. This adapts to different operating modes and logic requirements, resulting in simple and clear control logic. Furthermore, by outputting K AND gates, it receives K bits from the N-bit state code from the state machine, automatically supplementing the M-bit Gray code with additional bits. This standardizes data of different bit lengths into a uniform bit width, eliminating bit width differences, ensuring data format standardization, and facilitating subsequent circuit recognition, parsing, and processing.

[0153] By performing a time delay transition, it can be ensured that the M-bit Gray code from the encoding conversion sub-circuit is output stably at the specified time.

[0154] In one example, K=5. In the status register corresponding to the 8-bit status code, the first three bits of the status register store 3 bits of Gray code, and the last five bits of the status register store '0'.

[0155] like Figure 14 As shown, the output sub-circuit 323 includes three second buffers Tri_2, three fifth OR gates OR_5, and five AND gates AND.

[0156] The enable pins (en) of the three second buffers Tri_2 are connected to the output of the judgment sub-circuit 324, and the inputs of the three second buffers Tri_2 are used to receive 3 bits of the 8-bit state code from the state machine. The first inputs of the three fifth OR gates OR_5 are respectively connected to the three outputs of the temporary storage sub-circuit 322, and the second inputs of the three fifth OR gates OR_5 are respectively connected to the outputs of the three second buffers Tri_2. The outputs of the three fifth OR gates OR_5 serve as the three first outputs of the output sub-circuit 323. The first inputs of the five AND gates AND are used to receive 5 bits of the 8-bit state code from the state machine, the second inputs of the five AND gates AND are connected to the output of the judgment sub-circuit 324, and the outputs of the five AND gates AND serve as the five second outputs of the output sub-circuit 323.

[0157] When the enable pin en of the second buffer Tri_2 is active (high level), the second buffer Tri_2 is turned on, and data can be output normally. When the enable pin en of the second buffer Tri_2 is low level, the second buffer Tri_2 is blocked, and data cannot be output. The second buffer Tri_2 can be a 1-bit tri-state buffer, capable of receiving 1 bit of data.

[0158] The following combination Figure 14 The state coding conversion scheme based on the second conversion circuit is further explained.

[0159] When the frequency of the clock signal CLK is greater than 50MHz, the digital circuit is determined to be a high-speed digital circuit, requiring state machine encoding conversion. The output of the judgment sub-circuit 324 outputs an enable signal, enabling the allocation sub-circuit 325. The digital circuit can allocate a temporary storage area based on the M value, setting up three second flip-flops (DFFs).

[0160] When the digital circuit is powered on and reset, the reset signal RSTn is '0'. After passing through the first NOT gate NOT_1, it becomes '1', which causes the fourth OR gate OR_4 to output '1'. Therefore, the reset terminal R0 of the three second flip-flops DFF is '1', which causes the output terminal Q5 of the three second flip-flops DFF to be '0'. The initial value of the 3-bit Gray code status code is "000".

[0161] When the digital circuit finishes resetting, the reset signal RSTn is '1', which becomes '0' after passing through the first NOT gate NOT_1 and is input to the fourth OR gate OR_4. The output of the judgment sub-circuit 324 outputs a low-level enable signal, so the fourth OR gate OR_4 outputs a low level, making the reset terminals R0 of the three second flip-flops DFF '0'. At this time, when the clock signal CLK is valid, the output terminals Q5 of the three second flip-flops DFF are equal to the values ​​of their respective input terminals. The output of the judgment sub-circuit 324 outputs a low-level enable signal, making the enable terminals en of the three second buffers Tri_2 '0', thus the three second buffers Tri_2 have no output. Therefore, the output values ​​of the three fifth OR gates OR_5 are determined by the output terminals Q5 of the three second flip-flops DFF, that is, the 3-bit Gray code state encoding is the corresponding output value of the three fifth OR gates OR_5.

[0162] The encoding conversion sub-circuit 321 uses three third OR gates OR_3 to convert the one-hot code into the corresponding Gray code value. For example, when the 8-bit state code of the one-hot code output by the state machine is “00000001”, One_hot_code[6] is '0', One_hot_code[5] is '0', One_hot_code[2] is '0', and One_hot_code[1] is '0' and input to the first third OR gate OR_3, so the first third OR gate OR_3 outputs '0'. One_hot_code[5] is '0', One_hot_code[4] is '0', One_hot_code[3] is '0', and One_hot_code[2] is '0' and input to the second third OR gate OR_3, so that the second third OR gate OR_3 outputs '0'. One_hot_code[7] is '0', One_hot_code[6] is '0', One_hot_code[5] is '0', and One_hot_code[4] is '0'. These values ​​are input to the third OR gate OR_3, causing the third OR gate OR_3 to output '0'. Therefore, the input D5 of the three second flip-flops DFF is '0'. When the clock signal CLK is valid, the output Q5 of the three second flip-flops DFF is '0', so the output 3-bit Gray code status code is "000". At the same time, the output of the judgment sub-circuit 324 outputs a low-level enable signal, which is input to the five AND gates, causing the five AND gates to output '0'. Therefore, the supplementary status code of the 3-bit Gray code is "00000", and the Gray code output by the output sub-circuit 323 is "00000000".

[0163] Similarly, when other one-hot codes are input with an 8-bit status code, the completed Gray code output after passing through the encoding conversion sub-circuit 321, temporary storage sub-circuit 322, and output sub-circuit 323 is shown in Table 3.

[0164] Table 3

[0165]

[0166] When the frequency of the clock signal CLK is less than 50MHz, the digital circuit is determined to be a low-speed digital circuit and does not require state machine encoding conversion. At this time, the output of the judgment sub-circuit 324 outputs a high-level disable signal, which becomes low-level after passing through the first NOT gate NOT_1. The enable terminal en of the first buffer Tri_1 is low-level, which blocks the first buffer Tri_1. The value of N will not be input to the log function unit 3251 and the integer unit 3252, and the distribution sub-circuit 325 has no output.

[0167] The output of the 324 sub-circuit outputs a high-level disable signal, and no temporary storage area is allocated. The three second flip-flops (DFF) have no output, which is then routed to the three fifth OR gates (OR_5).

[0168] The output of the judgment sub-circuit 324 outputs a high-level disable signal, which makes the enable pins en of the three second buffers Tri_2 all '1'. Therefore, the three second buffers Tri_2 are turned on, so that the first, second, and third bits of the 8-bit state code of the one-hot code output by the state machine are output through three fifth OR gates OR_5. That is, the 3-bit Gray code state code is the first, second, and third bits of the 8-bit state code of the one-hot code output by the state machine.

[0169] Simultaneously, the output of the decision sub-circuit 324 outputs a high-level disable signal, which is input to one input of the five AND gates. This makes the output of the five AND gates equal to the value of the other input, i.e., the supplementary state code of the 3-bit Gray code is the 4th, 5th, 6th, 7th, and 8th bits of the 8-bit state code of the one-hot code output by the state machine. Therefore, the state machine still operates in the one-hot code encoding mode, and the value of the output remains the 8-bit state code of the one-hot code output by the state machine.

[0170] According to embodiments of this application, the circuit design for the remaining states is similar, requiring a corresponding number of increment / decrement flip-flops.

[0171] Figure 15 This is a schematic diagram of a state control circuit according to another embodiment of this application.

[0172] like Figure 15As shown, according to an embodiment of this application, the conversion circuit 3 includes a first conversion circuit 31 and a second conversion circuit 32. The state control circuit further includes a mode selection circuit 6. The mode selection circuit 6 is connected to the state machine 2, the first conversion circuit 31, and the second conversion circuit 32. The mode selection circuit 6 is configured to output a first selection signal at its output terminal in response to the inherent delay of the state machine 2 being less than a preset delay, and to output a second selection signal at its output terminal in response to the inherent delay of the state machine 2 being greater than the preset delay. The first selection signal enables the first conversion circuit 31, and the second selection signal enables the second conversion circuit 32. The first conversion circuit 31 and the second conversion circuit 32 each have a selection signal terminal, which is connected to the output terminal of the mode selection circuit 6.

[0173] Figure 16 This is a schematic diagram of a state control scheme based on a mode selection circuit according to an embodiment of this application.

[0174] like Figure 16 As shown, the inherent delay Delay_D of the state machine is the inherent delay parameter for each cycle of the state machine. In the state control scheme based on the first transition circuit, for an N-bit state code with a one-hot code, the inherent delay of state machine 2 is N times the clock signal CLK. The preset delay Exp can be an acceptable delay time for each cycle of the state machine, input by the user. In one example, the mode selection circuit may include a delay comparator C_CMP. Port number 1 of the delay comparator C_CMP receives the preset delay Exp, and port number 2 of the delay comparator C_CMP receives the inherent delay Delay_D of the state machine.

[0175] If the inherent delay Delay_D of the state machine is greater than the preset delay Exp, it indicates that the user cannot accept the inherent delay of the state machine. The second selection signal output by the delay comparator C_CMP is '1', enabling the second conversion circuit and executing the second scheme digital logic (the state control scheme based on the second conversion circuit). During the system compilation of the digital circuit, the second scheme digital logic is compiled into a second configuration file, which is stored in the external memory area of ​​the digital circuit. When the digital circuit is powered on again, the second scheme digital logic is executed by loading the second configuration file from the external memory area.

[0176] If the inherent delay Delay_D of state machine 2 is less than the preset delay Exp, it indicates that the user can accept the inherent delay of the state machine. The first selection signal output by the delay comparator C_CMP is '0', enabling the first conversion circuit and executing the first scheme digital logic (the state control scheme based on the first conversion circuit). During the system compilation of the digital circuit, the first scheme digital logic is compiled into a first configuration file, which is stored in the external memory area of ​​the digital circuit. When the digital circuit is powered on again, the first scheme digital logic is run by loading the first configuration file from the external memory area.

[0177] Figure 17 This is a schematic diagram of loading a configuration file for a digital circuit according to an embodiment of this application.

[0178] like Figure 17 As shown, the first configuration file and the second configuration file can override each other. For example, the digital circuit currently stores the first configuration file, and the user can burn the second configuration file to the external storage area to replace the first configuration file. The second configuration file will be loaded and run after the digital circuit is powered on again, and then the first configuration file can be used to replace the second configuration file again.

[0179] The control logic of the state control scheme based on the first transition circuit is simple and does not occupy additional storage space. However, a preset state is inserted between every two adjacent states, and generating a transition signal will take at least one clock cycle. Therefore, the process of each state machine will have a delay of at least 1 × N = N clock cycles. The state machine process based on the state control scheme of the second transition circuit does not have a delay problem, but it needs to occupy an additional storage area to store Gray code values. As the number of bits N of the one-hot code increases, the number of bits occupied in the registers also increases.

[0180] Therefore, when a state machine is applied to a high-speed digital circuit, the encoding conversion sub-circuit can be used to convert the one-hot code to Gray code to eliminate metastability and ensure the stability of data processing. When the state machine is applied to a low-speed digital circuit, the one-hot code is still used to save register resources and improve the flexibility of the application. The state control circuit of this application embodiment can solve the problem of metastability in the state encoding of the one-hot code of the state machine, effectively improve the operational safety and stability of the state machine in high-speed digital circuits, and can realize the conversion from one-hot code to Gray code to adapt to different circuit structures. The state control circuit of this application embodiment improves safety, flexibility, and is easier to deploy and implement without affecting the existing system functions.

[0181] The judgment module determines whether the state machine is applied to a high-speed digital circuit. In this case, it converts the one-hot code to Gray code to eliminate metastability and ensure data processing stability. When the state machine is applied to a low-speed digital circuit, it still uses one-hot code to save register resources. The state control circuit of this application embodiment can select different circuit structures according to user needs, offering high compatibility and flexibility.

[0182] The third scheme is a state control scheme based on a mode selection circuit, which is compatible with the state control scheme based on the first conversion circuit and the state control scheme based on the second conversion circuit. The corresponding circuit structure can be modified accordingly.

[0183] Figure 18 This is a schematic diagram of a state control circuit according to another embodiment of this application.

[0184] like Figure 18 As shown in one example, the state machine and transition circuit can be located inside the field-programmable gate array (FPGA), while the controller can be an onboard microcontroller, which can be located outside the FPGA. The mode selection circuit can be a delay comparator C_CMP. The FPGA's bus interface needs to support both the first and second schemes simultaneously. That is, the controller connects to the FPGA via a clock signal pin, a reset signal pin, N control signal pins, N trigger signal pins, and a preset frequency pin. After the user sets the specific value of the preset delay, it can be output by the controller to port 1 of the delay comparator C_CMP. The inherent delay generated by the FPGA can be input to port 2 of the delay comparator C_CMP. The delay comparator C_CMP outputs either a first selection signal or a second selection signal to the FPGA.

[0185] Figure 19 This is a schematic diagram of a switching sub-circuit based on the third scheme in an embodiment of this application.

[0186] like Figure 19 As shown, the first OR gate OR_1 of the control unit 3121 based on the third scheme switching sub-circuit can also be a three-input OR gate. The third input terminal of the first OR gate OR_1 serves as the selection signal terminal of the first conversion circuit. The third input terminal of the first OR gate OR_1 receives the first selection signal choose_sig1 output from the output terminal of the mode selection circuit. The first selection signal choose_sig1 being '0' does not affect the function of the switching sub-circuit.

[0187] If the first selection signal choose_sig1 is '1', it indicates that the second option is selected. When the first selection signal choose_sig1 is '1', the first OR gate OR_1 in the five control units 3121 outputs a high level, thus keeping the reset terminal R0 of the first flip-flop D_FF in the five control units 3121 in a reset state and outputting '0'. Furthermore, when the digital circuit is powered on and reset, since the transition signal is invalid (low level), the status code is always an invalid state of "00000", representing that the switching sub-circuit is not working.

[0188] Figure 20 This is a schematic diagram of the second conversion circuit based on the third scheme in an embodiment of this application.

[0189] like Figure 20 As shown, the fourth OR gate OR_4 of the temporary storage sub-circuit 322 of the second conversion circuit based on the third scheme can also be a three-input OR gate. The second conversion circuit based on the third scheme can also include a third NOT gate NOT_3, a first AND gate AND_1, and a second AND gate AND_2.

[0190] The second selection signal, choose_sig2, is input to the third input of the fourth OR gate, OR_4, via the third NOT gate, NOT_3. The first input of the first AND gate, AND_1, and the first input of the second AND gate, AND_2, receive the second selection signal, choose_sig2. The second inputs of the first AND gate, AND_1, and AND_2 are connected to the output of the judgment sub-circuit 324. The output of the first AND gate, AND_1, is connected to the first input of the fourth OR gate, OR_4, and the enable pin (en) of the three second buffers, Tri_2. The output of the second AND gate, AND_2, is connected to the inputs of the five AND gates.

[0191] When the second selection signal choose_sig2 is '0', it means that the first scheme is selected. Then, the second selection signal choose_sig2 becomes '1' after passing through the third NOT gate NOT_3, which causes the fourth OR gate OR_4 to output '1', so that the three second flip-flops DFF are always in the reset state and output '0'.

[0192] When the second selection signal choose_sig2 is '0', the first AND gate AND_1 outputs '0', making the enable terminals en of the three second buffers Tri_2 in an invalid state of '0'. Therefore, the three second buffers Tri_2 have no output, and the 3-bit Gray code status code is "000". Simultaneously, when the second selection signal choose_sig2 is '0', the second AND gate AND_2 outputs '0', which in turn makes the three fifth OR gates OR_5 all output '0', and the 3-bit Gray code supplementary status code is "00000". Therefore, the Gray code output by the output sub-circuit 323 is always "00000000", indicating that the second conversion circuit is not working.

[0193] When the second selection signal choose_sig2 is '1', it indicates that the second scheme is selected, and the second conversion circuit uses... Figure 8 The circuit structure shown implements the function of converting one-hot codes to Gray codes.

[0194] The state control circuit of this application embodiment can ensure continuous operation, is easy to use, does not affect the functions of existing systems, and is easy to deploy and implement.

[0195] Figure 21 This is a schematic diagram of a digital circuit according to an embodiment of this application.

[0196] like Figure 21 As shown, a digital circuit can include a host computer and hardware devices; a digital circuit can also be a computer. (Combined with...) Figure 11 and Figure 18 Controllers, field-programmable gate arrays (FPGAs), and cryptographic modules can form a hardware device.

[0197] The hardware device is built into the computer server via a PCIe bus interface, communicating with the host computer application software on the computer server. It receives data sent by the host computer, encrypts the data, and then returns it to the host computer. The state machine can be set to 5 states. The operation of the state machine in each state is as follows: In the subprocess of state 1, the computer server reads data; in the subprocess of state 2, the computer server reads the key; in the subprocess of state 3, the computer server sends data and the key to the cryptographic chip; in the subprocess of state 4, the computer server waits for the cryptographic chip to complete the data encryption; in the subprocess of state 5, the computer server returns the encrypted data to the controller.

[0198] According to an embodiment of this application, the state code provided by the state machine to the transition circuit is a one-hot code, all bits of the state code of the preset state are zero, and the state code of the predetermined format is Gray code.

[0199] This application also proposes a control method for a state control circuit.

[0200] According to an embodiment of this application, the control method includes: a state machine, under the control of a controller, provides a state code to a transition circuit, the transition circuit including at least one of a first transition circuit and a second transition circuit; the first transition circuit, under the control of the controller, switches the state code provided by the state machine from a first state to a preset state and returns it to the state machine, then switches the state code from the preset state to a second state and returns it to the state machine, wherein the state code of the preset state undergoes a one-bit transition relative to both the state code of the first state and the state code of the second state; or, the second transition circuit, under the control of the controller, converts the state code of the first state or the second state provided by the state machine into a predetermined format and returns the state code of the predetermined format to the state machine, wherein the state code of the predetermined format undergoes a one-bit transition when switching from the first state to the second state; the state machine, under the control of the controller, stores the state code returned by the transition circuit in the state register of the state machine.

[0201] According to embodiments of this application, the controller can control the first conversion circuit to switch the state code of the state machine from a first state to a preset state, and then from the preset state to a second state. This transforms the scheme requiring two bit transitions for a one-hot code into a one-bit transition, effectively eliminating metastability. The controller can also control the second conversion circuit to convert the first or second state of the state machine into a predetermined format. The switching of the state code in the predetermined format from the first state to the second state transforms the scheme requiring two bit transitions for a one-hot code into a one-bit transition, also effectively eliminating metastability.

[0202] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0203] The units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0204] The foregoing has provided a detailed description of a state control circuit and its control method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A state control circuit, characterized in that, include: Controller; A state machine, connected to a controller, is used to provide state codes to the transition circuit under the control of the controller, and to store the state codes returned by the transition circuit into the state machine's state register; and The conversion circuit includes at least one of a first conversion circuit and a second conversion circuit; in, The first conversion circuit is connected to the state machine and the controller. Under the control of the controller, it first switches the state code provided by the state machine from the first state to the preset state and returns it to the state machine. Then, it switches the state code from the preset state to the second state and returns it to the state machine. The state code of the preset state undergoes a one-bit transition relative to the state code of the first state and the state code of the second state. The second conversion circuit is connected to the state machine and the controller, and is used to convert the state code of the first state or the second state provided by the state machine into a predetermined format under the control of the controller, and return the state code of the predetermined format to the state machine, wherein a bit transition occurs when the state code of the predetermined format switches from the first state to the second state; The state code provided by the state machine to the transition circuit is a one-hot code, all bits of the state code of the preset state are zero, and the state code of the predetermined format is Gray code. The second conversion circuit includes: The encoding conversion sub-circuit, connected to the state machine, is used to convert the N-bit state code from the state machine into M-bit Gray code, where M and N are both integers greater than 1. M ≥ N; A temporary storage sub-circuit, connected to the encoding conversion sub-circuit, is used to store M-bit Gray codes; The output sub-circuit, connected to the temporary storage sub-circuit and the state machine, is used to output the M-bit Gray code stored in the temporary storage sub-circuit to the state machine. The judgment sub-circuit is connected to the controller and is used to receive clock signals from the controller. When the frequency of the clock signal is higher than the preset frequency, an enable signal is output at the output terminal of the judgment sub-circuit. When the frequency of the clock signal is lower than the preset frequency, a disable signal is output at the output terminal of the judgment sub-circuit. The distribution subcircuit, connected to the judgment subcircuit and the temporary storage subcircuit, is used to enable the temporary storage subcircuit in response to receiving an enable signal from the judgment subcircuit, and to disable the temporary storage subcircuit in response to receiving a disable signal from the judgment subcircuit. The output sub-circuit is also connected to the decision sub-circuit. The output sub-circuit is used to output the M-bit Gray code stored in the temporary storage sub-circuit to the state machine in response to receiving an enable signal from the decision sub-circuit, and to return the N-bit state code received from the state machine to the state machine in response to receiving a disable signal.

2. The state control circuit according to claim 1, characterized in that, The first conversion circuit includes: The delay sub-circuit is used to receive control signals and trigger signals from the controller, and delay the trigger signal according to the control signal to obtain the switching signal; The switching subcircuit, connected to the delay subcircuit and the state machine, is used to receive state codes from the state machine. Under the control of the trigger signal from the controller, it switches the received state code from the first state to the preset state and returns it to the state machine. Under the control of the transition signal from the delay subcircuit, it switches the state code from the preset state to the second state and returns it to the state machine. In the preset state, all bits of the state code are zero.

3. The state control circuit according to claim 2, characterized in that, The state machine includes: The status register, connected to the switching sub-circuit and the controller, is used to store the status code returned by the switching sub-circuit under the control of the clock signal from the controller, and to provide the stored status code to the switching sub-circuit. The signal synchronization circuit is connected to the delay sub-circuit, the switching sub-circuit, and the controller. It is used to receive clock signals, control signals, and trigger signals from the controller. Under the control of the clock signal, it provides the control signals and trigger signals to the delay sub-circuit and provides the trigger signals to the switching sub-circuit.

4. The state control circuit according to claim 3, characterized in that, The status code is an N-bit code, and both the control signal and the trigger signal are N signals. The switching sub-circuit includes N control units, among which... The input terminal of the nth control unit is connected to the nth output terminal of the status register, and is used to receive the nth bit of the N-bit status code from the status register; The output of the nth control unit is connected to the (n+1)th input of the status register, and is used to output the (n+1)th bit of the N-bit status code to the status register, where n = 1, 2, …, N. When n = N, the output of the Nth control unit is connected to the first input of the status register, and is used to output the first bit of the N-bit status code to the status register. The trigger signal terminal of the nth control unit is connected to the signal synchronization circuit and is used to receive the nth trigger signal from N trigger signals. The switching signal terminal of the nth control unit is connected to the delay sub-circuit to receive the nth of N switching signals; The nth control unit is used to convert the nth state code into zero and provide it to the (n+1)th input of the state register under the control of the nth trigger signal; and to restore the nth state code to 1 and provide it to the (n+1)th input of the state register under the control of the nth transition signal.

5. The state control circuit according to claim 4, characterized in that, The control unit includes: The first OR gate has its first input terminal used to receive the inverted signal of the reset signal from the controller, and its second input terminal used as the trigger signal terminal of the control unit. The first flip-flop has its reset terminal connected to the output terminal of the first OR gate, its input terminal serving as the input terminal of the control unit, and its clock terminal used to receive the clock signal from the controller. The second OR gate has its first input connected to the output of the first flip-flop, its second input serving as the switching signal of the control unit, and its output serving as the output of the control unit.

6. The state control circuit according to claim 4, characterized in that, The delay sub-circuit includes N timers, wherein: The clock input of the nth timer is connected to the controller to receive clock signals from the controller; The first input terminal of the nth timer is connected to the signal synchronization circuit to receive the nth trigger signal from N trigger signals. The second input terminal of the nth timer is connected to the signal synchronization circuit to receive the nth of N control signals; The output of the nth timer is connected to the transition signal terminal of the nth control unit, and is used to output the nth of N transition signals.

7. The state control circuit according to claim 1, characterized in that, The encoding conversion sub-circuit includes M third OR gates. At least one bit of the N-bit state code output by the state machine is provided to the corresponding input of the corresponding third OR gate. The outputs of the M third OR gates are used to output M-bit Gray codes.

8. The state control circuit according to claim 1, characterized in that, The temporary storage sub-circuit includes: The fourth OR gate has its first input connected to the output of the judgment sub-circuit, and its second input is used to receive the inverted signal of the reset signal from the controller. M second flip-flops, the reset terminals of the M second flip-flops are connected to the output of the fourth OR gate, the clock terminals of the M second flip-flops are connected to the controller to receive the clock signal, the input terminals of the M second flip-flops are connected to the M output terminals of the encoding conversion sub-circuit to receive M-bit Gray code, and the output terminals of the M second flip-flops serve as the output terminals of the temporary storage sub-circuit.

9. The state control circuit according to claim 1, characterized in that, The output sub-circuit includes: M second buffers, the enable terminals of the M second buffers are connected to the output terminals of the decision sub-circuit, and the input terminals of the M second buffers are used to receive M bits from the N-bit state code from the state machine; M fourth OR gates, the first inputs of the M fourth OR gates are respectively connected to the M outputs of the temporary storage sub-circuit, the second inputs of the M fourth OR gates are respectively connected to the outputs of the M second buffers, and the outputs of the M fourth OR gates serve as the M first outputs of the output sub-circuit. K AND gates, the first input of the K AND gates is used to receive K bits from the N-bit state code of the state machine, the second input of the K AND gates is connected to the output of the decision sub-circuit, and the output of the K AND gates serves as the K second outputs of the output sub-circuit, where K+M=N and K is an integer greater than 1.

10. The state control circuit according to claim 1, characterized in that, A state machine includes: The status register, connected to the controller and the second conversion circuit, is used to store the M-bit Gray code provided by the second conversion circuit according to the clock signal provided by the controller. The state transition circuit, connected to the controller and the second transition circuit, is used to receive a clock signal and N trigger signals from the controller, and provide the N trigger signals as an N-bit state code to the second transition circuit according to the clock signal.

11. The state control circuit according to claim 1, characterized in that, The conversion circuit includes a first conversion circuit and a second conversion circuit; The state control circuit further includes a mode selection circuit, which is connected to the state machine, the first transition circuit, and the second transition circuit. The mode selection circuit is used to output a first selection signal at its output terminal in response to the inherent delay of the state machine being less than a preset delay, and to output a second selection signal at its output terminal in response to the inherent delay of the state machine being greater than the preset delay. The first selection signal is used to enable the first transition circuit, and the second selection signal is used to enable the second transition circuit. The first conversion circuit and the second conversion circuit each have a selection signal terminal, which is connected to the output terminal of the mode selection circuit.

12. A control method for a state control circuit as described in any one of claims 1 to 11, characterized in that, The control method includes: Under the control of the controller, the state machine provides state codes to the transition circuit, which includes at least one of the first transition circuit and the second transition circuit. Under the control of the controller, the first conversion circuit switches the state code provided by the state machine from the first state to a preset state and returns it to the state machine, then switches the state code from the preset state to the second state and returns it to the state machine. The state code of the preset state undergoes a one-bit transition relative to both the state code of the first state and the state code of the second state. Alternatively, under the control of the controller, the second conversion circuit converts the state code of the first or second state provided by the state machine into a predetermined format and returns the state code of the predetermined format to the state machine. The state code of the predetermined format undergoes a one-bit transition when switching from the first state to the second state. Under the control of the controller, the state machine stores the state code returned by the transition circuit into the state machine's state register.

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