Arrayed waveguide grating router and photonic integrated platform

Abstract

The application provides an arrayed waveguide grating router and a photonic integrated platform, relates to the technical field of optical fiber communication, and is used for improving the transmission performance of an arrayed waveguide grating router AWGR.The specific technical scheme is as follows: the arrayed waveguide grating router comprises: at least two arrayed waveguide structures and a slab waveguide structure, the at least two arrayed waveguide structures are connected with the slab waveguide structure; wherein, in the region where the at least two arrayed waveguide structures are connected with the slab waveguide structure, a separation deep groove is arranged between two adjacent arrayed waveguide structures in the at least two arrayed waveguide structures, and a separation material is arranged in the separation deep groove.The application is applied to the scene of transmitting data through optical fibers.

Description

Technical Field

[0001] This application relates to the field of optical fiber communication technology, and in particular to an arrayed waveguide grating router and a photonic integration platform. Background Technology

[0002] With the advent of the era of big data and cloud computing, optical communication networks are evolving towards ultra-high speed, ultra-large capacity, and all-optical switching. Arrayed Waveguide Grating Routers (AWGRs), as core passive devices in wavelength division multiplexing optical networks and data center optical interconnect architectures, have attracted widespread attention due to their advantages such as wavelength loop routing characteristics, compact size, and compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) processes. Typically, the arrayed waveguide in a high-performance AWGR usually adopts a ridge waveguide structure.

[0003] However, when the array waveguide adopts a ridge waveguide structure, the optical field is very likely to leak laterally through the bottom residual slab layer and couple into the adjacent array waveguide, resulting in severe crosstalk between adjacent channels, which significantly reduces the signal-to-noise ratio and transmission quality of the AWGR, thus causing poor routing performance of the AWGR. Summary of the Invention

[0004] This application provides an arrayed waveguide grating router and a photonic integration platform to improve the routing performance of AWGR.

[0005] In a first aspect, embodiments of this application provide an arrayed waveguide grating router, which includes at least two arrayed waveguide structures and a planar waveguide structure, wherein the at least two arrayed waveguide structures are connected to the planar waveguide structure; wherein, in the region where the at least two arrayed waveguide structures are connected to the planar waveguide structure, an isolation groove is provided between two adjacent arrayed waveguide structures, the isolation groove extends along the extension direction of the arrayed waveguide structure, and an isolation material is provided in the isolation groove.

[0006] The technical solution provided in this application brings at least the following beneficial effects: Since an isolation deep groove is provided between two adjacent array waveguide structures in the region where at least two array waveguide structures of the array waveguide router are connected to the planar waveguide structure, and the isolation deep groove extends along the extension direction of the array waveguide structure, and an isolation material is provided in the isolation deep groove to construct a strong limiting optical barrier between adjacent array waveguide structures, the optical signals that diffuse laterally in adjacent array waveguide structures can be blocked when transmitted to the isolation deep groove. This avoids the situation where optical signals enter adjacent array waveguide structures, reduces crosstalk between adjacent channels, and thus improves the signal-to-noise ratio and transmission quality of the array waveguide grating router, thereby improving the routing performance of the array waveguide grating router.

[0007] One possible implementation is that the above-mentioned array waveguide structure includes: a substrate layer; a planar waveguide disposed on the substrate layer; and a ridge waveguide disposed on the planar waveguide; wherein the above-mentioned isolation trench cuts off the planar waveguides of two adjacent array waveguide structures, extending directly to the substrate layer.

[0008] In another possible implementation, the distance between the first surface of the ridge waveguide and the first wall of the isolation trench is greater than or equal to a distance threshold; wherein the first surface is the side of the ridge waveguide facing the isolation trench; and the first wall is the trench wall of the isolation trench facing the ridge waveguide.

[0009] Another possible implementation is that the surface of the wall of the aforementioned isolation trench has a rough surface, which is configured to cause diffuse reflection of the optical signal.

[0010] Another possible implementation is that the above-mentioned arrayed waveguide grating router further includes: a parasitic drainage waveguide structure, one end of which is disposed in an isolation trench, and the parasitic drainage waveguide structure extends along the direction of the isolation trench; wherein the parasitic drainage waveguide structure is used to absorb optical signals in the isolation trench.

[0011] Another possible implementation is that the above-mentioned array waveguide structure includes: a substrate layer; a planar waveguide disposed on the substrate layer; a ridge waveguide disposed on the planar waveguide; wherein one end of the above-mentioned parasitic drainage waveguide structure is connected to the substrate layer.

[0012] Another possible implementation is that the height of the parasitic waveguide structure in the first direction is the same as the height of the array waveguide structure in the first direction; wherein, the first direction is the direction from the substrate layer to the ridge waveguide.

[0013] Another possible implementation is that the second surface of the parasitic waveguide structure has a smooth surface; wherein the second surface is the surface of the parasitic waveguide structure facing the wall of the isolation trench.

[0014] Another possible implementation involves providing a light guide structure at the end of the parasitic waveguide structure that is away from the planar waveguide structure; wherein the light guide structure is used to guide the optical signal absorbed by the parasitic waveguide structure to a predetermined area.

[0015] Another possible implementation is that the number of the parasitic drainage waveguide structures is at least one; wherein the at least one parasitic drainage waveguide structure is arranged in parallel.

[0016] Secondly, embodiments of this application provide a photonic integration platform, which includes an arrayed waveguide grating router as described in the first aspect.

[0017] The beneficial effects of the second aspect mentioned above are described in the corresponding description of the first aspect and will not be repeated here. Attached Figure Description

[0018] Figure 1 This is one of the structural schematic diagrams of an arrayed waveguide grating router provided in an embodiment of this application;

[0019] Figure 2 This is a second schematic diagram of the structure of an arrayed waveguide grating router provided in an embodiment of this application;

[0020] Figure 3 This is the third schematic diagram of an arrayed waveguide grating router provided in the embodiments of this application;

[0021] Figure 4 An enlarged schematic diagram of the physical gap region of an arrayed waveguide grating router provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the simulation results of an arrayed waveguide grating router provided in an embodiment of this application.

[0023] Figure label:

[0024] 10-Arrayed waveguide structure, 101-Substrate layer, 102-Planar waveguide component, 103-Ridge waveguide component, 1031-First surface, 11-Planar waveguide structure, 111-Input planar waveguide structure, 112-Output planar waveguide structure, 12-Isolation deep trench, 121-Rough surface, 122-First trench wall, 13-Isolation material, 14-Physical gap region, 15-Parasitic drainage waveguide structure, 16-Input waveguide, 17-Output waveguide. Detailed Implementation

[0025] The arrayed waveguide grating router and photonic integration platform provided in this application will be described in detail below with reference to the accompanying drawings.

[0026] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0027] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0028] The terms "at least one," "at least one of," etc., used in the specification and claims of this application refer to any one, any two, or a combination of two or more of the included items. For example, at least one of a, b, and c can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple. Similarly, "at least two" refers to two or more items, and its meaning is similar to that of "at least one."

[0029] In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0030] The arrayed waveguide grating router and photonic integration platform provided in this application embodiment can be applied to scenarios where data is transmitted via optical fiber.

[0031] With the advent of the era of big data and cloud computing, optical communication networks are evolving towards ultra-high speed, ultra-large capacity, and all-optical switching. Arrayed Waveguide Grating Routers (AWGRs), as core passive devices in wavelength division multiplexing optical networks and data center optical interconnect architectures, have attracted widespread attention due to their advantages such as wavelength loop routing characteristics, compact size, and compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) processes. Typically, the arrayed waveguide in a high-performance AWGR usually adopts a ridge waveguide structure.

[0032] However, when the array waveguide adopts a ridge waveguide structure, the optical field is very likely to leak laterally through the bottom residual slab layer and couple into the adjacent array waveguide, resulting in severe crosstalk between adjacent channels, which significantly reduces the signal-to-noise ratio and transmission quality of the AWGR, thus causing poor routing performance of the AWGR.

[0033] To suppress crosstalk in AWGRs, existing technologies have proposed a variety of solutions.

[0034] One existing technique attempts to suppress coupling crosstalk by non-uniformly adjusting the spacing between arrayed waveguides, abandoning the traditional equal-spacing arrangement, and disrupting the phase matching condition between adjacent waveguides. However, this method has a limitation: it violates the stringent phase focusing requirements of the Rowland circle geometry of the arrayed waveguide grating. Non-uniform waveguide spacing distorts the focusing position of the optical field in the output planar waveguide, introducing significant phase errors. While this reduces crosstalk to some extent, it brings serious negative effects, namely a significant increase in device insertion loss and worsening loss non-uniformity between different channels, making it difficult to meet the stringent power budget requirements of high-performance optical networks.

[0035] Furthermore, in another existing technology, cascaded 1×2 arbitrary beamsplitters replace the traditional input waveguide and input star coupler as the input structure of the AWG array waveguide. While this method attempts to improve performance by precisely controlling the splitting ratio to optimize the input optical field distribution, its structural design is overly complex and primarily suitable for simple 1×N splitting or filtering scenarios. For N×N architectures requiring wavelength loop routing, cascaded beamsplitters not only significantly increase the device footprint but also introduce accumulated insertion loss and phase error due to multiple cascades. More importantly, this approach primarily improves the input end and does not fundamentally address the lateral mode leakage problem caused by the presence of the bottom slab layer in the array waveguide transmission section itself, thus having limited effectiveness in reducing crosstalk between adjacent channels.

[0036] It is understandable that existing technologies still have significant limitations in addressing the crosstalk problem of SOI ridge waveguide AWGRs. First, while one existing technology can theoretically suppress coupling, it compromises the perfection of the Rowland circle focusing geometry, leading to an unavoidable increase in phase error and insertion loss, and failing to guarantee loss consistency across all output channels. Second, another existing technology is structurally overly redundant, making it difficult to scale to high-port-count cyclic routing applications, and it fails to address the fundamental problem of lateral mode leakage in the array waveguide transmission region due to the presence of the bottom slab layer. More generally, existing designs largely lack active management mechanisms for overflowing stray light, allowing background light to propagate disorderly within the chip substrate or cladding, ultimately resulting in severe background noise or low noise.

[0037] In summary, there is an urgent need for an innovative technical solution that can physically eliminate crosstalk paths without sacrificing device losses and integration density.

[0038] To address the aforementioned technical problems, embodiments of this application provide an arrayed waveguide grating router and a photonic integration platform. The arrayed waveguide grating router includes at least two arrayed waveguide structures and a planar waveguide structure, wherein the at least two arrayed waveguide structures are connected to the planar waveguide structure; wherein, in the region where the at least two arrayed waveguide structures are connected to the planar waveguide structure, an isolation groove is provided between two adjacent arrayed waveguide structures, and an isolation material is provided in the isolation groove. Because in the region where at least two arrayed waveguide structures of the arrayed waveguide grating router are connected to the planar waveguide structure, an isolation deep groove is provided between two adjacent arrayed waveguide structures, and an isolation material is provided in the isolation deep groove to build a strong limiting optical barrier between adjacent arrayed waveguide structures, the optical signals that are laterally diffused in the adjacent arrayed waveguide structures can be blocked when they are transmitted to the isolation deep groove. This can prevent the optical signals from entering the adjacent arrayed waveguide structures, reduce crosstalk between adjacent channels, and thus improve the signal-to-noise ratio and transmission quality of the arrayed waveguide grating router. In this way, the routing performance of the arrayed waveguide grating router can be improved.

[0039] It is understood that this application aims to solve the inherent planar mode leakage and crosstalk problems of SOI ridge waveguides without sacrificing device insertion loss or increasing process complexity. By introducing isolation trenches extending into the buried oxide layer between adjacent array waveguide structures, the lateral propagation path of stray light is physically and completely cut off. Ultimately, this application enables high-performance wavelength routing functionality with extremely high channel isolation.

[0040] The arrayed waveguide grating router and photonic integration platform provided in this application will be described in detail below with reference to the accompanying drawings.

[0041] See Figure 1 This is a schematic diagram of the structure of an arrayed waveguide grating router provided in an embodiment of this application. Figure 1 As shown, the arrayed waveguide grating router provided in this application embodiment includes: at least two arrayed waveguide structures 10 and a planar waveguide structure 11, wherein the at least two arrayed waveguide structures 10 are connected to the planar waveguide structure 11; wherein, in the region where the at least two arrayed waveguide structures 10 are connected to the planar waveguide structure 11, an isolation deep groove 12 is provided between two adjacent arrayed waveguide structures 10, the isolation deep groove extends along the extension direction of the arrayed waveguide structure 10, and an isolation material 13 is provided in the isolation deep groove 12.

[0042] In some embodiments of this application, the at least two arrayed waveguide structures 10 can be arrayed waveguide grating arms. The main body of the at least two arrayed waveguide structures 10 adopts a low-loss ridge waveguide structure to reduce sidewall scattering loss and phase error during optical field transmission.

[0043] In some examples, for each of at least two arrayed waveguide structures 10, combined with Figure 2 The array waveguide structure 10 may include a substrate 101; a planar waveguide 102 disposed on the substrate 101; and a ridge waveguide 103 disposed on the planar waveguide 102.

[0044] The aforementioned substrate 101 may also be referred to as a buried oxide layer (BOX), etc., but this application embodiment does not limit it in this way.

[0045] The array waveguide structure 10 can be fabricated on an SOI wafer with a top silicon thickness of 220 nm. The height from the substrate layer 101 to the ridge waveguide 103 can be 220 nm. Through a shallow etching process (etching depth of approximately 130 nm), planar waveguides 102 with a thickness of approximately 90 nm are retained on both sides of the waveguide. The optical field energy is mainly confined to the region of the ridge waveguide 103 and the region of the planar waveguide 102 below it for transmission.

[0046] It should be noted that this application does not impose any restrictions on the dimensions of the various components of the array waveguide structure 10, and those skilled in the art can choose according to their needs.

[0047] Here, the applicant discovered in practical application that in the existing AWGR design, the planar waveguide 102 of adjacent array waveguide structures 10 is connected. The planar waveguide 102 constitutes the physical bridge for the lateral leakage of optical signals between adjacent array waveguide structures 10, which is the main path leading to coherent crosstalk.

[0048] In some embodiments of this application, combined with Figure 1 The aforementioned planar waveguide structure 11 may include at least one of the following: an input planar waveguide structure 111 and an output planar waveguide structure 112.

[0049] In some embodiments of this application, the above-mentioned planar waveguide structure 11 can adopt the classic Rowland circle structure to provide a free propagation region to achieve diffraction and focusing of the light field.

[0050] In some embodiments of this application, the region where the above-mentioned at least two arrayed waveguide structures 10 are connected to the planar waveguide structure 11 can be understood as the region within a predetermined range at the connection point where the arrayed waveguide structure 10 and the planar waveguide structure 11 are connected.

[0051] Among them, such as Figure 3 and Figure 4 As shown, the region where the at least two arrayed waveguide structures 10 are connected to the planar waveguide structure 11 can be the physical gap region 14 between the tapered transition regions Taper of adjacent arrayed waveguide structures 10.

[0052] At the waveguide interface, to reduce mode mismatch loss, the optical field is significantly broadened in the Taper region. Simultaneously, due to the extremely small spacing between adjacent waveguides within this physical gap region 14, the broadened optical field is highly susceptible to mode overlap. Therefore, optical signals are prone to lateral leakage and cross-coupling through the bottom planar waveguide 102, leading to severe adjacent channel crosstalk and significantly reducing the signal-to-noise ratio and transmission quality of the AWGR. Therefore, an isolation groove 12 can be provided between two adjacent array waveguide structures 10 within this physical gap region 14 to isolate the path between the planar waveguide 102 of one array waveguide structure 10 and the planar waveguide 102 of the other array waveguide structure 10.

[0053] In some embodiments of this application, the aforementioned isolation groove 12 serves not only as a physical barrier but also as a container for the parasitic drainage structure, providing the necessary physical space for the capture and elimination of stray light. The isolation groove 12 is shaped like an inverted trapezoid conforming to the shape of the gap. Of course, the isolation groove 12 can also be of other shapes, and this application does not limit this.

[0054] In some embodiments of this application, combined with Figure 3 and Figure 4As shown, the geometric profile of the aforementioned isolation trench 12 conforms to the gradual shape of the tapered transition region Taper of the adjacent array waveguide structure 10. As the array waveguide structure 10 extends outward from the interface with the planar waveguide structure 11, the spacing between adjacent array waveguide structures 10 gradually increases, and the width of the isolation trench 12 also expands in a V-shape accordingly.

[0055] In some embodiments of this application, the length of the isolation deep trench 12 extending along the extension direction of the array waveguide structure 10 can be 50 μm. Of course, the length can also be other lengths, and this application does not limit this.

[0056] In some embodiments of this application, combined with Figure 2 The array waveguide structure 10 includes: a substrate layer 101; a planar waveguide 102 disposed on the substrate layer 101; and a ridge waveguide 103 disposed on the planar waveguide 102; wherein the isolation trench 12 cuts off the planar waveguides 102 of two adjacent array waveguide structures 10 and extends directly to the substrate layer 101.

[0057] Thus, since the isolation trench can sever the planar waveguide components of two adjacent array waveguide structures, reaching the substrate layer, a strong optical barrier is constructed between the adjacent array waveguide structures. Therefore, the optical signals that are laterally diffused in the adjacent array waveguide structures are blocked when they are transmitted to the isolation trench, thereby preventing the optical signals from entering the adjacent array waveguide structures, reducing crosstalk between adjacent channels, and thus improving the signal-to-noise ratio and transmission quality of the array waveguide grating router. In this way, the routing performance of the array waveguide grating router can be improved.

[0058] In some embodiments of this application, the surface of the wall of the isolation trench 12 has a rough surface 121, which is configured to cause diffuse reflection of the optical signal.

[0059] In some examples, the walls of the isolation deep trench 12 can be understood as the physical cutoff boundaries of the two side walls of the isolation deep trench 12 (including the first trench wall 122 in the following embodiments), i.e., the planar waveguide 102 of the array waveguide structure 10.

[0060] In some examples, the rough surface 121 described above can be a sawtooth or corrugated structure at the micro-nano scale. The period and amplitude of the sawtooth structure are typically designed in the subwavelength range (e.g., period of 200nm-300nm, amplitude of 50nm-100nm). Of course, the period and amplitude of the sawtooth structure can also be other periods and other amplitudes, which are not limited in the embodiments of this application.

[0061] In other examples, the roughened surface 121 described above may also be a sinusoidal corrugated, trapezoidal corrugated, or surface roughening structure with random distribution characteristics. Alternatively, instead of directly etching the physical sidewalls at the edge of the isolation trench 12, one or more rows of photonic crystal holes or a non-periodic air hole array may be arranged close to the cutoff boundary of the planar waveguide 102 of the array waveguide structure 10.

[0062] In this embodiment, the rough surface 121 is used to convert the optical signal of the incident planar waveguide 102 into incoherent scattered light.

[0063] It is understandable that when stray light signals remaining in the planar waveguide 102 diffuse laterally and collide with the deeply etched boundary (e.g., the wall of the isolation trench 12), the rough surface 121 will induce a strong diffuse reflection effect. This non-reflective reflection not only prevents the light beam from entering the trench or being reflected back to the main waveguide in a coherent manner, but also effectively disrupts the wavefront phase of the light signal, transforming it into an incoherent background scattered light signal, thereby greatly reducing the probability of coherent crosstalk.

[0064] Thus, it can be seen that since the surface of the wall of the isolation trench is rough, stray light signals incident on the rough surface can undergo diffuse reflection, thereby disrupting the wavefront phase of the light signal and converting it into an incoherent background scattered light signal. Therefore, the probability of coherent crosstalk is greatly reduced.

[0065] In some examples, combined Figure 3 and Figure 4 As shown, the distance between the first surface 1031 of the ridge waveguide 103 and the first groove wall 122 of the isolation deep groove 12 is greater than or equal to a distance threshold; wherein, the first surface 1031 is the side of the ridge waveguide 103 facing the isolation deep groove 12; and the first groove wall 122 is the groove wall of the isolation deep groove 12 facing the ridge waveguide 103.

[0066] Optionally, the aforementioned distance threshold can be set to any value from 0.1 μm to 0.15 μm.

[0067] Thus, since the distance between the first surface of the ridge waveguide and the first wall of the isolation deep groove is greater than or equal to the distance threshold, it can be ensured that the tail of the fundamental mode field in the array waveguide structure will not touch the rough surface of the isolation deep groove, thereby avoiding additional scattering loss or phase distortion of the optical signal.

[0068] In some embodiments of this application, the aforementioned insulating material may include, but is not limited to, a silicon dioxide overlayer grown by plasma-enhanced chemical vapor deposition (PECVD).

[0069] It is understandable that, due to the huge refractive index difference between monocrystalline silicon (refractive index n≈3.45) and filled silicon dioxide (refractive index n≈1.45), the isolation trench 12 creates a huge optical barrier between adjacent array waveguide structures 10, physically and completely severing the lateral connection of the planar waveguide 102 of adjacent array waveguide structures 10, forcing the optical signal that might have leaked to undergo total reflection or be blocked, thereby eliminating the direct crosstalk caused by leakage of the planar waveguide 102.

[0070] This application provides an arrayed waveguide grating router, which includes at least two arrayed waveguide structures and a planar waveguide structure. The at least two arrayed waveguide structures are connected to the planar waveguide structure. In the region where the at least two arrayed waveguide structures are connected to the planar waveguide structure, an isolation groove is provided between two adjacent arrayed waveguide structures. The isolation groove extends along the extension direction of the arrayed waveguide structure, and an isolation material is provided in the isolation groove. Because in the region where at least two arrayed waveguide structures of the arrayed waveguide grating router are connected to the planar waveguide structure, an isolation deep groove is provided between two adjacent arrayed waveguide structures. This isolation deep groove extends along the extension direction of the arrayed waveguide structure and contains an isolation material to build a strong limiting optical barrier between adjacent arrayed waveguide structures. Therefore, the optical signal that diffuses laterally in the adjacent arrayed waveguide structures can be blocked when it is transmitted to the isolation deep groove, thereby preventing the optical signal from entering the adjacent arrayed waveguide structure, reducing crosstalk between adjacent channels, and thus improving the signal-to-noise ratio and transmission quality of the arrayed waveguide grating router. In this way, the routing performance of the arrayed waveguide grating router can be improved.

[0071] Of course, in order to further eliminate crosstalk problems, a diversion waveguide structure can be set in the isolation deep trench 12 to divert stray light in the isolation deep trench 12 to other areas. An example will be given below.

[0072] In some embodiments of this application, combined with Figure 2 , Figure 3 and Figure 4 As shown, the above-mentioned array waveguide grating router further includes a parasitic waveguide structure 15, one end of which is disposed in the isolation deep trench 12, and the parasitic waveguide structure 15 extends along the direction of the isolation deep trench 12; wherein, the parasitic waveguide structure 15 is used to absorb optical signals in the isolation deep trench 12.

[0073] In some examples, the parasitic waveguide structure 15 can be a silicon nanowire with a height of 220 nm and a width of 150 nm to 200 nm. The silicon nanowire can be in a weak light-guiding state. Since the parasitic waveguide structure 15 is in a state where a high-refractive-index (silicon) element is surrounded by a low-refractive-index (silicon dioxide) element, it has a natural light trapping effect. Therefore, it is specifically used to adsorb scattered light energy in the cladding filling the isolation trench 12 through evanescent wave coupling or direct mode overlap effect. Of course, the size of the silicon nanowire can also be other sizes, which is not limited in this embodiment.

[0074] In some examples, after absorbing the optical signal, the parasitic drainage waveguide structure 15 can divert the optical signal to other areas along the direction of the isolation trench 12.

[0075] Thus, since a parasitic waveguide structure is also provided in the isolation trench, the optical signal in the isolation trench can be absorbed by the parasitic waveguide structure and diverted to other areas. Therefore, the optical signal in the isolation trench can be completely eliminated, achieving extremely low background noise or low noise.

[0076] In some examples, the array waveguide structure 10 described above includes: a substrate 101; a planar waveguide 102 disposed on the substrate 101; and a ridge waveguide 103 disposed on the planar waveguide 102; wherein one end of the parasitic drainage waveguide structure 15 is connected to the substrate 101.

[0077] Thus, since one end of the parasitic waveguide structure can be connected to the substrate, the parasitic waveguide structure can absorb the optical signal between the two sidewalls of the isolation trench, preventing some optical signals from passing through the parasitic waveguide structure. Therefore, the optical signal in the isolation trench can be completely eliminated, achieving extremely low background noise or low noise.

[0078] In some examples, the height of the parasitic waveguide structure 15 in the first direction is the same as the height of the array waveguide structure 10 in the first direction; wherein the first direction is the direction from the substrate layer 101 to the ridge waveguide 103.

[0079] Thus, since the height of the parasitic waveguide structure in the first direction is the same as the height of the array waveguide structure in the first direction, it can be ensured that the parasitic waveguide structure can also absorb stray light signals between adjacent array waveguide structures. Therefore, the stray light signals can be completely eliminated, achieving extremely low background noise or low noise.

[0080] In some examples, the second surface of the parasitic drainage waveguide structure 15 has a smooth surface; wherein the second surface is the surface of the parasitic drainage waveguide structure 15 facing the wall of the isolation deep trench 12.

[0081] It is understood that there can be two second surfaces, one facing one wall of the isolation deep groove 12, and the other facing the other wall of the isolation deep groove 12.

[0082] Thus, it can be seen that since the second surface of the parasitic waveguide structure has a smooth surface, the low-loss characteristics of the parasitic waveguide structure as a transmission medium can be ensured.

[0083] In some examples, a light guide structure is provided at the end of the parasitic drainage waveguide structure 15 that is away from the planar waveguide structure 11; wherein the light guide structure is used to guide the optical signal absorbed by the parasitic drainage waveguide structure 15 to a predetermined area.

[0084] Optionally, the aforementioned predetermined region can be an invalid region at the edge of the chip or a dedicated light absorption region (such as a germanium absorber or a highly doped silicon region).

[0085] Optionally, the light guide structure can be a curved structure with a large radius of curvature to guide the absorbed light signal to a predetermined area for final dissipation. Alternatively, the light guide structure can be an adiabatic conical cutoff structure, allowing the light field to leak vertically to the substrate layer 101. Alternatively, the light guide structure can be directly connected to the predetermined area to achieve active absorption and heat dissipation of background noise energy.

[0086] Thus, it can be seen that since a light guide structure is provided at the end of the parasitic waveguide structure that is far from the planar waveguide structure, the light signal absorbed by the parasitic waveguide structure can be guided to the predetermined area through the light guide structure. Therefore, stray light signals between two adjacent array waveguide structures can be completely eliminated, achieving extremely low background noise or low noise.

[0087] In some examples, the number of the parasitic drainage waveguide structures 15 is at least one; wherein the at least one parasitic drainage waveguide structure 15 is arranged in parallel.

[0088] Thus, since at least two parasitic waveguide structures can be set, i.e., more parasitic waveguide structures can be set, the area of ​​the effective cross section for capturing optical signals can be increased. Therefore, the efficiency of absorbing optical signals in the isolation trench can be improved, and the optical signals in the isolation trench can be further eliminated, achieving extremely low background noise or low noise.

[0089] In summary, this application proposes a multi-stage crosstalk suppression mechanism for SOI ridge waveguide AWGR. Addressing the inherent planar mode leakage and stray light scattering problems at the interface of arrayed waveguide structures during transmission, this application improves upon the traditional passive design approach of simply increasing the spacing between adjacent arrayed waveguide structures. It adopts a design strategy of physically cutting off incoherent light scattering between channels combined with active diversion. By constructing microstructured isolation trenches and parasitic diversion waveguides in the gap regions between adjacent arrayed waveguide structures, this application can physically block crosstalk paths, destroy the coherence of stray light, and ultimately strip background noise energy from the signal optical path, thereby achieving extremely high channel isolation.

[0090] Specifically, this patent aims to completely sever the lateral light-guiding path of the planar waveguide at the bottom of the ridge waveguide. In conventional SOI ridge waveguide processes, the remaining planar layer (e.g., 90 nm thick) acts as a physical bridge for optical field coupling between adjacent array waveguide structures, causing optical energy to leak laterally in planar mode. This application uses a deep etching process to etch the region between adjacent array waveguide structures downwards down to the substrate layer, forming a physical break. Due to the large refractive index difference between the silicon core layer (refractive index approximately 3.45) and the silicon dioxide cladding layer filled in the deep trench (refractive index approximately 1.45), this deep trench structure constructs a strongly confined optical barrier, forcing the light field that originally diffused laterally in the substrate layer to undergo total internal reflection or blockage upon encountering the interface, thereby fundamentally eliminating the direct crosstalk caused by planar mode leakage. Furthermore, if the sidewalls of the isolation trench are optically smooth surfaces, the blocked stray light is prone to specular reflection, which may then couple back to the main waveguide, causing return loss, or be reflected into adjacent waveguides in the form of coherent light. To address this, this application introduces a micro-nano scale sawtooth design on the sidewalls of the internal structure of the isolation trench. When stray light or higher-order modes collide with these rough interfaces, incoherent diffuse reflection occurs. This diffuse reflection effect disperses the originally concentrated beam into isotropic background light, completely destroying the wavefront phase consistency of the optical field. Since the beam splitting mechanism of AWGR is highly dependent on phase matching, the incoherent scattered light cannot form effective interference superposition in adjacent waveguides, thereby greatly reducing the level of coherent crosstalk.

[0091] Although physical isolation and diffuse reflection prevent direct crosstalk, scattered light energy still exists in the cladding as background noise. To eliminate this background noise, this application designs a high-refractive-index silicon-based parasitic waveguide on the BOX layer at the center of the isolation trench. According to the coupling theory of optical waveguides, stray light located in the low-refractive-index cladding tends to couple into the high-refractive-index silicon core layer. This waveguide acts as an optical trap, capable of attracting ambient diffusely reflected background light through evanescent wave coupling or direct mode overlap. Subsequently, this captured light energy is transmitted along the waveguide to the ineffective region or radiation absorption region of the chip for dissipation, thereby purifying the electromagnetic environment between the array waveguides and minimizing the background crosstalk noise of the device.

[0092] The photonic integration platform provided in this application includes the arrayed waveguide grating router described in the above embodiments.

[0093] In some embodiments of this application, the aforementioned photonic integration platform may include, but is not limited to, a silicon-on-insulator (SOI) platform, a silicon-on-insulator (SiN) platform, an indium-on-insulator (InP) platform, and a thin-film lithium niobate (LNOI) platform.

[0094] It is understood that although the embodiments of this application are applicable not only to ridge waveguides on silicon-on-insulator (SOI) platforms, they can also be applied to other photonic integration platforms based on ridge waveguide structures. For example, in material systems such as silicon nitride (SiN), indium phosphide (InP), or thin-film lithium niobate (LNOI), if the waveguide structure also retains a bottom planar layer and has lateral mode leakage problems, the combined architecture of the isolation deep trench and suspended drainage waveguide of this application can be used for optimization. Any device design involving suppressing crosstalk between ridge waveguide arrays through physical isolation and waveguide drainage is covered by the technical concept of this application.

[0095] This application provides a photonic integration platform including the aforementioned arrayed waveguide grating router. Because an isolation deep groove is provided between two adjacent arrayed waveguide structures in the region where at least two arrayed waveguide structures of the arrayed waveguide grating router are connected to a planar waveguide structure, and this isolation deep groove extends along the extension direction of the arrayed waveguide structure, and an isolation material is disposed in the isolation deep groove to construct a strong limiting optical barrier between adjacent arrayed waveguide structures, the laterally diffused optical signals in adjacent arrayed waveguide structures can be blocked when transmitted to the isolation deep groove. This prevents optical signals from entering adjacent arrayed waveguide structures, reduces crosstalk between adjacent channels, and thus improves the signal-to-noise ratio and transmission quality of the arrayed waveguide grating router, thereby improving the routing performance of the arrayed waveguide grating router.

[0096] The following will use complete examples to illustrate the specific solutions of the arrayed waveguide grating router and photonic integration platform provided in the embodiments of this application.

[0097] like Figure 1 As shown, this application provides an arrayed waveguide grating router (AWGR) fabricated based on a silicon-on-insulator (SOI) photonic integration platform. The device has an N×N cyclic routing architecture in its optical topology (where N is the number of input / output channels, such as 16, 32, etc.), sequentially comprising along the optical signal propagation direction: N input waveguides 16, an input planar waveguide, an arrayed waveguide grating arm composed of M waveguides of unequal length, an output planar waveguide, and N output waveguides 17. Both the input and output planar waveguides (i.e., planar waveguide structures 11) adopt the classic Rowland circle structure to provide a free propagation region for diffraction and focusing of the optical field. The core improvement of this application is located at the fan-shaped interface connecting the arrayed waveguide grating arm and the input / output planar waveguide, i.e., the physical gap region between the tapered transition areas (Taper) of adjacent arrayed waveguide structures. Within this region, the physical isolation (i.e., isolation trench 12) constructed by the deep etching process and the drainage structure (i.e., parasitic drainage waveguide structure 15) are used to synergistically solve the planar mode crosstalk problem unique to ridge waveguides.

[0098] Combination Figure 2 As shown in the schematic diagram of the waveguide cross-section, the main body of the array waveguide structure 10 in this embodiment adopts a low-loss ridge waveguide structure (i.e., ridge waveguide 103) to reduce sidewall scattering loss and phase error during optical field transmission. Specifically, the device is fabricated on an SOI wafer with a top silicon thickness of 220 nm, and the total height of the array waveguide structure 10 is 220 nm. Through a shallow etching process (etching depth of approximately 130 nm), a bottom planar layer (i.e., planar waveguide 102) with a thickness of approximately 90 nm is retained on both sides of the waveguide. The optical field energy is mainly confined to the ridge region (i.e., the region of ridge waveguide 103) and the planar region below it (i.e., the region of planar waveguide 102) for transmission. In traditional AWGR designs, this continuous 90 nm thick planar layer constitutes a physical bridge for lateral leakage of optical signals between adjacent array waveguide structures, and is the main path leading to coherent crosstalk. To block this path, this application introduces a deep-substrate isolation structure (i.e., isolation trench 12 and / or parasitic drainage waveguide structure) between adjacent array waveguide structures. Combined with Figure 3 and Figure 4As shown in the schematic diagram of the partial planar structure of the device, a microstructured isolation trench is designed within the V-shaped or horn-shaped gap region formed between the tapered transition regions of two adjacent array waveguide structures. This trench structure is a physical disconnection region formed by a secondary photolithography and deep etching process. Unlike the conventional shallow etching region with a depth of only 130 nm, the etching depth of this isolation trench extends through the remaining 90 nm planar layer, reaching the bottom buried oxide layer and exposing the silicon dioxide substrate. The interior of this trench is then completely filled with a silicon dioxide cladding layer grown by plasma-enhanced chemical vapor deposition (PECVD). Due to the huge refractive index contrast between single-crystal silicon (refractive index n≈3.45) and the filled silicon dioxide (refractive index n≈1.45), this trench constructs a huge optical barrier between adjacent waveguides, physically severing the lateral connection of the bottom slab layer. This forces the potentially leaking planar mode light field to undergo total internal reflection or be blocked, thereby eliminating direct crosstalk caused by planar leakage.

[0099] Further reference Figure 4 (Partial enlarged view of the planar section) The geometric contour of the isolation trench conforms to the gradual shape of the tapered transition region of the adjacent array waveguide. As the array waveguide extends outward from the interface of the planar waveguide structure, the spacing of the array waveguide structure gradually increases, and the width of the isolation trench expands accordingly in a V-shape. To ensure lossless transmission of the main signal light, a certain safety distance is reserved between the edge of the isolation trench (i.e., the physical cutoff boundary of the slab layer) and the ridge edge of the main array waveguide, for example, set to 0.1 μm to 0.15 μm. This design ensures that the tail of the fundamental mode field in the main waveguide does not touch the deeply etched rough interface, thereby avoiding additional scattering loss or phase distortion of the main signal. At the same time, one of the core innovations of this application lies in the sidewall morphology design of the microstructured isolation trench. The two sidewalls of the isolation trench, i.e., the physical cutoff boundary of the bottom planar layer (slab layer) of the main array waveguide, are not traditional smooth straight lines, but are deliberately designed as micro-nano scale sawtooth or corrugated structures. Specifically, the period and amplitude of this sawtooth structure are typically designed in the subwavelength range (e.g., period of 200nm-300nm, amplitude of 50nm-100nm). Its physical mechanism is as follows: when stray light remaining in the Slab layer diffuses laterally and impacts the deeply etched boundary, the rough, sawtooth interface induces a strong diffuse reflection effect. This non-reflective reflection not only prevents the light beam from entering the deep trench or being reflected back to the main waveguide in a coherent manner, but also effectively disrupts the wavefront phase of the light field, transforming it into incoherent background scattered light, thereby greatly reducing the probability of coherent crosstalk.

[0100] This isolation trench serves not only as a physical barrier but also as a container for the parasitic drainage structure, providing the necessary physical space for the capture and elimination of stray light. To eliminate background noise light scattered into the trench from the sawtooth sidewalls, this application integrates a parasitic drainage waveguide at the center of the isolation trench. Figure 2 As shown in the cross-sectional view, the guiding waveguide is a freestanding silicon strip waveguide preserved on the buried oxide layer (BOX). Its height matches the ridge height of the main array waveguide (e.g., 220 nm) and it remains unetched throughout. The guiding waveguide is designed to be narrow (e.g., 150 nm to 200 nm), placing it in a weakly confined state. This weak confinement characteristic allows for a wider mode field distribution (i.e., a longer evanescent wave tail), enabling it to capture and absorb scattered light energy from the cladding within the deep trench more effectively and over a wider range through evanescent wave coupling or direct mode overlap. Unlike the serrated sidewalls, the sidewalls of this parasitic guiding waveguide are designed with smooth surfaces to ensure low-loss characteristics as a transmission medium. The captured stray light is confined within the guiding waveguide and propagates backward along the waveguide. In practical layouts, the end of the guiding waveguide can be designed as a curved structure with a large radius of curvature to guide light to the ineffective area at the edge of the chip or a dedicated light absorption area (such as a germanium absorber or a highly doped silicon region) for final dissipation, thereby completely eliminating the messy scattered light in the free propagation region (FPR) fan-shaped interface area and achieving extremely low background noise or low noise.

[0101] In summary, the technical solution of this application forms an integrated crosstalk suppression design: First, the direct leakage path of the Slab layer is cut off by a deeply etched physical trench, and the sawtooth structure at the edge of the trench converts the coherent stray light attempting to cross the boundary into incoherent diffuse reflection light; Second, the parasitic guiding waveguide at the center of the trench efficiently collects and guides these diffuse reflection lights like an optical trap, thus achieving great suppression of crosstalk between adjacent channels without sacrificing the quality of the main signal transmission.

[0102] It should be noted that the descriptions of the various features in the above technical solutions can be found in the specific descriptions in the above embodiments, and will not be repeated here in the embodiments of this application.

[0103] To enable those skilled in the art to better understand the technical solutions of this application, a set of specific device design parameters based on the silicon-on-insulator (SOI) platform are provided below as non-limiting embodiments. This embodiment is fabricated based on a standard SOI photonic process platform, wherein the top silicon layer thickness is 220 nm, the substrate layer thickness is 2 μm, and the upper cladding layer is 3 μm thick silicon dioxide. A 12×12 channel AWGR device designed on this platform uses a ridge waveguide structure as the core routing component. The overall height of the ridge waveguide is 220 nm, and the width is 500 nm to ensure single-mode transmission. The bottom slab waveguide has a thickness of 90 nm. The device design has a central operating wavelength of 1550nm and a channel spacing of 100GHz (approximately 0.8nm). The connection between the input / output waveguide (i.e., planar waveguide structure 11) and the planar waveguide (i.e., planar waveguide component 102) adopts a linear adiabatic tapered transition with a tapered tip width of 800nm. The initial physical gap between adjacent tapered tips is set to 200nm and diverges linearly as it moves away from the planar waveguide interface.

[0104] In this embodiment, the microstructured isolation trench disposed within the gap between adjacent array waveguide structures is an inverted trapezoid conforming to the shape of the gap. The starting position of this inverted trapezoidal trench is approximately 2 μm from the interface between the planar waveguide and the array waveguide structure (i.e., the interface between the array waveguide structure and the planar waveguide structure), and its length along the light propagation direction is set to 50 μm. The silicon material within the isolation trench region is completely etched down to the buried oxide layer, with an etching depth of 220 nm (penetrating the Slab layer). To achieve physical isolation while protecting the master mode transmission, a constant safety distance of 0.5 μm is maintained between the sidewall edge of the isolation trench and the edge of the ridge waveguide. The serrated microstructure at the edge of the isolation trench is designed as a periodic triangular corrugation with a period of 250 nm (satisfying the subwavelength condition) and an amplitude of 80 nm to maximize the diffuse reflection efficiency of stray light in the 1550 nm band. The parasitic drainage waveguide structure located at the very center of this inverted trapezoidal trench is designed as a smooth silicon nanowire with a height of 220 nm and a width of 180 nm. The guiding waveguide structure begins at the narrow end of the deep trench (near the FPR) and extends towards the wide end along the central axis of the isolated deep trench, with a length consistent with the trench length. To efficiently extract the captured stray light, an adiabatic bent structure with a curvature radius of 5 μm is connected to the end of the guiding waveguide, directing the light energy to the substrate radiation region away from the main optical path. The sidewalls of the parasitic guiding waveguide structure remain optically smooth, thereby ensuring efficient scattering, trapping, and transmission.

[0105] Based on the specific structural parameters described above, a full-wave simulation of the transmission spectrum of the AWGR device was performed using the finite-difference time-domain (FDTD) method. The results are as follows: Figure 5As shown. Simulation results show that within the passband range near the center wavelength of 1550nm, the main channel insertion loss of the device is approximately 2.5dB, which is not significantly worse than that of a conventional device without isolation structures, proving the effectiveness of the safety spacing design. More importantly, Figure 5 The spectral curves show that the crosstalk level of adjacent channels was significantly suppressed to below -45dB, far superior to the -25dB to -30dB crosstalk level typically found in traditional SOI ridge waveguide AWGRs. This performance improvement of over 15dB directly verifies the excellent effect of the combined work of physically cutting off the Slab layer, sawtooth diffuse reflection, and parasitic drainage waveguide.

[0106] In summary, this application addresses the problems of existing technologies that reduce crosstalk by non-uniformly adjusting waveguide spacing, leading to geometric distortion of the Rowland circle focusing, increased insertion loss, and uneven channel loss. This application proposes a completely different solution: a collaborative suppression mechanism combining an isolation trench and a guiding waveguide with incoherent scattering physical cutoff, significantly improving crosstalk suppression capabilities. The isolation trench, deeply etched into the buried oxide layer, completely cuts off the lateral light guiding path of the bottom planar layer of the SOI ridge waveguide. The serrated microstructure at the trench edge converts interface reflected light into incoherent diffuse reflection light, effectively disrupting the phase consistency of stray light and preventing its coherent crosstalk. The parasitic guiding waveguide at the center of the trench acts as an optical trap, actively absorbing and exporting residual background noise. This design neither alters the standard geometric arrangement of the arrayed waveguides on the Rowland circle nor compromises the smoothness of the main waveguide sidewalls. Therefore, this application significantly reduces crosstalk while maintaining the excellent low insertion loss characteristics and loss uniformity between channels of AWGR, avoiding the sacrifice of transmission quality for improved isolation. This allows the crosstalk between adjacent channels of AWGR to be reduced to below -45dB, which is significantly better than the -25dB level typically found in traditional designs, greatly improving the signal-to-noise ratio and channel isolation of the device.

[0107] Compared with the cited prior art, this application has significant integration advantages. The isolation and current-draining structure of this application is a micro-nano-scale modification of the waveguide gap region (originally an ineffective region), which increases the physical size of the device by almost nothing, thus facilitating high-density photonic integration. Meanwhile, the deep etched trenches (i.e., isolation trenches), sawtooth sidewalls, and suspended current-draining waveguides (i.e., parasitic current-draining waveguide structures) of this application are all fully compatible with standard silicon-on-insulator (SOI) photonic manufacturing processes. It can be achieved through a combination of conventional ridge waveguide etching and strip waveguide deep etching steps, without the need for special light-absorbing materials or heterogeneous integration processes, offering significant advantages such as low cost, high yield, and ease of large-scale manufacturing.

[0108] In summary, this embodiment, through specific parameter design and simulation verification, fully demonstrates the feasibility of achieving high-performance, low-crosstalk wavelength routing under standard SOI process conditions. This design not only completely solves the long-standing problem of planar mode leakage in silicon-based AWGRs, but also suppresses background noise to an extremely low level through microstructured optical field manipulation, providing an ideal passive core device solution for high-density, high signal-to-noise ratio on-chip optical interconnect networks.

[0109] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Although embodiments of the present application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the claims and their equivalents.

Claims

1. An arrayed waveguide grating router, characterized in that, The arrayed waveguide grating router includes: at least two arrayed waveguide structures and a planar waveguide structure, wherein at least two of the arrayed waveguide structures are connected to the planar waveguide structure; In the region where at least two of the arrayed waveguide structures are connected to the planar waveguide structure, an isolation deep groove is provided between two adjacent arrayed waveguide structures, the isolation deep groove extends along the extension direction of the arrayed waveguide structure, and an isolation material is provided in the isolation deep groove.

2. The arrayed waveguide grating router according to claim 1, characterized in that, The arrayed waveguide structure includes: Substrate layer; A planar waveguide, wherein the planar waveguide is disposed on the substrate layer; A ridge waveguide, wherein the ridge waveguide is disposed on the planar waveguide; The isolation trench cuts off the planar waveguide components of two adjacent array waveguide structures, extending directly to the substrate layer.

3. The arrayed waveguide grating router according to claim 2, characterized in that, The distance between the first surface of the ridge waveguide and the first wall of the isolation deep trench is greater than or equal to the distance threshold. Wherein, the first surface is the side of the ridge waveguide facing the isolation trench; the first trench wall is the trench wall of the isolation trench facing the ridge waveguide.

4. The arrayed waveguide grating router according to claim 1, characterized in that, The surface of the wall of the isolation trench is roughened, and the roughened surface is configured to cause diffuse reflection of the optical signal.

5. The arrayed waveguide grating router according to claim 1, characterized in that, The arrayed waveguide grating router also includes: A parasitic drainage waveguide structure, one end of which is disposed in the isolation deep groove, and the parasitic drainage waveguide structure extends along the direction of the isolation deep groove; The parasitic waveguide structure is used to absorb optical signals within the isolation trench.

6. The arrayed waveguide grating router according to claim 5, characterized in that, The arrayed waveguide structure includes: Substrate layer; A planar waveguide, wherein the planar waveguide is disposed on the substrate layer; A ridge waveguide, wherein the ridge waveguide is disposed on the planar waveguide; One end of the parasitic waveguide structure is connected to the substrate layer.

7. The arrayed waveguide grating router according to claim 6, characterized in that, The height of the parasitic drainage waveguide structure in the first direction is the same as the height of the arrayed waveguide structure in the first direction; Wherein, the first direction is the direction from the substrate layer to the ridge waveguide.

8. The arrayed waveguide grating router according to claim 5, characterized in that, The second surface of the parasitic waveguide structure has a smooth surface; The second surface is the surface of the parasitic waveguide structure facing the wall of the isolation trench.

9. The arrayed waveguide grating router according to claim 5, characterized in that, A light guide structure is provided on the end of the parasitic waveguide structure that is away from the planar waveguide structure. The light guiding structure is used to guide the optical signal absorbed by the parasitic waveguide structure to a predetermined area.

10. The arrayed waveguide grating router according to any one of claims 5 to 9, characterized in that, The number of the parasitic drainage waveguide structure is at least one; At least one of the parasitic drainage waveguide structures is arranged in parallel.

11. A photonic integration platform, characterized in that, Includes an arrayed waveguide grating router as described in any one of claims 1 to 10.

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