Optical chip, chip structure and preparation method of optical chip

Abstract

This invention provides an optical chip, a chip structure, and a method for fabricating the optical chip, comprising: a dielectric layer located on a substrate; an optical device layer including a core layer and a first cladding layer covering the core layer; the core layer in one optical device layer and the core layer in another optical device layer respectively having overlapping coupling regions along the thickness direction of the substrate, the coupling regions including non-closed ring waveguides; a via structure layer located between the two optical device layers, the via structure layer including at least one micro-ring waveguide and a second cladding layer covering the micro-ring waveguide, the micro-ring waveguide being located between the two overlapping coupling regions; the micro-ring waveguide including a closed ring waveguide; wherein, the center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the micro-ring waveguide located between the coupling regions are on the same straight line, and the radii of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the micro-ring waveguide located between the coupling regions are the same, realizing multi-layer stacking and simplifying fabrication.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to an optical chip, a chip structure, and a method for fabricating the optical chip. Background Technology

[0002] With the rapid development of technologies such as artificial intelligence and cloud computing, modern society's requirements for chip performance continue to increase. Optical interconnects, due to their advantages of large transmission bandwidth, high spatial density, low power consumption, and strong anti-crosstalk capability, are gradually replacing electrical interconnects, which have reached a bottleneck due to inherent defects, and have become the preferred solution for signal transmission within and between chips.

[0003] However, optical signals are limited in their transmission direction, almost exclusively propagating within a single horizontal plane. Furthermore, the waveguide dimensions and coupling spacing used for optical signal transmission are much smaller than the metal wires and vias used for high-frequency electrical signal transmission. This makes it difficult to achieve multi-layer stacking of optical waveguides and metal wires on the same chip, hindering the improvement of packaging density. To achieve multi-layer stacking of chip structures, existing technologies mainly employ straight waveguide coupling or ladder-type optical vias to achieve vertical coupling transmission of optical signals. However, straight waveguide coupling easily increases the size of the optical chip and cannot cover large vertical heights, still hindering the improvement of packaging density. Ladder-type optical vias, on the other hand, suffer from complex fabrication processes and difficulty in controlling device quality. Therefore, how to achieve multi-layer stacking of optical chips while reducing the size of the optical chip and simplifying the fabrication process has become one of the urgent technical challenges to be solved.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an optical chip, a chip structure, and a method for fabricating the optical chip, so as to solve the problem that it is difficult to reduce the package size and simplify the fabrication process of optical chips while achieving multi-layer stacking in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides an optical chip, comprising:

[0007] Substrate;

[0008] A dielectric layer is located on the substrate;

[0009] At least two optical device layers are sequentially stacked on the dielectric layer. Each optical device layer includes a core layer and a first cladding layer covering the core layer. The core layer in one optical device layer and the core layer in the other optical device layer each have a coupling region that overlaps with each other along the thickness direction of the substrate. The coupling region includes a non-closed ring waveguide.

[0010] A via structure layer is located between two optical device layers. The via structure layer includes at least one microring waveguide and a second cladding layer covering the microring waveguide. The microring waveguide is located between the two overlapping coupling regions. The microring waveguide includes a closed ring waveguide.

[0011] Wherein, the center of the non-closed loop waveguide in the overlapping coupling region and the center of the closed loop waveguide in the micro-loop waveguide located between the coupling regions are on the same straight line, and the radius of the non-closed loop waveguide in the overlapping coupling region and the closed loop waveguide in the micro-loop waveguide located between the coupling regions are the same.

[0012] In one embodiment, the optical chip further includes:

[0013] The closed loop waveguide and the non-closed loop waveguide have the same width along the direction of light wave propagation; or,

[0014] The waveguide width of the closed loop waveguide and the waveguide width of the non-closed loop waveguide gradually change along the direction of light propagation. In one embodiment, the via structure layer includes N micro-loop waveguides and N second cladding layers covering the micro-loop waveguides; wherein, one second cladding layer covers one micro-loop waveguide, and multiple micro-loop waveguides and second cladding layers are stacked sequentially along a direction perpendicular to the top surface of the substrate; wherein, N is greater than or equal to 2.

[0015] In one embodiment, the vertical spacing between the two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer.

[0016] In one embodiment, the optical chip further includes:

[0017] An electrical connection structure is located within the first cladding layer and the second cladding layer, and the electrical connection structure is correspondingly connected to a core layer.

[0018] Secondly, this application also provides a chip structure, including an optical chip and an electronic integrated circuit as described in any one of the embodiments of this application; wherein the optical chip and the electronic integrated circuit are connected.

[0019] Thirdly, this application also provides a method for fabricating an optical chip, comprising:

[0020] Provide substrate;

[0021] A dielectric layer is formed on the substrate;

[0022] A first optical device layer is formed on the dielectric layer, the optical device layer including a core layer and a first cladding layer covering the core layer;

[0023] A via structure layer is formed on the first optical device layer, the via structure layer including at least one micro-ring waveguide and a second cladding layer covering the micro-ring waveguide;

[0024] A second optical device layer is formed on the via structure layer, the optical device layer including a core layer and a first cladding layer covering the core layer;

[0025] The core layers of the first and second optical device layers each have overlapping coupling regions along the thickness direction of the substrate. The microring waveguide is located between the two overlapping coupling regions. Each coupling region includes a non-closed ring waveguide and the microring waveguide includes a closed ring waveguide. The center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the microring waveguide between the coupling regions are on the same straight line, and the radii of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the microring waveguide between the coupling regions are the same.

[0026] In one embodiment, the method for fabricating the optical chip further includes:

[0027] The closed loop waveguide and the non-closed loop waveguide have the same width along the direction of light wave propagation; or,

[0028] The waveguide width of the closed loop waveguide and the waveguide width of the non-closed loop waveguide gradually change along the propagation direction of the light wave. In one embodiment, the via structure layer includes N micro-loop waveguides and N second cladding layers covering the micro-loop waveguides; forming the via structure layer on the first optical device layer includes:

[0029] A micro-ring waveguide and a second cladding layer covering the micro-ring waveguide are formed on the first optical device layer;

[0030] Repeat the above steps until the vertical height of the via structure in the thickness direction of the substrate reaches the preset height;

[0031] Where N is greater than or equal to 2.

[0032] In one embodiment, the vertical spacing between the two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer.

[0033] As described above, the optical chip, chip structure, and method for fabricating the optical chip of the present invention have the following beneficial effects:

[0034] The optical chip, chip structure, and method for fabricating the optical chip of the present invention include a substrate, a dielectric layer, at least two optical device layers sequentially stacked on the dielectric layer, and a via structure layer; the dielectric layer is located on the substrate; the optical device layer includes a core layer and a first cladding layer covering the core layer; the core layer in one optical device layer and the core layer in another optical device layer respectively have coupling regions that overlap each other along the thickness direction of the substrate, and the coupling regions include non-closed ring waveguides; the via structure layer is located between the two optical device layers, and the via structure layer includes at least one micro-ring waveguide and a second cladding layer covering the micro-ring waveguide, the micro-ring waveguide being located between the two overlapping coupling regions; the micro-ring waveguide includes a closed ring waveguide; wherein, the center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the micro-ring waveguide located between the coupling regions are on the same straight line, and the radii of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the micro-ring waveguide located between the coupling regions are the same. This application achieves a multi-layer stacked structure by placing a via structure layer between two optical device layers and a micro-ring waveguide in the via structure layer between two coupling regions, thereby enabling light waves to couple from one optical device layer to another through the via structure layer. Since the micro-ring waveguide includes a closed ring waveguide and the coupling region includes a non-closed ring waveguide, the closed and non-closed ring waveguides do not require special structures in the vertical direction. Each waveguide layer can be fabricated using the same process as planar waveguides, thus simplifying the fabrication process. Compared to straight waveguide coupling, the micro-ring waveguide, as a via, can span a larger vertical distance without occupying a large volume, thereby improving the packaging density. Attached Figure Description

[0035] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0036] Figure 1 This is a schematic flowchart of a method for fabricating an optical chip according to an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the structure obtained in step S104 of the optical chip fabrication method provided in one embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the structure obtained in step S106 of the optical chip fabrication method provided in one embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the structure obtained in step S108 of the optical chip fabrication method provided in one embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the structure of the coupling region provided in one embodiment of this application;

[0041] Figure 6 This is a schematic diagram of the microring waveguide provided in one embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the microring waveguide provided in another embodiment of this application;

[0043] Figure 8 This is a schematic diagram of the overlapping coupling regions and micro-ring waveguide in an optical chip provided in one embodiment of this application;

[0044] Figure 9 This is a schematic diagram of the structure obtained in step S110 of the optical chip fabrication method provided in one embodiment of this application;

[0045] Figure 10 This is a top view of the coupling region provided in one embodiment of this application;

[0046] Figure 11 This is a top view of the microring waveguide provided in one embodiment of this application.

[0047] Figure 12 This is a top view of the coupling region provided in another embodiment of this application;

[0048] Figure 13 This is a schematic diagram of the structure of an optical chip provided in one embodiment of this application;

[0049] Figure 14 This is a schematic diagram of the structure of an optical chip provided in another embodiment of this application;

[0050] Figure 15 This is a schematic diagram of the structure of the optical chip provided in another embodiment of this application;

[0051] Figure 16 This is a top view of the coupling region provided in another embodiment of this application;

[0052] Figure 17 This is a top view of the coupling region provided in another embodiment of the present application;

[0053] Figure 18 This is a top view of the microring waveguide provided in another embodiment of this application. Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0056] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0059] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] As mentioned in the background section, optical signals are limited in their transmission direction, almost exclusively propagating within a single horizontal plane. This makes it difficult to achieve multi-layer stacking of optical waveguides within an optical chip, thus restricting the improvement of packaging density. In existing technologies, multi-layer stacking of optical waveguides can be achieved using straight waveguide coupling. This method involves using straight waveguides for transmission within the same horizontal plane and coupling different layers of straight waveguides in the vertical direction, allowing the optical signal to propagate vertically. However, straight waveguide coupling has a short coupling distance, making it difficult to span large vertical distances and accommodate metal wires. Furthermore, since straight waveguide coupling uses evanescent wave coupling, a large straight waveguide length is required, resulting in a large optical chip package size. Additionally, close spacing between different layers of straight waveguides can cause crosstalk between waveguides in uncoupled areas. Using trapezoidal optical vias to achieve multi-layer stacking of optical waveguides involves setting the optical vias between different layers to a trapezoidal shape, allowing the optical signal to propagate vertically. However, the fabrication process for trapezoidal optical vias is complex, and device quality is difficult to control.

[0062] For the reasons mentioned above, please refer to Figures 1-15 This application provides a method for fabricating an optical chip, comprising: steps S102-S110.

[0063] Step S102: Provide substrate 10.

[0064] As an example, substrate 10 may be constructed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 10 may be a single-layer structure or a multi-layer structure. For example, substrate 10 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 10 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of substrate 10 should not limit the scope of protection of this disclosure.

[0065] Step S104: Form a dielectric layer 20 on the substrate 10.

[0066] As an example, the material of the dielectric layer 20 may include a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a silicon oxynitride layer, etc. This application does not impose specific restrictions on the material of the dielectric layer 20, as long as it can be matched with the refractive index of the core layer 302 so that the optical signal can be transmitted within the core layer 302.

[0067] Step S106: A first optical device layer 30 is formed on the dielectric layer 20. The optical device layer 30 includes a core layer 302 and a first cladding layer 306 covering the core layer 302.

[0068] As an example, the material of the core layer 302 may include silicon dioxide, monocrystalline silicon, silicon nitride, polymer materials, etc. The material of the first cladding layer 306 may include silicon dioxide, a silicon nitride layer, aluminum oxide, or a silicon oxynitride layer, etc. This application does not impose specific limitations on the materials of the core layer 302 and the first cladding layer 306.

[0069] As an example, the first cladding layer 306 covering the core layer 302 includes the first cladding layer 306 covering the surface of the core layer 302 except for the bottom surface, or the core layer 302 is located inside the first cladding layer 306. For example, the core layer 302 in the first optical device layer 30 is located on the dielectric layer 20, and the first cladding layer 306 in the first optical device layer 30 covers the dielectric layer 20 and the core layer 302 in the first optical device layer 30, or the first cladding layer 306 in the first optical device layer 30 is located on the dielectric layer 20, and the core layer 302 in the first optical device layer 30 is located inside the first cladding layer 306 in the first optical device layer 30.

[0070] Step S108: A via structure layer 40 is formed on the first optical device layer 30. The via structure layer 40 includes at least one micro-ring waveguide 402 and a second cladding layer 404 covering the micro-ring waveguide 402.

[0071] As an example, the material of the micro-ring waveguide 402 may include silicon dioxide, single-crystal silicon, silicon nitride, polymer materials, etc. The material of the second cladding 404 may include silicon dioxide, a silicon nitride layer, aluminum oxide, or a silicon oxynitride layer, etc. This application does not impose specific limitations on the materials of the micro-ring waveguide 402 and the second cladding 404. For example, the first cladding 306 and the second cladding 404 may be made of the same material. If the first cladding 306 and the second cladding 404 are made of the same material, such as... Figure 4 As shown, a cladding layer of 60 is used for illustration. Among them, Figure 4 The process of preparing a magnified view of the area defined by the dashed box is as follows: Figures 5-7 As shown.

[0072] As an example, the second cladding 404 covering the microring waveguide 402 includes: the second cladding 404 covering the surface of the microring waveguide 402 other than the bottom surface, or the microring waveguide 402 being located within the second cladding 404. For example, the microring waveguide 402 in the first via structure layer 40 is located on the first optical device layer 30, and the second cladding 404 in the first via structure layer 40 covers the first optical device layer 30 and the microring waveguide 402, or the second cladding 404 in the first via structure layer 40 is located on the first optical device layer 30, and the microring waveguide 402 in the first via structure layer 40 is located within the second cladding 404 in the first via structure layer 40.

[0073] Step S110: A second optical device layer 30 is formed on the via structure layer 40. The optical device layer 30 includes a core layer 302 and a first cladding layer covering the core layer 302. The core layer 302 in the first optical device layer 30 and the core layer 302 in the second optical device layer 30 each have overlapping coupling regions 304 along the thickness direction of the substrate 10. A micro-ring waveguide 402 is located between the two overlapping coupling regions 304. The coupling region 304 includes a non-closed ring waveguide. The micro-ring waveguide 402 includes a closed ring waveguide. The center of the non-closed ring waveguide of the overlapping coupling region 304 and the center of the closed ring waveguide of the micro-ring waveguide 402 located between the coupling regions 304 are on the same straight line, and the radii of the non-closed ring waveguide of the overlapping coupling region 304 and the closed ring waveguide of the micro-ring waveguide 402 located between the coupling regions 304 are the same.

[0074] in, Figure 9 A magnified view of the area defined by the dashed box is shown below. Figure 8 As shown.

[0075] Please refer to the following: Figures 10-12 A non-closed loop waveguide is a non-perfect circular ring, while a closed loop waveguide is a perfect circular ring. As an example, the line connecting the center points of multiple cross-sections of a non-closed loop waveguide is the centerline of the ring containing the non-closed loop waveguide, and the radius of the non-closed loop waveguide is the radius of the centerline of the ring containing the non-closed loop waveguide. Similarly, the line connecting the center points of multiple cross-sections of a closed loop waveguide is the centerline of the ring containing the closed loop waveguide, and the radius of the closed loop waveguide is the radius of the centerline of the ring containing the closed loop waveguide.

[0076] As an example, the center of the non-closed loop waveguide of the overlapping coupling regions 304 and the center of the closed loop waveguide of the micro-loop waveguide 402 located between the coupling regions 304 are on the same straight line, which is parallel to the thickness direction of the substrate 10.

[0077] In the above embodiments, the method for fabricating an optical chip includes: providing a substrate; forming a dielectric layer on the substrate; forming a first optical device layer on the dielectric layer, the optical device layer including a core layer and a first cladding layer covering the core layer; forming a via structure layer on the first optical device layer, the via structure layer including at least one microring waveguide and a second cladding layer covering the microring waveguide; forming a second optical device layer on the via structure layer, the optical device layer including a core layer and a first cladding layer covering the core layer; wherein, the core layer in the first optical device layer and the core layer in the second optical device layer respectively have coupling regions that overlap each other along the thickness direction of the substrate, and the microring waveguide is located between the two overlapping coupling regions; the coupling region includes a non-closed ring waveguide; the microring waveguide includes a closed ring waveguide; the center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the microring waveguide located between the coupling regions are on the same straight line, and the radius of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the microring waveguide located between the coupling regions are the same. This application achieves a multi-layer stacked structure by placing a via structure layer between two optical device layers and a micro-ring waveguide in the via structure layer between two coupling regions, thereby enabling light waves to couple from one optical device layer to another through the via structure layer. Since the micro-ring waveguide includes a closed ring waveguide and the coupling region includes a non-closed ring waveguide, the closed and non-closed ring waveguides do not require special structures in the vertical direction. Each waveguide layer can be fabricated using the same process as planar waveguides, thus simplifying the fabrication process. Compared to straight waveguide coupling, the micro-ring waveguide, as a via, can span a larger vertical distance without occupying a large volume, thereby improving the packaging density.

[0078] In some embodiments, please refer to Figures 13-15 The method for fabricating an optical chip further includes the steps of forming a via structure layer 40 on a second optical device layer 30 and forming a third optical device layer 30 on the via structure layer 40; wherein, the core layer 302 in the second optical device layer 30 and the core layer 302 in the third optical device layer 30 each have overlapping coupling regions 304 along the thickness direction of the substrate 10, and a micro-ring waveguide 402 is located between the two overlapping coupling regions 304; the coupling region 304 includes a non-closed ring waveguide; the micro-ring waveguide 402 includes a closed ring waveguide; the center of the non-closed ring waveguide of the overlapping coupling region 304 and the center of the closed ring waveguide of the micro-ring waveguide 402 located between the coupling regions 304 are on the same straight line, and the radii of the non-closed ring waveguide of the overlapping coupling region 304 and the closed ring waveguide of the micro-ring waveguide 402 located between the coupling regions 304 are the same.

[0079] As an example, the first cladding layer 306 and the second cladding layer 404 can be made of the same material. If the first cladding layer 306 and the second cladding layer 404 are made of the same material, such as... Figures 13-15As shown, a cladding layer of 60 is used for illustration. Among them, Figures 13-15 The process of preparing a magnified view of the area defined by the dashed box is as follows: Figures 5-8 As shown.

[0080] In some embodiments, the method for fabricating an optical chip further includes: a closed loop waveguide and a non-closed loop waveguide having a waveguide width that is equal along the direction of light wave propagation.

[0081] In some embodiments, the waveguide width of a closed loop waveguide and the waveguide width of a non-closed loop waveguide gradually change along the propagation direction of the light wave.

[0082] For example, please refer to Figure 16 , Figure 17 When the non-closed ring waveguide is the coupling region in the optical device layer serving as the signal transmitting end, the waveguide width of the non-closed ring waveguide gradually decreases along the propagation direction of the light wave. When the non-closed ring waveguide is the coupling region in the optical device layer serving as the signal receiving end, the waveguide width of the non-closed ring waveguide gradually increases along the propagation direction of the light wave.

[0083] For example, please refer to Figure 18 The closed loop waveguide may include a first half-ring 412 for signal transmission and a second half-ring 414 for signal reception. The two half-rings are symmetrically distributed. The waveguide width of the first half-ring 412 gradually decreases along the direction of light wave transmission, and the waveguide width of the second half-ring 414 gradually increases along the direction of light wave transmission.

[0084] In the above embodiments, the waveguide widths of the closed-loop waveguide and the non-closed-loop waveguide gradually change along the direction of light wave propagation, thereby reducing the effective refractive index of the via structure layer, enhancing the penetration depth of the evanescent wave, and thus improving the coupling effect between waveguide layers.

[0085] In some embodiments, the via structure layer includes N micro-ring waveguides and N second cladding layers covering the micro-ring waveguides; forming the via structure layer on the first optical device layer includes: forming a micro-ring waveguide and a second cladding layer covering the micro-ring waveguide on the first optical device layer; repeating the above steps until the vertical height of the via structure in the thickness direction of the substrate reaches a preset height; wherein, N is greater than or equal to 2.

[0086] As an example, please continue to refer to Figures 5-8 N equals 2. The via structure layer 40 includes a first micro-ring waveguide 402, a first second cladding 404 covering the first micro-ring waveguide 402, a second micro-ring waveguide 402, and a second second cladding 404 covering the second micro-ring waveguide 402.

[0087] In some embodiments, please refer to Figure 4 , Figure 9as well as Figures 13-15 The method for fabricating an optical chip further includes the step of forming an electrical connection structure 50 while forming an optical device layer 30 or a via structure layer 40; the electrical connection structure 50 is located within a first cladding layer 306 and a second cladding layer 404, and an electrical connection structure 50 is correspondingly connected to a core layer 302.

[0088] As an example, the electrical connection structure 50 and the core layer 302 can be directly connected, or they can be adjusted and connected non-contactly through an electric field or other means.

[0089] In the above embodiments, the electrical connection structure 50 is used to provide the required electrical signals to the optical device layer 30.

[0090] In some embodiments, the vertical spacing between two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer.

[0091] As an example, the vertical spacing between two overlapping coupling regions along the thickness direction of the substrate is 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, etc.

[0092] In the above embodiments, the vertical spacing between two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer, thereby accommodating metal wires and enabling optical waveguides and metal wires to be stacked in the same chip.

[0093] In some embodiments, please refer to Figure 15 This application also provides an optical chip, comprising: a substrate 10, a dielectric layer 20, at least two optical device layers 30 sequentially stacked on the dielectric layer, and a via structure layer 40; wherein, the dielectric layer 20 is located on the substrate 10; the optical device layer 30 includes a core layer 302 and a first cladding layer 306 covering the core layer 302; the core layer 302 in one optical device layer 30 and the core layer 302 in another optical device layer 30 each have a coupling region 304 that overlaps with each other along the thickness direction of the substrate 10, and the coupling region 304 includes a non-closed ring waveguide; the via structure layer 40 is located between the two optical device layers 30. The via structure layer 40 includes at least one microring waveguide 402 and a second cladding 404 covering the microring waveguide 402. The microring waveguide 402 is located between two overlapping coupling regions 304. The microring waveguide 402 includes a closed ring waveguide. The center of the non-closed ring waveguide of the overlapping coupling region 304 and the center of the closed ring waveguide of the microring waveguide 402 located between the coupling regions 304 are on the same straight line, and the radii of the non-closed ring waveguide of the overlapping coupling region 304 and the closed ring waveguide of the microring waveguide 402 located between the coupling regions 304 are the same.

[0094] In the above embodiments, the optical chip includes a substrate, a dielectric layer, at least two optical device layers sequentially stacked on the dielectric layer, and a via structure layer; the dielectric layer is located on the substrate; the optical device layer includes a core layer and a first cladding layer covering the core layer; the core layer in one optical device layer and the core layer in another optical device layer respectively have coupling regions that overlap each other along the thickness direction of the substrate, and the coupling regions include non-closed ring waveguides; the via structure layer is located between the two optical device layers, and the via structure layer includes at least one micro-ring waveguide and a second cladding layer covering the micro-ring waveguide, the micro-ring waveguide is located between the two overlapping coupling regions; the micro-ring waveguide includes a closed ring waveguide; wherein, the center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the micro-ring waveguide located between the coupling regions are on the same straight line, and the radii of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the micro-ring waveguide located between the coupling regions are the same. This application achieves a multi-layer stacked structure by placing a via structure layer between two optical device layers, with a micro-ring waveguide within the via structure layer positioned between two coupling regions. This allows light waves to couple from one optical device layer to another via the via structure layer, thus realizing a multi-layer stacked structure. Since the micro-ring waveguide includes a closed-loop waveguide and the coupling region includes a non-closed-loop waveguide, neither the closed nor non-closed-loop waveguides require special structures in the vertical direction. Each waveguide layer can be fabricated using the same process as planar waveguides, resulting in a simple fabrication process. Compared to straight waveguide coupling, the micro-ring waveguide, acting as a via, can span a larger vertical distance without occupying a large volume, improving packaging density. Furthermore, the non-closed-loop waveguide prevents optical signals from entering the ring from the end, avoiding signal crosstalk.

[0095] In some embodiments, the waveguide width of the closed loop waveguide and the non-closed loop waveguide are equal along the direction of light wave propagation.

[0096] In some embodiments, the waveguide width of a closed loop waveguide and the waveguide width of a non-closed loop waveguide gradually change along the propagation direction of the light wave.

[0097] In some embodiments, the via structure layer includes N micro-ring waveguides and N second cladding layers covering the micro-ring waveguides; wherein, one second cladding layer covers one micro-ring waveguide, and multiple micro-ring waveguides and the second cladding layers are stacked sequentially along a direction perpendicular to the top surface of the substrate; wherein, N is greater than or equal to 2.

[0098] In some embodiments, the vertical spacing between two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer.

[0099] In some embodiments, the chip further includes an electrical connection structure located within the first cladding layer and the second cladding layer, wherein the electrical connection structure is connected to a core layer.

[0100] In some embodiments, this application also provides a chip structure, including an optical chip and an electronic integrated circuit according to any one of the embodiments of this application; wherein the optical chip and the electronic integrated circuit are connected.

[0101] In summary, the optical chip, chip structure, and fabrication method of the present invention include a substrate, a dielectric layer, at least two optical device layers sequentially stacked on the dielectric layer, and a via structure layer; the dielectric layer is located on the substrate; the optical device layer includes a core layer and a first cladding layer covering the core layer; the core layer in one optical device layer and the core layer in another optical device layer respectively have coupling regions that overlap each other along the thickness direction of the substrate, and the coupling regions include non-closed ring waveguides; the via structure layer is located between the two optical device layers, and the via structure layer includes at least one micro-ring waveguide and a second cladding layer covering the micro-ring waveguide, the micro-ring waveguide being located between the two overlapping coupling regions; the micro-ring waveguide includes a closed ring waveguide; wherein, the center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the micro-ring waveguide located between the coupling regions are on the same straight line, and the radii of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the micro-ring waveguide located between the coupling regions are the same. This application achieves a multi-layer stacked structure by placing a via structure layer between two optical device layers, and a micro-ring waveguide within the via structure layer between two coupling regions. This allows light waves to couple from one optical device layer to another through the via structure layer, thus realizing a multi-layer stacked structure. Since the micro-ring waveguide includes a closed ring waveguide and the coupling region includes a non-closed ring waveguide, neither the closed nor non-closed ring waveguides require special structures in the vertical direction. Each waveguide layer can be fabricated using the same process as planar waveguides, resulting in a simple fabrication process. Compared to straight waveguide coupling, the micro-ring waveguide, acting as a via, can span a larger vertical distance without occupying a large volume, thereby increasing packaging density. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An optical chip, characterized in that, include: Substrate; A dielectric layer is located on the substrate; At least two optical device layers are sequentially stacked on the dielectric layer. Each optical device layer includes a core layer and a first cladding layer covering the core layer. The core layer in one optical device layer and the core layer in the other optical device layer each have a coupling region that overlaps with each other along the thickness direction of the substrate. The coupling region includes a non-closed ring waveguide. A via structure layer is located between two optical device layers. The via structure layer includes at least one microring waveguide and a second cladding layer covering the microring waveguide. The microring waveguide is located between the two overlapping coupling regions. The microring waveguide includes a closed ring waveguide. Wherein, the center of the non-closed loop waveguide in the overlapping coupling region and the center of the closed loop waveguide in the micro-loop waveguide located between the coupling regions are on the same straight line, and the radius of the non-closed loop waveguide in the overlapping coupling region and the closed loop waveguide in the micro-loop waveguide located between the coupling regions are the same.

2. The optical chip according to claim 1, characterized in that, The optical chip also includes: The closed loop waveguide and the non-closed loop waveguide have the same width along the direction of light wave propagation; or, The waveguide width of the closed loop waveguide and the waveguide width of the non-closed loop waveguide gradually change along the direction of light wave propagation.

3. The optical chip according to claim 1, characterized in that, The via structure layer includes N micro-ring waveguides and N second cladding layers covering the micro-ring waveguides; wherein, one second cladding layer covers one micro-ring waveguide, and multiple micro-ring waveguides and second cladding layers are stacked sequentially along a direction perpendicular to the top surface of the substrate; wherein, N is greater than or equal to 2.

4. The optical chip according to claim 1, characterized in that, The vertical spacing between the two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer.

5. The optical chip according to claim 1, characterized in that, The optical chip also includes: An electrical connection structure is located within the first cladding layer and the second cladding layer, and the electrical connection structure is correspondingly connected to a core layer.

6. A chip structure, characterized in that, It includes the optical chip and electronic integrated circuit according to any one of claims 1-5; wherein the optical chip is connected to the electronic integrated circuit.

7. A method for fabricating an optical chip, characterized in that, include: Provide substrate; A dielectric layer is formed on the substrate; A first optical device layer is formed on the dielectric layer, the optical device layer including a core layer and a first cladding layer covering the core layer; A via structure layer is formed on the first optical device layer, the via structure layer including at least one micro-ring waveguide and a second cladding layer covering the micro-ring waveguide; A second optical device layer is formed on the via structure layer, the optical device layer including a core layer and a first cladding layer covering the core layer; The core layers of the first and second optical device layers each have overlapping coupling regions along the thickness direction of the substrate. The microring waveguide is located between the two overlapping coupling regions. Each coupling region includes a non-closed ring waveguide and the microring waveguide includes a closed ring waveguide. The center of the non-closed ring waveguide in the overlapping coupling region and the center of the closed ring waveguide in the microring waveguide between the coupling regions are on the same straight line, and the radii of the non-closed ring waveguide in the overlapping coupling region and the closed ring waveguide in the microring waveguide between the coupling regions are the same.

8. The method for fabricating an optical chip according to claim 7, characterized in that, The method for fabricating the optical chip further includes: The closed loop waveguide and the non-closed loop waveguide have the same width along the direction of light wave propagation; or, The waveguide width of the closed loop waveguide and the waveguide width of the non-closed loop waveguide gradually change along the direction of light wave propagation.

9. The method for fabricating an optical chip according to claim 7, characterized in that, The via structure layer includes N micro-ring waveguides and N second cladding layers covering the micro-ring waveguides; The process of forming a via structure layer on the first optical device layer includes: A micro-ring waveguide and a second cladding layer covering the micro-ring waveguide are formed on the first optical device layer; Repeat the above steps until the vertical height of the via structure in the thickness direction of the substrate reaches the preset height; Where N is greater than or equal to 2.

10. The method for fabricating an optical chip according to claim 7, characterized in that, The vertical spacing between the two overlapping coupling regions along the thickness direction of the substrate is greater than or equal to 1 micrometer.

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