Data reading and writing device, method, processor, board and computer equipment

Abstract

The embodiment of the application discloses a data reading and writing device, method, processor, board and computer equipment, and relates to the technical field of semiconductors. The device comprises a first memory, a second memory, a first request processing unit connected with the first memory, and a second request processing unit connected with the second memory; the first request processing unit is used for determining a first target request from a first candidate request, and reading and writing first data indicated by the first target request from the first memory, the first candidate request is used for requesting reading and writing the first memory, and the first request processing unit comprises an input port for receiving the first candidate request sent by a second processor; the second request processing unit is used for determining a second target request from a second candidate request, and reading and writing second data indicated by the second target request from the second memory, the second candidate request is used for requesting reading and writing the second memory, and the second request processing unit comprises an input port for receiving the second candidate request sent by a first processor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a data read / write device, method, processor, board, and computer equipment. Background Technology

[0002] Processors that process large amounts of data (such as AI processors) typically include a Vector Processing Unit (VPU) for performing vector operations and a Matrix Processing Unit (MPU) for performing matrix operations. The VPU and MPU have their own data storage units: Vector Memory (VM) stores the vector operation data of the VPU, and Matrix Memory (MM) stores the matrix operation data of the MPU.

[0003] There may be a need for integrated computing between the MPU and VPU. For example, the results of the MPU's calculations may need to be sent to the VPU for processing, or vice versa. In related technologies, to achieve integrated computing between the MPU and VPU, data transfer between the VM and MM is required through Direct Memory Access (DMA).

[0004] However, using DMA to move data between VM and MM requires a certain amount of time, and the data movement results in more read and write operations to the memory, which in turn leads to higher processor power consumption. Summary of the Invention

[0005] This application provides a data read / write device, method, processor, circuit board, and computer equipment. The technical solution is as follows:

[0006] On one hand, embodiments of this application provide a data read / write device, the device including a first memory, a second memory, a first request processing unit connected to the first memory, and a second request processing unit connected to the second memory;

[0007] The first memory is used to store first data related to the operation of the first processor, and the second memory is used to store second data related to the operation of the second processor;

[0008] The first request processing unit is configured to determine a target first request from the received candidate first requests, the candidate first request being used to request reading or writing the first memory, and the first request processing unit includes an input port for receiving the candidate first request issued by the second processor;

[0009] The first request processing unit is further configured to read and write the first data indicated by the target first request from the first memory;

[0010] The second request processing unit is configured to determine a target second request from the received candidate second requests, the candidate second request being used to request reading or writing the second memory, and the second request processing unit includes an input port for receiving the candidate second request issued by the first processor;

[0011] The second request processing unit is further configured to read and write the second data indicated by the target second request from the second memory.

[0012] On the other hand, embodiments of this application provide a data read / write method, the method comprising:

[0013] The first request processing unit determines the target first request from the received candidate first requests. The candidate first request is used to request to read or write to the first memory. The first request processing unit includes an input port for receiving the candidate first request issued by the second processor. The first request processing unit is connected to the first memory, which is used to store first data related to the operation of the first processor.

[0014] The first request processing unit reads and writes the first data indicated by the target first request from the first memory.

[0015] The second request processing unit determines the target second request from the received candidate second requests. The candidate second request is used to request reading and writing to the second memory. The second request processing unit includes an input port for receiving the candidate second request issued by the first processor. The second request processing unit is connected to the second memory, which is used to store second data related to the operation of the second processor.

[0016] The second request processing unit is further configured to read and write the second data indicated by the target second request from the second memory.

[0017] On the other hand, embodiments of this application provide a processor that is equipped with the data read / write device as described above.

[0018] On the other hand, embodiments of this application provide a board that is equipped with a processor as described above.

[0019] On the other hand, embodiments of this application provide a computer device that is provided with the boards as described above.

[0020] In this embodiment, since the first processing request unit includes an input port for receiving a first candidate request issued by the second processor, the first processing request unit can receive the first candidate request issued by the second processor to the first memory. When the first processing request unit determines the first candidate request as a first target request, the first processing request unit reads and writes the first data indicated by the first target request from the first memory, thus enabling the second processor to access the first memory. Similarly, since the second processing request unit includes an input port for receiving a second candidate request issued by the first processor, the second processing request unit can receive the second candidate request issued by the first processor to the second memory. When the second candidate request unit determines the second candidate request as a second target request, the second processing request unit reads and writes the second data indicated by the second target request from the second memory, thus enabling the first processor to access the second memory. Through the data read / write device provided in this application, data transfer between the first and second memories can be achieved without DMA, thus avoiding the time and power consumption consumed by data transfer, resulting in higher data read / write efficiency and improved processor performance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram illustrating data transfer between VM and MM via DMA in related technologies;

[0023] Figure 2 This is a schematic diagram of a data read / write device provided in an exemplary embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the input ports and output ports included in the first read request processing unit, the first write request processing unit, the second read request processing unit, and the second write request processing unit provided in an exemplary embodiment of this application;

[0025] Figure 4 This is a schematic diagram of a first read splitter, a first write splitter, a second read splitter, and a second write splitter provided in an exemplary embodiment of this application;

[0026] Figure 5This is a schematic diagram of a request processing unit provided in an exemplary embodiment of this application, including an evictarbiter unit and a trim unit;

[0027] Figure 6 This is a schematic diagram of the structure of a first read request processing unit provided in an exemplary embodiment of this application;

[0028] Figure 7 This is a schematic diagram of the structure of the first read request processing unit provided in another exemplary embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the structure of the first read request processing unit provided in another exemplary embodiment of this application;

[0030] Figure 9 This is a flowchart of a data read / write method provided in an exemplary embodiment of this application;

[0031] Figure 10 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0033] First, the terms used in the embodiments of this application will be introduced.

[0034] Vector Processing Unit (VPU): A processing unit in an AI processor used to perform vector operations. The VPU can perform operations on vector data, thus offering higher computational efficiency compared to traditional scalar processors that process individual data points one at a time. Data related to vector operations is typically stored in a vector memory. The vector processor can retrieve the data to be operated on from the vector memory, perform vector operations, and write the results back to the vector memory.

[0035] Vector Memory (VM): Used to store data related to vector operations performed by the vector processor. This includes data to be processed, intermediate results, and the final result of vector operations. The data type stored in the vector memory can be vector, numerical, matrix, tensor, linked list, set, graph, queue, or other possible types; there are no restrictions on this.

[0036] Matrix Processing Unit (MPU): A processing unit in an AI processor used to perform matrix operations. The MPU can perform operations on matrix data. Data related to matrix operations is typically stored in a matrix memory. The MPU can retrieve the data to be operated on from the matrix memory, perform matrix operations, and write the results back to the matrix memory.

[0037] Matrix memory (MM) is used to store data related to vector operations performed by a matrix processor. This includes data to be processed, intermediate results, and the final result of matrix operations. The data type stored in a matrix memory can be a matrix, or a number, vector, tensor, linked list, set, graph, queue, or any other possible type; there are no restrictions on this.

[0038] Direct Memory Access (DMA): A hardware device that performs data access (or data movement) to provide high-speed data transfer between peripherals and memory, and between memory devices. For example, DMA can move data from vector memory (VM) to matrix memory (MM), or vice versa.

[0039] In related technologies, when there is a need for converged computing between MPU and VPU, data needs to be moved between VM and MM via DMA.

[0040] See Figure 1 , Figure 1 This is a schematic diagram illustrating data transfer between VM and MM via DMA in related technologies.

[0041] like Figure 1 As shown, the vector processor (VPU) can retrieve data related to vector operations from the vector memory (VM), and the matrix processor (MPU) can retrieve data related to matrix operations from the matrix memory (MM).

[0042] When there is a need for converged computing between the MPU and VPU (e.g., the result of the MPU's operation needs to be sent to the VPU for processing, or the result of the VPU's operation may be sent to the MPU for processing), data transfer between the VM and MM needs to be performed through Direct Memory Access (DMA). DMA can also perform data transfer between the external bus and internal memory.

[0043] However, when there is a need for converged computing between the MPU and VPU, using DMA to move data between the VM and MM requires a certain amount of time, and the data movement results in more read and write operations to the memory, which in turn leads to higher processor power consumption.

[0044] Therefore, this application provides a data read / write device that enables a vector processor to access a matrix memory and a matrix processor to access a vector memory without data transfer via DMA, thereby greatly improving data read / write efficiency, reducing the number of memory read / write operations, and lowering processor power consumption.

[0045] See Figure 2 , Figure 2 This is a schematic diagram of a data read / write device provided in an exemplary embodiment of this application.

[0046] In some embodiments, the data read / write device includes a first memory, a second memory, a first request processing unit connected to the first memory, and a second request processing unit connected to the second memory.

[0047] like Figure 2 The data read / write device includes a first memory 230, a second memory 240, a first request processing unit 210, and a second request processing unit 220. The first request processing unit 210 is connected to the first memory 230, and the second request processing unit 220 is connected to the second memory 240.

[0048] The first memory is used to store first data related to the operation of the first processor, and the second memory is used to store second data related to the operation of the second processor.

[0049] Optionally, the first memory 230 and the second memory 240 may include one or more static random access memory (SRAM) or any other possible memory device, such as dynamic random access memory (DRAM), non-volatile memory, etc., without any limitation.

[0050] In some embodiments, the first processor and the second processor are different processors that perform different operations. For example, the first processor is a vector processor for performing vector operations, and the second processor is a matrix processor for performing matrix operations. Alternatively, the first processor and the second processor can also be processors that perform any other possible operations; for example, the first processor can be a tensor processor and the second processor a vector processor; or the first processor can be a matrix processor and the second processor a tensor processor.

[0051] In other embodiments, the first processor and the second processor may also be different processors performing the same operations, each corresponding to its own memory. As an example only, in the case where the first processor is a first vector processor and the second processor is a second vector processor, data related to vector operations performed by the first processor is stored in the first vector memory, and data related to vector operations performed by the second processor is stored in the second vector memory.

[0052] This specification uses the example of a first processor and a second processor performing different operations, with the first processor being a vector memory and the second processor being a matrix processor, but this does not constitute a limitation.

[0053] Optionally, when the first processor is a vector memory, the first memory is used to store first data related to vector operations. The first data can be data to be operated on during the vector operation process, intermediate operation results, and the final operation result, etc. The data type of the first data can be a vector, or it can be a number, matrix, tensor, linked list, set, graph, queue, or other possible types, without limitation.

[0054] Optionally, when the second processor is a matrix memory, the second memory is used to store second data related to matrix operations. The second data can be data to be operated on during the matrix operation process, intermediate operation results, and the final operation result, etc. The data type of the second data can be a matrix, or it can be a numerical value, vector, tensor, linked list, set, graph, queue, or other possible types, without limitation.

[0055] In some embodiments, the first request processing unit is configured to determine a first target request from the received first candidate requests and read / write first data indicated by the first target request from the first memory.

[0056] In some embodiments, the first request processing unit includes an input port for receiving a first candidate request and an output port for outputting a first target request.

[0057] The first candidate request is used to request read or write to the first memory.

[0058] Optionally, the first candidate request can be a first candidate read / write request or a first candidate write request. Specifically, the first candidate read request is used to request reading first data from the first memory; the first candidate write request is used to request writing first data to the first memory.

[0059] Optionally, different first candidate requests may come from different request sources.

[0060] In one possible scenario, the first processor may request to read or write the first data in the first memory; that is, the request source of the first candidate request may be the first processor.

[0061] In another possible scenario, Direct Memory Access (DMA) can request to read or write the first data in the first memory; that is, the request source of the first candidate request may be DMA.

[0062] In another possible scenario, the second processor may request to read or write the first data in the first memory; that is, the request source of the first candidate request may also be the second processor.

[0063] In some embodiments, the first request processing unit includes an input port for receiving a first candidate request issued by a second processor.

[0064] like Figure 2 In the first request processing unit 210, there is an input port 211 for receiving a first candidate request issued by the second processor 202.

[0065] In some embodiments, different input ports correspond to different request sources. The first request processing unit 210 receives first candidate requests sent by each request source through each input port.

[0066] In some embodiments, the same request source may correspond to at least two different input ports, without limitation.

[0067] Optionally, the first request processing unit 210 acquires a first candidate request from the input port at preset time intervals. If the request content of the first candidate request is empty, the first request processing unit 210 receives an invalid first candidate request. If the request content of the first candidate request is not empty, the first request processing unit 210 receives a valid first candidate request.

[0068] Upon receiving the first candidate request, the first request processing unit 210 determines the first target request from the first candidate requests.

[0069] Regarding the specific method of determining the first target request, in one possible scenario, the first request processing unit 210 can determine the first target request based on the validity of each first candidate request, for example, by determining the valid first candidate request as the first target request.

[0070] Regarding the specific method for determining the first target request, in another possible scenario, the first request processing unit 210 may adopt a round-robin scheduling method to schedule the first target request from each first candidate request.

[0071] Alternatively, the first request processing unit 210 may also use any other possible method to determine the first target request from the received first candidate requests. For more details on determining the first target request, please refer to the embodiments below, which will not be repeated here.

[0072] In some embodiments, the first request processing unit 210 reads and writes the first data indicated by the first target request from the first memory 230 through the output port of the first target request.

[0073] In some embodiments, the second request processing unit is configured to determine the second target request from the received second candidate requests and read / write the second data indicated by the second target request from the second memory.

[0074] In some embodiments, the second request processing unit includes an input port for receiving a second candidate request and an output port for outputting a second target request.

[0075] The second candidate request is used to request reading or writing to the second memory.

[0076] Optionally, the second candidate request can be a second candidate read / write request or a second candidate write request. Specifically, a second candidate read request is used to request reading second data from the second memory; a second candidate write request is used to request writing second data to the second memory.

[0077] Optionally, different second candidate requests may come from different request sources.

[0078] In one possible scenario, the second processor may request to read or write second data in the second memory; that is, the source of the second candidate request may be the second processor.

[0079] In another possible scenario, direct memory access (DMA) can request to read or write second data in a second memory; that is, the source of the second candidate request may be DMA.

[0080] In another possible scenario, the first processor may request to read or write the second data in the second memory; that is, the source of the second candidate request may also be the first processor.

[0081] In some embodiments, the second request processing unit includes an input port for receiving a second candidate request issued by the first processor.

[0082] like Figure 2 In the process, the second request processing unit 220 includes an input port 221 for receiving a second candidate request issued by the first processor 201.

[0083] In some embodiments, different input ports correspond to different request sources. The second request processing unit 220 receives second candidate requests sent by each request source through each input port.

[0084] In some embodiments, the same request source may correspond to at least two different input ports, without limitation.

[0085] Optionally, the second request processing unit 220 acquires a second candidate request from the input port at preset time intervals. If the request content of the second candidate request is empty, the second request processing unit 220 receives an invalid second candidate request. If the request content of the second candidate request is not empty, the second request processing unit 220 receives a valid second candidate request.

[0086] Upon receiving the second candidate request, the second request processing unit 220 determines the second target request from the second candidate requests.

[0087] Regarding the specific method of determining the second target request, in one possible scenario, the second request processing unit 220 can determine the second target request based on the validity of each second candidate request, for example, by determining the valid second candidate request as the second target request.

[0088] Regarding the specific method for determining the second target request, in another possible scenario, the second request processing unit 220 may adopt a round-robin scheduling method to schedule the second target request from each second candidate request.

[0089] Alternatively, the second request processing unit 220 may also determine the second target request from the received second candidate requests in any other possible manner. For more details on determining the second target request, please refer to the embodiments below, which will not be repeated here.

[0090] In some embodiments, the second request processing unit 220 reads and writes the second data indicated by the second target request from the second memory 240 through the output port of the second target request.

[0091] It should be noted that the above embodiments only illustrate the general architecture of the data read and write device. The device may also include more or fewer components, or combine certain components. This embodiment does not limit this.

[0092] In summary, since the first processing request unit includes an input port for receiving a first candidate request from the second processor, it can receive the first candidate request from the second processor to the first memory. When the first processing request unit determines the first candidate request to be a first target request, it reads and writes the first data indicated by the first target request from the first memory, thus enabling the second processor to access the first memory. Similarly, since the second processing request unit includes an input port for receiving a second candidate request from the first processor, it can receive the second candidate request from the first processor to the second memory. When the second candidate request unit determines the second candidate request to be a second target request, it reads and writes the second data indicated by the second target request from the second memory, thus enabling the first processor to access the second memory. The data read / write device provided in this application eliminates the need for data transfer between the first and second memories via DMA, enabling the first processor to access the second memory and the second processor to access the first memory. This avoids the time and power consumption associated with data transfer, resulting in higher data read / write efficiency and improved processor performance.

[0093] In one possible scenario, the request processing unit receives candidate requests through an input port and outputs the target request through an output port.

[0094] In some embodiments, the first request processing unit is configured to receive a first candidate request through a first request input port.

[0095] The first designated request input port in the first request input port is used to receive the first designated candidate request, and the first designated candidate request is the first candidate request issued by the second processor.

[0096] In related technologies, there is no input port for receiving the first candidate request sent by the second processor, that is, the second processor cannot access the first memory. However, in this embodiment, the first request processing unit can receive the first candidate request sent by the second processor through the first designated request input port, thereby enabling the second processor to access the first memory.

[0097] In some embodiments, the first request processing unit is further configured to read and write first data indicating the first target request from the first memory through the first request output port.

[0098] The number of first request output ports is the same as the number of read / write ports of the first memory, and the number of first request input ports is greater than the number of first request output ports.

[0099] For illustrative purposes only, the number of first request input ports is 4, and the number of first request output ports and read / write ports of the first memory are both 3. This example will be used in the following description, but those skilled in the art can arbitrarily set the number of first request input ports, first request output ports, and read / write ports of the first memory according to actual needs, as long as the number of first request output ports is the same as the number of read / write ports of the first memory, and the number of first request input ports is greater than the number of first request output ports. For example, the number of first request input ports could be 8, and the number of first request output ports and read / write ports of the first memory could both be 6; no restrictions are imposed in this regard.

[0100] Increasing the number of read / write ports in the first memory would result in a large number of traces between the newly added read / write ports and the various SRAMs in the first memory, thus increasing the processor area. For example, if the number of first request input ports is 4, the number of first request output ports and the number of read / write ports in the first memory would need to be increased from 3 to 4, leading to a large number of traces between the newly added first memory read / write ports and the various SRAMs in the first memory. However, in the data read / write device of this embodiment, for example, if the number of first request input ports is 4, the number of first request output ports and the number of read / write ports in the first memory remain at 3. Since the number of first request output ports is the same as the number of read / write ports in the first memory, the processor performance is improved while avoiding the large number of traces caused by the newly added read / write ports, thus saving processor area.

[0101] Similarly, the second request processing unit has similar settings to the first request processing unit.

[0102] In some embodiments, the second request processing unit is configured to receive a second candidate request through a second request input port.

[0103] The second designated request input port in the second request input port is used to receive the second designated candidate request, and the second designated candidate request is the second candidate request issued by the first processor.

[0104] In related technologies, there is no input port for receiving a second candidate request sent by the first processor, that is, the first processor cannot access the second memory. However, in this embodiment, the second request processing unit can receive the second candidate request sent by the first processor through the second designated request input port, thereby enabling the first processor to access the second memory.

[0105] In some embodiments, the second request processing unit is further configured to read and write second data indicated by the second target request from the second memory through the second request output port.

[0106] The number of second request output ports is the same as the number of read / write ports of the second memory, and the number of second request input ports is greater than the number of second request output ports.

[0107] For illustrative purposes only, the number of second request input ports is 3, and the number of second request output ports and read / write ports of the second memory are both 2. This example will be used in the following description, but those skilled in the art can arbitrarily set the number of second request input ports, second request output ports, and read / write ports of the second memory according to actual needs, as long as the number of second request output ports is the same as the number of read / write ports of the first memory, and the number of second request input ports is greater than the number of second request output ports. For example, the number of second request input ports could be 7, and the number of second request output ports and read / write ports of the second memory could both be 5; no restrictions are imposed in this regard.

[0108] Increasing the number of read / write ports in the second memory would result in a large number of traces between the newly added read / write ports and the various SRAMs in the second memory, thus increasing the processor area. For example, if the number of second request input ports is 3, the number of second request output ports and the number of read / write ports in both the second and second memory need to be increased from 2 to 3, leading to a large number of traces between the newly added second memory read / write ports and the various SRAMs in the second memory. However, in the data read / write device of this embodiment, for example, if the number of second request input ports is 3, the number of second request output ports and the number of read / write ports in the second memory remain at 2. Since the number of second request output ports is the same as the number of read / write ports in the second memory, the processor performance is improved while avoiding the large number of traces caused by the newly added read / write ports, thus saving processor area.

[0109] In some embodiments, the first request processing unit includes a first read request processing unit and a first write request processing unit. The second request processing unit includes a second read request processing unit and a second write request processing unit.

[0110] See Figure 3 , Figure 3 This is a schematic diagram of the input ports and output ports included in the first read request processing unit, the first write request processing unit, the second read request processing unit, and the second write request processing unit provided in an exemplary embodiment of this application.

[0111] In some embodiments, the first read request processing unit is configured to determine a first target read request from a first candidate read request received through a first read request input port, and to read first read data indicated by the first target read request from a first memory through a first read request output port.

[0112] The number of first read request output ports is the same as the number of read ports of the first memory, and the number of first read request input ports is greater than the number of first read request output ports.

[0113] like Figure 3 As shown, the first request processing unit includes a first read request processing unit 310 and a first write request processing unit 320.

[0114] The first read request processing unit 310 has four first read request input ports, including ports 311, 312, 313, and 314. The number of first read request output ports is the same as the number of read ports in the first memory, both being three. Specifically, the first read request output ports include ports 315, 316, and 317, and the first memory read ports include ports 351, 352, and 353.

[0115] Port 314 is the first designated read request input port, used to receive the first designated candidate read request, and the first designated candidate read request is the first candidate read request issued by the second processor 302.

[0116] In some embodiments, the first write request processing unit is configured to determine a first target write request from a first candidate write request received through a first write request input port, and to write first write data indicating the first target write request to a first memory through a first write request output port.

[0117] The number of first write request output ports is the same as the number of write ports of the first memory, and the number of first write request input ports is greater than the number of first write request output ports.

[0118] like Figure 3 In the first write request processing unit 320, there are 3 first write request input ports and 2 first write request output ports. The first memory 350 includes 2 write ports.

[0119] Port 321 is the first designated write request input port, used to receive the first designated candidate write request, and the first designated candidate write request is the first candidate write request issued by the second processor 302.

[0120] Similarly, in some embodiments, the second read request processing unit is used to determine a second target read request from a second candidate read request received through the second read request input port, and to read the second read data indicated by the second target read request from the second memory through the second read request output port.

[0121] The number of second read request output ports is the same as the number of read ports of the second memory, and the number of second read request input ports is greater than the number of second read request output ports.

[0122] like Figure 3 In the second read request processing unit 330, there are 4 second read request input ports and 3 second read request output ports. The second memory 360 includes 3 read ports.

[0123] Port 331 is the second designated read request input port, used to receive the second designated candidate read request, and the second designated candidate read request is the second candidate read request issued by the first processor 301.

[0124] In some embodiments, the second write request processing unit is configured to determine a second target write request from a first candidate write request received through a second write request input port, and to write second write data indicating the second target write request to a second memory through a second write request output port.

[0125] The number of second write request output ports is the same as the number of write ports of the second memory, and the number of second write request input ports is greater than the number of second write request output ports.

[0126] like Figure 3 In the second write request processing unit 340, there are 3 second write request input ports and 2 second write request output ports. The second memory 360 includes 2 read ports.

[0127] Port 341 is the second designated write request input port, used to receive the second designated candidate write request, and the second designated candidate write request is the second candidate write request issued by the first processor 301.

[0128] The following explanation uses the example of a first memory being a vector memory, a second memory being a matrix memory, a first processor being a vector processor, and a second processor being a matrix processor.

[0129] Since the first processor can send requests to the first memory or the second memory, and the second processor can also send requests to the first memory or the second memory, the requests can be sent to the corresponding request processing units through a splitter to read and write the corresponding memory.

[0130] In some embodiments, the data read / write device further includes a first splitter and a second splitter.

[0131] The first splitter is connected to the first request processing unit and the second request processing unit, respectively, and the second splitter is connected to the first request processing unit and the second request processing unit, respectively.

[0132] In some embodiments, the first splitter includes a first read splitter and a first write splitter, and the second splitter includes a second read splitter and a second write splitter.

[0133] See Figure 4 , Figure 4 This is a schematic diagram of a first read splitter, a first write splitter, a second read splitter, and a second write splitter provided in an exemplary embodiment of this application.

[0134] In some embodiments, the first splitter is configured to send the first read / write request as a second candidate request to the second request processing unit when the first read / write address contained in the first read / write request issued by the first processor belongs to the second memory; or, when the first read / write address belongs to the first memory, send the first read / write request as a first candidate request to the first request processing unit.

[0135] Taking the first read splitter 401 as an example, if the first read address contained in the first read request vr0 (vector read0) issued by the first processor belongs to the second memory 460, the first read splitter 401 sends vr0 as the second candidate request to the second read request processing unit 430; or, if the first read address belongs to the first memory 450, it sends vr0 as the first candidate request to the first read request processing unit 410.

[0136] Taking the first write splitter 402 as an example, if the first write address contained in the first write request vw (vector write) issued by the first processor belongs to the second memory 460, the first write splitter 402 sends vw as the second candidate request to the second write request processing unit 440; or, if the first write address belongs to the first memory 450, it sends vw as the first candidate request to the first write request processing unit 420.

[0137] In some embodiments, the second splitter is used to send the second read / write request as a first candidate request to the first request processing unit when the second read / write address contained in the second read / write request issued by the second processor belongs to the first memory; or, when the second read / write address belongs to the second memory, the second read / write request is sent as a second candidate request to the second request processing unit.

[0138] Taking the second read splitter 403 as an example, if the second read address contained in the second read request mr0 (matrix read0) issued by the second processor belongs to the first memory 450, the second read request is sent to the first read request processing unit 410 as the first candidate request; or, if the second read address belongs to the second memory 460, the second read request is sent to the second read request processing unit 430 as the second candidate request.

[0139] Taking the second write splitter 404 as an example, if the second write address contained in the second write request mw (matrix write) issued by the second processor belongs to the first memory 450, the second write request is sent to the first write request processing unit 420 as the first candidate request; or, if the second write address belongs to the second memory 460, the second write request is sent to the second write request processing unit 440 as the second candidate request.

[0140] In some embodiments, when the first read / write request issued by the first processor is a request to read or write the first memory, it does not need to go through a splitter, such as the first read request vr1(vector read 1) being a request that does not need to go through a splitter.

[0141] In some embodiments, when the second read / write request issued by the second processor is a request to read or write the second memory, it does not need to go through the splitter, such as the second read request mr1 (matrix read 1) being a request that does not need to go through the splitter.

[0142] In some embodiments, DMA can send read / write requests to a first memory or a second memory. For example... Figure 4 In the code, dvr (dma vector read) is a DMA request to read from the first memory; dvw (dma vector write) is a DMA request to write to the first memory; dmr (dma matrix read) is a DMA request to read from the second memory; and dvw (dma matrix write) is a DMA request to write to the second memory.

[0143] Since the number of request input ports is greater than the number of request output ports, the request processing unit needs to identify the smaller number of target requests from the larger number of candidate requests.

[0144] Regarding the specific process of identifying the target request from the candidate requests, in some embodiments, the request processing unit includes an evict arbiter and a trim unit. For example, a first request processing unit includes a first evict arbiter and a first trim unit, and a second request processing unit includes a second evict arbiter and a second trim unit.

[0145] The first eviction arbitration unit is used to determine the first invalid request from the first non-designated candidate requests received from the first request input port other than the first designated request input port; the first pruning unit is used to prune the first invalid request.

[0146] The validity of a request can be categorized as either valid or invalid.

[0147] Regarding the specific method by which the request processing unit determines the validity of a request, in some embodiments, if the request content is empty, the request is considered invalid; if the request content is not empty, the request is considered valid.

[0148] Regarding the specific method by which the request processing unit determines the validity of a request, in some embodiments, the request includes a validity identifier. For example, if the validity identifier is 1, the request is a valid request; if the validity identifier is 0, the request is an invalid request.

[0149] In some embodiments, the first request input port includes a first designated request input port and a first undesignated request input port, wherein the first designated request input port is used to receive a first candidate request issued by the second processor, and the first undesignated request input port is used to receive a first candidate request issued by other request sources outside the second processor (such as the first processor, DMA, or any other possible request source).

[0150] Similarly, the second eviction arbitration unit is used to determine the second invalid request from the non-second designated candidate requests received from the second request input port other than the second designated request input port; the second pruning unit is used to prune the second invalid request.

[0151] In some embodiments, the second request input port includes a second specified request input port and a second unspecified request input port, wherein the second specified request input port is used to receive a second candidate request issued by the first processor, and the second unspecified request input port is used to receive a second candidate request issued by other request sources outside the first processor (such as the second processor, DMA, or any other possible request source).

[0152] See Figure 5 , Figure 5 This is a schematic diagram of a request processing unit provided in an exemplary embodiment of this application, including an evict arbiter unit and a trim unit.

[0153] like Figure 5 As shown, the first read request processing unit 510 includes a first eviction arbitration read unit 511 and a first pruning read unit 512. The first eviction arbitration read unit 511 is used to determine a first invalid read request from the first non-specified candidate read requests; the first pruning read unit 512 is used to prune the first invalid read request.

[0154] The first write request processing unit 520 includes a first eviction arbitration write unit 521 and a first pruning write unit 522. The first eviction arbitration write unit 521 is used to determine a first invalid write request from the first non-designated candidate write requests; the first pruning write unit 522 is used to prune the first invalid write request.

[0155] The second read request processing unit 530 includes a second eviction arbitration read unit 531 and a second pruning read unit 532. The second eviction arbitration read unit 531 is used to determine a second invalid read request from the second non-designated candidate read requests; the second pruning read unit 532 is used to prune the second invalid read request.

[0156] The second write request processing unit 540 includes a second eviction arbitration write unit 541 and a second pruning write unit 542. The second eviction arbitration write unit 541 is used to determine a second invalid write request from the second non-designated candidate write requests; the second pruning write unit 542 is used to prune the second invalid write request.

[0157] Regarding the specific structure of the expulsion arbitration unit, in some embodiments, the expulsion arbitration unit includes an arbiter and a mask unit. For example, a first expulsion arbitration unit includes a first arbiter and a first mask unit, and a second expulsion arbitration unit includes a second arbiter and a second mask unit.

[0158] The following description uses the first deportation arbitration unit in the first read request processing unit as an example. The other deportation arbitration units (including the first deportation arbitration unit in the first write request processing unit, the second deportation arbitration unit in the second read request processing unit, and the second deportation arbitration unit in the second write request processing unit) adopt a similar structure and will not be repeated here.

[0159] See Figure 6 , Figure 6 This is a schematic diagram of the structure of the first read request processing unit provided in an exemplary embodiment of this application.

[0160] like Figure 6 As shown, the first read request processing unit includes a first eviction arbitration unit 610 and a first pruning unit 620. The first eviction arbitration unit 610 includes a first arbitrator 611 and a first mask 612.

[0161] In some embodiments, the first arbitrator is used to arbitrate a first invalid candidate request from the first non-designated candidate requests.

[0162] Regarding the specific method by which the first arbitrator arbitrates the first invalid candidate request from the first non-designated candidate requests, in one possible scenario, the first arbitrator adopts a polling method to arbitrate the first invalid candidate request from the first non-designated candidate requests.

[0163] For illustrative purposes only. Figure 6 The first candidate request includes request vr0 issued by the first processor, request vr1 issued by the first processor, request dvr issued by the DMA, and request mr0 issued by the second processor.

[0164] Among them, requests vr0, vr1, and dvr come from other request sources besides the second processor, so requests vr0, vr1, and dvr are the first non-specified candidate requests; requests mr0 come from the second processor, so requests mr0 are the first specified candidate requests.

[0165] In some embodiments, the first arbitrator 611 uses a round-robin approach to arbitrate a first candidate invalid request from the first non-designated candidate requests (request vr0, request vr1, and request dvr). For example, request vr0 is selected as the first candidate invalid request in the first instance; request vr1 is selected as the first candidate invalid request in the second instance; request dvr is selected as the first candidate invalid request in the third instance; and request vr0 is selected as the first candidate invalid request in the fourth instance, and so on.

[0166] In some embodiments, the first mask is used to determine a first invalid request based on a first candidate invalid request and the validity of each first candidate request. The specific method by which the first mask determines the first invalid request includes the following.

[0167] (1) The first mask is used to determine the first candidate invalid request as the first invalid request and modify the validity of the first candidate invalid request from valid to invalid when the first non-specified candidate request is a valid request and the first specified candidate request is also a valid request.

[0168] like Figure 6 In this context, assuming the first arbitrator 611 arbitrates request vr0 as the first candidate invalid request from request vr0, request vr1, and request dvr. If the first non-designated candidate request (request vr0, request vr1, and request dvr) is a valid request, and the first designated candidate request mr0 is also a valid request, the first masker 612 determines the first candidate invalid request (request vr0) as the first invalid request and modifies the validity of the first candidate invalid request (request vr0) from valid to invalid.

[0169] In some embodiments, the first pruning unit is used to prune the first invalid request and replace it with the first designated candidate request.

[0170] like Figure 6 In the process, the first pruning unit 620 prunes the first invalid request (request vr0) and replaces it with the first designated candidate request mr0.

[0171] (2) The first mask is further configured to determine the invalid request among the first non-specified candidate requests as the first invalid request when there is at least one first non-specified candidate request that is an invalid request and the first specified candidate request is a valid request.

[0172] See Figure 7 , Figure 7 This is a schematic diagram of the structure of the first read request processing unit provided in another exemplary embodiment of this application.

[0173] like Figure 7 As shown, the first eviction arbitration unit 710 includes a first arbitrator 711 and a first mask 712. Request dvr in the first non-designated candidate request is an invalid request, and the first designated candidate request (request mr0) is a valid request. The first mask 712 determines the invalid request (request dvr) in the first non-designated candidate request as the first invalid request.

[0174] In some embodiments, the first pruning unit is used to prune the first invalid request and replace it with the first designated candidate request.

[0175] like Figure 7 In the process, the first pruning unit 720 prunes the first invalid request (request dvr) and replaces it with the first designated candidate request mr0.

[0176] (3) The first mask is also used to determine the first designated candidate request as the first invalid request when each of the first non-designated candidate requests is a valid request and the first designated candidate request is an invalid request.

[0177] See Figure 8 , Figure 8 This is a schematic diagram of the structure of the first read request processing unit provided in another exemplary embodiment of this application.

[0178] like Figure 8 As shown, the first expulsion arbitration unit 810 includes a first arbitrator 811 and a first mask 812. When each of the first non-designated candidate requests (including request vr0, request vr1, and request dvr) is a valid request, and the first designated candidate request (request mr0) is an invalid request, the first mask 812 determines the first designated candidate request (request mr0) as the first invalid request.

[0179] In some embodiments, the first pruning unit is used to prune the first invalid request. For example... Figure 8 In the process, the first pruning unit 820 will request mr0 to be pruned.

[0180] In some embodiments, the second request processing unit includes a second arbitrator and a second mask. The second arbitrator is used to arbitrate a second candidate invalid request from the second unspecified candidate requests; the second mask is used to determine the second invalid request based on the second candidate invalid request and the validity of each second candidate request.

[0181] Optionally, the second arbitrator is used to arbitrate the second invalid candidate request from the second non-designated candidate requests using a polling method.

[0182] Optionally, the second mask is used to determine the second candidate invalid request as the second invalid request and modify the validity of the second candidate invalid request from valid to invalid when the second non-specified candidate request is a valid request and the second specified candidate request is also a valid request.

[0183] Optionally, the second mask is further configured to determine the invalid request among the second non-specified candidate requests as the second invalid request if at least one second non-specified candidate request is an invalid request and the second specified candidate request is a valid request.

[0184] Optionally, the second pruning unit is used to prune the second invalid request and replace it with the second specified candidate request.

[0185] Optionally, the second mask is further configured to determine the second specified candidate request as the second invalid request if each of the second unspecified candidate requests is a valid request and the second specified candidate request is an invalid request.

[0186] Similarly, the second arbitrator and the second mask in the second request processing unit have similar functions to the first arbitrator and the first mask in the first request processing unit, and will not be described in detail here.

[0187] In one possible scenario, the first request processing unit is further configured to receive a first response from the first memory to the first target request, and send the first response to the first request source corresponding to the first target request.

[0188] Optionally, the first request source may include one or more of a first processor, a second processor, a DMA, or any other possible request source.

[0189] As an example only, in the case where the first target request is a request for the second processor to read the first memory, the first request processing unit will return the first read data read from the first memory based on the read address contained in the first target request to the second processor.

[0190] As an example only, in the case where the first target request is a request for the second processor to write to the first memory, the first request processing unit writes the first write data contained in the first target request to the first memory and returns a write success message to the second processor.

[0191] In some embodiments, if the first request source corresponding to the first candidate request does not receive the first response within a predetermined time period, it resends the first candidate request to the first request processing unit.

[0192] For example Figure 6 In the case where the first candidate request vr0 is pruned by the first pruning unit 620, if the first request source (first processor) of the first candidate request vr0 does not receive a first response within a predetermined time period, the first processor retransmits the first candidate request to the first request processing unit. By retransmitting the first candidate request, it can be ensured that the first candidate request pruned by the first pruning unit can receive a response subsequently.

[0193] Similarly, the second request processing unit is also used to receive the second response from the second memory to the second target request, and to send the second response to the second request source corresponding to the second target request.

[0194] Optionally, the second request source may include one or more of the first processor, the second processor, DMA, or any other possible request source.

[0195] As an example only, in the case where the second target request is a request for the first processor to read the second memory, the second request processing unit returns the second read data read from the second memory based on the read address contained in the second target request to the first processor.

[0196] As an example only, in the case where the second target request is a request for the first processor to write to the second memory, the second request processing unit writes the second write data contained in the second target request to the second memory and returns a write success message to the first processor.

[0197] In some embodiments, if the second request source corresponding to the second candidate request does not receive the second response within a predetermined time period, it resends the second candidate request to the second request processing unit.

[0198] See Figure 9 , Figure 9 This is a flowchart of a data read / write method provided in an exemplary embodiment of this application. In some embodiments, the data read / write method is performed by a data read / write device as provided in any of the above embodiments.

[0199] In some embodiments, the data read / write device includes a first memory, a second memory, a first request processing unit connected to the first memory, and a second request processing unit connected to the second memory.

[0200] The first memory is used to store first data related to the operation of the first processor, and the second memory is used to store second data related to the operation of the second processor.

[0201] Optionally, the first and second memories may include one or more static random access memories (SRAMs), or any other possible memory devices, such as dynamic random access memories (DRAMs), non-volatile memories, etc., without any limitation.

[0202] In some embodiments, the first processor and the second processor are processors that perform different operations. For example, the first processor is a vector processor for performing vector operations, and the second processor is a matrix processor for performing matrix operations. However, the first and second processors can also be processors that perform any other possible operations; for example, the first processor could be a tensor processor and the second processor a vector processor; or the first processor could be a matrix processor and the second processor a tensor processor. This specification uses the example of a vector memory as the first processor and a matrix processor as the second processor, but this does not constitute a limitation.

[0203] Optionally, when the first processor is a vector memory, the first memory is used to store first data related to vector operations. The first data can be data to be operated on during the vector operation process, intermediate operation results, and the final operation result, etc. The data type of the first data can be a vector, or it can be a number, matrix, tensor, linked list, set, graph, queue, or other possible types, without limitation.

[0204] Optionally, when the second processor is a matrix memory, the second memory is used to store second data related to matrix operations. The second data can be data to be operated on during the matrix operation process, intermediate operation results, and the final operation result, etc. The data type of the second data can be a matrix, or it can be a numerical value, vector, tensor, linked list, set, graph, queue, or other possible types, without limitation.

[0205] The method includes the following steps.

[0206] Step 901: The first request processing unit determines the first target request from the received first candidate requests and reads and writes the first data indicated by the first target request from the first memory. The first candidate request is used to request to read and write the first memory, and the first request processing unit includes an input port for receiving the first candidate request issued by the second processor. The first request processing unit is connected to the first memory, and the first memory is used to store the first data related to the operation of the first processor.

[0207] In some embodiments, the first request processing unit is configured to determine a first target request from the received first candidate requests and read / write first data indicated by the first target request from the first memory.

[0208] In some embodiments, the first request processing unit includes an input port for receiving a first candidate request and an output port for outputting a first target request.

[0209] The first candidate request is used to request read or write to the first memory.

[0210] Optionally, the first candidate request can be a first candidate read / write request or a first candidate write request. Specifically, the first candidate read request is used to request reading first data from the first memory; the first candidate write request is used to request writing first data to the first memory.

[0211] Optionally, different first candidate requests may come from different request sources.

[0212] In one possible scenario, the first processor may request to read or write the first data in the first memory; that is, the request source of the first candidate request may be the first processor.

[0213] In another possible scenario, Direct Memory Access (DMA) can request to read or write the first data in the first memory; that is, the request source of the first candidate request may be DMA.

[0214] In another possible scenario, the second processor may request to read or write the first data in the first memory; that is, the request source of the first candidate request may also be the second processor.

[0215] In some embodiments, the first request processing unit includes an input port for receiving a first candidate request issued by a second processor.

[0216] like Figure 2 In the first request processing unit 210, there is an input port 211 for receiving a first candidate request issued by the second processor 202.

[0217] In some embodiments, different input ports correspond to different request sources. The first request processing unit 210 receives first candidate requests sent by each request source through each input port.

[0218] In some embodiments, the same request source may correspond to at least two different input ports, without limitation.

[0219] Optionally, the first request processing unit 210 acquires a first candidate request from the input port at preset time intervals. If the request content of the first candidate request is empty, the first request processing unit 210 receives an invalid first candidate request. If the request content of the first candidate request is not empty, the first request processing unit 210 receives a valid first candidate request.

[0220] Upon receiving the first candidate request, the first request processing unit 210 determines the first target request from the first candidate requests.

[0221] Regarding the specific method of determining the first target request, in one possible scenario, the first request processing unit 210 can determine the first target request based on the validity of each first candidate request, for example, by determining the valid first candidate request as the first target request.

[0222] Regarding the specific method for determining the first target request, in another possible scenario, the first request processing unit 210 may adopt a round-robin scheduling method to schedule the first target request from each first candidate request.

[0223] Alternatively, the first request processing unit 210 may also use any other possible method to determine the first target request from the received first candidate requests. For more details on determining the first target request, please refer to the embodiments below, which will not be repeated here.

[0224] In some embodiments, the first request processing unit 210 reads and writes the first data indicated by the first target request from the first memory 230 through the output port of the first target request.

[0225] Step 902: The second request processing unit determines the second target request from the received second candidate requests and reads and writes the second data indicated by the second target request from the second memory. The second candidate request is used to request to read and write the second memory, and the second request processing unit includes an input port for receiving the second candidate request issued by the first processor. The second request processing unit is connected to the second memory, which is used to store the second data related to the operation of the second processor.

[0226] In some embodiments, the second request processing unit is configured to determine the second target request from the received second candidate requests and read / write the second data indicated by the second target request from the second memory.

[0227] In some embodiments, the second request processing unit includes an input port for receiving a second candidate request and an output port for outputting a second target request.

[0228] The second candidate request is used to request reading or writing to the second memory.

[0229] Optionally, the second candidate request can be a second candidate read / write request or a second candidate write request. Specifically, a second candidate read request is used to request reading second data from the second memory; a second candidate write request is used to request writing second data to the second memory.

[0230] Optionally, different second candidate requests may come from different request sources.

[0231] In one possible scenario, the second processor may request to read or write second data in the second memory; that is, the source of the second candidate request may be the second processor.

[0232] In another possible scenario, direct memory access (DMA) can request to read or write second data in a second memory; that is, the source of the second candidate request may be DMA.

[0233] In another possible scenario, the first processor may request to read or write the second data in the second memory; that is, the source of the second candidate request may also be the first processor.

[0234] In some embodiments, the second request processing unit includes an input port for receiving a second candidate request issued by the first processor.

[0235] like Figure 2 In the process, the second request processing unit 220 includes an input port 221 for receiving a second candidate request issued by the first processor 201.

[0236] In some embodiments, different input ports correspond to different request sources. The second request processing unit 220 receives second candidate requests sent by each request source through each input port.

[0237] In some embodiments, the same request source may correspond to at least two different input ports, without limitation.

[0238] Optionally, the second request processing unit 220 acquires a second candidate request from the input port at preset time intervals. If the request content of the second candidate request is empty, the second request processing unit 220 receives an invalid second candidate request. If the request content of the second candidate request is not empty, the second request processing unit 220 receives a valid second candidate request.

[0239] Upon receiving the second candidate request, the second request processing unit 220 determines the second target request from the second candidate requests.

[0240] Regarding the specific method of determining the second target request, in one possible scenario, the second request processing unit 220 can determine the second target request based on the validity of each second candidate request, for example, by determining the valid second candidate request as the second target request.

[0241] Regarding the specific method for determining the second target request, in another possible scenario, the second request processing unit 220 may adopt a round-robin scheduling method to schedule the second target request from each second candidate request.

[0242] Alternatively, the second request processing unit 220 may also determine the second target request from the received second candidate requests in any other possible manner. For more details on determining the second target request, please refer to the embodiments below, which will not be repeated here.

[0243] In some embodiments, the second request processing unit 220 reads and writes the second data indicated by the second target request from the second memory 240 through the output port of the second target request.

[0244] In summary, since the first processing request unit includes an input port for receiving a first candidate request from the second processor, it can receive the first candidate request from the second processor to the first memory. When the first processing request unit determines the first candidate request to be a first target request, it reads and writes the first data indicated by the first target request from the first memory, thus enabling the second processor to access the first memory. Similarly, since the second processing request unit includes an input port for receiving a second candidate request from the first processor, it can receive the second candidate request from the first processor to the second memory. When the second candidate request unit determines the second candidate request to be a second target request, it reads and writes the second data indicated by the second target request from the second memory, thus enabling the first processor to access the second memory. The data read / write device provided in this application eliminates the need for data transfer between the first and second memories via DMA, enabling the first processor to access the second memory and the second processor to access the first memory. This avoids the time and power consumption associated with data transfer, resulting in higher data read / write efficiency and improved processor performance.

[0245] In some embodiments, the data read / write device in this application may be integrated into a processor. This application provides a processor that includes the data read / write device as provided in any of the above embodiments.

[0246] Optionally, the processor can be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), or other processors with data read and write requirements. This application embodiment does not limit this.

[0247] This application also provides a board card, which is provided with a processor as described above.

[0248] This board may include a printed circuit board (PCB) whose supported interface types match the processor, which can be connected to an integrated circuit board. For example, this board can be a single-board computer, a graphics card, a sound card, etc. Alternatively, the PCB may be a motherboard, with the processor directly connected to it. This board can also be a main control board, a line card, a network card, etc.

[0249] This application also provides a computer device, which in some embodiments may be a server.

[0250] See Figure 10 , Figure 10 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application.

[0251] Specifically, the computer device 1000 includes a system bus 1001, a board 1002, and other devices 1004. The board 1002 includes a processor 1003. The processor 1003 can be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU).

[0252] Optionally, other devices 1004 include system memory consisting of random access memory and read-only memory, a basic input / output (I / O) system that facilitates information transfer between various devices within the computer, and a mass storage device for storing the operating system, applications, and other program modules. The basic input / output system includes a display for showing information and input devices such as a mouse and keyboard for user input. Both the display and the input devices are connected to the processing unit via an input / output controller connected to the system bus 1001. The basic input / output system may also include an input / output controller for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller also provides output to a display screen, printer, or other types of output devices.

[0253] The mass storage device is connected to the processing unit via a mass storage controller connected to the system bus 1001. The mass storage device and its associated computer-readable medium provide non-volatile storage for the computer device 1000. That is, the mass storage device may include computer-readable media such as a hard disk or drive.

[0254] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The aforementioned system memories and mass storage devices can be collectively referred to as memory.

[0255] The memory stores one or more programs, which are configured to be executed by one or more processing units. The one or more programs contain instructions for implementing the methods described above, and the processing units execute the one or more programs to implement the methods provided in the various method embodiments described above.

[0256] According to various embodiments of this application, the computer device 1000 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 1000 can be connected to a network via a network interface unit connected to the system bus 1001, or it can use the network interface unit to connect to other types of networks or remote computer systems.

[0257] The memory further includes one or more programs stored in the memory, and the one or more programs include steps performed by a computer device in the methods provided in the embodiments of this application.

[0258] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data read / write device, characterized in that, The device includes a first memory, a second memory, a first request processing unit connected to the first memory, and a second request processing unit connected to the second memory. The first memory is used to store first data related to the operation of the first processor, and the second memory is used to store second data related to the operation of the second processor; The first request processing unit is configured to determine a first target request from the received first candidate requests and read / write the first data indicated by the first target request from the first memory. The first candidate request is used to request to read / write the first memory, and the first request processing unit includes an input port for receiving the first candidate request issued by the second processor. The second request processing unit is configured to determine a second target request from the received second candidate requests, and read / write the second data indicated by the second target request from the second memory. The second candidate request is used to request to read / write the second memory, and the second request processing unit includes an input port for receiving the second candidate request issued by the first processor.

2. The apparatus according to claim 1, characterized in that, The first request processing unit is configured to receive the first candidate request through a first request input port, wherein a first designated request input port in the first request input port is configured to receive a first designated candidate request, and the first designated candidate request is the first candidate request issued by the second processor. The first request processing unit is configured to read and write the first data indicated by the first target request from the first memory through the first request output port. The number of the first request output ports is the same as the number of read and write ports of the first memory, and the number of the first request input ports is greater than the number of the first request output ports. The second request processing unit is configured to receive the second candidate request through the second request input port, wherein the second specified request input port in the second request input port is configured to receive the second specified candidate request, and the second specified candidate request is the second candidate request issued by the first processor; The second request processing unit is configured to read and write the second data indicated by the second target request from the second memory through the second request output port. The number of the second request output ports is the same as the number of read and write ports of the second memory, and the number of the second request input ports is greater than the number of the second request output ports.

3. The apparatus according to claim 2, characterized in that, The first request processing unit includes a first eviction arbitration unit and a first pruning unit, and the second request processing unit includes a second eviction arbitration unit and a second pruning unit; The first expulsion arbitration unit is used to determine a first invalid request from the first non-designated candidate requests received from the first request input port other than the first designated request input port; The first pruning unit is used to prune the first invalid request; The second expulsion arbitration unit is used to determine a second invalid request from non-second designated candidate requests received from the second request input port other than the second designated request input port; The second pruning unit is used to prune the second invalid request.

4. The apparatus according to claim 3, characterized in that, The first deportation arbitration unit includes a first arbitrator and a first mask, and the second deportation arbitration unit includes a second arbitrator and a second mask; The first arbitrator is used to arbitrate a first invalid candidate request from the first non-designated candidate requests; The first mask is used to determine the first invalid request based on the first candidate invalid request and the validity of each of the first candidate requests; The second arbitrator is used to arbitrate a second invalid candidate request from the second unspecified candidate request; The second mask is used to determine the second invalid request based on the second candidate invalid request and the validity of each of the second candidate requests.

5. The apparatus according to claim 4, characterized in that, The first arbitrator is used to arbitrate invalid candidate requests from the first non-designated candidate requests using a polling method; The second arbitrator is used to arbitrate the second invalid candidate request from the second non-designated candidate requests using a polling method.

6. The apparatus according to claim 4, characterized in that, The first mask is used to determine the first invalid candidate request as the first invalid request and modify the validity of the first invalid candidate request from valid to invalid when the first non-specified candidate request is a valid request and the first specified candidate request is also a valid request. The first mask is further configured to determine the invalid request among the first non-specified candidate requests as the first invalid request when at least one of the first non-specified candidate requests is an invalid request and the first specified candidate request is a valid request. The first pruning unit is used to prune the first invalid request and replace it with the first designated candidate request; The second mask is used to determine the second candidate invalid request as the second invalid request and modify the validity of the second candidate invalid request from valid to invalid when both the second non-specified candidate request and the second specified candidate request are valid requests. The second mask is further configured to determine the invalid request among the second non-specified candidate requests as the second invalid request when at least one of the second non-specified candidate requests is an invalid request and the second specified candidate request is a valid request; The second pruning unit is used to prune the second invalid request and replace it with the second designated candidate request.

7. The apparatus according to claim 4, characterized in that, The first mask is further configured to determine the first designated candidate request as the first invalid request when each of the first non-designated candidate requests is a valid request and the first designated candidate request is an invalid request. The second mask is further configured to determine the second specified candidate request as the second invalid request when each of the second non-specified candidate requests is a valid request and the second specified candidate request is an invalid request.

8. The apparatus according to claim 2, characterized in that, The first request processing unit includes a first read request processing unit and a first write request processing unit, and the second request processing unit includes a second read request processing unit and a second write request processing unit; The first read request processing unit is configured to determine a first target read request from a first candidate read request received through a first read request input port, and to read first read data indicated by the first target read request from the first memory through a first read request output port. The number of the first read request output ports is the same as the number of read ports of the first memory, and the number of the first read request input ports is greater than the number of the first read request output ports. The first write request processing unit is configured to determine a first target write request from a first candidate write request received through a first write request input port, and to write the first write data indicated by the first target write request to the first memory through a first write request output port. The number of the first write request output ports is the same as the number of write ports of the first memory, and the number of the first write request input ports is greater than the number of the first write request output ports. The second read request processing unit is configured to determine a second target read request from a second candidate read request received through a second read request input port, and to read second read data indicated by the second target read request from the second memory through a second read request output port. The number of the second read request output ports is the same as the number of read ports of the second memory, and the number of the second read request input ports is greater than the number of the second read request output ports. The second write request processing unit is configured to determine a second target write request from a first candidate write request received through a second write request input port, and to write second write data indicated by the second target write request to the second memory through a second write request output port. The number of the second write request output ports is the same as the number of write ports of the second memory, and the number of the second write request input ports is greater than the number of the second write request output ports.

9. The apparatus according to any one of claims 1 to 8, characterized in that, The device further includes a first splitter and a second splitter, wherein the first splitter is connected to the first request processing unit and the second request processing unit respectively, and the second splitter is connected to the first request processing unit and the second request processing unit respectively. The first splitter is configured to send the first read / write request as the second candidate request to the second request processing unit when the first read / write request issued by the first processor contains a first read / write address that belongs to the second memory. Alternatively, if the first read / write address belongs to the first memory, the first read / write request is sent to the first request processing unit as the first candidate request; The second splitter is configured to send the second read / write request as the first candidate request to the first request processing unit when the second read / write request issued by the second processor contains a second read / write address that belongs to the first memory. Alternatively, if the second read / write address belongs to the second memory, the second read / write request is sent to the second request processing unit as the second candidate request.

10. The apparatus according to any one of claims 1 to 9, characterized in that, The first request processing unit is further configured to receive a first response from the first memory to the first target request, and send the first response to the first request source corresponding to the first target request; The second request processing unit is further configured to receive a second response from the second memory to the second target request, and send the second response to the second request source corresponding to the second target request.

11. The apparatus according to any one of claims 1 to 10, characterized in that, The first memory is a vector memory, the second memory is a matrix memory, the first processor is a vector processor, and the second processor is a matrix processor.

12. A data read / write method, characterized in that, The method includes: The first request processing unit determines a first target request from the received first candidate requests and reads and writes first data indicated by the first target request from the first memory. The first candidate request is used to request to read and write the first memory, and the first request processing unit includes an input port for receiving the first candidate request issued by the second processor. The first request processing unit is connected to the first memory, and the first memory is used to store the first data related to the operation of the first processor. The second request processing unit determines a second target request from the received second candidate requests and reads and writes second data indicated by the second target request from the second memory. The second candidate request is used to request to read and write the second memory, and the second request processing unit includes an input port for receiving the second candidate request issued by the first processor. The second request processing unit is connected to the second memory, which is used to store the second data related to the operation of the second processor.

13. A processor, characterized in that, The processor is provided with a data read / write device as described in any one of claims 1 to 11.

14. A circuit board, characterized in that, The board is equipped with the processor as described in claim 13.

15. A computer device, characterized in that, The computer device is equipped with the board as described in claim 14.

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