Resistive random access memory with gradient-doped resistive switching layer and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor memory devices, and discloses a resistive random access memory (RRAM) with a gradient-doped resistive switching layer and a preparation method thereof. The memory comprises a bottom metal layer, an intermetallic insulating layer, a bottom electrode, a resistive switching layer, an oxygen storage layer, a top electrode and a top metal layer which are stacked in sequence. The resistive switching layer contains a trace amount of a doping element, the concentration of the doping element is linearly or stepwisely distributed along the film thickness direction, and the doping concentration gradually decreases from the upper surface of the resistive switching layer to the bottom electrode. The concentration gradient forms a decreasing channel of oxygen vacancy formation energy in the longitudinal direction of the film, thereby guiding the directional growth and rupture of a conductive filament along a specific path under the drive of an electric field. The application eliminates the randomness of nucleation of the conductive channel, improves the resistance consistency of the device in Set and Reset operations, effectively reduces the operating voltage, improves the array yield and repeatability, and further simplifies the peripheral circuit design and reduces the area overhead of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory device technology, specifically to a resistive switching memory with a gradient-doped resistive switching layer and its fabrication method. Background Technology

[0002] Resistive random access memory (RRAM) has become an important development direction for next-generation non-volatile memory technology due to its advantages such as simple structure, fast read / write speed, and compatibility with traditional CMOS processes. Its core working mechanism relies on the reversible formation and breakage of conductive filaments inside the dielectric film under the action of an external electric field, thereby realizing the switching between high and low resistance states.

[0003] However, in existing resistive switching memory devices, the intrinsic lattice defects within the conventional undoped or uniformly doped metal oxide resistive switching layer exhibit a high degree of spatial randomness. This microscopic physical disorder means that the generation locations of oxygen vacancies and the connection paths of conductive filaments under electric field drive cannot be precisely fixed. The uncontrollable multi-filament competitive growth mechanism in each erase / write cycle directly causes drastic fluctuations in the device's operating voltage and severe dispersion in the resistive switching parameters, making it difficult to achieve commercial-grade yield and operational repeatability for large-scale device arrays. To cope with the huge parameter drift between array cells, memory chips are forced to introduce cumbersome read / write verification algorithms and large redundant error correction modules at the system level, significantly increasing the design complexity of peripheral driving circuits and chip area overhead.

[0004] Furthermore, as memory arrays shrink to higher densities, traditional dry etching processes can cause lattice damage and dangling bonds on the sidewalls of extremely thin resistive switching layers. In the absence of effective boundary isolation structures, these damaged sidewall interfaces become channels for mass exchange. Under high-temperature thermal stress, external moisture accelerates its intrusion into the device along the sidewalls, while internal oxygen vacancies readily diffuse laterally towards the damaged edges. This edge effect generates parallel parasitic leakage paths outside the main conductive channels, leading to the breakdown of the device's insulating state and severely weakening the memory's high-temperature data retention capability and long-term operational reliability. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a resistive switching memory with a gradient-doped resistive switching layer and its fabrication method, which solves the problems of large device operating voltage dispersion, poor resistance state consistency and low array yield caused by the randomness of the growth path of conductive filaments inside the resistive switching layer in existing resistive switching memories.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, this application provides a resistive switching memory with a gradient-doped resistive switching layer, employing the following technical solution: It includes a bottom metal layer, a bottom electrode and an intermetallic insulating layer, a bottom electrode, a resistive switching layer, an oxygen storage layer, a top electrode, and a top metal layer, which are stacked sequentially. Wherein, a through hole is provided through the insulating layer between the bottom electrode and the metal layer to connect the bottom electrode and the metal layer, and the through hole connects the bottom metal layer and the bottom electrode; The top metal layer is connected to the top electrode via a top through-hole; The thickness of the resistive switching layer is 10 to 200 Å. The resistive switching layer contains trace doping elements. The concentration of the trace doping elements exhibits a linear or stepwise concentration gradient distribution along the thickness direction of the resistive switching layer, and the doping concentration of the trace doping elements gradually decreases from the upper surface of the resistive switching layer towards the bottom electrode. The trace doping element is selected from one or more of Al, Si, P, S, Ga, Ge, As, Se, In, Sn, Sb, and Te.

[0008] By adopting the above technical solution, the introduction of trace doping elements with gradually decreasing concentration from the top surface to the bottom within the resistive switching layer alters the internal lattice environment of the dielectric film and establishes a specific concentration gradient with a larger concentration at the top and a smaller concentration at the bottom. Therefore, the technical effects of highly concentrated device operating voltage, directional and controllable growth of conductive filaments, and extended erase / write fatigue life are achieved. The specific mechanism of action is as follows: Step 1: Doping elements replace metal atoms in the resistive switching layer substrate lattice or enter interstitial sites, locally reducing the oxygen vacancy formation energy in the lattice. The highly doped upper surface region has a lower oxygen vacancy formation energy, while the low-doped or undoped lower region maintains an intrinsically high formation energy state.

[0009] Step 2: Under the drive of a positive electric field, a lattice oxygen dissociation reaction occurs. Since the top layer has the lowest formation energy, this region is the first to dissociate, releasing oxygen ions and generating oxygen vacancies. Subsequently, the local electric field strengthens, guiding the generation of oxygen vacancies in the lower layers sequentially along the gradient concentration direction.

[0010] Step 3: The oxygen ions generated by dissociation migrate and accumulate towards the oxygen storage layer. The concentration gradient establishes a specific channel with minimum energy resistance in the longitudinal direction of the resistive switching layer, eliminating random interference from intrinsic lattice defects and suppressing random nucleation and growth competition of side filaments in other regions, thus achieving deterministic connection of a single conductive channel.

[0011] Step 4: During data erasure with a reverse electric field, a defect recombination reaction occurs. Oxygen ions in the oxygen storage layer face an energy barrier distribution that is lower at the top and higher at the bottom, allowing for barrier-free backflow along a preset energy gradient. This distribution effectively prevents long-term accumulation of oxygen ions at the top layer interface and solidification of conductive channels during reverse erasure, maintaining the balance of internal reversible chemical reactions.

[0012] Preferably, it also includes an etch barrier layer, a sidewall protection layer, and an inter-device filling layer disposed on the periphery; the etch barrier layer is disposed on the top electrode; The sidewalls of the bottom electrode, resistive switching layer, oxygen storage layer, top electrode, and etch barrier layer are flush and form the device sidewalls, and the device sidewalls are surrounded by the sidewall protective layer. The gaps around the sidewall protective layer are filled with the inter-device filler layer, and the top through-hole penetrates the inter-device filler layer, the sidewall protective layer, and the etching barrier layer and contacts the top electrode.

[0013] By adopting the above technical solution, a highly conformal sidewall protective layer seamlessly encapsulates the device sidewalls. Since plasma dry etching processes generate dangling bonds and lattice damage on the resistive switching layer sidewalls, the sidewall protective layer physically cuts off the path of lateral diffusion of internal oxygen vacancies along the damaged interface. Simultaneously, it blocks the intrusion of external environmental moisture along the interface, preventing the formation of leakage paths parallel to the main channel on the sidewall surface. This ensures the long-term data retention capability of the resistive switching memory device under high-temperature stress.

[0014] Preferably, the thickness of the connection between the bottom electrode and the metal layer via is 150–2000 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Pd, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON. The thickness of the bottom electrode is 10–1500 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, WN, TiON, TaON, and AlON. The substrate material of the resistive switching layer is one of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO, or a mixture of at least two of these materials. The thickness of the oxygen storage layer is 10 to 1000 Å, and the material is selected from one or more combinations of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, NiOx, TiN, TaN, AlN, TiON, TaON, and AlON. The thickness of the top electrode is 10–5000 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON.

[0015] By adopting the above technical solution, the critical dimensions and material selection boundaries of each thin film functional layer are defined. Under different physical thicknesses and mixed material systems, the gradient doping mechanism can play a role in local energy regulation, supporting normal switching operation in ultra-thin sizes and insulation barrier control in thicker sizes, ensuring the universality and consistency of the electrical characteristics of large-scale array devices.

[0016] Preferably, the thickness of the insulating layer between the bottom electrode and the metal is 150–2000 Å, and it is a composite structure composed of one or more of SiO2, nitrogen-doped silicon carbide, and plasma-enhanced silicon oxide; the bottom region in contact with the bottom metal layer in the composite structure is made of nitrogen-doped silicon carbide, and the top region in contact with the bottom electrode is made of plasma-enhanced silicon oxide.

[0017] By adopting the above technical solution, the nitrogen-doped silicon carbide at the bottom provides high-strength barrier properties to prevent the bottom metal elements from thermally diffusing into the resistive switching region during subsequent high-temperature processes; the plasma-enhanced silicon oxide at the top provides good interface flatness and adhesion, maintaining the structural integrity and electrical insulation stability of the bottom electrode architecture.

[0018] Preferably, the thickness of the etching barrier layer is 100–5000 Å, and the material is composed of one or more of SiON, Si3N4, and plasma-enhanced silicon oxide; The thickness of the sidewall protective layer is 10–500 Å, and the material is selected from one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, Si3N4, and tetraethylsilane-derived silicon oxide; The bottom of the sidewall protective layer extends to cover the exposed surface of the insulating layer between the bottom electrode and the metal; the thickness of the inter-device filling layer is 10 to 10,000 Å, and the material is tetraethylsilane-derived silicon dioxide or organic silica glass; The thickness of the top through-hole is 100–2000 Å, and the material is Cu or W.

[0019] By adopting the above technical solution, the dense structure combination of the sidewall protective layer and the inter-device filling layer constructs a fully enclosed peripheral insulation network for the device. The extension of the sidewall protective layer to the bottom covers and repairs the local interface exposure caused by etching, and blocks the physical leakage path between adjacent device units.

[0020] Secondly, this application provides a method for fabricating a resistive switching memory with a gradient-doped resistive switching layer, employing the following technical solution: The process includes depositing a bottom electrode and an intermetallic insulating layer on a bottom metal layer, photolithographic etching to form holes, depositing conductive material to form vias connecting the bottom electrode and the metal layer, and performing chemical mechanical polishing planarization; then depositing the bottom electrode and a resistive switching layer sequentially on the planarized surface. The resistive switching layer is doped with trace dopant elements using an ion implantation process. By controlling the energy of ion implantation to gradually decrease or decrease in stages during the implantation process, the trace dopant elements can form a linear or stepped concentration gradient distribution from the top surface to the bottom in the thickness direction of the resistive switching layer. The parameters of the ion implantation process are controlled as follows: implantation energy 1 keV to 50 keV, implantation dose 1 × 10⁻⁶. 10 ~1×10 16 ions / cm2, implantation angle relative to wafer normal 0°~30°, implantation temperature 25℃~400℃; Above the resistive switching layer after ion implantation, an oxygen storage layer and a top electrode are sequentially deposited in vapor phase; photolithography and plasma etching are performed, extending to the bottom of the bottom electrode to form an independent device array pattern, followed by filling with insulating dielectric and planarizing by grinding; Etching creates holes that expose the top electrode, and the conductive metal is filled to form a top via and planarized; an upper metal layer is deposited on the planarized surface and etched to form a top metal layer.

[0021] By employing the above technical solution, and by using ion implantation technology with strictly limited parameter boundaries to adjust the doping depth, the distribution of trace dopant elements in the longitudinal direction of the thin film can be precisely controlled without compromising the macroscopic insulating properties of the resistive switching layer. Setting the upper limit of the implantation energy to 50 keV eliminates the problem of cascade collision damage caused by high-energy ions penetrating the thin film and within the bottom electrode and insulating layer, thus avoiding physical short-circuit failure at the bottom interface. This fabrication method transforms the microscopic random lattice defect generation process into a macroscopic process with pre-set parameters, improving film quality and initial device yield.

[0022] Preferably, in order to form the stepped concentration gradient distribution within the resistive switching layer, the process of doping the resistive switching layer with trace dopant elements using ion implantation is performed in multiple stages. During the execution of the multiple stages, the injection energy of the later stage is lower than that of the earlier stage, and the injection dose of the later stage is greater than that of the earlier stage, so that the doping concentration of the trace dopant element gradually decreases from the upper surface of the resistive switching layer to the bottom.

[0023] By employing the above technical solution, the combined effect of the lower implantation energy and the larger implantation dose in the latter stage ensures that most doped elements remain in the shallow surface of the resistive switching layer, with only a small portion penetrating into the deeper layers during the initial high-energy stage. Multi-stage synergistic parameter control forces the synthesis of a reverse implantation depth curve that is larger at the top and smaller at the bottom at the physical process level, guaranteeing the stable establishment of the oxygen vacancy-directed induction mechanism.

[0024] Preferably, in the process of depositing the bottom electrode and the intermetallic insulating layer, a plasma-enhanced chemical vapor deposition process is used to prepare the composite structure. Specifically, nitrogen-doped silicon carbide material is first deposited on the bottom metal layer as the bottom region of the bottom electrode and the intermetallic insulating layer; then, the deposition process gas is switched to continuously deposit plasma-enhanced silicon oxide material as the top region of the bottom electrode and the intermetallic insulating layer.

[0025] By adopting the above technical solution, the preparation of a double-layer composite structure is completed in the in-situ processing chamber by continuously switching process gases, which prevents the exposure, oxidation and impurity contamination of the intermediate interface and enhances the interlayer bonding force between heterogeneous materials.

[0026] Preferably, in the process of depositing the resistive switching layer, atomic layer deposition or physical vapor deposition is used for deposition; and when the substrate material of the resistive switching layer is a mixed oxide composed of multiple metal oxides, the mixed oxide is formed by co-deposition or alternating pulse deposition of the material sources corresponding to the multiple metal oxides.

[0027] By adopting the above technical solution, relying on atomic layer deposition and alternating pulse control, atomic-level precision control of the thickness of ultra-thin dielectric films is achieved, ensuring the uniform distribution of the spatial stoichiometry of multi-component mixed metal oxides, and providing a uniform intrinsic material substrate for the subsequent construction of a uniform doping environment.

[0028] Preferably, after the sequential vapor deposition of the oxygen storage layer and the top electrode, a process for depositing an etch barrier layer is further included. In the process of forming an independent device array pattern and filling it with insulating dielectric, the specific process is to perform plasma dry etching to form device sidewalls with flush sidewalls; and to use conformal deposition process to form a sidewall protective layer, so that the sidewall protective layer wraps the device sidewalls without gaps and extends to cover the exposed surface of the bottom electrode and the metal-to-metal insulating layer exposed by etching. The inter-device filler layer is deposited to fill gaps and planarize the surface; the etching forms a hole that exposes the top electrode, specifically penetrating the inter-device filler layer, the sidewall protective layer, and the etching barrier layer.

[0029] By employing the above technical solution, dry etching penetrates the entire core working thin film layer in one pass to form a vertically flush profile cross-section, ensuring the fidelity of the device array pattern under a relatively small linewidth. Subsequent conformal deposition ensures that the sidewall protective layer adheres tightly along the height direction and self-seales the micro-steps on the underlying insulating surface caused by the over-etching process, achieving complete physical isolation between the resistive switching layer and the external environment.

[0030] This application provides a resistive switching memory with a gradient-doped resistive switching layer and its fabrication method. It has the following advantages: 1. This application introduces a gradient distribution of trace doping elements with a concentration that gradually decreases from the top surface to the bottom within the resistive switching layer. This creates a directional dissociation channel for oxygen vacancies with minimal energy resistance in the longitudinal direction of the thin film, enabling the conductive filaments to grow and break controllably along a fixed path under the drive of an electric field. This improves the consistency of the device's resistance value during resistive switching operation and effectively reduces the operating voltage.

[0031] 2. This application employs an ion implantation process with limited energy upper limit and phased step-by-step control during the preparation process. This not only accurately establishes the concentration gradient at a specific depth inside the film, but also avoids physical collision damage to the bottom insulating network caused by high-energy ions penetrating the film. This improves the basic physical manufacturing yield and electrical cycle repeatability of the resistive switching memory array.

[0032] 3. The gradient doping structure and process of this application endow the core device with a highly concentrated operating voltage window and low array parameter dispersion, so that the macro memory array does not need to set up a wide range of driving modules or redundant error correction compensation mechanisms to overcome random fluctuations during operation control. Therefore, it can simplify the design architecture of the chip peripheral circuit and effectively reduce the overall area overhead. Attached Figure Description

[0033] Figure 1 A schematic diagram of the hierarchy of the resistive random access memory provided in an embodiment of this application; Figure 2 A flowchart illustrating the preparation process provided in this application embodiment; Figure 3 A scatter plot of the basic electrical parameters of the resistive switching memory cell provided in the embodiments of this application; Figure 4 The diagram shows the yield and turn-on voltage distribution characteristics of the resistive random access memory array provided in the embodiments of this application. Figure 5 The graph shows the reliability evolution characteristics of the resistive random access memory provided in the embodiments of this application.

[0034] The components are: 1. Bottom metal layer; 2. Insulating layer between bottom electrode and metal; 3. Via connecting bottom electrode and metal layer; 4. Bottom electrode; 5. Resistive switching layer; 6. Oxygen storage layer; 7. Top electrode; 8. Etching barrier layer; 9. Sidewall protection layer; 10. Inter-device filling layer; 11. Top via; 12. Top metal layer. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] See attached document Figure 1 The resistive switching memory of this application presents a multi-layer stacked system. The main body of the device is built on a bottom metal layer 1, and the bottom electrode and the inter-metal insulating layer 2 cover the bottom metal layer 1, providing physical isolation for the device. Specifically, the bottom electrode and the inter-metal insulating layer 2 are composite structures composed of nitrogen-doped silicon carbide and plasma-enhanced silicon oxide. The nitrogen-doped silicon carbide at the bottom has excellent resistance to metal diffusion, blocking the upward migration of atoms in the bottom metal layer 1; the plasma-enhanced silicon oxide at the top provides a lower dielectric constant to reduce parasitic capacitance. A through-hole 3 is provided through this composite structure to connect the bottom electrode and the metal layer. The through-hole is filled with conductive metal to establish a transmission path for signals at the bottom layer.

[0037] A bottom electrode 4, a resistive switching layer 5, an oxygen storage layer 6, and a top electrode 7 are sequentially stacked above the surface of the bottom electrode and the metal-insulating layer 2. The bottom electrode 4 and the top electrode 7 serve as the terminals for applying electrical signals, and their materials are selected from Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, and their corresponding conductive metal nitrides or metal oxynitrides. All of the selected materials possess stable bulk resistivity and work function matching that of the resistive switching material. In the device architecture of this application, these metals and alloy compounds are equivalent substitutes with the same electrical physical properties, capable of establishing stable Schottky barriers or ohmic contacts with the resistive switching layer interface during use, and effectively resisting electromigration effects under high-density current.

[0038] The resistive switching layer 5 is the core region for the device to realize the resistance state transition. Its substrate material is limited to one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO, or a mixture thereof.

[0039] These oxide materials all belong to transition metal oxides or main group oxide systems with high dielectric constants. Their common physical characteristic is that their internal resistive switching mechanism depends on the generation, migration and recombination of oxygen vacancies under the action of an external electric field.

[0040] When the substrate material is a mixture of at least two materials, the coexistence of different metal atoms modulates the coordination environment within the crystal lattice, thereby altering the overall bandgap of the thin film. The selection of this material group is based on the physical consistency of the valence change storage mechanism, and technicians can obtain basic resistive switching properties using any one of the components.

[0041] The resistive switching layer 5 contains trace doping elements selected from Al, Si, P, S, Ga, Ge, As, Se, In, Sn, Sb, and Te. After these main group or semiconductor impurity atoms enter the lattice of the metal oxide substrate, they alter the bonding state of oxygen atoms in the local region, effectively reducing the formation energy of oxygen vacancies. In this application, the concentration of the trace doping element exhibits a linear or stepwise concentration gradient distribution along the thickness direction of the resistive switching layer 5, gradually decreasing from the upper surface towards the bottom electrode 4.

[0042] For a resistive switching memory with this gradient doping structure, the implementation process of its internal resistive switching function can be described in the following stages: S101, apply a positive initialization voltage between the top electrode 7 and the bottom electrode 4; S102, oxygen ions in resistive switching layer 5 migrate to oxygen storage layer 6 under the drive of electric field. S103, because the concentration of trace doped elements inside the resistive switching layer 5 decreases from top to bottom, the formation energy of oxygen vacancies inside also shows a regular decrease, guiding the conductive filaments to nucleate and grow directionally from the high-doped region to the low-doped region. S104, a conductive filament connects the upper and lower electrodes, enabling the device to transition from a high-resistivity state to a low-resistivity state. This structural design eliminates random branching during filament growth and narrows the distribution range of the device's turn-on voltage.

[0043] The oxygen storage layer 6, located above the resistive switching layer 5, is made of an easily oxidizable metal or suboxide with strong oxygen absorption capacity. Its function is to receive and store oxygen ions that migrate out during stage S102, and release oxygen ions under reverse bias voltage to recombine with conductive filaments, thereby ensuring the durability of the device during erase and write cycles.

[0044] The resistive switching memory is surrounded by an etch barrier layer 8, a sidewall protection layer 9, and an inter-device filler layer 10. The etch barrier layer 8 covers the top electrode, and the sidewall protection layer 9 seamlessly wraps the device sidewalls formed by the bottom electrode 4 to the top electrode 7, extending to the surface of the bottom insulating layer. The sidewall protection layer 9 is made of a dense oxide or nitride material, which cuts off the path for the lateral diffusion of ambient moisture and internal oxygen ions. The inter-device filler layer 10 is made of tetraethylsilane-derived silicon dioxide or organic silica glass and fills the spaces between adjacent devices. This material, with its good step coverage and insulating properties, achieves physical isolation between independent device arrays. A top via 11 penetrates the above insulating wrapping structure, leading the electrode to the top metal layer 12.

[0045] For the photolithography, plasma dry etching, and metal deposition steps involved in the fabrication of the device in this application, those skilled in the art can select conventional process formulations and equipment parameters based on the etching selectivity of the selected material and the thin film stress requirements.

[0046] The resistive switching memory of this application has made multiple parallel selections of materials for each functional layer. These candidate materials are mostly located in the same group in the periodic table, or belong to the same type of compound with highly similar physicochemical properties in materials science.

[0047] For example, the selected silicon, germanium, and tin, as well as phosphorus, arsenic, and antimony, belong to the same group when introducing trace dopants into the resistive switching layer. These elements in the same group have similar atomic radii and outer electron configurations. When they enter the transition metal oxide lattice and form substitutional or interstitial defects, they can all produce similar modulation effects on the formation of local oxygen vacancies, thereby guiding the directional growth of conductive filaments.

[0048] Similarly, for the insulating medium and sidewall protection structure that constitute the periphery of the device, the listed silicon-containing dielectric materials or metal nitrides all provide a high-impedance physical isolation interface through a similar covalent bond network structure, blocking the lateral diffusion of water vapor and ions.

[0049] Based on the inherent commonalities in the aforementioned physicochemical properties, these elements or materials of the same group play the same technical function in the device architecture and operating mechanism defined in this application. Those skilled in the art can be fully certain that the aforementioned parallel materials constitute an equivalent substitution relationship, and that consistent device resistive switching performance and stability can be obtained by implementing substitutions in actual processes.

[0050] Given the equivalent mechanism and wide coverage of the above material systems, in order to further demonstrate the construction process of these material structures in micro-processes and to verify the control methods of parameters such as thickness and mixing ratio, the following are 1-3 examples of the preparation of related special films.

[0051] Preparation Example 1: This fabrication example provides a method for fabricating a composite structure of a bottom electrode and an intermetallic insulating layer, including the following steps: S201, the wafer that has undergone surface planarization and exposed the through-holes of the underlying metal layer is transferred to the reaction chamber of the plasma-enhanced chemical vapor deposition equipment, and the base temperature of the reaction chamber is set between 300°C and 400°C to maintain the base vacuum of the chamber.

[0052] In step S202, silicon source gas, carbon source gas, and nitrogen-containing reactive gas are simultaneously introduced into the reaction chamber. The radio frequency power supply is then activated to excite the plasma, causing a chemical reaction of the reactive gases on the wafer surface. A nitrogen-doped silicon carbide thin film with a thickness set within a specific range is deposited, serving as the bottom region of the composite structure.

[0053] S203: Maintain the wafer in situ within the reaction chamber, cutting off the flow of carbon source gas and nitrogen-containing reaction gas. Introduce oxygen or nitrous oxide into the reaction chamber as the oxygen source gas, working in conjunction with the silicon source gas to maintain radio frequency plasma discharge. Continuously deposit a plasma-enhanced silicon oxide film on the already formed nitrogen-doped silicon carbide surface as the top region of the composite structure.

[0054] S204, monitor the deposition time to control the thickness of the top region. After the total thickness reaches the requirement of 150-2000 Å, turn off the RF power supply and the reaction gas to complete the preparation of the composite structure.

[0055] For the loading and transport of wafers and the cleaning of the reaction chamber during the deposition process, those skilled in the art can use conventional semiconductor processing principles.

[0056] Preparation Example 2: This preparation example provides a method for preparing a resistive switching layer mixed oxide substrate composed of two metal oxides. Taking the formation of an HfAlO mixed thin film as an example, the method includes the following steps: S301, the wafer with the bottom electrode is transferred to the reaction chamber of the atomic layer deposition equipment, the reaction temperature is set to 250°C, and high-purity nitrogen is introduced as a carrier gas and purge gas to establish a stable reaction environment.

[0057] S302, a hafnium-containing precursor is pulsed into the reaction chamber to saturate its chemical adsorption on the wafer surface, and nitrogen gas is introduced to purge the excess precursor. Water vapor or ozone is introduced as an oxidant to react chemically with the hafnium precursor adsorbed on the surface, forming a monolayer of hafnium oxide. Nitrogen gas is then introduced to purge the reaction byproducts.

[0058] S303, an aluminum-containing precursor is pulsed into the reaction chamber to saturate its adsorption on the surface, and then nitrogen gas is introduced for purging; an oxidant is introduced to react with the aluminum precursor to form a monolayer of aluminum oxide, and then nitrogen gas is introduced for purging.

[0059] S304: Based on the required ratio of hafnium oxide to aluminum oxide in the target mixture, set the ratio of alternating runs of the hafnium oxide sub-cycle (S302) and the aluminum oxide sub-cycle (S303) in the overall deposition process. Repeat this alternating process until a HfAlO mixed oxide substrate with a total thickness reaching the set value is formed on the bottom electrode surface.

[0060] Preparation Example 3: This fabrication example provides a conformal fabrication method for a device sidewall protective layer, including the following steps: S401, Prepare a wafer that has been completed by plasma dry etching of the main resistive switching stack structure. The surface of the wafer shows an array of individual device pillars, exposing vertical or inclined device sidewalls from the top electrode to the bottom electrode.

[0061] S402 employs atomic layer deposition (ALD) to introduce metal precursor molecules of a selected material into the reaction environment. Utilizing a self-limiting surface chemical reaction mechanism, the precursor molecules form a uniformly thick monomolecular adsorption layer on the exposed top plane of the device pillar, the device sidewalls, and the exposed surface of the bottom insulating layer.

[0062] S403, introduces co-reactants into the reaction environment, causing them to chemically bond with the aforementioned monomolecular adsorption layer, generating a solid dielectric material molecular layer.

[0063] S404 involves repeating the adsorption and reaction process cycle. Based on the step-covering characteristics of the self-limiting reaction, the generated insulating film seamlessly conforms to the microscopic undulations of the device sidewalls and grows at a uniform thickness until a sidewall protective layer with a thickness between 10 and 500 Å is formed. This thin film structure achieves complete physical encapsulation of the exposed areas on the device sidewalls and bottom.

[0064] See attached document Figure 2 Having clarified the preparation mechanism of the basic film layer and the special hybrid material, in order to fully verify the applicability of this application under different thicknesses, ion implantation parameters and types of doping elements, the following provides specific device examples 1-3 in conjunction with the complete device assembly process.

[0065] Example 1: This embodiment provides a method for fabricating a resistive switching memory with a stepped gradient doped resistive switching layer, including the following steps: S101, on the bottom metal layer 1 with tungsten connecting vias, a bottom electrode and intermetallic insulating layer 2 with a total thickness of 1000 Å is deposited according to the method of Preparation Example 1 described above. The insulating layer is subjected to photolithography and plasma etching to form holes, and titanium nitride conductive material is filled to form vias 3 connecting the bottom electrode and the metal layer. The surface is planarized by chemical mechanical polishing.

[0066] S102, a TiN thin film with a thickness of 500 Å is deposited on the planarized surface as the bottom electrode 4 using a physical vapor deposition process.

[0067] S103, using atomic layer deposition, a 100 Å thick HfO2 thin film is deposited on the bottom electrode 4 as a resistive switching layer 5.

[0068] S104, the resistive switching layer 5 is doped using an ion implantation process, with Al as the implanting element. To form a stepped concentration gradient distribution that gradually decreases from the top surface to the bottom, the implantation process is performed in three stages, maintaining the wafer implantation temperature at 25°C and setting the implantation angle to 7° relative to the wafer normal to avoid ion channel effects.

[0069] The specific parameters are set as follows: In the first stage, an energy of 30 keV was injected, with a dose of 1 × 10⁻⁶. 12 ions / cm 2 ; In the second stage, an energy of 15 keV was injected, with a dose of 5 × 10⁻⁶. 13 ions / cm 2 ; In the third stage, an energy of 5keV was injected, with a dose of 2×10⁻⁶. 14 ions / cm 2 By controlling the energy reduction and dosage increase in the later stage, a higher concentration of Al ions is retained in the shallow layer of resistive switching layer 5, forming a stepped doping distribution with higher concentrations at the top and lower concentrations at the bottom.

[0070] S105, on the surface of the resistive switching layer 5 after ion implantation, a TiOx film with a thickness of 200 Å is sequentially vapor-deposited as an oxygen storage layer 6, and a TiN film with a thickness of 1000 Å is deposited as a top electrode 7, followed by the deposition of a Si3N4 film with a thickness of 500 Å as an etching barrier layer 8.

[0071] S106, photolithography and plasma dry etching are performed. The etching depth extends downwards to the bottom of the bottom electrode 4, forming an independent array of columnar patterns with flush sidewalls.

[0072] S107, according to the method of the aforementioned preparation example 3, an atomic layer deposition process is used to form a SiO2 sidewall protective layer 9 with a thickness of 50 Å, which seamlessly wraps the device sidewall and extends to cover the exposed surface of the underlying insulation.

[0073] S108 uses a chemical vapor deposition process to deposit a 5000 Å thick tetraethylsilane-derived silicon oxide as the inter-device filling layer 10, fills the interlayer gaps, and performs planarization using chemical mechanical polishing.

[0074] S109, photolithography is used to form a hole penetrating the above-mentioned insulating layer, exposing the top electrode 7. Tungsten is filled into the hole and planarized to form a top via 11 with a thickness of 500 Å. Finally, an upper metal layer is deposited and etched to form a top metal layer 12.

[0075] Example 2: This embodiment provides a method for fabricating a resistive switching memory with a linear gradient doped resistive switching layer, including the following steps: S201, a bottom electrode and an intermetallic insulating layer 2 with a thickness of 150 Å are deposited on the bottom metal layer 1. After forming a hole, Pt is filled to form a through hole 3 with a thickness of 150 Å connecting the bottom electrode and the metal layer, and then planarization is performed.

[0076] S202, a 10 Å thick Pt film is sequentially deposited on the planarized surface as the bottom electrode 4 and a 10 Å thick Ta2O5 film is deposited as the resistive switching layer 5.

[0077] S203, phosphorus (P) was implanted into resistive switching layer 5 using ion implantation. Due to the extremely thin film, to create a continuous linear concentration gradient distribution, the energy of the implantation device was designed to decrease linearly over time. The initial implantation energy was controlled to start at 1 keV and continuously decrease to lower levels, while the implantation current was gradually increased to achieve a total implanted dose of 1 × 10⁻⁶. 10 ions / cm 2 The injection angle is set to 0°, and the injection temperature is maintained at 25°C.

[0078] S204, a 10 Å thick TaOx film is deposited as an oxygen storage layer 6, and a 10 Å thick Ru film is deposited as a top electrode 7, and covered with a 100 Å thick SiON etching barrier layer 8.

[0079] S205, after performing patterned etching to form the array, a conformal deposition process is used to generate an HfO2 sidewall protective layer 9 with a thickness set at 10 Å. Subsequently, organic silica glass is spin-coated as an inter-device filler layer 10, which is then cured and planarized to maintain a thickness of 10 Å.

[0080] S206, etching to form a hole exposing the top electrode 7, filling with Cu to form a top via 11 with a thickness of 100 Å, and depositing and shaping the top metal layer 12.

[0081] Example 3: This embodiment provides a method for fabricating a large-size resistive switching memory with a hybrid oxide substrate, including the following steps: S301, deposit a bottom electrode and an intermetallic insulating layer 2 with a thickness of 2000 Å on the bottom metal layer 1, form a via and fill it with W to form a via 3 with a thickness of 2000 Å connecting the bottom electrode and the metal layer and planarize it.

[0082] S302, a W thin film with a thickness reaching the upper limit of 1500 Å is deposited sequentially as the bottom electrode 4. Following the method of preparation example 2, an HfAlO thin film with a thickness of 200 Å is deposited as the resistive switching layer 5 using an alternating atomic layer deposition process.

[0083] S303, high-temperature ion implantation of Si was performed on the hybrid substrate resistive switching layer 5. The wafer heating stage temperature was set to 400℃ to promote lattice repair. To establish a deep, large thickness gradient, a five-stage stepped implantation process was performed. The first stage initially used a maximum energy of 50keV and a relatively small dose to push ions into the bottom layer; The energy was then progressively reduced to 10 keV while the dose was increased simultaneously. This multi-stage accumulation resulted in a final total injected dose reaching the upper limit of 1×10⁻⁶. 16 ions / cm 2 The injection angle is 30° to control the longitudinal penetration depth.

[0084] S304, HfOx with a thickness of 1000 Å is deposited sequentially as an oxygen storage layer 6, W with a thickness of 5000 Å as a top electrode 7, and plasma-enhanced silicon oxide with a thickness of 5000 Å as an etch barrier layer 8.

[0085] S305 uses a dry etching process to divide the device array and a 500 Å thick Al2O3 sidewall protective layer 9 is generated using a conformal process. A tetraethylsilane-derived silicon oxide layer with a thickness of up to 10,000 Å is deposited as an inter-device filling layer 10 and planarized.

[0086] S306, etch extremely deep holes to expose the top electrode 7, and fill with conductive metal to complete the fabrication of a top through-hole 11 with a thickness of 2000 Å and a top metal layer 12.

[0087] Comparative Examples 1-5: Comparative Example 1: Compared with Example 1, the difference is that the process step of micro-doping element ion implantation in resistive switching layer 5 is omitted, and the interior of resistive switching layer 5 is in an undoped state, while the rest are the same.

[0088] Comparative Example 2: Compared with Example 1, the difference lies in the change of the ion implantation process. A single implantation operation was performed using a single set of medium implantation energy of 15 keV and total dose, resulting in a basically uniform concentration distribution of implanted Al elements along the thickness direction of the resistive switching layer 5, without establishing a concentration gradient; all other aspects remained the same.

[0089] Comparative Example 3: Compared to Example 1, the difference lies in the reverse setting of the progressive logic of ion implantation parameters. During the multi-stage execution, the implantation energy of the later stage is set to be higher than that of the previous stage, and the implantation dose of the later stage is lower than that of the previous stage. This implantation logic results in a concentration superposition effect of Al elements increasing from shallow to deep within the resistive switching layer 5, ultimately establishing a reverse concentration gradient distribution that gradually increases from the upper surface to the bottom electrode. All other aspects remain the same.

[0090] Comparative Example 4: Compared to Example 1, the difference is that the starting energy of the first stage of the ion implantation process was increased to 80 keV. This energy value exceeds the set parameter boundary, triggering deep penetration of ions; all other aspects are the same.

[0091] Comparative Example 5: Compared with Example 1, the difference is that the process step of atomic layer deposition to form the sidewall protective layer 9 is omitted. After completing the plasma dry etching of the independent array pattern, the inter-device filling layer 10 is directly deposited, so that the inter-device filling layer 10 directly wraps the exposed resistive switching layer and electrode sidewalls, and the rest is the same.

[0092] Test Example 1-3: Test Example 1: 1. Place the wafer on the probe stage of the semiconductor parameter analyzer and maintain the test environment temperature at room temperature (25℃) and relative humidity below 40%.

[0093] 2. Place the test probes on the test pads of the top and bottom metal layers of the device to establish an electrical connection. Set the bottom metal layer to ground and apply the voltage signal from the top metal layer.

[0094] 3. During the initialization phase, apply a forward DC voltage scan to the device starting from 0V. Set the scan step to 0.05V and simultaneously set the compliance current in the instrument to 100μA to prevent excessive Joule heat from burning out the device when the conductive filament passes through.

[0095] 4. Record the current-voltage response curve. When the current through the device jumps and reaches the compliant current threshold, stop the voltage scan and record the applied voltage at this time as the device's initial voltage (FormingVoltage).

[0096] 5. During the routine switching test phase, apply positive and negative DC voltage scans sequentially to the initialized device. First, apply a positive scan voltage until the device transitions from a high-resistance state to a low-resistance state, and record the voltage at the current jump point as the turn-on voltage. ); then a negative scan voltage is applied until the device recovers from a low-resistance state to a high-resistance state, and the absolute value of the point where the current drops sharply is recorded as the turn-off voltage ( ). ).

[0097] 6. For the wafers of Examples 1 to 3, randomly select 5 independent resistive switching memory cells and repeat the tests in steps 2 to 5 above, extract the specific voltage parameters and record them.

[0098] Table 1. Test data of basic electrical parameters of resistive switching memory cells in Examples 1 to 3

[0099] in conclusion: Based on the recorded data in Table 1 and Figure 2 The scatter plot of electrical parameters shown in Examples 1 to 3 indicates that the device units prepared in these examples all exhibited stable resistance transition characteristics during DC scan testing.

[0100] observe Figure 3 The square data points in subfigure (a), used in Example 1 as a reference device with medium thickness and implantation parameters, show initialization voltages concentrated in the range of 1.8V to 1.9V. This value is lower than the conventional forming voltage threshold for undoped hafnium oxide films of the same thickness.

[0101] Figure 3 Sub-figures (b) and (c) further show that the turn-on voltage stabilizes around 0.8V, and the turn-off voltage is around -1.1V. The test results indicate that the stepped aluminum ion concentration distribution within the resistive switching layer alters the internal lattice environment of the dielectric film. Due to the lower oxygen vacancy formation energy in the shallow, highly doped regions, oxygen ions are released first under the influence of the electric field, subsequently guiding the generation of oxygen vacancies in the lower, less doped regions. This concentration gradient establishes a directional dissociation path, reducing the local electric field strength required for initial device conduction.

[0102] Example 2 uses a resistive switching layer thickness of 10 Å and a linear concentration gradient parameter. For example... Figure 3 As shown by the circular data points in subplot (a), the overall voltage distribution is at its lowest level, with its initial voltage dropping to around 1.1V. Figure 3 Subgraphs (b) and (c) show that the absolute values ​​of the turn-on and turn-off voltages remained around 0.5V and 0.7V, respectively. At the extreme physical thickness, no voltage drop to zero or drastic fluctuations were observed at the data points of each test unit, indicating no physical breakdown or short-circuit failure of the device, and a stable positive and negative operating window was maintained. This data verifies that the micro-concentration gradient constructed using a low-energy linear decay injection process can limit the lateral expansion behavior of conductive filaments in an ultrathin dielectric layer, maintain a fixed longitudinal growth path, and meet the switching operation requirements of thinner devices.

[0103] Example 3 uses high-temperature, high-energy, multi-stage implantation parameters for a 200 Å thick mixed oxide substrate. Figure 3 The triangular data points in subplot (a) indicate that, due to the physical thickness, this group of devices has the highest absolute value of initial voltage, but the upper limit is still limited to 3.0V.

[0104] Figure 3 In subplots (b) and (c), the turn-on and turn-off voltages fluctuate between 1.5V and -1.8V, respectively. Combined with... Figure 2 The lateral distribution trend of the three sub-plots shows that, in Example 3, even at higher operating voltages, the data points of the five random test units still maintain a parallel narrow band distribution, with low dispersion between devices and no severe data divergence as film thickness increases. The results demonstrate that the deep gradient structure established by multi-stage implantation plays a local energy regulation role within the thick film, eliminating the influence of random intrinsic defects within the material on the nucleation sites of conductive filaments and ensuring the consistency of electrical parameters among units in the batch of devices.

[0105] Test Example 2: 1. A wafer-level automated probe station was used to test each group of prepared wafers. The test environment was set to normal temperature and humidity. The probe station was equipped with a shockproof table and an electromagnetically shielded anechoic chamber.

[0106] 2. Randomly select an array region containing 100 consecutive resistive switching memory cells from the wafers of Example 1, Comparative Example 1, Comparative Example 2 and Comparative Example 4 as the test sample set.

[0107] 3. Control the test probes to sequentially contact the top and bottom electrodes of each cell in the sample set. First, perform an initial leakage current test by applying a 0.1V DC read voltage to the device and recording the steady-state current value. Set the judgment criteria: if the read current at 0.1V is greater than 10μA, the device is judged to have a physical short circuit failure; if the read current is less than 10μA, it is judged to be in a valid high-resistance insulation state. Record the number of initial short-circuited cells in each group and calculate the basic array yield.

[0108] 4. Perform a DC voltage scan test on the high-resistivity device that is determined to be valid, including Forming and Setting operations. The test conditions are the same as those in steps 3 to 5 of Test Example 1.

[0109] 5. Extract the turn-on voltage that causes the device to transition from a high-resistivity state to a low-resistivity state during each forward scan. (Value).

[0110] 6. Summarize the test data, calculate the mean and standard deviation of the effective turn-on voltage in each sample set, and calculate the coefficient of variation (CV = standard deviation / mean) to evaluate the parameter dispersion of the array device.

[0111] Table 2. Array yield and turn-on voltage of Example 1 and each comparative example ( Sampling test data

[0112] in conclusion: Based on the statistical data in Table 2 and Figure 3 The distribution characteristics shown in the diagram directly affect the yield and electrical parameter consistency of the device array, as well as the doping distribution state and ion implantation energy parameters.

[0113] like Figure 4 As shown in subfigure (a), Comparative Example 4, which uses high-energy ion implantation at 80 keV (exceeding the specified range), experienced a base array yield reduction to 32.0%. High-energy implantation triggered an ion penetration effect, causing aluminum ions to penetrate the resistive switching layer and generate collision damage within the bottom electrode and insulating layer. This disrupted the physical insulation network at the bottom, resulting in a large number of devices being in an initial short-circuit state. Figure 4 In subfigure (b), the cumulative probability curve of the turn-on voltage of the effective cell in Comparative Example 4 (dashed line with cross mark) shows an irregular scattering, with a coefficient of variation of 30.87%. The test results indicate that excessive injected energy will damage the structural integrity of the bottom interface, causing the remaining device to lose its stable resistive switching capability.

[0114] Comparative Example 1 contains undoped pure hafnium oxide. Figure 4 Subgraph (a) shows a base yield of 96.0%. However... Figure 4 In subfigure (b), the cumulative probability curve of the turn-on voltage (with the dashed circle) for this group of devices has the largest span and the gentlest slope. The turn-on voltage of specific units is widely distributed in the range of 0.8V to 2.0V, with an overall coefficient of variation of 22.61%. The formation of oxygen vacancies inside the undoped thin film depends on intrinsic lattice defects. Due to the randomness of the spatial distribution of intrinsic defects, the nucleation and growth paths of conductive filaments are not fixed, causing fluctuations in the operating voltage threshold.

[0115] Comparative Example 2, employing a uniform doping process, achieved a basic yield of 95.0%. For example... Figure 4 As shown in the cumulative probability curve of the turn-on voltage in sub-figure (b) (with a triangle and dashed line), its overall distribution shifts towards the lower voltage region compared to Comparative Example 1, with the overall mean decreasing to 0.95V. However, the curve still exhibits a significant sloping range, with a coefficient of variation of 17.68%. The uniformly distributed dopant effectively reduces the oxygen vacancy formation energy throughout the entire dielectric film. Under the influence of an applied electric field, multiple filaments are simultaneously excited within the resistive switching layer. The competition mechanism among these multiple filaments makes it impossible to accurately predict the instantaneous state of the conductive channel connection, resulting in a relatively wide distribution range for the turn-on voltage.

[0116] Example 1 employs a stepped gradient doping structure with decreasing doping from top to bottom. Figure 4 Subgraph (a) shows that its baseline yield reached 98.0%. Figure 4 In subfigure (b), the cumulative probability curve of the turn-on voltage (with solid squares) of Example 1 exhibits a nearly vertical, steep shape. The turn-on voltage of the test unit is highly concentrated around 0.82V, and the coefficient of variation is reduced to 4.63%. The longitudinal concentration gradient establishes a directional channel with minimal energy resistance inside the film. Under the drive of the electric field, oxygen ions continuously dissociate along this gradient path, suppressing the nucleation and growth of side filaments in other regions. The longitudinal concentration gradient design eliminates the randomness problem of filament growth, establishes a fixed unidirectional conduction path, and achieves a high degree of consistency in the turn-on voltage of large-scale device arrays.

[0117] Test Example 3: 1. Place the wafer to be tested in a semiconductor probe station equipped with a heated chuck. Connect the top and bottom metal layer test pads of the device to the semiconductor parameter analyzer and pulse generator module using coaxial cables.

[0118] 2. Perform an endurance test. Set the probe station ambient temperature to 25°C. Continuously apply the set pulse sequence to the device, including a positive Set pulse with an amplitude of +1.5V and a pulse width of 50ns, and a negative Reset pulse with an amplitude of -1.8V and a pulse width of 50ns.

[0119] 3. During the durability erase / write cycle, the instrument pauses the applied operating pulse at logarithmic intervals (1st, 100th, 10000th, 100000th, and 1000000th cycles), inserts a DC read voltage with an amplitude of 0.1V, and measures and records the resistance values ​​of the device in the low resistance state (LRS) and high resistance state (HRS). If the ratio of high to low resistance states is less than 10 or the device cannot complete the resistance state transition, it is recorded as fatigue failure.

[0120] 4. Perform high-temperature data retention test. Select brand-new device cells on the wafer that have not undergone fatigue testing, complete the initialization operation, and set the individual cells to stable high-resistivity and low-resistivity states respectively.

[0121] 5. Raise and maintain the temperature of the probe station heating chuck to 125°C to simulate a harsh high-temperature operating environment.

[0122] 6. Under constant high temperature conditions, apply a 0.1V reading voltage at predetermined time intervals (1st second, 100th second, 1000th second, 10000th second) to extract the resistance value and record the resistance decay data accumulated with temperature and time.

[0123] Table 3. Reliability test data of device units in Example 1, Comparative Example 3, and Comparative Example 5

[0124] in conclusion: Based on the test data in Table 3 and Figure 5 (a) shows the durability evolution diagram, where the direction of the doping gradient within the resistive switching layer directly affects the device's cycle life under continuous electrical stress. Figure 5 In (a), the high and low resistance state data curves (solid lines with squares) of Example 1 remain stable within 1,000,000 cycles, with a high-to-low resistance ratio greater than 200. The high resistance state data curve (dashed line with circles) of Comparative Example 3 shows a decreasing trend after 10,000 cycles, dropping to 3100Ω at 100,000 cycles, indicating the device is in an unerasable low-resistance locked state. Comparative Example 3 uses a reverse concentration gradient, with a low vacancy formation energy at the bottom layer and a high formation energy at the top layer. After applying a positive pulse to turn on the device, oxygen ions migrating to the upper oxygen storage layer face an energy barrier at the high formation energy interface of the top layer under the drive of a negative erasure pulse, hindering their downward flow and recombination with vacancies. Long-term accumulation of oxygen ions at the interface leads to the solidification of the conductive filaments, causing early fatigue failure. The positive gradient in Example 1 constructs an energy channel with a low top and high bottom, allowing oxygen ions to flow back along the energy gradient during the erasure operation, maintaining the balance of the internal reversible chemical reaction.

[0125] In high-temperature data retention testing, the external isolation structure determines the resistive stability of the device under thermal stress conditions. For example... Figure 5 As shown in (b), the high-resistivity data curve (with triangular dashed line) of Comparative Example 5 without a sidewall protective layer degrades over time. After testing at 125°C for 10,000 seconds, its high-resistivity resistance drops from 295,400 Ω to 12,500 Ω, and the device loses its ability to retain stored data. Plasma etching generates dangling bonds and lattice damage on the sidewalls of the resistive switching layer. Without sidewall enclosure and isolation, high-temperature thermal stress accelerates the intrusion of external moisture along the sidewall interface, while internal oxygen vacancies diffuse laterally along the damaged interface. This material exchange generates a leakage path parallel to the main channel on the device sidewall surface, leading to the collapse of the high-resistivity insulating state. The resistance drift of the high-resistivity and low-resistivity curves of Example 1 under the same test conditions is less than 10%, verifying that the sidewall protective layer prepared by atomic layer deposition can cut off the lateral diffusion path and isolate environmental interference, ensuring the long-term data retention capability of the storage device.

Claims

1. A resistive switching memory with a gradient-doped resistive switching layer, characterized in that, It includes the following components stacked in sequence: bottom metal layer (1), bottom electrode and metal insulating layer (2), bottom electrode (4), resistive switching layer (5), oxygen storage layer (6), top electrode (7), and top metal layer (12). Wherein, a through hole (3) connecting the bottom electrode and the metal layer is provided through the insulating layer (2) between the bottom electrode and the metal layer, and the through hole (3) connecting the bottom electrode and the metal layer connects the bottom metal layer (1) and the bottom electrode (4). The top metal layer (12) is connected to the top electrode (7) through a top through hole (11); The thickness of the resistive switching layer (5) is 10 to 200 Å. The resistive switching layer (5) contains trace doping elements. The concentration of the trace doping elements is distributed linearly or stepwise along the thickness direction of the resistive switching layer (5). The doping concentration of the trace doping elements gradually decreases from the upper surface of the resistive switching layer (5) towards the bottom electrode (4). The trace doping element is selected from one or more of Al, Si, P, S, Ga, Ge, As, Se, In, Sn, Sb, and Te.

2. The resistive switching memory with a gradient-doped resistive switching layer according to claim 1, characterized in that, It also includes an etching barrier layer (8), a sidewall protection layer (9), and an inter-device filling layer (10) disposed on the periphery. The etching barrier layer (8) is disposed on the top electrode (7); The sidewalls of the bottom electrode (4), resistive switching layer (5), oxygen storage layer (6), top electrode (7) and etching barrier layer (8) are flush and form the device sidewalls, and the device sidewalls are surrounded by the sidewall protective layer (9). The gap around the sidewall protective layer (9) is filled with the inter-device filling layer (10), and the top through hole (11) penetrates the inter-device filling layer (10), the sidewall protective layer (9) and the etching barrier layer (8) and contacts the top electrode (7).

3. A resistive switching memory with a gradient-doped resistive switching layer according to claim 1, characterized in that, The thickness of the through hole (3) connecting the bottom electrode and the metal layer is 150-2000 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Pd, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON. The thickness of the bottom electrode (4) is 10 to 1500 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, WN, TiON, TaON, and AlON. The substrate material of the resistive switching layer (5) is one of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, HfAlO or a mixture of at least two of these materials; The thickness of the oxygen storage layer (6) is 10 to 1000 Å, and the material is selected from one or more combinations of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, NiOx, TiN, TaN, AlN, TiON, TaON, and AlON. The thickness of the top electrode (7) is 10 to 5000 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON.

4. A resistive switching memory with a gradient-doped resistive switching layer according to claim 1, characterized in that, The thickness of the bottom electrode and the metal-insulating layer (2) is 150 to 2000 Å, and it is a composite structure composed of one or more of SiO2, nitrogen-doped silicon carbide, and plasma-enhanced silicon oxide. The bottom region of the composite structure that is in contact with the bottom metal layer (1) is made of nitrogen-doped silicon carbide, and the top region that is in contact with the bottom electrode (4) is made of plasma-enhanced silicon oxide.

5. A resistive switching memory with a gradient-doped resistive switching layer according to claim 2, characterized in that, The thickness of the etching barrier layer (8) is 100 to 5000 Å, and the material is composed of one or more of SiON, Si3N4, and plasma-enhanced silicon oxide; The thickness of the sidewall protective layer (9) is 10-500 Å, and the material is selected from one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, Si3N4, and tetraethylsilane-derived silicon oxide; The bottom of the sidewall protective layer (9) extends to cover the exposed surface of the bottom electrode and the metal-to-metal insulating layer (2); The thickness of the inter-device filling layer (10) is 10 to 10,000 Å, and the material is tetraethylsilane-derived silicon dioxide or organic silicon dioxide glass. The thickness of the top through hole (11) is 100 to 2000 Å, and the material is Cu or W.

6. A method for fabricating a resistive switching memory with a gradient-doped resistive switching layer, characterized in that, Fabricating a resistive switching memory with a gradient-doped resistive switching layer as described in any one of claims 1-5, comprising: A bottom electrode and an intermetallic insulating layer (2) are deposited on the bottom metal layer (1). After photolithography etching to form holes, conductive material is deposited to form a through hole (3) connecting the bottom electrode and the metal layer, and chemical mechanical polishing is performed for planarization. A bottom electrode (4) and a resistive switching layer (5) are sequentially deposited on the planarized surface. The resistive switching layer (5) is doped with trace dopant elements using an ion implantation process; By controlling the energy of ion implantation to gradually decrease or decrease in stages during the implantation process, the trace dopant elements form a linear or stepped concentration gradient distribution from the top surface to the bottom in the thickness direction of the resistive switching layer (5). The parameters of the ion implantation process are controlled as follows: Injection energy 1keV~50keV, injection dose 1×10 10 ~1×10 16 ions / cm 2 The implantation angle is 0° to 30° relative to the wafer normal, and the implantation temperature is 25° to 400°. Above the resistive switching layer (5) after ion implantation, an oxygen storage layer (6) and a top electrode (7) are sequentially deposited in vapor phase. Photolithography and plasma etching are performed, extending to the bottom electrode (4) and stopping to form an independent device array pattern. Then, insulating dielectric filling and grinding are performed to planarize the pattern. Etching creates holes that expose the top electrode (7), and filling them with conductive metal to form a top via (11) and planarizing it; A top metal layer is deposited on the planarized surface and etched to form a top metal layer (12).

7. The preparation method according to claim 6, characterized in that, In order to form the stepped concentration gradient distribution in the resistive switching layer (5), the process of doping the resistive switching layer (5) with trace dopant elements by ion implantation is performed in multiple stages. During the execution of the multiple stages, the injection energy of the later stage is lower than that of the earlier stage, and the injection dose of the later stage is greater than that of the earlier stage, so that the doping concentration of the trace dopant element gradually decreases from the upper surface of the resistive switching layer (5) to the bottom.

8. The preparation method according to claim 6, characterized in that, In the process of depositing the bottom electrode and the intermetallic insulating layer (2), the composite structure is prepared by plasma-enhanced chemical vapor deposition. The specific process is as follows: First, nitrogen-doped silicon carbide material is deposited on the bottom metal layer (1) as the bottom region of the bottom electrode and the metal-interconnected insulating layer (2); Subsequently, the deposition process gas was switched, and plasma-enhanced silicon oxide material was continuously deposited as the top region of the bottom electrode and the metal-to-metal insulating layer (2).

9. The preparation method according to claim 6, characterized in that, In the process of depositing the resistive layer (5), atomic layer deposition or physical vapor deposition is used for deposition. Furthermore, when the substrate material of the resistive switching layer (5) is a mixed oxide composed of multiple metal oxides, the mixed oxide is formed by co-deposition or alternating pulse deposition of the material sources corresponding to the multiple metal oxides.

10. The preparation method according to claim 6, characterized in that, Following the sequential vapor deposition of the oxygen storage layer (6) and the top electrode (7), a process is also included to deposit an etch barrier layer (8); The specific process of forming an independent device array pattern and filling it with insulating dielectric is as follows: Plasma dry etching is performed to form device sidewalls with flush sidewalls; A conformal deposition process is used to form a sidewall protective layer (9), which wraps the device sidewall without gaps and extends to cover the exposed surface of the bottom electrode and the metal-to-metal insulating layer (2) exposed by etching. The inter-device filling layer (10) is used to fill gaps and planarize; The etching forms a hole that exposes the top electrode (7), specifically penetrating the inter-device fill layer (10), the sidewall protection layer (9), and the etching barrier layer (8).

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