Semiconductor test structure

Abstract

A semiconductor test structure includes a carrier, a conductive layer, an adhesive portion, and semiconductor elements. The conductive layer is on the carrier and includes a continuous surface, the continuous surface includes a first region and a second region. A first adhesive portion and a second adhesive portion are on the conductive layer and cover the first region and expose the second region. A first semiconductor element and a second semiconductor element are on the first adhesive portion and the second adhesive portion, respectively, wherein the first semiconductor element includes a first lower electrode, a first semiconductor stack, and a first upper electrode, in a cross-sectional view, the first lower electrode faces the first adhesive portion, and the first upper electrode faces away from the first adhesive portion.

Description

Technical Field

[0001] This invention relates to semiconductor test structures, and particularly to a semiconductor test structure and its fabrication method for electroluminescence testing of vertical micro-light-emitting diodes. Background Technology

[0002] Semiconductor components such as light-emitting diodes (LEDs) have advantages such as low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed, and good photoelectric properties such as stable emission wavelength. Therefore, they are widely used in electronic devices such as household appliances, equipment indicator lights, and displays.

[0003] A vertical micro LED is a light-emitting diode structure with dimensions on the micrometer scale and p and n electrodes located on opposite sides of the light-emitting layer. To test whether the electrical or luminescent characteristics of an LED meet predetermined specifications, electroluminescence (EL) measurements are typically performed by touching the p and n electrodes with a probe. For fabricating different electronic devices, multiple LEDs can be fixed to temporary substrates using curing adhesive and transferred between different temporary substrates or from temporary substrates to a target substrate. However, because the lower electrode of current vertical micro LEDs is usually embedded in the curing adhesive, only photoluminescence (PL) measurements can be performed on vertical micro LEDs, and EL measurements are not readily available. Furthermore, the photoelectric characteristics measured by photoluminescence measurements often differ from the photoelectric characteristics of the diode during actual use, which is detrimental to the quality control of vertical micro LEDs. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor test structure and its fabrication method. This semiconductor test structure can be fabricated using chip-on-carrier (COC) and chip-on-wafer (COW) fabrication processes to achieve electroluminescence measurement, thereby overcoming the problems encountered in the prior art.

[0005] According to an embodiment of the present invention, a semiconductor test structure is provided, comprising a carrier, a conductive layer, a first adhesive portion, a second adhesive portion, a first semiconductor element, and a second semiconductor element. The conductive layer is located on the carrier and includes a continuous surface, the continuous surface including a first region and a second region. The first adhesive portion and the second adhesive portion are located on the conductive layer, covering the first region and exposing the second region. The first semiconductor element and the second semiconductor element are respectively located on the first adhesive portion and the second adhesive portion, wherein the first semiconductor element includes a first lower electrode, a first semiconductor stack, and a first upper electrode. In a cross-sectional view, the first lower electrode faces the first adhesive portion, and the first upper electrode faces away from the first adhesive portion. Attached Figure Description

[0006] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0007] Figure 1 , Figure 2 and Figure 3 These are cross-sectional schematic diagrams of semiconductor test structures according to some embodiments of the present invention;

[0008] Figure 4 These are top views of semiconductor test structures according to some embodiments of the present invention;

[0009] Figure 5 , Figure 6 and Figure 7 This is a cross-sectional schematic diagram illustrating different fabrication stages of a semiconductor test structure using a chip-on-carrier (COC) fabrication process according to an embodiment of the present invention, wherein... Figure 5 This is still a top-down view of one of the manufacturing processes;

[0010] Figure 8 , Figure 9 and Figure 10 This is a cross-sectional schematic diagram of different fabrication process stages of a semiconductor test structure fabricated using a chip-on-carrier (COC) fabrication process according to another embodiment of the present invention.

[0011] Figure 11 This is a cross-sectional schematic diagram of different fabrication process stages of a semiconductor test structure fabricated using a chip-on-wafer (COW) fabrication process according to yet another embodiment of the present invention.

[0012] Symbol explanation:

[0013] 100A, 100B, 100C... Semiconductor test structures

[0014] 101···Carrier

[0015] 102··· Adhesive layer

[0016] 103···Conductive layer

[0017] 103S··· Continuous Surface

[0018] 104··· Thin film conductive layer

[0019] 104S··· Continuous Surface

[0020] Block 105

[0021] 110··· Semiconductor Components

[0022] 110-1··· First Semiconductor Component

[0023] 110-2··· Second Semiconductor Component

[0024] 111···Semiconductor stack

[0025] 113, 113' ... Upper electrode

[0026] 115, 115' ... lower electrode

[0027] 117··· Conductive protrusions

[0028] 118··· Protective Layer

[0029] 201...First probe

[0030] 202...Second probe

[0031] 203··· Adhesion Part

[0032] 203-1···First Adhesion Part

[0033] 203-2···Second Adhesive Part

[0034] 401, 411...carrier boards

[0035] 403, 415... Adhesive

[0036] 405 laser

[0037] 407···Etching process

[0038] 413··· Bonding adhesive

[0039] 417, 419... Etching process

[0040] 501···Wafer (Chip)

[0041] 503··· Semiconductor Stacking

[0042] A1···First District

[0043] A2...Second District

[0044] C··· Sectional View

[0045] T···Top view

[0046] S101, S103, S105, S107, S109, S111, S113, S201, S203, S205, S207, S209, S211, S213, S301, S303, S305... Steps Detailed Implementation

[0047] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. Various embodiments in this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any relationship between different embodiments and / or configurations.

[0048] Furthermore, regarding spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the orientation of each element during use and operation. As the orientation of each element varies (rotated 90 degrees or other orientations), the related descriptions of its orientation should be interpreted in a similar manner.

[0049] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0050] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0051] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0052] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details are within the scope of knowledge of those skilled in the art.

[0053] Figure 1 This is a cross-sectional schematic diagram of a semiconductor test structure 100A according to an embodiment of the present invention. The semiconductor test structure 100A includes a carrier 101, a conductive layer 103, a plurality of semiconductor elements 110, and a plurality of adhesive portions 203. The conductive layer 103 is located on the carrier 101 and includes a continuous surface 103S. The plurality of adhesive portions 203 are located on the conductive layer 103, covering a first region A1 of the continuous surface 103S and exposing a second region A2 of the continuous surface 103S. In one embodiment, the plurality of adhesive portions 203 are located on the conductive layer 103 laterally separated from each other, wherein "laterally" means along... Figure 1The X-axis and / or Y-axis directions are specified. In another embodiment, a plurality of adhesive portions 203 may be laterally connected to each other on the conductive layer 103, covering a first region A1 of the continuous surface 103S and exposing a second region A2 of the continuous surface 103S. A plurality of semiconductor elements 110 are disposed on the carrier 101 and the conductive layer 103, and each semiconductor element 110 is located on a corresponding adhesive portion 203. The semiconductor element 110 may include a transistor element or a semiconductor light-emitting element, such as a vertical micro light-emitting diode element, but is not limited thereto.

[0054] The adhesive portion 203 may be a polymer. Depending on the embodiment, the adhesive portion 203 may contain polyimide (PI), epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), cycloolefin (COP), or benzocyclobutane (BCB), but is not limited thereto.

[0055] According to some embodiments of the present invention, the carrier 101 is used to support the conductive layer 103 and a plurality of semiconductor elements 110 disposed thereon, and the carrier 101 and the conductive layer 103 are permeable to light emitted by the semiconductor elements 110, making it easy to observe whether the semiconductor elements 110 are lit during electroluminescence measurement. The carrier 101 can be a non-epitaxy material or a non-growth substrate, such as a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to one embodiment of the present invention, the carrier 101 can be a glass substrate, a sapphire substrate, or a quartz substrate.

[0056] The conductive layer 103 is composed of a transparent metal oxide or a thin metal layer that can form an ohmic contact with the semiconductor layer of the semiconductor element 110. Transparent metal oxides include, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO), or gallium aluminum zinc oxide (GAZO). According to one embodiment, the conductive layer 103 may be an indium tin oxide (ITO) layer.

[0057] The carrier 101 and conductive layer 103 are made of materials that can be penetrated by lasers or non-coherent light, allowing the semiconductor device 110 to be separated from the carrier 101 and conductive layer 103 by a laser lift-off (LLO) fabrication process. According to one embodiment, when performing the laser lift-off (LLO) fabrication process, if the adhesive portion 203 is disposed on the front side of the carrier 101, the laser can enter the carrier 101 from the back side of the carrier 101, irradiate the adhesive portion 203, and then penetrate out from the front side of the carrier 101.

[0058] The plurality of semiconductor elements 110 includes a first semiconductor element 110-1, a second semiconductor element 110-2, and an m-th semiconductor element, where m is a positive integer greater than 2. The plurality of semiconductor elements 110 may have different, identical, or similar structures and dimensions. In a cross-sectional view, the first semiconductor element 110-1 and the second semiconductor element 110-2 are laterally separated from each other, and a portion of the continuous surface 103S of the conductive layer 103 is located between the first semiconductor element 110-1 and the second semiconductor element 110-2.

[0059] According to one embodiment, each semiconductor element 110 may include a light-emitting element, and the first semiconductor element 110-1 includes a semiconductor stack 111, an upper electrode 113, and a lower electrode 115. In a cross-sectional view, the lower electrode 115 faces the corresponding first adhesive portion 203-1, and the upper electrode 113 faces away from the first adhesive portion 203-1. The first semiconductor element 110-1 also includes a conductive bump 117 located between the lower electrode 115 and the conductive layer 103. The conductive bump 117 includes a convex surface protruding towards the conductive layer 103, and a portion of the convex surface of the conductive bump 117 directly contacts the conductive layer 103, thereby creating an electrical connection between the lower electrode 115 and the conductive layer 103. The second semiconductor element 110-2 has the same or similar structure as the first semiconductor element 110-1, including a semiconductor stack 111, an upper electrode 113, a lower electrode 115, and conductive protrusions 117. In the cross-sectional view, the lower electrode 115 faces the corresponding second adhesive portion 203-2, and the upper electrode 113 faces away from the second adhesive portion 203-2. In addition, the lower electrode 115 also faces the carrier 101 and the conductive layer 103, and the upper electrode 113 faces away from the carrier 101 and the conductive layer 103. The first adhesive portion 203-1 and the second adhesive portion 203-2 fix the first semiconductor element 110-1 and the second semiconductor element 110-2 onto the conductive layer 103, respectively. Neither the first adhesive portion 203-1 nor the second adhesive portion 203-2 directly contacts the sidewall of the semiconductor stack 111. The first adhesive portion 203-1 and the second adhesive portion 203-2 cover the sidewalls of the lower electrode 115 and the conductive protrusion 117, as well as part of the bottom surface of the semiconductor stack 111.

[0060] According to one embodiment, the semiconductor stack 111 comprises, from bottom to top, a P-type semiconductor layer, a multiple quantum well (MQW) and an N-type semiconductor layer, stacked sequentially. The lower electrode 115 is a p-type electrode and contacts the P-type semiconductor layer, and the upper electrode 113 is an n-type electrode and contacts the N-type semiconductor layer, but is not limited thereto. In another embodiment, the semiconductor stack 111 comprises, from bottom to top, an N-type semiconductor layer, a multiple quantum well (MQW) and a P-type semiconductor layer, stacked sequentially. The lower electrode 115 may be an n-type electrode and contacts the N-type semiconductor layer, and the upper electrode 113 may be a p-type electrode and contacts the P-type semiconductor layer. According to one embodiment, the lower electrode 115 may be composed of a metal, such as chromium (Cr), nickel (Ni), gold (Au), titanium (Ti), platinum (Pt), aluminum (Al), tin (Sn), or a combination thereof. The upper electrode 113 may be composed of a transparent metal oxide, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), or other suitable transparent conductive materials. The conductive protrusion 117 is composed of solder.

[0061] According to an embodiment of the present invention, each semiconductor element 110 includes a light-emitting surface and a non-light-emitting surface disposed opposite to each other, and the light transmittance of the electrode located on the light-emitting surface is higher than that of the electrode and the conductive protrusion 117 located on the non-light-emitting surface. Figure 1 In the illustrated embodiment, the light-emitting surface of the semiconductor element 110 faces away from the carrier 101, while the non-light-emitting surface faces the carrier 101; according to other embodiments, for example... Figure 2 and Figure 3 In the embodiment shown, the light-emitting surface of the semiconductor element 110 faces the carrier 101 and the non-light-emitting surface faces away from the carrier 101.

[0062] like Figure 1 As shown, when performing electroluminescence measurement on the semiconductor test structure 100A, the first probe 201 can directly or indirectly contact the upper electrode 113 of a semiconductor element 110 in the semiconductor test structure 100A, and the second probe 202 can directly or indirectly contact the conductive layer 103. The first probe 201 can directly apply a first voltage to the upper electrode 113, and the second probe 202 can apply a second voltage (the first voltage and the second voltage values ​​are different) to the conductive layer 103 in the second region A2 exposed on the continuous surface 103S, and conduct the second voltage originating from the second probe 202 to the lower electrode 115 through the conductive layer 103 and the conductive protrusion 117. According to an embodiment of the present invention, the second probe 202 does not need to directly contact the conductive protrusion 117 and the lower electrode 115 of the semiconductor element 110 to achieve the purpose of electroluminescence measurement. Therefore, even if the lower electrode 115 of the semiconductor element 110 is embedded in the adhesive portion 203, electroluminescence measurement of the semiconductor element 110 can still be performed, and it is not limited to photoluminescence measurement.

[0063] Figure 2This is a cross-sectional schematic diagram of a semiconductor test structure 100B according to another embodiment of the present invention. The semiconductor test structure 100B includes a carrier 101, an adhesive layer 102, a thin-film conductive layer 104, a plurality of semiconductor elements 110, and a plurality of adhesive portions 203. The thin-film conductive layer 104, the adhesive layer 102, and the carrier 101 are permeable to light emitted by the semiconductor elements 110, making it easy to observe whether the semiconductor elements 110 are lit during electroluminescence measurements. The thin-film conductive layer 104 is a multilayer film structure, including a base film and a conductive, light-transmitting metal oxide layer, wherein the light-transmitting metal oxide layer directly contacts the lower electrode 115 of the semiconductor element 110, and the base film is close to the adhesive layer 102. The adhesive layer 102 is located between the thin-film conductive layer 104 and the carrier 101 to attach the thin-film conductive layer 104 to the carrier 101. According to one embodiment, the light-transmitting metal oxide layer of the thin-film conductive layer 104 is, for example, an indium tin oxide (ITO) layer. The base film has sufficient mechanical strength to support the light-transmitting metal oxide layer. The composition of the base film is, for example, polyethylene terephthalate (PET). The adhesive layer 102 is, for example, an optical clear adhesive (OCA), but is not limited thereto. The adhesive layer 102 and the thin-film conductive layer 104 are made of materials that can be penetrated by lasers or non-coherent light, so that the semiconductor device 110 can be separated from the thin-film conductive layer 104 by a laser lift-off (LLO) fabrication process.

[0064] A plurality of semiconductor elements 110 include a first semiconductor element 110-1, a second semiconductor element 110-2, and an m-th semiconductor element, where m is a positive integer greater than 2. In a cross-sectional view, the first semiconductor element 110-1 and the second semiconductor element 110-2 are laterally separated from each other. According to one embodiment, each semiconductor element 110 may have different, identical, or similar structures and dimensions, including a semiconductor stack 111, an upper electrode 113, a lower electrode 115, and a conductive protrusion 117, wherein the conductive protrusion 117 is located on the upper electrode 113 and directly contacts the upper electrode 113, and the lower electrode 115 directly contacts the thin-film conductive layer 104, such that an electrical connection is formed between the lower electrode 115 and the thin-film conductive layer 104. According to one embodiment, the semiconductor stack 111 includes an N-type semiconductor layer, a multiple quantum well (MQW), and a P-type semiconductor layer stacked sequentially from bottom to top, the lower electrode 115 being an n-type electrode and contacting the N-type semiconductor layer, and the upper electrode 113 being a p-type electrode and contacting the P-type semiconductor layer, but is not limited thereto. In another embodiment, the semiconductor stack 111 comprises a P-type semiconductor layer, a multiple quantum well (MQW) layer, and an N-type semiconductor layer stacked sequentially from bottom to top. The lower electrode 115 may be a p-type electrode and contact the P-type semiconductor layer, and the upper electrode 113 may be an n-type electrode and contact the N-type semiconductor layer. According to one embodiment, the lower electrode 115 includes a light-transmitting layer, which may be composed of a light-transmitting metal oxide, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), or other suitable light-transmitting conductive materials. The lower electrode 115 is located between the semiconductor stack 111 and the thin-film conductive layer 104, wherein the light-transmitting layer of the lower electrode 115 is embedded in the corresponding adhesive portion 203, and the light-transmitting layer directly contacts the thin-film conductive layer 104. The upper electrode 113 may be composed of a metal, such as chromium (Cr), nickel (Ni), gold (Au), titanium (Ti), platinum (Pt), aluminum (Al), tin (Sn), or a combination thereof, and the conductive protrusion 117 may be composed of solder. In the cross-sectional view, the lower electrode 115 faces the adhesive portion 203, and the upper electrode 113 faces away from the adhesive portion 203. In addition, the lower electrode 115 also faces the carrier 101 and the thin film conductive layer 104, while the upper electrode 113 faces away from the carrier 101 and the thin film conductive layer 104.

[0065] The thin-film conductive layer 104 includes a continuous surface 104S. In one embodiment, a plurality of adhesive portions 203 are laterally connected to each other on the thin-film conductive layer 104, covering a first region A1 of the continuous surface 104S and exposing a second region A2 of the continuous surface 104S. The plurality of adhesive portions 203 include a first adhesive portion 203-1 and a second adhesive portion 203-2 laterally connected to each other, which respectively fix the first semiconductor element 110-1 and the second semiconductor element 110-2 to the thin-film conductive layer 104. Each adhesive portion 203 covers the side surface of the lower electrode 115, a portion of the bottom surface of the semiconductor stack 111, and a portion of the sidewall, and each adhesive portion 203 directly contacts the sidewall of the semiconductor stack 111.

[0066] like Figure 2 As shown, the first probe 201 and the second probe 202 can respectively contact the conductive protrusion 117 and the thin-film conductive layer 104 of a semiconductor element 110 in the semiconductor test structure 100B. The first probe 201 can apply a first voltage to the upper electrode 113 via the conductive protrusion 117, and the second probe 202 can apply a second voltage to the thin-film conductive layer 104 via the second region A2 exposed on the continuous surface 104S, and conduct the second voltage to the lower electrode 115 via the thin-film conductive layer 104. According to an embodiment of the present invention, the second probe 202 does not need to directly contact the lower electrode 115 of the semiconductor element 110 to achieve the purpose of electroluminescence measurement. Therefore, even if the lower electrode 115 of the semiconductor element 110 is embedded in the adhesive portion 203, electroluminescence measurement of the semiconductor element 110 can still be performed, without being limited to photoluminescence measurement. Figure 2 For details of other features of the semiconductor test structure 100B, please refer to the foregoing. Figure 1 The detailed description of the semiconductor test structure 100A will not be repeated here.

[0067] Figure 3This is a cross-sectional schematic diagram of a semiconductor test structure 100C according to another embodiment of the present invention. The semiconductor test structure 100C includes a carrier 101, a conductive layer 103, a plurality of semiconductor elements 110, and a plurality of adhesive portions 203. The plurality of semiconductor elements 110 includes a first semiconductor element 110-1, a second semiconductor element 110-2, and an m-th semiconductor element, where m is a positive integer greater than 2. In the cross-sectional view, the first semiconductor element 110-1 and the second semiconductor element 110-2 are laterally separated from each other. According to one embodiment, each semiconductor element 110 may have the same or similar structure and size, including a semiconductor stack 111, an upper electrode 113', a lower electrode 115', a conductive protrusion 117, and a protective layer 118, wherein the conductive protrusion 117 is located on the upper electrode 113', covering and contacting the upper electrode 113', the lower electrode 115' is located on the bottom surface of the semiconductor stack 111 and directly contacts the conductive layer 103, and the protective layer 118 covers the side of the lower electrode 115' and part of the sidewall of the semiconductor stack 111.

[0068] According to one embodiment, the semiconductor stack 111 includes a P-type semiconductor layer, a multiple quantum well (MQW) layer, and an N-type semiconductor layer stacked sequentially from bottom to top. The lower electrode 115' is a p-type electrode and contacts the P-type semiconductor layer, and the upper electrode 113' is an n-type electrode and contacts the N-type semiconductor layer, but is not limited thereto. In another embodiment, the semiconductor stack 111 includes an N-type semiconductor layer, a multiple quantum well (MQW) layer, and a P-type semiconductor layer stacked sequentially from bottom to top. The lower electrode 115' may be an n-type electrode and contacts the N-type semiconductor layer, and the upper electrode 113' may be a p-type electrode and contacts the P-type semiconductor layer. According to one embodiment, the lower electrode 115' is composed of a transparent metal oxide, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), or other suitable transparent conductive materials; the upper electrode 113' is composed of a metal, such as chromium (Cr), nickel (Ni), gold (Au), titanium (Ti), platinum (Pt), aluminum (Al), tin (Sn), or a combination thereof; and the conductive protrusion 117 is composed of solder. In the cross-sectional view, the lower electrode 115' faces the adhesive portion 203, and the upper electrode 113' faces away from the adhesive portion 203. Additionally, the lower electrode 115' also faces the carrier 101 and the conductive layer 103, while the upper electrode 113' faces away from the carrier 101 and the conductive layer 103.

[0069] The conductive layer 103 includes a continuous surface 104S. In one embodiment, a plurality of adhesive portions 203 are laterally connected to each other on the conductive layer 103, covering a first region A1 of the continuous surface 103S and exposing a second region A2 of the continuous surface 103S. The plurality of adhesive portions 203 include a first adhesive portion 203-1 and a second adhesive portion 203-2 laterally connected to each other, which respectively fix the first semiconductor element 110-1 and the second semiconductor element 110-2 to the conductive layer 103. Each adhesive portion 203 covers the side of the lower electrode 115' and a portion of the sidewall of the semiconductor stack 111, wherein a protective layer 118 is located between the adhesive portion 203 and the semiconductor stack 111, and between the adhesive portion 203 and the lower electrode 115'. The protective layer 118 is composed of an insulating or dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0070] like Figure 3 As shown, the first probe 201 and the second probe 202 can respectively contact the conductive protrusion 117 and the conductive layer 103 of a semiconductor element 110 in the semiconductor test structure 100C. The first probe 201 can apply a first voltage to the upper electrode 113' via the conductive protrusion 117, and the second probe 202 can apply a second voltage to the conductive layer 103 via the second region A2 exposed on the continuous surface 103S, and conduct the second voltage to the lower electrode 115' via the conductive layer 103. According to an embodiment of the present invention, the second probe 202 does not need to directly contact the lower electrode 115' of the semiconductor element 110 to achieve the purpose of electroluminescence measurement. Therefore, even if the lower electrode 115' of the semiconductor element 110 is embedded in the adhesive portion 203, electroluminescence measurement of the semiconductor element 110 can still be performed, without being limited to photoluminescence measurement. Figure 3 For details of other features of the semiconductor test structure 100C, please refer to the foregoing. Figure 1 The detailed description of the semiconductor test structure 100A will not be repeated here. In this embodiment, the adhesive portion 203 covers most of the sidewalls of the semiconductor stack 111, so that when the first probe 201 contacts the conductive protrusion 117, the corresponding semiconductor element 110 will not be displaced. Therefore, the semiconductor test structure 100C can provide a more robust test structure to resist the needle pressure of the first probe 201.

[0071] Figure 4 This is a top view schematic diagram of semiconductor test structures according to some embodiments of the present invention. These semiconductor test structures can be... Figure 1 , Figure 2 , Figure 3 Semiconductor test structures 100A, 100B, or 100C. For example... Figure 4As shown in (a), in one embodiment, multiple semiconductor elements 110 of the semiconductor test structure can be arranged in an array on the carrier 101. A conductive layer 103 or a thin-film conductive layer 104 is located on the carrier 101. An adhesive portion 203 covers a first region A1 of the conductive layer 103 or the thin-film conductive layer 104 and exposes a second region A2. In one embodiment, the second region A2 may be located on the left and right sides of the array of multiple semiconductor elements 110. The adhesive portion 203 fixes the multiple semiconductor elements 110 to the conductive layer 103 or the thin-film conductive layer 104. In some embodiments, the lower electrode or the conductive protrusion located on the lower side of the semiconductor element 110 is embedded in the adhesive portion 203, and the lower electrode or the conductive protrusion located on the lower side directly contacts the conductive layer 103 or the thin-film conductive layer 104. The upper electrode or the conductive protrusion located on the upper side is not covered by the adhesive portion 203. When performing electroluminescence measurements, a first probe 201 is used to contact the upper electrode of a semiconductor element 110 or a conductive protrusion located on the upper side, and a second probe 202 is used to contact the second region A2 exposed by the conductive layer 103 or the thin film conductive layer 104.

[0072] like Figure 4 As shown in (b), in another embodiment, a plurality of semiconductor elements 110 of the semiconductor test structure can be arranged in a block-like manner on the carrier 101 at intervals, wherein each block 105 contains a matrix of a plurality of semiconductor elements 110. In one embodiment, the plurality of blocks 105 can be arranged in a staggered manner, by selecting blocks of a plurality of semiconductor elements 110 to be transferred, and arranged at intervals on the carrier 101. A conductive layer 103 or a thin-film conductive layer 104 is located on the carrier 101, and an adhesive portion (not shown) covers a first region A1 of the conductive layer 103 or the thin-film conductive layer 104 and exposes a second region A2. In one embodiment, a plurality of second regions A2 can be located on the left and right sides and the top and bottom sides of a block 105. During electroluminescence measurement, a first probe 201 is used to contact the upper electrode of a semiconductor element 110 or the conductive protrusion located on the upper side, and a second probe 202 is used to contact the second region A2 exposed by the conductive layer 103 or the thin-film conductive layer 104. In this embodiment, each block 105 is adjacent to at least one second region A2, thereby shortening the current path during electroluminescence measurement and making the test easier. Furthermore, the spaced-apart second regions A2 expose a larger area of ​​the conductive layer 103 or thin-film conductive layer 104, facilitating contact between the second probe 202 and the conductive layer 103 or thin-film conductive layer 104 for testing. During sampling tests, electroluminescence measurements can be performed using semiconductor elements 110 in the same orientation and adjacent second regions A2 within each block 105, improving the consistency of the electroluminescence measurements.

[0073] Figure 5 , Figure 6 and Figure 7This is a cross-sectional schematic diagram illustrating different fabrication stages of a semiconductor test structure 100A using a chip-on-a-carrier (COC) fabrication process, according to an embodiment of the present invention. Figure 5 A top-down view of one stage of the manufacturing process is also shown. (See attached image.) Figure 5 In step S101, a carrier 101 is first provided, and a conductive layer 103 is formed on the carrier 101, wherein the conductive layer 103 completely covers the carrier 101 and has a continuous surface 103S. In one embodiment, the carrier 101 may be a sapphire substrate, and the conductive layer 103 may be an indium tin oxide (ITO) coating. In another embodiment, the carrier 101 and the conductive layer 103 may be provided by a glass substrate having indium tin oxide (ITO).

[0074] Continue reading Figure 5 In step S103, as shown in cross-sectional view C, an adhesive portion 203 is formed on the conductive layer 103. As shown in top view T, the adhesive portion 203 covers a first region A1 of the continuous surface 103S of the conductive layer 103 and exposes a second region A2, wherein the second region A2 is located on the left and right sides of the first region A1. In one embodiment, spin coating, soft baking, and patterning processes can be used to form the adhesive portion 203, which may be composed of polyimide (PI) or epoxy resin (EPO).

[0075] Next, refer to Figure 5 In step S105, a plurality of semiconductor elements 110 are provided and fixed to a carrier plate 401 using adhesive 403. In one embodiment, the carrier plate 401 may be a sapphire substrate, and the adhesive 403 may be composed of benzocyclobutane (BCB). Each semiconductor element 110 may include a semiconductor stack 111, an upper electrode 113, a lower electrode 115, and a conductive protrusion 117, wherein the upper electrode 113 and a portion of the sidewalls of the semiconductor stack 111 are embedded in the adhesive 403. Details of these features of the semiconductor element 110 can be found in the foregoing. Figure 1 The detailed description of the semiconductor test structure 100A will not be repeated here.

[0076] Then, refer to Figure 6In step S107, the structure provided in step S105 is flipped over and bonded to the structure in step S103, wherein the lower electrode 115 and conductive protrusion 117 of the semiconductor element 110 face the adhesive portion 203. In step S107, a bonding process with pressure applied from both above and below is used to bond multiple semiconductor elements 110 on the carrier plate 401 to the conductive layer 103 on the carrier 101. Because the adhesive portion 203 on the conductive layer 103 provided in step S103 is thin, and there is cohesive force between the adhesive portion 203 and the lower electrode 115 and conductive protrusion 117, after the bonding process in step S107, the adhesive portion 203 will gather around the lower electrode 115 and conductive protrusion 117, forming multiple adhesive portions 203 that are laterally separated from each other, and the convex surface of the conductive protrusion 117 directly contacts the conductive layer 103. (Continue reading...) Figure 6 In step S109, a laser lift-off (LLO) process can be used to irradiate a laser 405 from the back of the carrier plate 401 to decompose or vaporize the adhesive 403, so that the carrier plate 401 is separated from the semiconductor element 110 and the adhesive 403 remains on the semiconductor element 110.

[0077] Then, refer to Figure 7 In step S111, an etching process 407, such as inductively coupled plasma (ICP) etching, can be used to remove all the adhesive 403. (Continue reading...) Figure 7 In step S113, after removing the adhesive 403, the upper electrode 113 of the semiconductor element 110 is exposed to form a semiconductor test structure 100A. The first probe 201 and the second probe 202 are used to contact the upper electrode 113 of the semiconductor element 110 and the second region A2 exposed by the conductive layer 103, respectively, to perform electroluminescence measurement.

[0078] Figure 8 , Figure 9 and Figure 10 This is a cross-sectional schematic diagram illustrating different fabrication stages of a semiconductor test structure 100B using a chip-on-a-carrier (COC) fabrication process according to another embodiment of the present invention. (See also...) Figure 8 In step S201, a plurality of semiconductor elements 110 are first provided and fixed to a carrier plate 401 using adhesive 403. In one embodiment, the carrier plate 401 may be a sapphire substrate, and the adhesive 403 may be composed of benzocyclobutane (BCB). Each semiconductor element 110 includes a semiconductor stack 111, an upper electrode 113, a lower electrode 115, and a conductive protrusion 117, wherein the lower electrode 115 and a portion of the sidewalls of the semiconductor stack 111 are embedded in the adhesive 403.

[0079] Continue reading Figure 8 In step S203, the structure from step S201 is flipped over, and the semiconductor element 110 is bonded to another carrier plate 411 using adhesive 413, wherein the upper electrode 113 and conductive protrusion 117 of the semiconductor element 110 are embedded in the adhesive 413. Then, a laser lift-off (LLO) process can be used to irradiate the back of the carrier plate 401 with a laser to decompose or vaporize the adhesive 403, causing the carrier plate 401 to separate from the semiconductor element 110, while the adhesive 403 remains on the semiconductor element 110. Next, an etching process, such as inductively coupled plasma (ICP) etching, can be used to remove all the adhesive 403 to expose the lower electrode 115 of the semiconductor element 110.

[0080] Then, refer to Figure 9 In step S205, adhesive 415 is formed on the carrier plate 411, and the semiconductor element 110 is embedded in the adhesive 415. In one embodiment, the adhesive 415 in the form of a dry film can be used, and the semiconductor element 110 is embedded in the adhesive 415 by imprint bonding. (Continue reading) Figure 9 In step S207, an etching process 417, such as inductively coupled plasma (ICP) etching or other dry etching processes, can be used to remove a portion of the adhesive 415 to reduce the top surface height of the adhesive 415 until the lower electrode 115 of the semiconductor element 110 is exposed.

[0081] Next, refer to Figure 10 In step S209, a carrier 101 is provided, and a thin-film conductive layer 104 is attached to the carrier 101 using an adhesive layer 102. Then, the thin-film conductive layer 104 is bonded to a semiconductor element 110 located on a carrier plate 411 using adhesive 415, wherein the thin-film conductive layer 104 directly contacts the lower electrode 115 of the semiconductor element 110. (Continue reading...) Figure 10 In step S211, the structure from step S209 is flipped over. A laser lift-off (LLO) process is used to irradiate the back of the carrier plate 411 with a laser to decompose or vaporize the adhesive 413, separating the carrier plate 411 from the semiconductor device 110, while leaving the adhesive 413 on the semiconductor device 110. Next, an etching process 419, such as a dry etching process, is used to remove all the adhesive 413 and most of the adhesive 415.

[0082] See also Figure 10In step S213, after removing the bonding adhesive 413 and most of the adhesive 415, the upper electrode 113, conductive protrusion 117, and sidewalls of the semiconductor stack 111 of the semiconductor element 110 are exposed to form a semiconductor test structure 100B, wherein the remaining adhesive 415 serves as an adhesive portion 203. The first probe 201 and the second probe 202 are used to contact the conductive protrusion 117 of the semiconductor element 110 and the second region A2 exposed by the thin-film conductive layer 104, respectively, to perform electroluminescence measurements. In this embodiment, the thin-film conductive layer 104 is attached to the carrier 101 using the adhesive layer 102, which is convenient and fast to fabricate. Furthermore, no thermal fabrication process is required during steps S209 to S213, thus ensuring that the electrical properties of the thin-film conductive layer 104 are not affected.

[0083] Figure 11 This is a cross-sectional schematic diagram illustrating different fabrication stages of a semiconductor test structure 100C using a chip-on-wafer (COW) fabrication process, according to yet another embodiment of the present invention. (See also...) Figure 11 In step S301, a semiconductor stack 503 epitaxially grown on wafer 501 is first provided, and the semiconductor stack 503 is patterned to form a mesa structure of a plurality of semiconductor elements 110. Then, a lower electrode 115' is formed on the top surface of the mesa structure of semiconductor elements 110, and a protective layer 118 is formed oriented on the sidewall of the mesa structure, wherein the protective layer 118 has an opening to expose the lower electrode 115'.

[0084] Continue reading Figure 11 In step S303, a carrier 101 with a conductive layer 103 formed thereon is provided, and then the conductive layer 103 is bonded to the semiconductor stack 503 using an adhesive portion 203, wherein the lower electrode 115' of the semiconductor element 110 directly contacts the conductive layer 103, and the adhesive portion 203 fills the space between the platform structures.

[0085] See also Figure 11In step S305, the structure from step S303 is flipped over, and a laser lift-off (LLO) process is used to irradiate a laser from the back side of wafer 501 to separate the semiconductor material between wafer 501 and semiconductor stack 503, thus separating wafer 501 from semiconductor stack 503. Then, semiconductor stack 503 is thinned and patterned to form a semiconductor stack 111 of multiple semiconductor elements 110. The multiple semiconductor elements 110 are laterally separated from each other, and a protective layer 118 and an adhesive portion 203 surround a portion of the sidewalls of semiconductor stack 111, wherein the adhesive portion 203 covers a first region A1 of the continuous surface 103S of conductive layer 103 and exposes a second region A2. Subsequently, an upper electrode 113' and conductive protrusions 117 are formed on semiconductor stack 111 to complete semiconductor test structure 100C. Electroluminescence measurements are performed by contacting the first probe 201 and the second probe 202 with the conductive protrusion 117 and the second region A2 exposed by the conductive layer 103 of the semiconductor element 110, respectively.

[0086] According to the above embodiments, after completing the electroluminescence measurement of the semiconductor test structures 100A, 100B, and 100C, a transfer fabrication process can be subsequently performed to transfer the semiconductor elements 110 in the semiconductor test structures 100A, 100B, and 100C one by one to other carriers for grouping semiconductor elements 110 with similar or identical electrical or optical specifications. For example, a laser lift-off fabrication process can be used to irradiate selected semiconductor elements 110 (e.g., the first semiconductor element 110-1) from the back side of the carrier 101 with a laser to decompose or vaporize the adhesive portion 203 located between the semiconductor element 110 and the carrier 101, thereby separating the semiconductor element 110 from the carrier 101; while unselected semiconductor elements 110 are not irradiated by the laser and therefore remain on the front side of the carrier 101. In subsequent fabrication processes, other selected semiconductor elements 110 (e.g., second semiconductor element 110-2) can be transferred from carrier 101 to other carriers (not shown), and the transfer fabrication process can be repeated until all semiconductor elements 110 located on carrier 101 have been transferred to selected same and / or different carriers.

[0087] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor test structure, comprising: carrier; A conductive layer is located on the carrier and includes a continuous surface, the continuous surface including a first region and a second region; The first adhesive portion and the second adhesive portion are located on the conductive layer, covering the first region and exposing the second region; and The first semiconductor element and the second semiconductor element are respectively located on the first adhesive portion and the second adhesive portion. in, The first semiconductor element includes a first lower electrode, a first semiconductor stack, and a first upper electrode. In a cross-sectional view, the first lower electrode faces the first adhesive portion, and the first upper electrode faces away from the first adhesive portion.

2. The semiconductor test structure as described in claim 1, wherein, The carrier can be penetrated by light emitted from the first semiconductor element.

3. The semiconductor test structure as described in claim 1, wherein, A portion of the continuous surface lies between the first semiconductor element and the second semiconductor element.

4. The semiconductor test structure as described in claim 1, wherein, In this cross-sectional view, the first semiconductor element and the second semiconductor element are separated from each other.

5. The semiconductor test structure as described in claim 1, wherein, The first semiconductor element also includes conductive bumps located between the first lower electrode and the conductive layer.

6. The semiconductor test structure as described in claim 5, wherein, The conductive bump includes a convex surface that protrudes toward the conductive layer.

7. The semiconductor test structure as described in claim 1, wherein, In this cross-sectional view, the first adhesive portion does not directly contact the sidewall of the first semiconductor stack.

8. The semiconductor test structure as described in claim 1, wherein, The first lower electrode includes a light-transmitting layer located between the first semiconductor stack and the conductive layer. The light-transmitting layer is embedded in the corresponding first adhesive portion and is in direct contact with the conductive layer.

9. The semiconductor test structure as described in claim 8, wherein, In this cross-sectional view, the first adhesive portion directly contacts the sidewall of the first semiconductor stack.

10. The semiconductor test structure of claim 1, further comprising an adhesive layer located between the conductive layer and the carrier.

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