Silicon light light engine package structure and method
By adopting a vertical layout structure of dual-layer chip components in optoelectronic co-packaging, the PCB layout pressure problem caused by the horizontal layout of silicon photonic chips in optoelectronic co-packaging is solved, improving space utilization and coupling efficiency, and reducing parasitic inductance and high-frequency loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ACCELINK TECHNOLOGIES CO LTD
- Filing Date
- 2026-06-05
- Publication Date
- 2026-07-28
AI Technical Summary
In existing optoelectronic co-packaging solutions, the horizontal layout of silicon photonics chips leads to excessive layout pressure on printed circuit boards, increases fiber fan-out pressure, and affects PCB space utilization and coupling efficiency.
A dual-layer chip assembly structure is adopted, in which the first chip and the second chip are interconnected with the circuit board through flip-chip technology and laid out in a stacked manner. The first fiber array and the second fiber array are respectively aligned and coupled with the chip to achieve a vertical layout, which reduces the space occupied by the chip and fiber array on the circuit board and improves space utilization.
The vertically arranged dual-layer chip assembly structure reduces the space occupied by the chip and fiber array on the circuit board, improves the vertical space utilization of the circuit board, reduces parasitic inductance and high-frequency loss, and improves the coupling efficiency of optical signal transmission.
Smart Images
Figure CN122469480A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optical communication technology, and in particular to a silicon photonics engine packaging structure and method. Background Technology
[0002] The increasing demand for Artificial Intelligence (AI) and the continuous evolution of data center communication bandwidth are placing ever-higher demands on the density of fiber optic communication. Optical module speeds are iteratively increasing from 400G to 800G, 1.6T, and 3.2T. There are two main ways to improve module speed: increasing the baud rate of a single channel and multi-channel parallel transmission. However, silicon photonic modulators currently only achieve a single-channel baud rate of 200G, and single-channel 400G is not yet commercially available. Increasing the number of channels to improve module speed is limited by protocol requirements and module size, only allowing for 8-channel parallel transmission. Furthermore, adding parallel channels increases the size of the photonic integrated circuit (PIC), putting pressure on the layout of the printed circuit board (PCB). Therefore, an optoelectronic co-packaging solution is proposed to increase the number of parallel transmission channels. The optical engine uses optoelectronic co-packaging to increase the number of channels, reduce power consumption per bit, and reduce signal loss.
[0003] NPO stands for Near-Packaged Optics. The core definition of NPO is to move the optical engine from a traditional front-panel pluggable location closer to the Application Specific Integrated Circuit (ASIC). However, the optical engine and ASIC remain two independent packages, typically mounted side-by-side on the same high-performance substrate (such as a silicon interposer or organic substrate). Compared to traditional pluggable module packaging, NPO eliminates the limitation on the number of optical engine channels, allowing for increased module speeds by increasing the number of parallel transmission channels. However, the length of silicon photonics chip modulators is limited by material bandwidth. As the number of PIC channels increases, the chip size grows larger, putting significant pressure on PCB layout. Methods to increase channel density, such as compressing channel spacing, are limited by single-mode fiber; excessively small spacing leads to decreased coupling efficiency and tolerance, and increased fiber fan-out pressure.
[0004] Currently, pluggable modules also face this problem. Chip sizes are increasing, severely squeezing PCB layout space. The flip-chip process commonly used for transimpedance amplifiers (TIAs) and photodiodes in the receiver requires larger pitch spacing, increasing the space occupied by printed circuit board assemblies (PCBAs). The layout of optical engines and fiber fan-out components are increasingly encroaching on PCB space, leading to ever-increasing pressure on PCB layout.
[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention
[0006] The technical problem to be solved by this invention is the excessive layout pressure on the PCB caused by the horizontal chip layout in existing optoelectronic co-packaging solutions.
[0007] The present invention adopts the following technical solution: In a first aspect, the present invention provides a silicon photonics engine packaging structure, including a circuit board 1 and a dual-layer chip assembly 2; The dual-layer chip assembly 2 includes a first chip 20 and a second chip 21 stacked together. The first chip 20 is interconnected with the circuit board 1 via a flip-chip process, and the second chip 21 is stacked on top of the first chip 20 and interconnected with the circuit board 1. A first fiber array 3 is fixed on the first chip 20, and a second fiber array 4 is fixed on the second chip 21. The first fiber array 3 is aligned and coupled with the first chip 20, and the second fiber array 4 is aligned and coupled with the second chip 21 to realize optical signal transmission.
[0008] Furthermore, the first chip 20 is soldered onto the circuit board 1, and the second chip 21 is stacked back-to-back on top of the first chip 20. The first chip 20 and the second chip 21 are bonded together, and the second chip 21 is interconnected with the circuit board 1 by wire bonding.
[0009] Furthermore, the first fiber array 3 and the second fiber array 4 are bonded together to form a fiber array unit 5, which is bonded to the coupling end face of the dual-layer chip assembly 2 for optical signal transmission.
[0010] Furthermore, the first chip 20 is soldered onto the circuit board 1, and the second chip 21 is stacked in an arch shape above the first chip 20, with the two arched legs 210 of the second chip 21 soldered onto the circuit board 1; The first fiber array 3 and the second fiber array 4 are separately disposed and aligned and coupled to the first chip 20 and the second chip 21, respectively.
[0011] Furthermore, on the side coupled to the first fiber array 3, the first chip 20 protrudes beyond the second chip 21 by a predetermined length, the first fiber array 3 is bonded to the coupling end face of the first chip 20, and the second fiber array 4 is attached to the upper surface of the second chip 21.
[0012] Furthermore, the second fiber array 4 includes a second base 40, with second cantilever 400 extending from both sides of the second base 40, and the second cantilever 400 overlapping and fixed to the upper surface of the second chip 21.
[0013] Furthermore, overlapping platforms 200 extend from both ends of the protruding section of the first chip 20. The overlapping platforms 200 are flush with or higher than the upper surface of the first chip 20, and the first fiber array 3 is overlapped on the overlapping platforms 200.
[0014] Furthermore, the first fiber array 3 includes a first base 30, and first cantilever 300 extends from both sides of the first base 30. The first cantilever 300 overlaps and is fixed to the upper surface of the overlapping platform 200.
[0015] Furthermore, the first chip 20 is a transmitting chip, a receiving chip, or a transceiver chip, and the second chip 21 is a transmitting chip, a receiving chip, or a transceiver chip.
[0016] Secondly, the present invention provides a silicon photonics engine packaging method for preparing the above-mentioned silicon photonics engine packaging structure, comprising: The first chip 20 is fixed onto the circuit board 1 and interconnected with the circuit board 1 by a flip-chip process; The second chip 21 is stacked on top of the first chip 20, and the second chip 21 is interconnected with the circuit board 1; The first fiber array 3 and the second fiber array 4 are aligned and coupled to the first chip 20 and the second chip 21, respectively, to realize optical signal transmission.
[0017] The beneficial effects of the present invention are as follows: the original horizontal layout of the first chip and the second chip are converted into a vertical layout by stacking, and the first fiber array and the second fiber array corresponding to the first chip and the second chip are also vertically arranged, which reduces the space occupied by the chip and the fiber array on the circuit board and improves the space utilization rate of the circuit board in the vertical direction. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0019] Figure 1 This is a schematic diagram of the overall structure of a silicon photonics engine packaging structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the overall structure of a silicon photonics engine packaging structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a dual-layer chip assembly and fiber array unit provided in an embodiment of the present invention; Figure 4 This is a first-view structural diagram of a transmitter and receiver provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a transmitter and receiver from a second perspective according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a first chip and a second chip provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a second chip and a second fiber array provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a first chip and a second chip provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of an overlapping platform provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of an overlapping platform provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a first fiber optic array provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of a second fiber optic array provided in an embodiment of the present invention; Figure 13 This is a schematic flowchart of a silicon photonics engine packaging method provided in an embodiment of the present invention.
[0020] The attached figures are labeled as follows: Circuit board 1, double-layer chip assembly 2, first chip 20, overlapping platform 200, first bump 201, second chip 21, arch foot 210, second bump 211, gold wire 213, first fiber array 3, first base 30, first cantilever 300, first cover plate 31, first fiber 32, second fiber array 4, second base 40, second cantilever 400, second cover plate 41, second fiber 42, fiber array unit 5, transmitter 6, receiver 7. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0022] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.
[0023] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
[0024] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.
[0025] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0026] Example 1: Embodiment 1 of the present invention provides a silicon photonics engine packaging structure, wherein the silicon photonics engine packaging structure includes at least the following: Figure 1 and Figure 2 The two implementations shown both include a circuit board 1 and a dual-layer chip assembly 2. The dual-layer chip assembly 2 includes a first chip 20 and a second chip 21 stacked together. The shapes of the first chip 20 and the second chip 21 differ between the two implementations. The first chip 20 is interconnected to the circuit board 1 via a flip-chip process, and the second chip 21 is stacked on top of the first chip 20 and interconnected with the circuit board 1. This chip stacking method replaces the traditional slotting method for mounting optical devices, avoiding slotting on the PCBA, thereby freeing up more wiring area and improving circuit layout flexibility. The interconnection method between the second chip 21 and the circuit board 1 differs between the two implementations. Figure 1 The second chip 21 is mounted on the circuit board 1 and interconnected with the circuit board 1. Figure 2 The second chip 21 is flip-mounted on the circuit board 1 and interconnected with the circuit board 1; a first fiber array 3 is fixed on the first chip 20, and a second fiber array 4 is fixed on the second chip 21. The second fiber array 4 is disposed above the first fiber array 3. Taking the second fiber array 4 as an example, the second fiber array 4 can be fixed by directly bonding it to the end face of the second chip 21 (e.g., Figure 1 (As shown), it can also be overlapped on the second chip 21 and glued and fixed (as shown). Figure 2 (As shown); the first fiber array 3 is aligned and coupled to the first chip 20, and the second fiber array 4 is aligned and coupled to the second chip 21 to realize optical signal transmission.
[0027] The original horizontal layout of the first chip 20 and the second chip 21 is converted into a vertical layout by stacking. The first fiber array 3 and the second fiber array 4 corresponding to the first chip 20 and the second chip 21 are also vertically laid out, which reduces the space occupied by the chips and fiber arrays on the circuit board 1 and improves the space utilization rate of the circuit board 1 in the vertical direction.
[0028] Next Figure 1 The silicon photonics engine packaging structure shown will be explained in detail.
[0029] See Figure 3 The first chip 20 is soldered onto the circuit board 1, and the second chip 21 is stacked back-to-back on top of the first chip 20. The first chip 20 and the second chip 21 are bonded together, and the second chip 21 is interconnected with the circuit board 1 by wire bonding.
[0030] In one optional embodiment, a first bump 201, such as a bump gold ball or copper pillar, is provided on the pad surface of the first chip 20. The first chip 20 is inverted on the circuit board 1 with the pad surface facing down, and the first bump 201 is soldered to the corresponding pad on the circuit board 1.
[0031] Since the projections of the first chip 20 and the second chip 21 on the horizontal plane are the same, in order to achieve interconnection between the second chip 21 and the circuit board 1, in an optional embodiment, the first chip 20 and the second chip 21 are vertically stacked on the non-functional layer, that is, the second chip 21 is stacked back to back on top of the first chip 20 to form the double-layer chip assembly 2, forming a compact integrated double-layer chip assembly 2, avoiding crosstalk of optical, electrical and thermal signals, and significantly saving PCB layout space.
[0032] In practical applications, the adhesive used to bond and fix the first chip 20 and the second chip 21 can be die bond adhesive or underfill adhesive, etc., which shall be determined by those skilled in the art based on the actual situation. After bonding and fixing, the pad surface of the second chip 21 faces upward. In an optional embodiment, gold wire 213 is used to pull from the pad surface of the second chip 21 to the corresponding pad on the circuit board 1 to achieve interconnection between the second chip 21 and the circuit board 1.
[0033] Continue reading Figure 3 The first fiber array 3 and the second fiber array 4 are bonded together to form a fiber array unit 5, which is bonded to the coupling end face of the double-layer chip assembly 2 for optical signal transmission.
[0034] In one optional embodiment, based on the relative positions of the first chip 20 and the second chip 21, the second fiber array 4 is bonded and fixed above the first fiber array 3 to form a fiber array unit 5. Both the first fiber array 3 and the second fiber array 4 are 125µm single-mode fiber arrays. The two sets of 125µm single-mode fibers are placed side-by-side, perfectly matching the thickness of the dual-layer chip assembly 2 to achieve dual-layer alignment coupling. The unified coupling end face formed by the stacked first chip 20 and second chip 21 has a larger bonding contact area, further improving fiber alignment accuracy and overall optical coupling efficiency. After the dual-layer single-mode fiber is fanned out, it can be connected to a 32-channel multi-fiber precision ferrule to achieve interconnection with conventional pluggable optical modules. Furthermore, the cover plate at the bottom of the fiber array unit 5 is lengthened to ensure that the end-face bonding coupling adhesive effectively covers the optical port area, preventing dust intrusion and optical path contamination. The fiber array unit 5 and the dual-layer chip assembly 2 are bonded and cured with end-face bonding coupling adhesive, effectively avoiding a decrease in coupling efficiency due to optical path deformation caused by PCBA deformation.
[0035] In practical applications, the first chip 20 is a transmitter chip, a receiver chip, or a transceiver chip, and the second chip 21 is a transmitter chip, a receiver chip, or a transceiver chip. In one optional embodiment, the circuit board 1 is provided with two dual-layer chip assemblies 2, and each dual-layer chip assembly 2 is equipped with a corresponding first fiber array 3 and a second fiber array 4, such as... Figure 4 As shown, when both the first chip 20 and the second chip 21 are transmitting chips, the first chip 20 and the second chip 21, together with the corresponding first fiber array 3 and the second fiber array 4, constitute the transmitting end 6; when both the first chip 20 and the second chip 21 are receiving chips, the first chip 20 and the second chip 21, together with the corresponding first fiber array 3 and the second fiber array 4, constitute the receiving end 7. It should be noted that... Figure 4 The gold wire 213 used for bonding in the second chip 21 of the receiver 7 is not shown in the diagram. However, the corresponding gold wire 213 can be set in the receiver 7, referring to the transmitter 6. Figure 5 As shown.
[0036] It should be noted that the first chip 20 and the second chip 21 can also be optoelectronic integrated chips, and the driver or TIA can be integrated on the first chip 20 and the second chip 21 through the Flip Chip process.
[0037] In practice, wire bonding leads to problems such as high parasitic inductance, high high-frequency loss, and large space occupation. Furthermore, since the first chip 20 and the second chip 21 are fixed together with adhesive, uneven adhesive application can easily cause angular misalignment between them. Similarly, the first fiber array 3 and the second fiber array 4, also fixed together with adhesive, exhibit angular misalignment after assembly. During the bonding and assembly of the dual-layer chip assembly 2 and the fiber array unit 5, various angular misalignments are superimposed, resulting in poor coupling efficiency. Moreover, relying solely on end-face bonding to fix the dual-layer chip assembly 2 and the fiber array unit 5 lacks reliability and can easily introduce new angular misalignments during assembly. Therefore, Embodiment 2 of the present invention provides a second chip 21 with a differentiated structural form and separately arranges the first fiber array 3 and the second fiber array 4 to avoid the adverse effects of superimposed angular deviations on coupling efficiency.
[0038] Specifically, in one alternative implementation, see [reference] Figure 6 The first chip 20 is directly connected to the circuit board 1 through a bump, and the second chip 21 is stacked on top of the first chip 20 in an arch shape. The two arched feet 210 of the second chip 21 are directly connected to the circuit board 1 through bumps.
[0039] In one optional embodiment, a first bump 201, such as a bump gold ball or copper pillar, is provided on the pad surface of the first chip 20. The first chip 20 is inverted on the circuit board 1 with the pad surface facing down, and the first bump 201 is soldered to the corresponding pad on the circuit board 1.
[0040] In one optional embodiment, the second chip 21 is arched over the first chip 20. The arched portion is fitted over the first chip 20. The arched portion and the upper surface of the first chip 20 may not be fixed, or they may be bonded together with an adhesive such as die bond or underfill adhesive. The type of adhesive is determined by those skilled in the art based on the actual situation. The arched feet 210 are fitted on both sides of the first chip 20. The bottom of the arched feet 210 is provided with pads. The pads are provided with second bumps 211, such as bump balls or copper pillars. The pads are inverted onto the circuit board 1 with the pads facing down. The second bumps 211 are soldered to the corresponding pads on the circuit board 1. In this way, both the first chip 20 and the second chip 21 are interconnected with the circuit board 1 using a bump through-hole method, which reduces the space occupied by the double-layer chip assembly 2 and reduces parasitic inductance and high-frequency loss.
[0041] To improve coupling efficiency, the first fiber array 3 and the second fiber array 4 are separately disposed and aligned and coupled to the first chip 20 and the second chip 21, respectively. The second fiber array 4 is disposed above the first fiber array 3 with a preset distance between them, so that the first fiber array 3 and the second fiber array 4 do not interfere with each other. The first fiber array 3 is bonded to the coupling end face of the first chip 20 by end-face adhesive coupling glue. The second fiber array 4 overlaps and adheres to the surface of the second chip 21. The contact position of the second fiber array 4 and the second chip 21 is fixed by end-face adhesive coupling glue. Figure 7 As shown.
[0042] To facilitate coupling between the first chip 20 and the first fiber array 3, see [reference] Figure 8 On the side coupled to the first fiber array 3, the first chip 20 protrudes beyond the second chip 21 by a preset length. The preset length is determined by those skilled in the art based on the actual situation. By staggering the coupling end faces of the first chip 20 and the second chip 21, the first fiber array 3 and the second fiber array 4 will not affect each other during coupling, and it is easy to operate.
[0043] It is easy to understand that splicing the fiber array onto the chip provides a better fixation effect than bonding the fiber array to the coupling end face of the chip. Therefore, to improve the overall stability of the structure, splicing platforms 200 extend from both ends of the protruding section of the first chip 20. The first chip 20 is T-shaped, and the splicing platforms 200 are flush with the upper surface of the first chip 20 (e.g., Figure 9 (as shown) or higher than the upper surface of the first chip 20 (e.g. Figure 10 As shown), the first fiber array 3 is lapped on the lapping platform 200.
[0044] Taking the example that the bonding platform 200 is higher than the upper surface of the first chip 20, the structure of the first fiber array 3 and the second fiber array 4 will be specifically described.
[0045] See Figure 11The first fiber array 3 includes a first base 30, with first cantilever 300s extending from both sides of the first base 30. The first cantilever 300s overlap and are fixed to the upper surface of the overlapping platform 200. In an optional embodiment, L-shaped first cantilever 300s extend from both side walls of the first base 30, with the height of the first cantilever 300 being higher than that of the first base 30, allowing the first cover plate 31 to be snapped between the two first cantilever 300s to improve the overall stability of the structure. The first chip 20 and the first fiber array 3 are aligned, and the coupling efficiency is monitored. When the coupling efficiency meets the requirements, the two inner side walls of the first cantilever 300 are attached and bonded to the overlapping platform 200, making the first fiber array 3 and the first chip 20 a whole, thereby ensuring the coupling efficiency between the first chip 20 and the first fiber array 3.
[0046] In one optional embodiment, a V-groove is provided on the first base 30, and a first cover plate 31 is bonded and fixed above the first base 30. The first optical fiber 32 is accommodated and fixed between the first base 30 and the cover plate along the V-groove. In actual use, the first optical fiber 32 can be a single-mode optical fiber with a diameter of 125μm.
[0047] See Figure 12 The second fiber array 4 includes a second base 40, and second cantilever 400 extends from both sides of the second base 40. The second cantilever 400 overlaps and is fixed to the upper surface of the second chip 21.
[0048] In one optional embodiment, L-shaped second cantilever 400s extend from both side walls of the second base 40. The height of the second cantilever 400 is higher than that of the second base 40, allowing the second cover plate 41 to be snapped between the two second cantilever 400s to improve the overall stability of the structure. The second chip 21 and the second fiber array 4 are aligned, and the coupling efficiency is monitored. Once the coupling efficiency meets the requirements, the two inner side walls of the second cantilever 400 are attached and bonded to the upper surface of the second chip 21, making the second fiber array 4 and the second chip 21 a single unit, thus ensuring the coupling efficiency between the second chip 21 and the second fiber array 4.
[0049] In one optional embodiment, a V-groove is provided on the second base 40, and a second cover plate 41 is bonded and fixed above the second base 40. The second optical fiber 42 is accommodated and fixed between the second base 40 and the cover plate along the V-groove. In actual use, the second optical fiber 42 can be a single-mode optical fiber with a diameter of 125μm.
[0050] It should be noted that, in order to avoid the first fiber array 3 and the second fiber array 4 affecting each other's coupling efficiency, such as... Figure 12 As shown in the enlarged view with the dotted circle in the figure, there is a preset distance between the first cover plate 31 and the second base 40, that is, there is no direct contact between the first fiber array 3 and the second fiber array 4. When the first chip 20 and the second chip 21 are bonded and fixed, the angular deviation between the first chip 20 and the second chip 21 will not affect the coupling efficiency between the first fiber array 3 and the first chip 20, or between the second fiber array 4 and the second chip 21.
[0051] In fact, in the case described in Embodiment 1, where the first chip 20 is directly connected to the circuit board 1 via a bump, and the second chip 21 is interconnected with the circuit board 1 via wire bonding, the second fiber array 4 can also be attached to the upper surface of the second chip 21; if the first chip 20 protrudes beyond the second chip 21 by a preset distance, the first fiber array 3 can also be attached to the attachment platform 200 to improve the overall stability and coupling efficiency of the structure.
[0052] Similar to Embodiment 1, in this embodiment, the first chip 20 can also be a transmitter chip, a receiver chip, or a transceiver chip, and the second chip 21 can also be a transmitter chip, a receiver chip, or a transceiver chip. In practical applications, the packaging structure corresponding to Embodiment 2 has better structural reliability and optical path coupling efficiency, but the manufacturing cost is relatively high. In practical application scenarios, the packaging schemes of the transmitter 6 and the receiver 7 can be flexibly configured. The transmitter 6 and the receiver 7 can simultaneously use the packaging structure of Embodiment 1 or the packaging structure of Embodiment 2, or the transmitter 6 and the receiver 7 can each use the packaging structures of different embodiments. The specific selection should be determined by those skilled in the art based on the actual working conditions.
[0053] Example 2: See Figure 13 Embodiment 2 of the present invention provides a silicon photonics engine packaging method, which prepares the silicon photonics engine packaging structure described in Embodiment 1, specifically including steps 101 to 103.
[0054] Step 101: Fix the first chip 20 onto the circuit board 1 using a flip-chip process and interconnect it with the circuit board 1.
[0055] In one optional embodiment, the first chip 20 is inverted onto the circuit board 1 with its pads facing down, so that the first bumps 201 on the pads of the first chip 20 are soldered onto the corresponding pads of the circuit board 1, thereby achieving interconnection between the first chip 20 and the circuit board 1.
[0056] Step 102: Stack the second chip 21 on top of the first chip 20 and bond it together with the first chip 20, and interconnect the second chip 21 with the circuit board 1.
[0057] Corresponding to Embodiment 1, the second chip 21 is stacked back-to-back on top of the first chip 20 and is fixed together by adhesive. The pad surface of the second chip 21 faces upward. Bonding pads are provided on the circuit board 1 around the first chip 20. The pad surface of the second chip 21 and the bonding pads are interconnected by gold wires 213 to realize the interconnection between the second chip 21 and the circuit board 1.
[0058] Corresponding to Embodiment 2, the two arched feet 210 of the first chip 20 are arranged on both sides of the first chip 20. The lower surface of the two arched feet 210 is a pad surface. The second chip 21 is inverted onto the circuit board 1 with its pad surface facing down, so that the second bumps 211 provided on the pad surface of the second chip 21 are soldered to the corresponding pads on the circuit board 1, thereby realizing the interconnection between the second chip 21 and the circuit board 1. In practical applications, the arched surface of the second chip 21 can be bonded to the upper surface of the first chip 20 or simply attached to it.
[0059] Step 103: Align and couple the first fiber array 3 and the second fiber array 4 with the first chip 20 and the second chip 21 respectively to realize optical signal transmission.
[0060] Corresponding to Example 1 Figure 3 The second fiber array 4 is bonded and fixed above the first fiber array 3 to form a fiber array unit 5. Two sets of 125µm single-mode fibers are placed side-by-side in the fiber array unit 5. The fiber array unit 5 is bonded and fixed to the coupling end face of the dual-layer chip assembly 2, achieving dual-layer alignment coupling by perfectly matching the thickness of the dual-layer chip assembly 2. After being fanned out, the dual-layer single-mode fibers are connected to a 32-channel multi-fiber precision ferrule, enabling interconnection between the device and a standard pluggable optical module. By extending the bottom cover plate of the fiber array unit 5, the end face coupling adhesive completely covers the optical port area, preventing dust from entering and contaminating the optical path. The fiber array unit 5 and the dual-layer chip assembly 2 are bonded and cured with coupling adhesive, which can suppress optical path offset induced by PCBA substrate deformation and avoid coupling efficiency degradation.
[0061] Corresponding to Example 1 Figure 11The two first cantilever arms 300 of the first base 30 are respectively attached to the corresponding overlapping platform 200, so that the first chip 20 and the first fiber array 3 are aligned. After monitoring that the coupling efficiency meets the requirements, the first cantilever arms 300 are glued and fixed to the overlapping platform 200. Similarly, the two second cantilever arms 400 of the second base 40 are respectively attached to the upper surface of the corresponding second chip 21, so that the second chip 21 and the second fiber array 4 are aligned. After monitoring that the coupling efficiency meets the requirements, the second cantilever arms 400 are glued and fixed to the second chip 21.
[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A silicon photonics engine packaging structure, characterized in that, Includes a circuit board (1) and a double-layer chip assembly (2); The dual-layer chip assembly (2) includes a first chip (20) and a second chip (21) stacked together. The first chip (20) is interconnected with the circuit board (1) through a flip-chip process, and the second chip (21) is stacked on top of the first chip (20) and interconnected with the circuit board (1). A first fiber array (3) is fixed on the first chip (20), and a second fiber array (4) is fixed on the second chip (21). The first fiber array (3) is aligned and coupled with the first chip (20), and the second fiber array (4) is aligned and coupled with the second chip (21) to realize optical signal transmission.
2. The silicon photonics engine packaging structure according to claim 1, characterized in that, The first chip (20) is soldered onto the circuit board (1), and the second chip (21) is stacked back to back on top of the first chip (20). The first chip (20) and the second chip (21) are bonded together, and the second chip (21) is interconnected with the circuit board (1) by wire bonding.
3. The silicon photonics engine packaging structure according to claim 2, characterized in that, The first fiber array (3) and the second fiber array (4) are bonded together to form a fiber array unit (5), and the fiber array unit (5) is bonded to the coupling end face of the double-layer chip assembly (2) for optical signal transmission.
4. The silicon photonics engine packaging structure according to claim 1, characterized in that, The first chip (20) is soldered onto the circuit board (1), and the second chip (21) is stacked in an arch shape above the first chip (20), with the two arched feet (210) of the second chip (21) soldered onto the circuit board (1); The first fiber array (3) and the second fiber array (4) are set separately and are aligned and coupled to the first chip (20) and the second chip (21) respectively.
5. The silicon photonics engine packaging structure according to claim 4, characterized in that, On the side coupled to the first fiber array (3), the first chip (20) protrudes beyond the second chip (21) by a predetermined length.
6. The silicon photonics engine packaging structure according to claim 5, characterized in that, Overlapping platforms (200) extend from both ends of the protruding section of the first chip (20). The overlapping platforms (200) are flush with or higher than the upper surface of the first chip (20). The first fiber array (3) overlaps on the overlapping platforms (200).
7. The silicon photonics engine packaging structure according to claim 6, characterized in that, The first fiber array (3) includes a first base (30), and first cantilever (300) extends from both sides of the first base (30). The first cantilever (300) overlaps and is fixed to the upper surface of the overlapping platform (200).
8. The silicon photonics engine packaging structure according to claim 4, characterized in that, The second fiber array (4) includes a second base (40), and second cantilever (400) extends from both sides of the second base (40). The second cantilever (400) overlaps and is fixed to the upper surface of the second chip (21).
9. The silicon photonics engine packaging structure according to any one of claims 1-8, characterized in that, The first chip (20) is a transmitter chip, a receiver chip, or a transceiver chip, and the second chip (21) is a transmitter chip, a receiver chip, or a transceiver chip.
10. A method for packaging a silicon photonics engine, characterized in that, The preparation of the silicon photonic engine packaging structure according to any one of claims 1-9 comprises: The first chip (20) is fixed on the circuit board (1) by flip-chip process and interconnected with the circuit board (1); The second chip (21) is stacked on top of the first chip (20), and the second chip (21) is interconnected with the circuit board (1); The first fiber array (3) and the second fiber array (4) are aligned and coupled with the first chip (20) and the second chip (21) respectively to realize optical signal transmission.