A kind of superintendency fault-tolerant control method and system for series H-bridge inverter of track type wireless power transmission system

Abstract

The application discloses a kind of for the series H bridge inverter of track type wireless electric energy transmission system and system of over-ride fault-tolerant control method, it is related to wireless electric energy transmission technical field, the present application does not need high-speed communication between modules, only phase synchronization is reserved, current loop automatic takeover when fault is cut out is realized, track current fluctuation is small, and recovery is fast;When fault recovery is accessed, the output of recovery unit is gradually established by power ring domination, and the track current is maintained by current loop domination by healthy unit, without impact smooth redistribution;And by parameter design makes full load resistance, light load inductance, satisfies full load range soft switch, reduces loss.

Description

Technical Field

[0001] This invention relates to the field of wireless power transmission technology, and in particular to an override-tolerant fault control method and system for a series H-bridge inverter in a rail-mounted wireless power transmission system. Background Technology

[0002] Rail-mounted wireless power transfer (RWPT) systems are increasingly widely used in rail transit, automated guided vehicles (AGVs), and static / dynamic charging of electric vehicles due to their advantages such as flexible power supply, no mechanical wear, and adaptability to harsh environments. To improve system power supply capacity and redundancy, multiple H-bridge inverters are often connected in series or parallel, with the series structure being more suitable for long-distance rail power supply scenarios with high voltage and low current.

[0003] Existing technologies include control schemes for multi-inverter collaborative power supply. For example, CN112491151B discloses a serial-in parallel-out wireless power transfer system and its control method. In this system, the input terminals of the first wireless power transfer module and the second wireless power transfer module are connected in series and the output terminals are connected in parallel. The input voltage and output current of each module are collected by the transmitter controller, and the output voltage and current parameters are received by wireless communication. A frequency conversion phase-shift control method is used to achieve input voltage equalization and output current equalization. This technical solution effectively reduces the voltage stress of MOSFETs, but it has the following shortcomings: First, the control relies on the wireless communication between the transmitter controller and the receiver controller, as well as the centralized scheduling of the two inverter modules by the transmitter controller. Communication delays or failures may lead to system instability. Second, when an inverter module fails, the system needs to be reassigned control commands by the centralized controller, resulting in slow fault response and the inability to smoothly disconnect and restore the faulty module.

[0004] Another paper, CN121261431A, discloses a three-level contactless power supply control system based on series redundancy. This system features a three-level structure of power correction, voltage transformation, and full-bridge inverter, and is equipped with multiple functional modules, including a collaborative control module, a monitoring and switching module, and a diagnostic recording module. When an abnormal trend is detected, the monitoring and switching module switches the load to the backup module to achieve redundancy and fault tolerance. However, this technical solution relies on additional backup hardware and complex switching logic, resulting in high system costs. The switching process follows a discrete mode of fault detection → decision → physical switching, making it prone to current surges during recovery. Furthermore, the modules require high-level data exchange, such as encrypted communication and remote interaction, placing high demands on communication reliability and making it unsuitable for rail-mounted power supply scenarios with strict requirements for real-time performance and simplicity. Summary of the Invention

[0005] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this section, the abstract and title of the invention. Such simplifications or omissions shall not be used to limit the scope of the present invention.

[0006] In view of the aforementioned existing problems, the present invention is proposed.

[0007] Therefore, the technical problem solved by the present invention is that the existing technology in series multi-inverter wireless power transmission systems lacks a fault-tolerant control method that does not require high-speed communication, does not rely on backup hardware, and can achieve a smooth transition between fault switching and recovery access.

[0008] To solve the above-mentioned technical problems, the present invention introduces an override control mechanism, sets up a current loop and a power loop in parallel in the same inverter, and uses competitive selection to automatically switch the dominant loop.

[0009] A method for override-tolerant fault control of series H-bridge inverters in a rail-mounted wireless power transmission system is characterized by the following: constructing a rail-mounted wireless power transmission system topology with two H-bridge inverters connected in series, each H-bridge inverter having its input connected to a DC bus and its output connected to the rail side via a resonant network, and setting a fault-cutting disconnect switch in each inverter unit; performing equivalent conversion on the secondary load and compensation network to ensure the resonant parameters meet the resistive nature of the equivalent impedance, and configuring a rail compensation capacitor and parallel capacitor to meet the soft-switching conditions across the entire load range; collecting the rail current and the DC-side voltage and current of each inverter, setting a rail current loop and a power loop in each inverter, inputting the output of the rail current loop and the output of the power loop to a selector, and generating a phase-shift control quantity using override control; driving the inverter to output a high-frequency voltage according to the phase-shift control quantity, maintaining the rail current by the current loop of the healthy inverter during fault cut-out, establishing the output by the power loop of the recovery unit during fault recovery, and maintaining the power smooth redistribution by the current loop of the healthy inverter.

[0010] In a preferred embodiment of the present invention, the step of generating the phase-shift control quantity using overdrive control includes: outputting the current loop. and power loop output Simultaneously, the input selector generates the final phase-shift control quantity through the override control selection function. The expression for the final phase-shift control quantity is: .

[0011] As a preferred embodiment of the present invention, the step of making the resonant parameters satisfy the condition that the equivalent impedance is resistive includes: the secondary resonant parameters and the system angular frequency. satisfy:

[0012] in, This is the value of the secondary-side magnetizing inductance after being referred to the primary side. This is the value of the leakage inductance on the secondary side after being converted to the original side. This is the value of the secondary-side compensation capacitor referred back to the primary side; at this point, the impedance of the secondary side is equivalent to that of the primary side. The expression is:

[0013] in, This is the resistance value calculated from the equivalent load on the secondary side to the primary side.

[0014] As a preferred embodiment of the present invention, the configuration of the track compensation capacitor is described below. With parallel capacitor satisfy:

[0015]

[0016] in, For the equivalent inductance of the track, Parallel capacitor The effective value of the voltage on, This is the effective value of the track current. The equivalent impedance under full load conditions; To compensate for the track inductance; and under full load conditions, the overall impedance is resistive, but it becomes inductive when the load decreases, thus achieving soft switching across the entire load range.

[0017] As a preferred embodiment of the present invention, the maintenance of the track current dominated by the current loop of the healthy inverter during fault disconnection includes: when an inverter fails and is disconnected, the output power of the faulty inverter drops to zero, the power loop of the healthy inverter is suppressed due to the reference value returning to zero, the current loop output increases, and after the action of the override selection function, the final phase shift control quantity is dominated by the current loop.

[0018] As a preferred embodiment of the present invention, the control process during fault recovery includes: the healthy inverter has maintained the track current within the error range of a given value; the current loop output amplitude of the recovery unit is less than the power loop output amplitude, and after the selector takes the maximum value, the recovery unit gradually establishes output power under the control of the power loop; the healthy unit continues to maintain track current stability under the control of the current loop.

[0019] As a preferred embodiment of the present invention, the track current loop and the power loop employ controllers designed based on the generalized state averaging method and a small-signal model; wherein the controlled object of the current loop is the effective value of the track current, and the controlled object of the power loop is the DC-side input current or power; the two loops are designed with separate frequency bands.

[0020] In a preferred embodiment of the present invention, during normal operation, fault disconnection and recovery, the power coordination control between modules is achieved through an analog signal line that transmits the DC side power reference value, and the switching sequence of each inverter is kept synchronized through an external phase synchronization signal.

[0021] On the other hand, the present invention also provides an override fault-tolerant control system for series H-bridge inverters in a rail-mounted wireless power transmission system, comprising: two H-bridge inverters, the output terminals of which are connected to the rail side via a resonant network, and the input terminal of each inverter is connected to a DC bus; a fault disconnect switch set for each inverter unit; a current detection unit for collecting rail current; a DC side detection unit for collecting DC side voltage and DC side current of each inverter; and a controller within each inverter, the controller comprising: a rail current loop module, which generates a first phase shift angle based on the difference between the rail current setpoint and the feedback value. The power loop module generates a second phase shift angle based on the difference between the local power feedback value and the reference power value. Override selector, used to select and The larger value in the range is used as the final phase-shift control value. The PWM drive module generates inverter bridge switching pulses based on the final phase shift control quantity. During fault disconnection, the current loop module of the healthy inverter dominates, while during fault recovery, the power loop module of the recovery unit dominates, and the current loop module of the healthy inverter remains dominant.

[0022] The beneficial effects of this invention are as follows: This invention eliminates the need for high-speed communication between modules, retaining only phase synchronization and one analog signal line, enabling the current loop to automatically take over during fault disconnection, resulting in small track current fluctuations and rapid recovery; during fault recovery and reconnection, the recovery unit gradually establishes output under the guidance of the power loop, while the healthy unit maintains track current under the guidance of the current loop, achieving smooth redistribution without impact; and through parameter design, it achieves resistive characteristics under full load and inductive characteristics under light load, satisfying soft switching across the entire load range and reducing losses.

[0023] The control structure of this invention is simple and easy to implement in a digital controller. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a system topology diagram containing a front-end rectifier unit in an embodiment of the present invention; Figure 2 This is the equivalent circuit diagram of the secondary receiving end in an embodiment of the present invention; Figure 3 This is a connection diagram of the equivalent inductance on the track side and the equivalent load model in an embodiment of the present invention; Figure 4 This is a block diagram of the dual-loop override control during normal operation in an embodiment of the present invention; Figure 5 This is a block diagram of the dominant control of the current loop of the healthy inverter during fault cut-off in an embodiment of the present invention; Figure 6 This is a block diagram of the control of a healthy inverter when a faulty unit is restored to access in an embodiment of the present invention; Figure 7 This is a block diagram of the dominant control of the inverter power loop when the faulty unit is restored to the network in an embodiment of the present invention. Figure 8 This is a diagram showing the changes in track current and power during the fault cut-out and recovery access process in an embodiment of the present invention; Figure 9 This is a comparison chart of theoretical calculation and scanning simulation of the current-controlled object in an embodiment of the present invention; Figure 10 This is a comparison chart of theoretical calculation and scanning simulation of the power control object in an embodiment of the present invention; Figure 11 This is a schematic diagram of an override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system. Detailed Implementation

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort should fall within the scope of protection of this invention.

[0027] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0028] Example 1

[0029] like Figure 11 As shown, an override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transfer system includes: S100: Construct a rail-mounted wireless power transmission system topology with two H-bridge inverters connected in series for power supply. The input of each H-bridge inverter is connected to the DC bus, and the output is connected to the rail side via a resonant network. A fault disconnect switch is set in each inverter unit.

[0030] S101: The main circuit for constructing a rail-mounted wireless power transmission system powered by two inverters connected in series.

[0031] In this embodiment of the invention, two H-bridge inverters are used as the front-end high-frequency power supply unit. The input terminal of each inverter is connected to the DC bus, and the output terminal is connected to the rail side after passing through a resonant network. The two inverters are connected in series on the rail side to form a cooperative power supply structure for the load, such as... Figure 1 As shown.

[0032] Specifically, such as Figure 1 As shown, the complete connection relationship of AC input, front-end rectifier unit, DC bus detection quantity and two H-bridge inverters is further illustrated based on the main circuit of the system.

[0033] Three-phase AC input terminals include And neutral point N, the three-phase AC power is connected to two Vienna rectifiers respectively. The output terminal of the upper Vienna rectifier is connected to the DC bus of the first inverter, and its DC bus voltage is... The bus capacitance is The DC input current of the first inverter is marked as... The H-bridge input current is marked as The first H-bridge was built by , , , Composition, output voltage marked as . Through series resonant inductor Series resonant capacitor Parallel compensation capacitor connected afterwards Then, it is connected to the track side via a 1:1 isolation transformer and fault disconnect switch S1.

[0034] The output of the Vienna rectifier below is connected to the DC bus of the second inverter, and the DC bus voltage is... The bus capacitance is The DC-side input current of the second inverter is marked as follows: The H-bridge input current is marked as The second H-bridge is... , , , Composition, output voltage marked as . Through series resonant inductor Series resonant capacitor Parallel compensation capacitor connected afterwards Then, it is connected to the track side via a 1:1 isolation transformer and fault disconnect switch S2.

[0035] The first and second inverters are connected in series on the track side via S1 and S2. A series compensation capacitor is installed on the track side. Equivalent inductance of track The track current is marked as The first receiver on the secondary side uses mutual inductance. Coupled with the track inductance, the secondary coil is The compensation capacitor is The load is The nth receiver uses mutual inductance. Coupled with the track inductance, the secondary coil is The compensation capacitor is The load is .

[0036] Figure 1 In , The input current collected by the DC-side detection unit is used to calculate the DC-side input power of the two inverters; This is the track current detection quantity, used for track constant current control; , This is the DC bus voltage detection quantity for both inverters, used for DC side status monitoring and power calculation.

[0037] S102: A fault disconnect switch is set at the corresponding position of each inverter unit. When a fault occurs in an inverter, the faulty inverter is disconnected from the series system and the healthy inverter continues to maintain the rail power supply.

[0038] The fault disconnect switch is located in the series connection section of the two inverters via the resonant cavity output. Fault judgment criteria include abnormal DC-side voltage (overvoltage or undervoltage), IGBT overtemperature, or DC-side current overcurrent or undercurrent. In a preferred embodiment, the specific fault thresholds and operating logic are as follows: the DC-side overvoltage threshold is set to 800V, the undervoltage threshold is set to 600V, and the corresponding debouncing time (to prevent false alarms) is set to 50ms; the IGBT overtemperature threshold is set to 90℃, and no debouncing time is set for this fault; it responds immediately upon triggering. Once any fault is confirmed, the system immediately blocks the drive signal of the corresponding inverter, simultaneously controls the upstream three-phase input circuit breaker to open immediately, and disconnects the faulty module from the series circuit via the fault disconnect switch (which can be a contactor or solid-state relay).

[0039] It should be noted that the mechanical action of the relay has an inherent delay. During this delay, a small amount of energy may flow back into the faulty inverter. However, since the delay is extremely short and the energy is limited, this backflow does not affect the normal operation of the healthy inverter or the system safety.

[0040] S200: The secondary load and compensation network are equivalently converted to ensure that the resonant parameters meet the requirement that the equivalent impedance is resistive, and the track compensation capacitor and parallel capacitor are configured to meet the soft switching conditions for the entire load range.

[0041] S201: Perform primary-side equivalent conversion on the receiver load.

[0042] Based on single-unit analysis, the inverter bridge output section is equivalent to a duty cycle of... Square wave voltage source The track current is denoted as ;Transfer the output load of the secondary stage Before being referred to the rectifier bridge, it is denoted as This simplifies the analysis process.

[0043] Combining the transformer mutual inductance model and the T-type model conversion method, all secondary circuits are converted to the primary side, where... For the secondary side magnetizing inductance, For the calculated leakage inductance, compensation capacitance, and equivalent load, such as Figure 2 and Figure 3 As shown. Among them, Figure 2 Detailed equivalent circuit connection instructions for the secondary receiver are provided.

[0044] like Figure 2 As shown, the inverter output is equivalent to an AC voltage source. . The positive terminals are connected in series with a resonant inductor. and series resonant capacitor Then connect a parallel compensation capacitor. The upper part. The lower end is connected back The negative terminal is used to form a parallel compensation branch on the inverter side.

[0045] The equivalent impedance is shown in the blue box on the right. In this equivalent impedance, the track compensation capacitor Set in the upper branch, track current The flow proceeds from left to right along the upper branch. Secondary side compensation capacitor. Located on the right side of the upper branch, its right end is connected to the upper end of the equivalent load branch. Magnetizing inductor. It connects the upper and lower branches. The lower branch includes the track inductance conversion term. - and secondary side leakage Equivalent load resistance It connects the upper and lower nodes on the right end.

[0046] Should Figure 2 This is used to illustrate that the nth secondary receiving end, after being transformed by the mutual inductance model and compensation network, appears on the original side as... , , , The equivalent impedance formed by the combined components. The input terminal is... The output response is the track current. and equivalent load branch current.

[0047] An equivalent model was established based on a single inverter: the track current is denoted as... Secondary-side downstream load Before being referred to the rectifier bridge, it is denoted as ; in the resonant cavity and The design is based on the resonance relationship and the actual withstand voltage of the capacitor; the secondary side is calculated using the mutual inductance model and the T-type model. For secondary excitation inductance, and This refers to the calculated leakage inductance and compensation capacitor. Among them, It refers to a general term and ; It refers to a general term and .

[0048] like Figure 3 As shown, the inverter output equivalent voltage source The positive terminals are connected in series with a resonant inductor. and series resonant capacitor Then a parallel compensation capacitor is connected. The upper part. The lower end is connected back The negative end.

[0049] The blue box on the right shows the further simplified equivalent impedance of the track side. Track compensation capacitors are installed on the upper branch line. Track current The flow proceeds from left to right through this branch. An equivalent inductance for the track is incorporated into the lower branch. Connect the equivalent load impedance between the upper and lower nodes on the right end. . Figure 3 middle This represents the equivalent inductance branch obtained after equivalent processing of track compensation capacitors and track inductance, used to describe the dominant inductive component after track compensation.

[0050] Figure 3 This is used to illustrate that, after the secondary load is reduced and further simplified, the system can be considered as consisting of the inverter series resonant branch, the parallel compensation branch, and the track compensation capacitor. Track inductor and equivalent load The single-input equivalent circuit formed by these two components.

[0051] in, Indicates instantaneous value, Indicates a valid value.

[0052] Furthermore, let the switching frequency be denoted as Corresponding angular frequency The expression for the equivalent impedance at this time is:

[0053] in This indicates a parallel connection. The secondary resonant parameters and the system angular frequency satisfy the following relationship:

[0054] The equivalent impedance is resistive and can be simplified to:

[0055] in, This is the resistance value calculated from the equivalent load on the secondary side to the primary side.

[0056] In subsequent control strategy analysis and small-signal modeling, the secondary side of the system is simplified as a resistive load.

[0057] S202: Rail inductor To maintain a constant value, compensation capacitors can be configured appropriately. The track circuit is compensated with a suitable equivalent inductance to ensure that the system can control the track current through closed-loop control within the range from light load to full load. Track its valid value For a duty cycle of Square wave voltage source After being filtered by series resonant filtering, it is applied to the parallel capacitor. The effective value of the voltage on is:

[0058] Considering actual losses and control margins, the duty cycle under full load conditions is taken as follows: ( <1), the corresponding equivalent impedance is denoted as At this time, the compensation capacitor It can be derived from the following formula:

[0059] Note the compensation capacitor at this time. The track inductance after track inductance compensation is: ,but It can be represented as:

[0060] Furthermore, parallel capacitors This is used to limit the amplitude of the resonant cavity current, thereby reducing device current stress and system losses. Simultaneously, the equivalent impedance of the subsequent stage of the resonant cavity must be ensured during parameter design. It exhibits inductive properties to meet the conditions for soft switching across the entire load range. The full-load condition is taken as the most unfavorable condition for analysis. When the following equation is satisfied, the impedance The maximum value corresponds to the minimum resonant cavity current.

[0061] At this point, the overall impedance under full load conditions It exhibits resistivity, and when the load decreases, the overall impedance becomes inductive, satisfying the soft-switching requirements across the entire load range.

[0062] When the load decreases, the equivalent resistance R e The increase causes the impedance angle of the parallel network to change from 0 to a positive value, making the whole network inductive, which is beneficial for the inverter switching transistors to achieve zero-voltage turn-on.

[0063] S300: Collects track current and DC-side voltage and DC-side current of each inverter, sets up track current loop and power loop in each inverter, inputs the output of track current loop and power loop to selector, and uses override control to generate phase shift control quantity.

[0064] S301: Collects track current and DC-side status variables of each inverter and constructs a dual closed loop.

[0065] Collect track current and DC-side status parameters of each inverter. Collect track current separately. DC side voltage of each inverter and DC side current Based on this, the DC-side input power of each inverter is calculated. The track current serves as the feedback quantity for the system's constant current control, while the DC-side power serves as the feedback quantity for power coordination between modules. Simultaneously, each inverter incorporates a current loop and a power loop. The inputs to both closed loops are the track current setpoint, track current feedback value, local power feedback value, and reference power value; the output is the current loop output. and power loop output .

[0066] The function of collecting track current is implemented by the current detection unit, and the function of collecting DC-side voltage and current of each inverter is implemented by the DC-side detection unit. Each inverter is equipped with a controller, which includes: track current loop module (referred to as current loop), power loop module (referred to as power loop), override selector and PWM drive module.

[0067] To obtain the power loop reference value without relying on complex digital communication, this embodiment uses a separate analog signal line to connect the controllers of the two inverters. Each inverter transmits its locally measured DC-side power to the other inverter via this signal line in the form of analog voltage (0~10V) or current (4~20mA). The receiving end acquires the power reference value through an ADC. This analog signal line transmits only one signal, does not constitute real-time communication with higher layers, and is low in cost and highly reliable. When a fault is switched off, the power reference value signal output by the faulty inverter drops to zero. This signal is transmitted to the healthy inverter via the analog signal line, causing the power loop reference power value of the healthy inverter to drop to zero as well. The power loop output is suppressed to near zero under limiting. Meanwhile, the current loop of the healthy inverter outputs a larger phase shift angle due to the increased track current error. via overdrive selector After the action, the final phase-shift control quantity is dominated by the current loop. This process does not require switching the reference value of the power loop; it relies solely on the override competition mechanism to automatically complete the transfer of the dominant loop.

[0068] Specifically, to avoid competition between the two loops in the same frequency band, the current loop is designed as a fast loop and the power loop as a slow loop: at a switching frequency of 20kHz and a control period of 50μs, the cutoff frequency of the current loop is designed to be about 1kHz and the cutoff frequency of the power loop is designed to be about 100Hz, with a bandwidth difference of about 10 times. This allows the current loop to be responsible for quickly maintaining the track current, while the power loop is only used for slowly adjusting the power distribution.

[0069] Furthermore, non-dominant loops not selected by the override selector do not exit the calculation. The integral stage is processed using an integral limiting method to keep the output of the non-dominant loop near the final phase shift angle, avoiding the long-term accumulation of large integral quantities. When the loop becomes the dominant loop again, the output will not change abruptly due to integral saturation release.

[0070] S302: Generates the final phase-shifting control quantity based on the override control selection mechanism.

[0071] The outputs of the current loop and power loop are simultaneously input to the override selector, and the final phase-shift control quantity is generated through the override control selection function. , can be represented as:

[0072] in, The final phase shift angle command outputs the phase shift control value for the inverter's H-bridge. To prevent repeated switching of the dominant loop due to sampling noise or transient disturbances when the two loop outputs are close, the override selector employs a maximum value selection method with hysteresis and continuous acknowledgment time. Specifically, let the hysteresis threshold be... Confirmation time is Currently, when dominated by the current loop, only And continue Only after this is switching to power loop dominance allowed; and vice versa; when At the same time, the dominant cycle of the previous cycle remains unchanged.

[0073] Meanwhile, the output (comparison result) of the override selector is not directly applied to the H-bridge as the final phase shift angle, but is instead limited by amplitude and rate of change before becoming the final output. Even if the dominant ring switches, It also changes continuously according to the set slope to avoid track current surges during restoration or switching.

[0074] like Figure 4 As shown in the control block diagram, each inverter has a track current loop and a power loop, which share the same phase-shift control output.

[0075] Track current reference value Connect to the positive input terminal of the comparison circuit above, and the track current feedback value. The negative input of this comparison circuit is connected, and the difference between the two signals is used to obtain the track current error signal. This error signal is then input to the upper PI controller, which outputs the first phase shift angle command. .

[0076] Power reference value Connect the positive input terminal of the comparison circuit below to the DC-side power feedback value of the device. The negative input of this comparison circuit is connected, and the power error signal is obtained by subtracting the two inputs. This error signal is then input to the PI controller below, which outputs the second phase shift angle command. .

[0077] First phase shift angle Second phase shift angle Simultaneously input the Max selector. The Max selector compares the magnitudes of the two phase shift angle commands and outputs the larger value as the final phase shift control quantity. Final phase shift control quantity Simultaneously acting on the current object transfer function and power object transfer function .in, The output is the track current. And feed it back to the current loop comparison terminal; The output is DC-side power And feed it back to the power loop comparator.

[0078] therefore, Figure 4 The input signals include , , , The output signal is the final phase shift angle φ and the controlled output. , The current loop and power loop compete for override via a Max selector, with the control loop having the larger output ultimately dominating the H-bridge phase-shift control.

[0079] in, This is a reference value for track current. For the DC-side power of another inverter, This is the track current feedback value. This is the DC power of the machine. and These are the phase angles of the current loop and power loop outputs, respectively. This is the final phase shift angle (i.e., the inner phase shift angle). Let be the transfer function from track current to phase shift angle. This is the transfer function from DC power to phase shift angle.

[0080] The above operations are used to enable track current control and power coordination control to share the same manipulated quantity, and to automatically switch the dominant control target according to the system status, without fixing the master-slave control relationship. The final phase-shift control quantity is then sent to the PWM drive module to generate inverter bridge switching pulses, causing the inverter to output a corresponding high-frequency AC voltage and transmit power to the track side through the resonant network.

[0081] In summary, although the override selector is a restricted switching nonlinear element, the embodiments of this invention allow only one control loop to act as the dominant loop at any given time. It can be divided into a current loop dominant subsystem and a power loop dominant subsystem. During design, the phase margin of each subsystem is guaranteed to be no less than 45° and the gain margin no less than 6 dB. Combined with bandwidth separation, hysteresis confirmation, phase shift rate limitation, and non-dominant loop anti-integral saturation treatment, high-frequency switching and abrupt phase shift angle changes can be effectively avoided, ensuring that the nonlinearity introduced by the override selector does not compromise the stability of the engineering operation.

[0082] S400: Drives the inverter to output high-frequency voltage according to the phase shift control quantity. When the fault is cut off, the current loop of the healthy inverter dominates to maintain the rail current. When the fault is recovered, the power loop of the recovery unit dominates to establish the output. The current loop of the healthy inverter maintains the dominant power smooth redistribution.

[0083] S401: Fault-tolerant control analysis during normal operation, fault handoff, and recovery access.

[0084] When one of the inverters fails and is disconnected, the output power of the faulty inverter rapidly drops to zero. The power loop output of the healthy inverter is suppressed, while the track current loop increases its output to maintain the track current. After the override selection function is applied, the phase shift control is automatically dominated by the current loop. The control dominance transfer process during fault disconnection is as follows: Figure 5 As shown, the Figure 5 This indicates the control dominance of the healthy inverter after one of the inverters fails and exits the system.

[0085] Specifically, track current reference value With track current feedback value The input is fed into the comparison circuit above, and the comparison result is fed into the PI controller above, which outputs the current loop phase shift angle. After a fault is tripped, the healthy inverter needs to independently maintain the rail current, therefore the current loop output... Increase the value and enter the Max selector. Below, in the power loop, the power reference value is... DC-side power feedback value Entering the comparison phase. Because the output power of the faulty inverter drops to zero, the reference relationship of the power loop of the healthy inverter changes, and the power loop output is suppressed. Figure 5 The dashed box in the middle indicates that the power loop is in a non-dominant state, and its output... It is restricted to a position close to 0.

[0086] and Simultaneously input the Max selector, because... > The selector outputs the final phase shift angle. = Final phase shift angle enter and The orbital currents were obtained respectively. and DC side power .in, Continue to feed back to the current loop, The feedback continues to the power loop. Figure 5 This indicates that there is no need to reconfigure the controller when a fault is switched out, and the healthy inverter automatically takes over control of the current loop through the override selection mechanism, thereby maintaining the stability of the rail current.

[0087] Taking the failure of inverter B as an example: when the DC power of B rapidly drops to zero, the reference power in the power loop of inverter A... As the current decreases, its power loop output is suppressed to near zero under limiting, and inverter A automatically switches to current loop dominance and independently maintains the rail current. Thus, without relying on communication for control reconfiguration, the system can smoothly transition from dual-unit collaborative power supply to single-unit support operation.

[0088] Furthermore, when the faulty unit is restored to connection, the healthy inverter has maintained the rail current near the given value. Therefore, the current loop output of the restoration unit is relatively small, while the large power deviation results in a large power loop output. After the selector's action, the restoration unit first gradually builds up its output power, primarily driven by the power loop. Figure 7 As shown, the Figure 7 This indicates the initial stage of the restored inverter's control hierarchy.

[0089] Specifically, track current reference value With track current feedback value Input the comparison circuit above. Since the track current has been maintained near the given value by the healthy inverter at this point, the current error of the restored inverter is small, therefore the phase shift angle of the PI output in the upper current loop is... Smaller Figure 7 The dashed line indicates that the current loop is in a non-dominant state, with its output close to zero. Power reference value. Restore the DC-side power feedback value of the inverter Enter the comparison step below. Because the output power of the recovery inverter is low and the power error is large when it is first connected, the phase shift angle of the PI output in the power loop below is... Larger. Input Max Selector. Current Loop Output. With power loop output Simultaneously input the Max selector, because... > The selector outputs the final phase shift angle. = Final phase shift angle Acting on and This allows the inverter to gradually build up its output current and DC-side power.

[0090] Figure 7 This indicates that the power loop dominates the initial connection of the recovery unit, with the output power gradually increasing from zero to avoid track current surges caused by sudden phase shifts during the recovery connection.

[0091] Meanwhile, the healthy cell continues to be dominated by the current loop, such as Figure 6 As shown, the Figure 6 This indicates the control status of the original healthy inverter during the process of restoring the faulty unit to its connection.

[0092] Specifically, track current reference value With track current feedback value The error signal from the input comparison circuit above is input to the PI controller above, which outputs a current loop phase shift angle. Since the healthy inverter maintained stable rail current during the fault, it continues to primarily handle rail current stabilization during the initial recovery phase, maintaining effective current loop output. Below, in the power loop, the power reference value... With the DC side power feedback value of the machine Input comparison stage. Because the recovery unit has not yet built up sufficient power, the power loop output of the healthy inverter remains suppressed. Figure 6 The dashed line in the middle indicates that the power loop is in a non-dominant state, and its output... Approaching 0. Current loop output. With power loop output Simultaneously input the Max selector, because... big Final phase shift angle The final phase shift angle is still determined by the current loop output. Acting on and Each generates track current and DC side power This forms a feedback loop.

[0093] Figure 6 This means that when the faulty unit is restored to the grid, the healthy inverter will not immediately exit regulation, but will continue to be dominated by the current loop to ensure that the rail current does not experience a significant impact during the recovery process.

[0094] That is, when a faulty unit is restored to the grid, the system must meet two requirements: no impact on the track current and the restoration unit gradually assuming power. For healthy inverter A, since the track current has been maintained at a given value and the restoration unit has not yet built up sufficient power, the power loop of A is still suppressed, and therefore the current loop continues to dominate.

[0095] During normal operation, fault handoff, and recovery access, the system achieves phase synchronization through an external synchronization signal. Furthermore, this invention only retains the phase synchronization condition and does not require continuous real-time communication between higher layers of modules to exchange control commands, thus achieving automatic transfer of control and smooth power redistribution between modules. The overall mechanism is as follows: Figure 8 As shown, the Figure 8 This diagram illustrates typical operating waveforms of the system during fault disconnection, recovery, and entry into steady state. The horizontal axis represents the time progression direction, and the vertical axis represents the track current. and the output power of the two inverters , ,exist Figure 8 The intermediate representation is , .

[0096] Specifically, during the dual-machine coordination phase, both inverters jointly supply power to the track, and the track current... Power and The power distribution is basically even. At the moment of fault exit, the power of the faulty inverter rapidly drops to zero. Figure 8 The power curve of the faulty unit rapidly decreases from its original steady-state value. At this time, the healthy unit is dominated by the current loop, and its power curve rises to compensate for the power gap after the faulty unit exits the circuit. (Rail current) The drop was brief, and the value subsequently recovered to near the given value under the influence of the current loop in the healthy unit.

[0097] During the single-unit support current phase, the output power of the faulty unit remains zero, the healthy unit undertakes all power supply tasks, and the track current... Maintaining stability. Upon restoration, the faulty unit reconnects to the system. The restored unit initially operates under power loop dominance, with its output power gradually increasing from zero; the healthy unit's power decreases accordingly, but it still maintains stable track current through the current loop. During the gradual power sharing phase, the power outputs of the two inverters gradually converge. After reaching steady state, the system returns to a dual-unit coordinated power supply state, and the track current... By maintaining a value close to the given value, the power of the two inverters is re-evenly distributed. Figure 8 The dashed and vertical lines represent the state transition moments of fault exit recovery and entry into steady state, respectively. There is no electrical connection between the curves; they are only used to represent the signal change trends at different operating stages.

[0098] When the system is running normally, the two units work together to supply power, and the track current is stable near the given value. After a fault occurs, the output power of the faulty unit is quickly withdrawn, and the healthy unit smoothly takes over under the guidance of the current loop. The track current only fluctuates slightly for a short time and then recovers quickly. When the faulty unit is reconnected, its output power gradually increases under the action of the power loop, and the output power of the healthy unit drops accordingly, realizing a smooth redistribution of power and finally restoring the dual-unit collaborative operation state.

[0099] From a control perspective, the suppression of the power loop and the automatic takeover of the current loop during a fault are determined by a combination of competition mechanisms and phase shift limiting. This characteristic gives the system strong dynamic fault tolerance in the event of a sudden single-unit failure.

[0100] In this embodiment, the phase synchronization signal uses a square wave clock transmitted through a single signal line, and the frequency is consistent with the switching frequency.

[0101] S402: To analyze the dynamic characteristics of the system under the proposed control strategy, this embodiment of the invention takes a single H-bridge inverter as the research object and establishes a state-space average model and a small-signal model based on switching functions. Since the two inverters have the same topology and operate synchronously, the single-machine model can reflect the main control dynamic characteristics of the system.

[0102] Although current regulation and power regulation operate on the same topology and both use phase shift angles as control inputs, the response speeds of track current and DC-side power differ significantly, exhibiting different time scales. Therefore, this embodiment of the invention extracts the current control object and the power control object separately based on a unified small-signal model, and employs a frequency band separation method for hierarchical design to reduce the coupling between the two control objectives.

[0103] S403: Since the main state variables of a resonant network are AC quantities, the traditional state averaging method is difficult to effectively describe its dynamic characteristics. Therefore, this embodiment of the invention adopts the generalized state averaging method, using the fundamental Fourier coefficients of the state variables as equivalent state variables and ignoring higher-order harmonic components, thereby establishing a unified state-space averaging model.

[0104] In order to facilitate small-signal modeling, the phase-shift control quantity is... Convert to equivalent duty cycle The two satisfy a linear relationship: ,in, , Subsequent small signal analysis will all use... As a control input variable, the actual controller output... The correspondence can then be implicitly implied through the above relationships.

[0105] Select inductor current , and capacitor voltage , As state variables, the state equation of the resonant converter can be obtained as follows:

[0106] in For the switching function of the H-bridge, the Fourier coefficients of the l=0 and 1=1 terms are:

[0107] For phase-shift control within the H-bridge, the DC components of the inductor current and capacitor voltage remain zero. Therefore, the DC component of the state variable x is ignored, and we take... In this equation, the superscripts 0 and 1 represent the Fourier coefficients, with 0 representing the DC component and 1 representing the fundamental component; 1I and 1R represent the imaginary and real parts of the fundamental wave, respectively. It should be noted that the DC component is 0 here and can be ignored. This method is based on the fundamental wave analysis method, so higher harmonic components can be ignored.

[0108] Based on the differential property of Fourier coefficients, the state-space average model of the converter is:

[0109]

[0110] In the formula:

[0111] in, Let be the switching angular frequency, and I be the identity matrix.

[0112]

[0113] For steady-state input Steady-state operating point: It can be obtained from the equation AX+B=0.

[0114] S404: At the steady-state operating point, the control variable is... Apply a small signal perturbation, namely:

[0115] State variables of the converter This will deviate from the steady-state operating point ,Right now:

[0116] Based on this, linearization is performed, and the small-signal model of this control is obtained as follows:

[0117] In the formula,

[0118]

[0119]

[0120] Transform to Domain, obtain:

[0121] The transfer function of the small-signal model of the current loop system can be obtained as follows:

[0122] Record duty cycle to rail current The transfer functions of the real and imaginary parts are respectively and Furthermore, in the average model, the inductor current can be obtained by the following formula:

[0123] Therefore, duty cycle to rail current transfer function It can be represented as:

[0124] in, Inductance at steady-state operating point The real part of the fundamental component of the current is the steady-state value, corresponding to the DC operating point in the small-signal model. Inductance at steady-state operating point The imaginary part (steady-state value) of the fundamental component of the current. Duty cycle to rail current The real part of the transfer function reflects the relationship between the real part perturbation and the duty cycle perturbation. Duty cycle to rail current The imaginary component of the transfer function reflects the relationship between the imaginary perturbation and the duty cycle perturbation.

[0125] S405: Due to bus voltage This can be approximated as constant; the power loop's regulation of the DC-side power can be equivalently transformed into regulation of the DC-side current. Based on the same small-signal model, the DC-side current is further... The variable is selected as the output variable, thus establishing a small-signal model under power loop control. The ripple is negligible compared to the DC component, as can be seen from the property of the product of Fourier coefficients:

[0126] Applying a small signal perturbation at the steady-state operating point yields:

[0127] Power loop control in Similarly, the small-signal model of the domain can be written as:

[0128] In the formula,

[0129]

[0130]

[0131]

[0132] From this, the duty cycle can be obtained. Current before H-bridge transfer function However, there is a parallel connection between the bus capacitance and the equivalent load between the DC side and the H-bridge, thus the final duty cycle... to actual DC side current transfer function for:

[0133] in, This is the transfer function of the parallel impedance link formed by the DC bus capacitance and the equivalent load. Since there is no series inductor on the DC bus side of this system, This process degenerates into:

[0134] in, For DC bus capacitors, The equivalent load resistance varies with operating conditions. In this control system, the time constant of this filtering loop is much smaller than the response time of the current loop and the power loop, so its impact on the controller design can be ignored.

[0135] Example 2

[0136] To further verify the beneficial effects of the present invention, an experimental platform was built in this embodiment of the invention to conduct multi-condition tests, including the following steps: First, a track-mounted wireless power transfer experimental platform with the same topology and parameters as described above was built, and corresponding power devices, compensation networks, controllers, sensors, and fault disconnection units were configured.

[0137] The parameters for the series system are as follows: Table 1 Parameters of the Series System

[0138] Furthermore, steady-state operation experiments, load switching experiments, fault cut-out experiments, and fault recovery access experiments were conducted to test the changes in track current, bridge arm output voltage, and DC side current of the two inverters, respectively, in order to verify the effectiveness of the proposed method under different operating conditions.

[0139] like Figure 9 As shown, the Figure 9 This is a comparison of the frequency domain characteristics of the current-controlled object, used to verify the transmission relationship from the phase-shift control quantity to the track current in the small-signal model. Figure 9 The upper part is the amplitude-frequency response graph, with the horizontal axis representing frequency in Hz and the vertical axis representing amplitude in dB. Figure 9 The lower half is the phase-frequency response diagram. The horizontal axis is also the frequency, in Hz, and the vertical axis is the phase, in deg.

[0140] Figure 9 The solid blue line represents the theoretical calculation results, and the dashed red line represents the scanning simulation results. The input is the small-signal disturbance of the inverter phase-shift control quantity, and the output is the small-signal response of the track current It. By comparing the solid blue line and the dashed red line, it can be seen that in the low-to-mid frequency range, the theoretical calculation results and the scanning simulation results are basically consistent, indicating that the established small-signal model of the current-controlled object can reflect the main dynamic characteristics of the actual system.

[0141] It should be noted that, Figure 9 The data curves represent the amplitude and phase responses of the theoretical and simulation models in the frequency domain, and do not represent actual electrical wire connections.

[0142] like Figure 10 As shown, the Figure 10 This is a comparison chart of the frequency domain characteristics of the power control object, used to verify the transfer relationship from the phase-shift control quantity to the DC-side input current or DC-side power in the small-signal model. Figure 10 The upper part is the amplitude-frequency response graph, with the horizontal axis representing frequency in Hz and the vertical axis representing amplitude in dB. Figure 10 The lower half is the phase-frequency response diagram, with the horizontal axis representing frequency in Hz and the vertical axis representing phase in deg.

[0143] Figure 10The solid blue line represents the theoretical calculation results, and the dashed red line represents the scanning simulation results. The input is a small-signal disturbance of the inverter's phase-shift control, and the output is a small-signal response of the DC-side input current or equivalent DC-side power. Since the DC bus voltage is approximately constant, DC-side power regulation can be equivalent to DC-side current regulation. Figure 10 It can be used to illustrate the accuracy of the power loop control object model, and the degree of closeness between the blue solid line and the red dashed line is used to characterize the consistency between the theoretical model and the scanning simulation model.

[0144] The method also includes one or more processors and memory.

[0145] The memory is used to store operable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations, including the flow of an override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transfer system according to the foregoing embodiments, particularly... Figure 11 The flowchart of the method is shown.

[0146] Other aspects disclosed in the embodiments of the present invention also propose a computer-readable medium for storing software including instructions executable by one or more computers, which, upon execution, cause the one or more computers to perform operations including the flow of an override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transfer system according to the foregoing embodiments, particularly... Figure 11 The flowchart of the method is shown.

[0147] It should be recognized that embodiments of the present invention may be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium.

[0148] The method can be implemented using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program in the computer program, wherein the storage medium is configured such that the computer operates in a specific and predefined manner.

[0149] Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system; however, if required, the program can be implemented in assembly or machine language.

[0150] In any case, the language can be either compiled or interpreted.

[0151] Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit.

[0152] The processes described herein (or variations and / or combinations thereof) can be executed under the control of one or more computer systems configured with executable instructions, and can be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.

[0153] Furthermore, the method can be implemented in any suitable computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices.

[0154] Various aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether portable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein.

[0155] Furthermore, machine-readable code, or parts thereof, can be transmitted via wired or wireless networks.

[0156] When such media includes instructions or programs that combine with a microprocessor or other data processor to implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media.

[0157] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for override-tolerant fault control of a series H-bridge inverter in a rail-mounted wireless power transmission system, characterized in that: include: Construct a rail-mounted wireless power transmission system topology with two H-bridge inverters connected in series for power supply. The input terminal of each H-bridge inverter is connected to the DC bus, and the output terminal is connected to the rail side via a resonant network. A fault disconnect switch is set in each inverter unit. The secondary load and compensation network are equivalently converted to ensure that the resonant parameters meet the requirement that the equivalent impedance is resistive. The track compensation capacitor and parallel capacitor are configured to meet the soft switching condition for the entire load range. Collect the track current and the DC side voltage and DC side current of each inverter. Set up a track current loop and a power loop in each inverter. Input the output of the track current loop and the output of the power loop to the selector. Use override control to generate phase shift control quantity. The inverter outputs a high-frequency voltage based on the phase shift control quantity. When a fault is disconnected, the current loop of the healthy inverter dominates to maintain the rail current. When the fault is recovered, the power loop of the recovery unit dominates to establish the output. The current loop of the healthy inverter maintains the dominant power smooth redistribution. The generation of phase-shift control quantities using overdrive control includes: Output the current loop and power loop output Simultaneously, the input selector generates the final phase-shift control quantity through the override control selection function. The expression for the final phase-shift control quantity is: in, This is the overdrive selection function, used to select... and The larger value in the range is used as the final phase-shift control value. .

2. The override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in claim 1, characterized in that: The method of making the resonant parameters satisfy the equivalent impedance being resistive includes: Secondary side resonant parameters and system angular frequency satisfy: in, This is the value of the secondary-side magnetizing inductance after being referred to the primary side. This is the value of the leakage inductance on the secondary side after being converted to the original side. This is the value of the secondary-side compensation capacitor after being referred back to the primary side; At this point, the impedance of the secondary side is equivalent to that of the primary side. The expression is: in, This is the resistance value calculated from the equivalent load on the secondary side to the primary side.

3. The override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in claim 2, characterized in that: The configuration of track compensation capacitor With parallel capacitor The following relationship must be satisfied: in, To compensate for the track inductance; The track compensation capacitor is determined by the following formula. : in, For the equivalent inductance of the track, Parallel capacitor The effective value of the voltage on, This is the effective value of the track current. The equivalent impedance under full load conditions; Furthermore, under full load conditions, the overall impedance is resistive, but it becomes inductive when the load decreases, thus achieving soft switching across the entire load range.

4. The override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in claim 1, characterized in that: During fault cutoff, the current loop of the healthy inverter is responsible for maintaining the track current, including: When an inverter fails and is disconnected, the output power of the faulty inverter drops to zero. The power loop of the healthy inverter is suppressed because the reference value is zero, and the output of the current loop increases. After the action of the override selection function, the phase shift control quantity is finally dominated by the current loop.

5. The override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in claim 1, characterized in that: The control process during fault recovery access includes: The healthy inverter has maintained the rail current within the error range of the given value; The current loop output amplitude of the recovery unit is less than the power loop output amplitude. After the selector takes the maximum value, the recovery unit gradually builds up the output power under the control of the power loop. The healthy unit continues to maintain stable track current, dominated by the current loop.

6. The override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in claim 1, characterized in that: The track current loop and power loop employ controllers designed based on the generalized state averaging method and small-signal model. Among them, the controlled object of the current loop is the effective value of the track current, and the controlled object of the power loop is the DC side input current or power; Two-ring frequency band separation design.

7. The override-tolerant fault control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in claim 1, characterized in that: During normal operation, fault disconnection, and recovery, the power coordination control between modules is achieved through an analog signal line that transmits the DC-side power reference value, and the switching sequence of each inverter is kept synchronized through an external phase synchronization signal.

8. A override fault-tolerant control system for a series H-bridge inverter in a rail-mounted wireless power transmission system, implementing the override fault-tolerant control method for a series H-bridge inverter in a rail-mounted wireless power transmission system as described in any one of claims 1 to 7, characterized in that: include: Two H-bridge inverters are connected to the track side via a resonant network at their outputs, and the input of each inverter is connected to the DC bus. Each inverter unit is configured with a fault disconnect switch; A current detection unit is used to collect track current. The DC-side detection unit is used to collect the DC-side voltage and DC-side current of each inverter. Each inverter contains a controller, the controller comprising: The track current loop module generates the first phase shift angle based on the difference between the track current setpoint and the feedback value. ; The power loop module generates a second phase shift angle based on the difference between the local power feedback value and the reference power value. ; Override selector, used to select and The larger value in the range is used as the final phase-shift control value. ; The PWM drive module generates inverter bridge switching pulses based on the final phase shift control quantity; During fault disconnection, the current loop module of the healthy inverter takes the lead, while during fault recovery, the power loop module of the recovery unit takes the lead, and the current loop module of the healthy inverter remains dominant.

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