An FPGA-based intelligent chip reconfigurable computing system

Abstract

The application relates to the technical field of computers and discloses an intelligent chip reconfigurable computing system based on FPGA, aiming to solve the inherent contradiction between the flexibility of FPGA configuration and the computing efficiency in the prior art. The system comprises: a configuration management module for receiving task scheduling instructions and generating a configuration parameter set containing computing core mapping parameters, data flow routing parameters and storage access parameters; a reconfigurable computing array composed of a plurality of dynamically configurable computing units; an intelligent resource scheduling engine for real-time monitoring of the operating state, adaptive resource allocation based on machine learning prediction analysis and dynamic programming scheduling; and a high-speed data interconnection network supporting multi-channel parallel data transmission. The application realizes dynamic optimal configuration of hardware resources, breaks through the limitations of traditional FPGA static configuration, significantly improves the computing efficiency and resource utilization of the system, effectively reduces the power consumption of the system, and can be widely applied in the fields of artificial intelligence reasoning, signal processing and the like.

Description

Technical Field

[0001] This invention relates to the field of computer technology, specifically to a reconfigurable computing system based on an FPGA-based intelligent chip. Background Technology

[0002] With the rapid development of artificial intelligence technology, intelligent chips, as core computing power carriers, are playing an increasingly important role in fields such as cloud computing, edge computing, and autonomous driving. Reconfigurable computing technology, as a computing paradigm that can dynamically adjust hardware resource configuration according to different application needs, combines the flexibility of general-purpose processors with the efficiency of application-specific integrated circuits, thus becoming an important research direction in the field of intelligent chips. Field-programmable gate arrays (FPGAs), as the current mainstream reconfigurable hardware platform, are widely used to accelerate intelligent computing tasks such as neural network inference and image processing due to their abundant logic resources and parallel computing capabilities.

[0003] In reconfigurable computing systems based on field-programmable gate arrays (FPGAs), the efficiency of loading configuration data directly determines the actual computing power output performance of the system. Because traditional FPGAs use a global configuration mode, the complete configuration data volume typically reaches several megabytes, causing the configuration process to consume hundreds of milliseconds or even seconds. Limited by the physical bottleneck of configuration interface bandwidth, reducing configuration time is severely constrained, leading to a series of chain reactions such as excessive system response latency and prolonged idle time of computing resources. In dynamic application scenarios requiring frequent switching of computing tasks, the proportion of configuration overhead in the overall runtime increases significantly, severely weakening the performance advantages of reconfigurable computing architectures, thus creating a technical dilemma where intelligent chips cannot fully realize their hardware potential. Summary of the Invention

[0004] This application provides an FPGA-based intelligent chip reconfigurable computing system, which aims to resolve the inherent contradiction between FPGA configuration flexibility and computing efficiency in the prior art, and realize the dynamic optimal allocation and efficient utilization of hardware resources.

[0005] The first aspect of this application provides an FPGA-based intelligent chip reconfigurable computing system, comprising:

[0006] The configuration management module is used to receive task scheduling instructions and parse the type, resource requirements and performance indicators of computing tasks, and generate corresponding configuration parameter sets, wherein the configuration parameter sets include computing core mapping parameters, data flow routing parameters and storage access parameters;

[0007] A reconfigurable computing array consists of multiple dynamically configurable computing units, each containing a programmable logic module and a dedicated computing engine. The reconfigurable computing array dynamically adjusts the logical functions and interconnection topology of each computing unit according to the configuration parameter set output by the configuration management module to adapt to different types of computing tasks.

[0008] The intelligent resource scheduling engine is used to monitor the operating status of the reconfigurable computing array in real time, including the load rate, data throughput and power consumption information of each computing unit, and make adaptive resource allocation decisions based on the monitoring results, dynamically adjusting the execution position and execution order of tasks in the reconfigurable computing array;

[0009] A high-speed data interconnection network connects the configuration management module, the reconfigurable computing array, and the intelligent resource scheduling engine, and is used to transmit configuration commands, control signals, and computing data. The high-speed data interconnection network adopts a hierarchical routing architecture and supports multi-channel parallel data transmission.

[0010] In one optional implementation, each programmable logic module in the reconfigurable computing array includes: a lookup table structure, a flip-flop array, and a carry logic chain; the dedicated computing engine includes: a multiplication and accumulation unit, a matrix operation unit, and an activation function processing unit; the programmable logic modules and the dedicated computing engine are selectively connected through a programmable interconnect matrix to realize a hybrid computing architecture.

[0011] In one optional implementation, the intelligent resource scheduling engine includes: a state awareness unit, a predictive analysis unit, and a scheduling decision unit;

[0012] The state awareness unit collects real-time operating data of each computing unit through performance counters, including the number of execution cycles, cache hit rate, and pipeline stall cycles.

[0013] The predictive analysis unit uses a machine learning inference model to predict the expected performance of each computing unit when executing the computing task, based on historical running data and current task characteristics, and generates performance prediction results.

[0014] The scheduling decision unit determines the optimal task allocation scheme using a dynamic programming algorithm based on the performance prediction results and the preset optimization objectives, and sends the optimal task allocation scheme to the configuration management module for configuration update.

[0015] In one optional implementation, the configuration management module further includes: a configuration cache unit and a configuration prefetch unit;

[0016] The configuration cache unit is used to store the most recently used configuration parameter set. When the matching degree between a newly arrived computing task and the cached configuration parameter set exceeds a preset threshold, the cached configuration parameter set is directly called for configuration to reduce configuration latency.

[0017] The configuration update unit is used to identify the differences between the old and new configuration parameter sets, and only updates the configuration registers that have changed, so as to maintain the continuous operation of the unaffected areas and achieve a smooth transition in the configuration process.

[0018] In one optional implementation, the high-speed data interconnect network adopts a three-dimensional integrated architecture, including: internal metal layer interconnects, silicon interposer interconnects, and high-speed serial channels between chips; the internal metal layer interconnects are used to connect various functional modules within the same chip; the silicon interposer interconnects are used to connect multiple chips within the same package; and the high-speed serial channels between chips are used for data transmission across packages.

[0019] In one optional implementation, the reconfigurable computing system further includes a dynamic power management module, which collects system power consumption data in real time and dynamically adjusts the power supply voltage and clock frequency of each computing unit based on changes in task load, thereby reducing system power consumption while ensuring performance requirements.

[0020] In one optional implementation, the reconfigurable computing system further includes a security monitoring module, used to perform integrity and legality verification on the input configuration parameter set, detect potential security threats and abnormal configuration behaviors, and ensure that the system operates in a trusted state.

[0021] In one optional implementation, the intelligent resource scheduling engine also supports a multi-task parallel scheduling mode. When multiple computing tasks arrive simultaneously, the multiple computing tasks are divided into multiple batches according to the priority and resource requirements of each task, and an independent subset of computing resources is allocated to each batch to achieve hybrid parallelism in the spatial and temporal domains.

[0022] In one optional implementation, the reconfigurable computing array supports a hierarchical reconfigurable architecture, including: a coarse-grained reconfigurable layer and a fine-grained reconfigurable layer; the coarse-grained reconfigurable layer consists of multiple functional modules, each implementing a specific functional unit; the fine-grained reconfigurable layer consists of programmable logic units, implementing basic logical operations and data processing operations; the coarse-grained and fine-grained reconfigurable layers work together to achieve reconfigurable execution of computing tasks at different abstraction levels.

[0023] In one optional implementation, the configuration management module also supports configuration stream compression technology, which compresses and encodes the configuration parameter set before transmitting it in the high-speed data interconnection network. The receiving end decompresses the compressed configuration parameter set and then executes the configuration, thereby reducing the amount of configuration data transmitted and speeding up the configuration process.

[0024] In the FPGA-based intelligent chip reconfigurable computing system provided in this application, the configuration management module receives task scheduling instructions and generates a set of configuration parameters. The reconfigurable computing array dynamically adjusts its logical functions and interconnection topology according to the set of configuration parameters to adapt to the computing tasks. The intelligent resource scheduling engine monitors the running status in real time and adaptively allocates resources. The high-speed data interconnection network provides a data transmission channel between the modules.

[0025] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0026] By leveraging the collaborative efforts of the configuration management module, reconfigurable computing array, and intelligent resource scheduling engine, dynamic optimal configuration of hardware resources is achieved, overcoming the limitations of traditional FPGA static configuration and fully unleashing the flexibility potential of FPGAs. Through machine learning predictive analysis and dynamic programming scheduling decisions by the intelligent resource scheduling engine, optimal allocation of computing tasks among different computing units is realized, significantly improving system computing efficiency and resource utilization. The three-dimensional integrated architecture design of the high-speed data interconnect network ensures high-speed transmission of configuration instructions, control signals, and computational data, reducing the impact of data transmission latency on system performance. The adaptive adjustment of the dynamic power management module effectively reduces system power consumption while maintaining performance, improving the system's energy efficiency ratio. This system can be widely applied in fields such as artificial intelligence inference, signal processing, and communication baseband processing, which have high requirements for computational flexibility and efficiency, providing a new technical approach for next-generation intelligent computing platforms. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall technical process of the FPGA-based intelligent chip reconfigurable computing system proposed in this invention.

[0028] Figure 2 This is a schematic diagram illustrating the core principle and process of the intelligent resource scheduling engine in this invention;

[0029] Figure 3 This is a schematic diagram of the hierarchical reconfigurable architecture and hybrid computing process of the reconfigurable computing array in this invention;

[0030] Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow of the high-speed data interconnection network in this invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Reference Figure 1 The system includes: a configuration management module, a reconfigurable computing array, an intelligent resource scheduling engine, and a high-speed data interconnection network.

[0033] The FPGA-based intelligent chip reconfigurable computing system in this application aims to resolve the inherent contradiction between FPGA configuration flexibility and computing efficiency in existing technologies, achieving dynamic optimal allocation and efficient utilization of hardware resources. In this system, the configuration management module receives task scheduling instructions and parses the type, resource requirements, and performance indicators of the computing tasks, generating corresponding configuration parameter sets. These parameter sets include core mapping parameters, data flow routing parameters, and storage access parameters. The reconfigurable computing array consists of multiple dynamically configurable computing units. Based on the configuration parameter sets, the logical functions and interconnection topology of each computing unit are dynamically adjusted to adapt to different types of computing tasks. The intelligent resource scheduling engine monitors the operating status of the reconfigurable computing array in real time, makes adaptive resource allocation decisions based on the monitoring results, and dynamically adjusts the execution position and order of tasks within the reconfigurable computing array. A high-speed data interconnect network connects the configuration management module, the reconfigurable computing array, and the intelligent resource scheduling engine, used for transmitting configuration instructions, control signals, and computing data.

[0034] In this embodiment, in an FPGA-based intelligent chip reconfigurable computing system, dynamic optimal configuration of hardware resources is achieved through the collaborative work of a configuration management module, a reconfigurable computing array, and an intelligent resource scheduling engine. When a task scheduling instruction arrives at the configuration management module, the module first parses the instruction, extracts the type identifier of the computing task, and determines whether the task belongs to an artificial intelligence inference task, a signal processing task, or a communication baseband processing task, etc. Then, based on the task type, it determines the resource requirements, including the number, type, interconnect bandwidth, and storage capacity of the required computing units. Next, based on performance requirements, including throughput, latency, and energy efficiency ratio, it generates a complete set of configuration parameters. This set of configuration parameters includes computing core mapping parameters, which define the logical function allocation of each computing unit and the spatial deployment location of the computing cores; data flow routing parameters, which define the data transmission path and routing strategy between computing units; and storage access parameters, which define the access mode and access priority of each computing unit to local and shared storage. The configuration management module sends the configuration parameter set to the reconfigurable computing array through a high-speed data interconnect network to complete the hardware configuration of the computing task.

[0035] In this embodiment, the reconfigurable computing array dynamically adjusts the logical functions and interconnection topology of each computing unit according to a configuration parameter set. Taking an artificial intelligence inference task as an example, the configuration parameter set specifies that multiple computing units are configured in matrix operation mode, the interconnection topology between computing units is configured as a two-dimensional mesh topology, the data flow routing parameters are configured as pipelined data flow, and the storage access parameters are configured as a high-frequency access local cache mode. The programmable logic modules inside the computing units implement customized logic functions through lookup table structures, trigger arrays, and carry logic chains. The multiplication and accumulation unit in the dedicated computing engine performs matrix multiplication operations, the matrix operation unit performs large-scale parallel matrix operations, and the activation function processing unit performs activation function operations such as ReLU, Sigmoid, and Tanh. The programmable interconnection matrix dynamically establishes data channels between computing units according to the configuration parameter set, realizing a hybrid computing architecture. Through the above dynamic configuration process, the system can complete the execution from task reception to hardware configuration in milliseconds, significantly improving the configuration flexibility and computing efficiency of the FPGA.

[0036] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, each programmable logic module in the reconfigurable computing array includes: a lookup table structure, a flip-flop array, and a carry logic chain; the dedicated computing engine includes: a multiplication and accumulation unit, a matrix operation unit, and an activation function processing unit; the programmable logic modules and the dedicated computing engine are selectively connected through a programmable interconnect matrix to realize a hybrid computing architecture.

[0037] In this embodiment, the programmable logic module uses a traditional FPGA lookup table structure to implement general logic functions. Each lookup table structure consists of multiple four-input lookup table units, and each four-input lookup table unit can be configured to implement any four-input single-output Boolean function. The output of the lookup table unit is connected to flip-flops in a flip-flop array, which consists of D flip-flops and is used to temporarily store the calculation results of the lookup table, realizing pipelined logic operations. The carry logic chain is used to implement carry propagation in arithmetic operations, increasing the clock frequency of arithmetic operations. The inputs and outputs of the programmable logic module are configured through a programmable interconnect matrix, which consists of a large number of programmable switch units. By configuring the on / off states of the switch units, connections between arbitrary input and output ports can be achieved.

[0038] In this embodiment, the dedicated computing engine performs hardware optimization for specific types of computing tasks to achieve higher computational efficiency. The multiplication-accumulation unit integrates multiple hardware multipliers and adders, enabling multiple multiplication and accumulation operations to be completed within a single clock cycle, suitable for core computational patterns in convolution and matrix multiplication operations. The matrix operation unit adopts a systolic array structure, with multiple computing units arranged in a two-dimensional array, and data flowing in the array according to a fixed flow direction, achieving efficient execution of large-scale matrix operations. The activation function processing unit integrates lookup tables for commonly used activation functions such as ReLU, Sigmoid, Tanh, and Softmax, implementing activation function operations through table lookup, avoiding complex exponential and division operations, and significantly reducing the computational latency of activation functions. The programmable logic modules (PLMs) and dedicated computing engines are connected via a programmable interconnect matrix. When a computing task requires the use of the dedicated computing engine, the configuration management module specifies the path for data flow from the PLMs to the dedicated computing engine through a set of configuration parameters, enabling collaborative operation between the PLMs and the dedicated computing engine. When a computing task does not require the dedicated computing engine, the programmable interconnect matrix is ​​configured in bypass mode, allowing data to flow directly between the PLMs, thus realizing a hybrid computing architecture. This hybrid computing architecture significantly improves the execution efficiency of dedicated computing tasks while maintaining the flexibility of the FPGA.

[0039] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the intelligent resource scheduling engine includes: a state awareness unit, a predictive analysis unit, and a scheduling decision unit. The state awareness unit collects real-time operating data of each computing unit through performance counters, including the number of execution cycles, cache hit rate, and pipeline stall cycles. Based on historical operating data and current task characteristics, the predictive analysis unit uses a machine learning inference model to predict the expected performance of each computing unit when executing computing tasks and generates performance prediction results. The scheduling decision unit determines the optimal task allocation scheme using a dynamic programming algorithm based on the performance prediction results and preset optimization objectives, and sends the optimal task allocation scheme to the configuration management module for configuration updates.

[0040] In this embodiment, the intelligent resource scheduling engine is the core scheduling and control unit of the entire system, and its core principle framework is as follows: Figure 2 As shown, the state-aware unit collects real-time runtime data through performance counters integrated in each computing unit. These performance counters include an execution cycle counter, which counts the number of clock cycles consumed by each computing unit in executing a task; a cache hit rate counter, which counts the number of local cache hits and misses for each computing unit, calculating the cache hit rate as the ratio of hits to total accesses; and a pipeline stall cycle counter, which counts the number of pipeline stalls caused by data dependencies or resource conflicts in each computing unit. The state-aware unit periodically reads the count values ​​of each performance counter and converts them into standardized runtime status data. This runtime status data includes the load rate of each computing unit, defined as the ratio of the time occupied by the currently executing task to the total available time; data throughput, defined as the amount of data processed by each computing unit per unit time; and power consumption information, defined as the instantaneous power consumption value of each computing unit at the current moment.

[0041] In this embodiment, the predictive analysis unit, based on historical running data and current task features collected by the state-aware unit, uses a machine learning inference model to predict the expected performance of each computing unit when executing a specified computing task. The input to the predictive analysis unit includes a historical running data sequence and a feature vector of the current task. The historical running data sequence contains a time series of information on the load rate, data throughput, and power consumption of each computing unit over multiple past scheduling cycles. The current task feature vector includes the task type identifier, input data size, computational complexity, and latency constraints. The machine learning inference model employs a Long Short-Term Memory (LSTM) network structure, which includes an input layer, a bidirectional LSM layer, and a fully connected output layer. The LSM network's input layer receives the concatenation of the historical running data sequence and the current task feature vector. The bidirectional LSM layer extracts long-term dependency features from the time series. The fully connected output layer maps the extracted features to the performance prediction space, outputting performance prediction results such as the predicted execution cycle, cache hit rate, and pipeline efficiency for each computing unit.

[0042] In this embodiment, the scheduling decision unit determines the optimal task allocation scheme using a dynamic programming algorithm based on performance prediction results and preset optimization objectives. Optimization objectives can include maximizing system throughput, minimizing task latency, or maximizing energy efficiency. The dynamic programming algorithm models the task allocation problem as a multi-stage decision problem, where each stage corresponds to the allocation decision of a computing unit. State variables are defined as the available resources and expected performance of each computing unit at the current moment; decision variables are defined as which computing unit to allocate the current task to; execution benefit is defined as the performance improvement brought about by executing the task on that computing unit; and cost is defined as the configuration overhead incurred by task switching. The dynamic programming algorithm determines the globally optimal task allocation scheme by recursively calculating the maximum cumulative benefit from the current stage to the final stage. The scheduling decision unit sends the optimal task allocation scheme to the configuration management module, which updates the configuration parameter set according to the scheme, realizing the dynamic reallocation of computing tasks.

[0043] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the configuration management module further includes: a configuration cache unit and a configuration prefetch unit; the configuration cache unit is used to store the most recently used configuration parameter set. When the matching degree between a newly arrived computing task and the cached configuration parameter set exceeds a preset threshold, the cached configuration parameter set is directly called for configuration to reduce configuration latency; the configuration part update unit is used to identify the differences between the old and new configuration parameter sets, and only update the configuration registers that have changed, maintaining the continuous operation of unaffected areas and realizing a smooth transition in the configuration process.

[0044] In this embodiment, the configuration management module further optimizes configuration efficiency through a configuration cache unit and a configuration prefetch unit. The configuration cache unit is implemented using content-addressable memory, and each cache entry contains a feature key for the configuration parameter set and the corresponding configuration parameter set. The feature key consists of a task type identifier, a resource requirement identifier, and a performance indicator identifier. When a new task arrives, the configuration management module calculates the feature key for that task and performs a matching search in the configuration cache unit. When the matching degree of the feature key exceeds a preset threshold, the corresponding configuration parameter set is directly read from the configuration cache unit without regenerating the configuration parameter set, significantly reducing configuration latency. The configuration cache unit has limited capacity; when the cache is full, the least recently used algorithm is used to evict the least recently used cache entry, freeing up space to store a new configuration parameter set.

[0045] In this embodiment, the configuration update unit identifies the differences between the old and new configuration parameter sets to achieve incremental configuration. When a new task arrives, the configuration management module compares the new task's configuration parameter set bit by bit with the currently effective configuration parameter set to identify the configuration registers that have changed. The configuration update unit only sends the addresses and values ​​of the changed registers to the reconfigurable computing array, which then updates the corresponding configuration registers based on the received addresses and values. For configuration registers that have not changed, their original configuration state is maintained, and no reconfiguration is required. Through the configuration update unit, a smooth transition in the configuration process is achieved, avoiding the configuration latency and resource overhead caused by full configuration.

[0046] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system, in which a high-speed data interconnect network adopts a three-dimensional integrated architecture, including: internal metal layer interconnects, silicon interposer interconnects, and high-speed serial channels between chips; the internal metal layer interconnects are used to connect various functional modules within the same chip; the silicon interposer interconnects are used to connect multiple chips within the same package; and the high-speed serial channels between chips are used for data transmission across packages.

[0047] In this embodiment, the multi-level interaction relationship and data flow diagram of the high-speed data interconnection network are shown below. Figure 4 As shown, the internal metal layer interconnects of the chip employ a multi-layer metal wiring structure to achieve high-speed data connections between the configuration management module, reconfigurable computing array, and intelligent resource scheduling engine within the same chip. The wiring of the internal metal layer interconnects utilizes advanced process technology with nanometer-level linewidths, and low-dielectric-constant materials are used as interlayer dielectrics to reduce line delay and crosstalk. The internal metal layer interconnects support multi-voltage domain design, with different voltage domains connected via level conversion units to ensure correct signal transmission.

[0048] In this embodiment, silicon interposer interconnects utilize silicon interposer technology to integrate multiple FPGA chips within the same package. The silicon interposer is a thin silicon layer fabricated on a packaging substrate using semiconductor processes, on which high-density interconnects and micro-bumps are integrated. The wiring density of silicon interposer interconnects is significantly higher than that of traditional packaging substrates, enabling high-bandwidth data connections between chips. Silicon interposer interconnects support data transmission rates in the megabits per second range, meeting the data transmission requirements of multi-chip collaborative computing.

[0049] In this embodiment, the high-speed serial channel between chips is used for cross-package data transmission, employing a high-speed serial communication protocol such as PCIe or Fibre Channel. The transmission rate of the high-speed serial channel between chips can reach tens of gigabits per second, supporting long-distance data transmission. The high-speed serial channel between chips supports both point-to-point and bus connection modes. Point-to-point connections are suitable for dedicated data channels between two chips, while bus connections are suitable for multiple chips sharing a data channel. The high-speed data interconnect network manages the data flow between layers through a hierarchical routing architecture, enabling multi-channel parallel transmission of configuration commands, control signals, and computational data.

[0050] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the reconfigurable computing system further includes a dynamic power management module, which is used to collect system power consumption data in real time, dynamically adjust the power supply voltage and clock frequency of each computing unit based on changes in task load, and reduce system power consumption while ensuring performance requirements.

[0051] In this embodiment, the dynamic power management module optimizes energy efficiency through real-time power consumption monitoring and adaptive voltage and frequency adjustment. Integrated into the intelligent resource scheduling engine, the module collects real-time power consumption data from each computing unit using a power sensor. The power sensor employs a current-sensing amplifier to detect the current in the power supply circuit of each computing unit and calculates instantaneous power consumption based on the supply voltage. The dynamic power management module dynamically adjusts the supply voltage and clock frequency of each computing unit based on the power consumption data and the real-time load rate of each unit.

[0052] In this embodiment, when a low load rate is detected in a computing unit, the dynamic power management module reduces the clock frequency of that computing unit to decrease dynamic power consumption. The clock frequency adjustment is achieved through a phase-locked loop (PLL), with the PLL output frequency adjustable from hundreds of megahertz to gigahertz. When the overall system load is low, the dynamic power management module can also reduce the supply voltage of some computing units to further reduce static and dynamic power consumption. The supply voltage adjustment is achieved through a digitally controlled low-dropout regulator, with the output voltage adjustable from volts to volts. Through the above dynamic power management, while ensuring performance requirements, system power consumption can be reduced to tens of percent of the peak value, significantly improving the system's energy efficiency ratio.

[0053] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the reconfigurable computing system further includes: a security monitoring module, used to perform integrity verification and legality verification on the input configuration parameter set, detect potential security threats and abnormal configuration behaviors, and ensure that the system operates in a trusted state.

[0054] In this embodiment, the security monitoring module performs a security review of the configuration parameter set to prevent malicious configuration attacks. The security monitoring module integrates an integrity verification module and a validity verification module for the configuration parameter set. The integrity verification module uses a hash algorithm to perform a hash operation on the configuration parameter set, compares the calculated hash value with a pre-stored correct hash value, and detects whether the configuration parameter set has been tampered with during transmission. The validity verification module parses the specific content of the configuration parameter set and checks whether each parameter is within a legal range, such as whether the number of computing units exceeds the system limit, whether the interconnection topology meets physical constraints, and whether the storage access parameters are valid.

[0055] In this embodiment, when a security threat or abnormal behavior is detected in the configuration parameter set, the security monitoring module immediately reports to the system control unit and triggers a security protection mechanism. This mechanism includes refusing to execute the configuration parameter set, rolling back to the most recent secure configuration state, and triggering alarm signals. Through the security monitoring module, the system is ensured to operate in a trusted state, preventing system failures or data leaks caused by malicious configuration.

[0056] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the intelligent resource scheduling engine also supports a multi-task parallel scheduling mode. When multiple computing tasks arrive at the same time, the multiple computing tasks are divided into multiple batches according to the priority and resource requirements of each task, and an independent subset of computing resources is allocated to each batch to achieve hybrid parallelism in the spatial and temporal domains.

[0057] In this embodiment, the intelligent resource scheduling engine's multi-task parallel scheduling mode supports hybrid spatial and temporal parallelism for multiple computing tasks. Spatial domain parallelism refers to simultaneously allocating multiple computing tasks to different subsets of computing resources for execution, with each subset being independent of the others. Temporal domain parallelism refers to dividing the execution process of a single computing task into multiple time windows, executing different subtasks within different time windows. The intelligent resource scheduling engine divides multiple tasks into multiple batches using a batch processing scheduling algorithm based on the priority and resource requirements of each task.

[0058] In this embodiment, the batch scheduling algorithm first sorts all arriving tasks according to priority, with high-priority tasks placed at the front of the queue. Then, the scheduling algorithm calculates the set of tasks that each batch can accommodate based on the resource requirements of each task and the currently available computing resources. The scheduling algorithm employs a first-fit decreasing algorithm, which first arranges tasks in descending order of resource requirements, and then sequentially attempts to place each task into the first batch that can accommodate it. Through this multi-task parallel scheduling mode, the system can process multiple computing tasks simultaneously, significantly improving system throughput and resource utilization.

[0059] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the reconfigurable computing array supports a hierarchical reconfigurable architecture, including: a coarse-grained reconfigurable layer and a fine-grained reconfigurable layer; the coarse-grained reconfigurable layer consists of multiple functional modules, each implementing a specific functional unit; the fine-grained reconfigurable layer consists of programmable logic units, implementing basic logical operations and data processing operations; the coarse-grained and fine-grained reconfigurable layers work together to achieve reconfigurable execution of computing tasks at different abstraction levels.

[0060] In this embodiment, the hierarchical reconfigurable architecture and hybrid computing schematic diagram of the reconfigurable computing array are shown below. Figure 3 As shown, the coarse-grained reconfigurable layer adopts a functional module-level reconfigurable design. Each functional module implements a specific functional unit, such as a convolutional module, a pooling module, a fully connected module, and an activation function module. The internal structure of each functional module is optimized for its specific function, enabling the complete computation of that function within one clock cycle. When a computational task needs to use a certain function, it directly calls the corresponding functional module without reconfiguring the internal logic.

[0061] In this embodiment, the fine-grained reconfigurable layer adopts a reconfigurable design at the programmable logic unit (PLU) level. The PLU consists of lookup tables, flip-flops, and programmable interconnect resources, implementing basic logical operations and data processing. When a computational task requires new functionality not present in the coarse-grained functional modules, the scheduling engine can break down this functionality into multiple fine-grained basic operations and assign them to the fine-grained reconfigurable layer for execution. The fine-grained reconfigurable layer offers greater flexibility than the coarse-grained reconfigurable layer, but its execution efficiency is lower. The coarse-grained and fine-grained reconfigurable layers are connected via a programmable interconnect matrix to achieve collaborative operation. The scheduling engine adaptively selects whether to use the coarse-grained or fine-grained layer, or to use both layers simultaneously for hybrid computation, based on task characteristics, thus achieving reconfigurable execution of computational tasks at different abstraction levels.

[0062] In one embodiment, this application also provides an FPGA-based intelligent chip reconfigurable computing system. In this system, the configuration management module also supports configuration stream compression technology, which compresses and encodes the configuration parameter set and transmits it in a high-speed data interconnection network. The receiving end decompresses the compressed configuration parameter set and executes the configuration, thereby reducing the amount of configuration data transmission and speeding up the configuration process.

[0063] In this embodiment, configuration stream compression technology utilizes the spatial redundancy of configuration parameter sets for compression. The configuration parameter set contains a large number of configuration register addresses and values, where adjacent configuration registers often have the same or similar values, resulting in spatial redundancy. Configuration stream compression technology employs a run-length encoding algorithm, which encodes consecutively occurring identical values ​​into a single value and a repetition count, significantly reducing the data volume. Configuration stream compression technology also uses a dictionary encoding algorithm, which maps occurrences of configuration patterns to indices in a dictionary, using the indices to replace the complete configuration patterns, further reducing the data volume.

[0064] In this embodiment, the compressed configuration parameter set is transmitted via a high-speed data interconnection network. The configuration management module at the receiving end decompresses the compressed configuration parameter set, restores the original configuration parameter set, and then executes the configuration. The decompression process is the reverse of the compression process. First, the configuration mode is restored through the reverse process of dictionary encoding, and then the complete configuration parameter set is restored through the reverse process of run-length encoding. Through configuration stream compression technology, the amount of configuration data transmitted can be reduced to tens of percent of the original data volume, and the configuration speed can be increased several times.

[0065] The FPGA-based intelligent chip reconfigurable computing system proposed in this application achieves dynamic optimal configuration of hardware resources through the collaborative work of a configuration management module, a reconfigurable computing array, and an intelligent resource scheduling engine. This overcomes the limitations of traditional static FPGA configuration and fully unleashes the flexibility potential of FPGAs. Through machine learning predictive analysis and dynamic programming scheduling decisions by the intelligent resource scheduling engine, optimal allocation of computing tasks among different computing units is achieved, significantly improving the system's computing efficiency and resource utilization. The three-dimensional integrated architecture design of a high-speed data interconnect network ensures high-speed transmission of configuration instructions, control signals, and computing data, reducing the impact of data transmission latency on system performance. The adaptive adjustment of the dynamic power management module effectively reduces system power consumption while maintaining performance, improving the system's energy efficiency ratio. Security verification by the security monitoring module ensures the system operates in a trusted state. Through a layered reconfigurable architecture and hybrid computing, reconfigurable execution at different abstraction levels is achieved. This system can be widely applied in fields such as artificial intelligence inference, signal processing, and communication baseband processing, which have high requirements for computing flexibility and efficiency, providing a new technical approach for next-generation intelligent computing platforms.

[0066] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based intelligent chip reconfigurable computing system, characterized in that, include: The configuration management module is used to receive task scheduling instructions and parse the type, resource requirements and performance indicators of computing tasks, and generate a set of configuration parameters including computing core mapping parameters, data flow routing parameters and storage access parameters. A reconfigurable computing array consists of multiple dynamically configurable computing units, each of which includes a programmable logic module and a dedicated computing engine. The reconfigurable computing array dynamically adjusts the logical functions and interconnection topology of each computing unit according to the configuration parameter set. The intelligent resource scheduling engine is used to monitor the operating status of the reconfigurable computing array in real time, including the load rate, data throughput and power consumption information of each computing unit, and make adaptive resource allocation decisions based on the monitoring results, dynamically adjusting the execution position and execution order of tasks in the reconfigurable computing array; A high-speed data interconnection network connects the configuration management module, the reconfigurable computing array, and the intelligent resource scheduling engine. It is used to transmit configuration commands, control signals, and computing data. The high-speed data interconnection network adopts a hierarchical routing architecture and supports multi-channel parallel data transmission. 2.The FPGA-based smart chip reconfigurable computing system of claim 1, wherein, Each programmable logic module includes a lookup table structure, a flip-flop array, and a carry logic chain; each dedicated computing engine includes a multiplication and accumulation unit, a matrix operation unit, and an activation function processing unit; the programmable logic modules and the dedicated computing engines are selectively connected through a programmable interconnect matrix. 3.The FPGA-based smart chip reconfigurable computing system of claim 1, wherein, The intelligent resource scheduling engine includes a state awareness unit, a predictive analysis unit, and a scheduling decision unit. The state awareness unit collects real-time operating data of each computing unit through performance counters, including the number of execution cycles, cache hit rate, and pipeline stall cycle count. The predictive analysis unit uses a machine learning inference model to predict the expected performance of each computing unit when executing the computing task based on historical operating data and current task characteristics, and generates performance prediction results. The scheduling decision unit determines the optimal task allocation scheme using a dynamic programming algorithm based on the performance prediction results and the preset optimization objectives, and sends the optimal task allocation scheme to the configuration management module for configuration update.

4. The FPGA-based smart-chip reconfigurable computing system of claim 3, wherein, The intelligent resource scheduling engine also supports a multi-task parallel scheduling mode. When multiple computing tasks arrive at the same time, the multiple computing tasks are divided into multiple batches according to the priority and resource requirements of each task, and an independent subset of computing resources is allocated to each batch.

5. The FPGA-based intelligent chip reconfigurable computing system according to claim 1, characterized in that, The configuration management module further includes a configuration cache unit and a configuration part update unit. The configuration cache unit is used to store the most recently used configuration parameter set. When the matching degree between a newly arrived computing task and the cached configuration parameter set exceeds a preset threshold, the cached configuration parameter set is directly called for configuration. The configuration part update unit is used to identify the differences between the old and new configuration parameter sets and only update the configuration registers that have changed.

6. The FPGA-based smart-chip reconfigurable computing system of claim 1, wherein, The high-speed data interconnect network adopts a three-dimensional integrated architecture, including internal metal layer interconnects, silicon interposer interconnects, and high-speed serial channels between chips; the internal metal layer interconnects are used to connect various functional modules within the same chip; the silicon interposer interconnects are used to connect multiple chips within the same package. The high-speed serial channel between chips is used for data transmission across packages.

7. The FPGA-based smart-chip reconfigurable computing system of claim 1, wherein, It also includes a dynamic power management module, which is used to collect system power consumption data in real time and dynamically adjust the power supply voltage and clock frequency of each computing unit based on changes in task load.

8. The FPGA-based intelligent chip reconfigurable computing system of claim 1, wherein, It also includes a security monitoring module, which is used to perform integrity and legality verification on the input configuration parameter set, and detect potential security threats and abnormal configuration behavior.

9. The FPGA-based intelligent chip reconfigurable computing system of claim 1, wherein, The reconfigurable computing array supports a hierarchical reconfigurable architecture, including a coarse-grained reconfigurable layer and a fine-grained reconfigurable layer. The coarse-grained reconfigurable layer consists of multiple functional modules, each implementing a specific functional unit. The fine-grained reconfigurable layer consists of programmable logic units, implementing basic logical operations and data processing operations.

10. The FPGA-based intelligent chip reconfigurable computing system of claim 1, wherein, The configuration management module also supports configuration stream compression technology, which compresses and encodes the configuration parameter set before transmitting it in the high-speed data interconnection network. The receiving end decompresses the compressed configuration parameter set and then executes the configuration.

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